Index: firmware/App/Controllers/RTC.c =================================================================== diff -u -r526902d0a427e330e23ae5eaf433e89298643ac7 -r46ab59f1a24da466a153a8880f3e66460c80512b --- firmware/App/Controllers/RTC.c (.../RTC.c) (revision 526902d0a427e330e23ae5eaf433e89298643ac7) +++ firmware/App/Controllers/RTC.c (.../RTC.c) (revision 46ab59f1a24da466a153a8880f3e66460c80512b) @@ -43,6 +43,15 @@ #define RTC_MONTHS_INDEX 9 #define RTC_YEARS_INDEX 10 +// *************** MibSPI values ************* // +#define MIBSPI_MAX_BUFFER_LENGTH 127U +#define MIBSPI_CONTINUOUS_MODE 4U +#define MIBSPI_CHIP_SELECT_ACTIVE 1U +#define MIBSPI_CHIP_SELECT_DEACTIVE 0U +#define MIBSPI_NO_WDELAY 0U +#define MIBSPI_LOCK_TG 0U +#define MIBSPI_DATA_FORMAT_ZERO 0U + // This command puts RTC into read mode from // address 0 #define RTC_READ_FROM_REG0 0x00A0 @@ -134,8 +143,6 @@ static BOOL hasReadFromRAMRequested = TRUE; static U16 rxBuffer[MAXIMUM_NUM_OF_BUFFER]; -//static U16 txBuffer[] = {RTC_READ_FROM_REG0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -// 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}; static U16 txBuffer[MAXIMUM_NUM_OF_BUFFER]; @@ -154,9 +161,8 @@ static RTC_EXEC_STATE_T handleExecIdleState(); static RTC_EXEC_STATE_T handleExecReadState(); -static RTC_EXEC_STATE_T handleExecPrepRAMState(); -static RTC_EXEC_STATE_T handleExecRAMState(U08* address, U08* data, U32 length); -static RTC_EXEC_STATE_T handleExecRAMState(U08* address, U08* data, U32 length); +static RTC_EXEC_STATE_T handleExecPrepRAMState( U08* address ); +static RTC_EXEC_STATE_T handleExecRAMState( U08* data, U32 length ); static RTC_EXEC_STATE_T handleExecWriteState(); static BOOL setMibSPIBufferLength(U16 length); @@ -225,6 +231,22 @@ void execRTC() { + // FOR DEBUGGING PURPOSES ONLY + U08 address; + U08 data[8]; + U32 length; + address = 12; + data[0] = 4; + data[1] = 5; + data[2] = 6; + data[3] = 7; + data[4] = 8; + data[5] = 9; + data[6] = 3; + data[7] = 1; + length = sizeof(data); + // FOR DEBUGGING PURPOSED ONLY + switch ( RTCExecState ) { case RTC_EXEC_STATE_WAIT_FOR_POST: @@ -248,12 +270,12 @@ case RTC_EXEC_STATE_PREP_RAM: - RTCExecState = handleExecRAMState(0, 0, 0); + RTCExecState = handleExecPrepRAMState( &address ); break; case RTC_EXEC_STATE_RAM: - RTCExecState = handleExecRAMState(0, 0, 0); + RTCExecState = handleExecRAMState( &data[0], length ); break; case RTC_EXEC_STATE_WRITE: @@ -473,10 +495,14 @@ { result = RTC_EXEC_STATE_WRITE; } - else if ( hasWriteToRAMRequested || hasReadFromRAMRequested ) + else if ( hasWriteToRAMRequested ) { result = RTC_EXEC_STATE_PREP_RAM; } + else if ( hasReadFromRAMRequested ) + { + result = RTC_EXEC_STATE_PREP_RAM; + } // If write to RTC has been requested, we don't have to read // write must be finished first else if ( timeCounter == TIMER_COUNTER_TO_REQUEST_READ ) @@ -503,13 +529,13 @@ return result; } -static RTC_EXEC_STATE_T handleExecPrepRAMState(U08* address) +static RTC_EXEC_STATE_T handleExecPrepRAMState( U08* address ) { - RTC_EXEC_STATE_T result = RTCExecState; + RTC_EXEC_STATE_T result = RTC_EXEC_STATE_PREP_RAM; txBuffer[0] = RTC_PREP_RAM_READ_WRITE; - txBuffer[1] = 0x0000; - txBuffer[2] = 0x0000; + txBuffer[1] = (U16)( *address / 10 ); + txBuffer[2] = (U16)( *address % 10 ); setMibSPIBufferLength(3); @@ -518,6 +544,9 @@ if ( RTCServiceState == RTC_READ_COMPLETE && isStatusOk ) { result = RTC_EXEC_STATE_RAM; + + // Reset the RTC Service commands + RTCServiceState = RTC_SEND_COMMAND; } else if ( RTCServiceState == RTC_READ_COMPLETE && ! isStatusOk ) { @@ -527,55 +556,49 @@ return result; } -static RTC_EXEC_STATE_T handleExecRAMState(U08* address, U08* data, U32 length) +static RTC_EXEC_STATE_T handleExecRAMState( U08* data, U32 length ) { - RTC_EXEC_STATE_T result = RTCExecState; + RTC_EXEC_STATE_T result = RTC_EXEC_STATE_RAM; - if ( RTCExecState == RTC_EXEC_STATE_PREP_RAM ) + U08 i; + + if ( hasWriteToRAMRequested ) { - txBuffer[0] = RTC_PREP_RAM_READ_WRITE; - txBuffer[1] = 0x0000; - txBuffer[2] = 0x0000; + txBuffer[0] = RTC_WRITE_TO_RAM; - setMibSPIBufferLength(3); + for ( i = 0; i < length; i++ ) + { + // The zeroth element of txBuffer + // is the RAM command + txBuffer[i + 1] = data[i]; + } + setMibSPIBufferLength( length + 1 ); - result = RTC_EXEC_STATE_PREP_RAM; + // Set the buffer once and done + hasWriteToRAMRequested = FALSE; } - else if ( RTCExecState == RTC_EXEC_STATE_RAM ) + else if ( hasReadFromRAMRequested ) { - if ( hasWriteToRAMRequested ) + txBuffer[0] = RTC_READ_FROM_RAM; + + for ( i = 0; i < MAXIMUM_NUM_OF_BUFFER - 1; i++ ) { - txBuffer[0] = RTC_WRITE_TO_RAM; + txBuffer[i+1] = 0; } - else if ( hasReadFromRAMRequested ) - { - txBuffer[0] = RTC_READ_FROM_RAM; - } - txBuffer[1] = 0x0000; - txBuffer[2] = 0x0000; + // Max buffer length is 127, so 129 - 2 will be 127 + setMibSPIBufferLength( MAXIMUM_NUM_OF_BUFFER - 2 ); - setMibSPIBufferLength(3); - - result = RTC_EXEC_STATE_RAM; + // Set the buffer to the maximum since + // we don't know how many buffer are in a + hasReadFromRAMRequested = FALSE; } BOOL isStatusOk = serviceRTC( &txBuffer[0] ); if ( RTCServiceState == RTC_READ_COMPLETE && isStatusOk ) { - if ( RTCExecState == RTC_EXEC_STATE_PREP_RAM ) - { - result = RTC_EXEC_STATE_RAM; - // Reset the RTC Service commands - RTCServiceState = RTC_SEND_COMMAND; - } - else - { - result = RTC_EXEC_STATE_IDLE; - hasWriteToRAMRequested = FALSE; - hasReadFromRAMRequested = FALSE; - } + result = RTC_EXEC_STATE_IDLE; } else if ( RTCServiceState == RTC_READ_COMPLETE && ! isStatusOk ) { @@ -611,7 +634,6 @@ return result; } - // Private self test functions static RTC_SELF_TEST_STATE_T handleSelfTestStart() { @@ -711,59 +733,60 @@ static BOOL setMibSPIBufferLength( U16 length ) { // TODO: Check for the length of the buffer - U32 i = 0; - mibspiREG3->TGCTRL[0U] &= ~(uint32)((uint32)127U << 8U); + mibspiREG3->TGCTRL[0U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); - mibspiREG3->TGCTRL[1U] &= ~(uint32)((uint32)127U << 8U); + mibspiREG3->TGCTRL[1U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); mibspiREG3->TGCTRL[1U] |= (uint32)((uint32)length << 8U); - mibspiREG3->TGCTRL[2U] &= ~(uint32)((uint32)127U << 8U); + mibspiREG3->TGCTRL[2U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); mibspiREG3->TGCTRL[2U] |= (uint32)((uint32)(length+0U) << 8U); - mibspiREG3->TGCTRL[3U] &= ~(uint32)((uint32)127U << 8U); + mibspiREG3->TGCTRL[3U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); mibspiREG3->TGCTRL[3U] |= (uint32)((uint32)(length+0U+0U) << 8U); - mibspiREG3->TGCTRL[4U] &= ~(uint32)((uint32)127U << 8U); + mibspiREG3->TGCTRL[4U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); mibspiREG3->TGCTRL[4U] |= (uint32)((uint32)(length+0U+0U+0U) << 8U); - mibspiREG3->TGCTRL[5U] &= ~(uint32)((uint32)127U << 8U); + mibspiREG3->TGCTRL[5U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); mibspiREG3->TGCTRL[5U] |= (uint32)((uint32)(length+0U+0U+0U+0U) << 8U); - mibspiREG3->TGCTRL[6U] &= ~(uint32)((uint32)127U << 8U); + mibspiREG3->TGCTRL[6U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); mibspiREG3->TGCTRL[6U] |= (uint32)((uint32)(length+0U+0U+0U+0U+0U) << 8U); - mibspiREG3->TGCTRL[7U] &= ~(uint32)((uint32)127U << 8U); + mibspiREG3->TGCTRL[7U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); mibspiREG3->TGCTRL[7U] |= (uint32)((uint32)(length+0U+0U+0U+0U+0U+0U) << 8U); mibspiREG3->TGCTRL[8U] = (uint32)(length+0U+0U+0U+0U+0U+0U+0U) << 8U; mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(length+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); - while (i < (length-1U)) + while ( i < ( length - 1U ) ) { - mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ - | (uint16)((uint16)1U << 12U) /* chip select hold */ - | (uint16)((uint16)0U << 10U) /* enable WDELAY */ - | (uint16)((uint16)0U << 11U) /* lock transmission */ - | (uint16)((uint16)0U << 8U) /* data format */ + mibspiRAM3->tx[i].control = (uint16)((uint16)MIBSPI_CONTINUOUS_MODE << 13U) /* buffer mode */ + | (uint16)((uint16)MIBSPI_CHIP_SELECT_ACTIVE << 12U) /* chip select hold */ + | (uint16)((uint16)MIBSPI_NO_WDELAY << 10U) /* enable WDELAY */ + | (uint16)((uint16)MIBSPI_LOCK_TG << 11U) /* lock transmission */ + | (uint16)((uint16)MIBSPI_DATA_FORMAT_ZERO << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ i++; } - mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ - | (uint16)((uint16)0U << 12U) /* chip select hold */ - | (uint16)((uint16)0U << 10U) /* enable WDELAY */ - | (uint16)((uint16)0U << 8U) /* data format */ + mibspiRAM3->tx[i].control = (uint16)((uint16)MIBSPI_CONTINUOUS_MODE << 13U) /* buffer mode */ + | (uint16)((uint16)MIBSPI_CHIP_SELECT_DEACTIVE << 12U) /* chip select hold */ + | (uint16)((uint16)MIBSPI_NO_WDELAY << 10U) /* enable WDELAY */ + | (uint16)((uint16)MIBSPI_DATA_FORMAT_ZERO << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ i++; - return TRUE; + + return TRUE; } +