Index: firmware/App/Controllers/RTC.c =================================================================== diff -u -r6a5885338e9dea0c33085788de0df2f05864591f -r090b7303b8f6487879147191a3e5d6d783ed4af8 --- firmware/App/Controllers/RTC.c (.../RTC.c) (revision 6a5885338e9dea0c33085788de0df2f05864591f) +++ firmware/App/Controllers/RTC.c (.../RTC.c) (revision 090b7303b8f6487879147191a3e5d6d783ed4af8) @@ -20,16 +20,21 @@ #include "RTC.h" #include "mibspi.h" -// ********** private definitions ********** -#define RTC_REG_1_12_HOUR_MODE 0X0004 -#define RTC_REG_1_PORO 0X0008 -#define RTC_REG_1_CLK_STOPPED 0X0020 -#define RTC_REG_1_UNUSED 0X0040 -#define RTC_REG_1_EXT_CLK_MODE 0X0080 +// ********** Definitions ********** +#define RTC_REG_1_12_HOUR_MODE 0X0004 // 12-hour or 24-hour mode +#define RTC_REG_1_PORO 0X0008 // Power On Reset Override +#define RTC_REG_1_CLK_STOPPED 0X0020 // RTC source clock +#define RTC_REG_1_UNUSED 0X0040 // Unused +#define RTC_REG_1_EXT_CLK_MODE 0X0080 // RTC external or normal mode -#define RTC_REG_2_MASK 0X0000 +#define RTC_REG_2_MASK 0X00FF +#define RTC_REG_2_MSF 0X0080 // Minute or second interrupt +#define RTC_REG_2_CDTF 0X0008 // Countdown timer interrupt +#define RTC_REG_2_AF 0X0010 // Alarm interrupt +#define RTC_REG_2_TSF2 0X0020 // Timestamp interrupt -#define RTC_REG_3_MASK 0X0008 +#define RTC_REG_3_MASK 0X00FF +#define RTC_REG_3_BF 0x0008 // RTC registers indices #define RTC_REG_1_INDEX 1 @@ -60,32 +65,21 @@ #define MIBSPI_BUFFER_TRANS_BIT_SHIFT 8U #define RTC_RAM_PREP_BUFFER_LENGTH 3U -// This command puts RTC into read mode from -// address 0 -#define RTC_READ_FROM_REG0 0x00A0 -#define RTC_WRITE_TO_REG3 0x0023 -// For read or write operations in RAM, 1h and 1Ah -// must be sent that becomes 0x003A -#define RTC_PREP_RAM_READ_WRITE 0x003A +#define RTC_READ_FROM_REG0 0x00A0 // RTC read from address 0 +#define RTC_WRITE_TO_REG3 0x0023 +#define RTC_PREP_RAM_READ_WRITE 0x003A // RTC cmd prior to RAM ops +#define RTC_WRITE_TO_RAM 0x003C // RTC RAM write +#define RTC_READ_FROM_RAM 0x00BD // RTC RAM read -// For write operation in RAM, 1h and 1Ch will -// combined to 0x003C -#define RTC_WRITE_TO_RAM 0x003C +#define RTC_ACCURACY_TIMEOUT 1000 // ms +#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050 // ms -#define RTC_READ_FROM_RAM 0x00BD - -#define RTC_ACCURACY_TIMEOUT 1000 //ms -#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050 //ms - #define TIMER_COUNTER_TO_REQUEST_READ 18 #define MAX_ALLOWED_FAILED_RTC_TRANSFERS 2 - - #define GENERAL_NUM_OF_ITEMS_TO_READ 11 - typedef enum RTC_Self_Test_States { RTC_SELF_TEST_STATE_START = 0, @@ -144,24 +138,29 @@ static U32 RTCSelfTestTimer = 0; static U32 RTCPreviousSecond = 0; +static U32 RAMBufferLength = 0; + static U32 timeCounter = 1; static U32 numberOfFailedRTCTransfers = 0; static BOOL hasWriteToRTCRequested = FALSE; static BOOL hasReadFromRTCRequested = FALSE; -static BOOL hasWriteToRAMRequested = TRUE; +static BOOL hasWriteToRAMRequested = FALSE; static BOOL hasReadFromRAMRequested = FALSE; static U16 rxBuffer[MIBSPI_MAX_BUFFER_LENGTH + 1]; static U16 txBuffer[MIBSPI_MAX_BUFFER_LENGTH + 1]; +static U16 RAMBuffer[MIBSPI_MAX_BUFFER_LENGTH]; + // ********** Private functions prototype ********* static BOOL serviceRTC( U16* buffer ); static BOOL isRTCFunctional(); static U08 convertBCD2Decimal( U08 bcd ); static U08 convertDecimal2BCD( U08 decimal ); static U32 convertTime2Epoch(); static void updateReadTimestampStruct(); +static BOOL setMibSPIBufferLength( U16 length ); static RTC_SELF_TEST_STATE_T handleSelfTestStart(); static RTC_SELF_TEST_STATE_T handleSelfTestCheckCtrlRegs(); @@ -170,13 +169,11 @@ static RTC_EXEC_STATE_T handleExecIdleState(); static RTC_EXEC_STATE_T handleExecReadState(); -static RTC_EXEC_STATE_T handleExecPrepRAMState( U16 address ); -static RTC_EXEC_STATE_T handleExecWriteToRAMState( U08* data, U32 length ); -static RTC_EXEC_STATE_T handleExecReadFromRAMState( U32 length ); +static RTC_EXEC_STATE_T handleExecPrepRAMState(); +static RTC_EXEC_STATE_T handleExecWriteToRAMState(); +static RTC_EXEC_STATE_T handleExecReadFromRAMState(); static RTC_EXEC_STATE_T handleExecWriteState(); -static BOOL setMibSPIBufferLength( U16 length ); - // ********** Public functions ********** void initRTC() { @@ -241,22 +238,6 @@ void execRTC() { - // FOR DEBUGGING PURPOSES ONLY - U08 address; - U08 data[8]; - U32 length; - address = 12; - data[0] = 4; - data[1] = 5; - data[2] = 6; - data[3] = 71; - data[4] = 8; - data[5] = 9; - data[6] = 13; - data[7] = 115; - length = sizeof(data); - // FOR DEBUGGING PURPOSED ONLY - switch ( RTCExecState ) { case RTC_EXEC_STATE_WAIT_FOR_POST: @@ -265,6 +246,8 @@ RTCSelfTestResult == SELF_TEST_STATUS_PASSED ) { RTCExecState = RTC_EXEC_STATE_IDLE; + // Reset the RTC Service commands + RTCServiceState = RTC_SEND_COMMAND; } else if ( RTCSelfTestState == RTC_SELF_TEST_STATE_COMPLETE && RTCSelfTestResult == SELF_TEST_STATUS_FAILED ) @@ -280,17 +263,17 @@ case RTC_EXEC_STATE_PREP_RAM: - RTCExecState = handleExecPrepRAMState( address ); + RTCExecState = handleExecPrepRAMState(); break; case RTC_EXEC_STATE_WRITE_TO_RAM: - RTCExecState = handleExecWriteToRAMState( &data[0], length ); + RTCExecState = handleExecWriteToRAMState(); break; case RTC_EXEC_STATE_READ_FROM_RAM: - RTCExecState = handleExecReadFromRAMState( length ); + RTCExecState = handleExecReadFromRAMState(); break; case RTC_EXEC_STATE_WRITE: @@ -325,11 +308,70 @@ return timestamp; } -void writeToRAM( U16 address, U08* data, U32 length ) +void writeToRAM( U16 address, U16* data, U32 length ) { hasWriteToRAMRequested = TRUE; + RAMBufferLength = length; + + txBuffer[0] = RTC_PREP_RAM_READ_WRITE; + txBuffer[1] = ( address >> 8 ); + txBuffer[2] = ( address & 0x00FF ); + txBuffer[3] = RTC_WRITE_TO_RAM; + + U08 i; + for ( i = 0; i < RAMBufferLength; i++ ) + { + // The first 3 elements in txBuffer + // are filled + txBuffer[i + 4] = data[i]; + } } + +void readFromRAM( U16 address, U32 length ) +{ + hasReadFromRAMRequested = TRUE; + + RAMBufferLength = length; + + txBuffer[0] = RTC_PREP_RAM_READ_WRITE; + txBuffer[1] = ( address >> 8 ); + txBuffer[2] = ( address & 0x00FF ); + txBuffer[3] = RTC_READ_FROM_RAM; + + U08 i; + for ( i = 0; i < length; i++ ) + { + txBuffer[ i + 4 ] = 0; + } +} + +U16* getDataFromRAM( U16 address, U32 length ) +{ + U16* pointer; + // The read operation must have been finished + if ( ! hasReadFromRAMRequested ) + { + if ( length == RAMBufferLength ) + { + U08 i; + for ( i = 0; i < length; i++) + { + RAMBuffer[i] = rxBuffer[i + 1]; + } + + pointer = &RAMBuffer[0]; + } + else + { + pointer = 0; + } + + } + + return pointer; +} + // ********** Private functions ********* static BOOL serviceRTC( U16* buffer ) { @@ -389,8 +431,15 @@ U16 controlReg1 = rxBuffer[RTC_REG_1_INDEX]; U16 controlReg2 = rxBuffer[RTC_REG_2_INDEX]; - U16 controlReg3 = rxBuffer[RTC_REG_2_INDEX]; + U16 controlReg3 = rxBuffer[RTC_REG_3_INDEX]; + // Ignore the clear flags + controlReg2 = controlReg2 & ~RTC_REG_2_MSF; + controlReg2 = controlReg2 & ~RTC_REG_2_CDTF; + controlReg2 = controlReg2 & ~RTC_REG_2_AF; + controlReg2 = controlReg2 & ~RTC_REG_2_TSF2; + controlReg3 = controlReg3 & ~RTC_REG_3_BF; + if ( ! controlReg1 & RTC_REG_1_12_HOUR_MODE ) { // Set the alarm for 24 hour mode @@ -416,12 +465,12 @@ // Set the alarm for clock set on external mode hasTestPassed = FALSE; } - if ( ! controlReg2 & RTC_REG_2_MASK ) + if ( controlReg2 & RTC_REG_2_MASK ) { // Set the alarm for register 2 hasTestPassed = FALSE; } - if ( ! controlReg3 & RTC_REG_3_MASK ) + if ( controlReg3 & RTC_REG_3_MASK ) { // Set the alarm for register 3 hasTestPassed = FALSE; @@ -495,6 +544,75 @@ read_ts.years = decimalYears; } +static BOOL setMibSPIBufferLength( U16 length ) +{ + BOOL transferStatus = FALSE; + + // The max allowed buffer length in the + // MibSPI RAM is 127 + if ( length <= MIBSPI_MAX_BUFFER_LENGTH ) + { + U32 i = 0; + + mibspiREG3->TGCTRL[0U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + mibspiREG3->TGCTRL[1U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[1U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + mibspiREG3->TGCTRL[2U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[2U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + mibspiREG3->TGCTRL[3U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[3U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + mibspiREG3->TGCTRL[4U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[4U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + mibspiREG3->TGCTRL[5U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[5U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + mibspiREG3->TGCTRL[6U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[6U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + mibspiREG3->TGCTRL[7U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[7U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + mibspiREG3->TGCTRL[8U] = (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT; + + mibspiREG3->LTGPEND = ( mibspiREG3->LTGPEND & 0xFFFF00FFU ) | + (uint32)( ((uint32)length - 1U) << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + + while ( i < ( length - 1U ) ) + { + mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT ) /* buffer mode */ + | (uint16)( (uint16)MIBSPI_CHIP_SELECT_ACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT ) /* chip select hold */ + | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT ) /* enable WDELAY */ + | (uint16)( (uint16)MIBSPI_LOCK_TG << MIBSPI_LOCK_TRANS_BIT_SHIFT ) /* lock transmission */ + | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ + i++; + } + mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT ) /* buffer mode */ + | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT ) /* chip select hold */ + | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT ) /* enable WDELAY */ + | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ + + + i++; + + transferStatus = TRUE; + } + else + { + transferStatus = FALSE; + } + + return transferStatus; +} + static RTC_EXEC_STATE_T handleExecWriteState() { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_WRITE; @@ -542,16 +660,21 @@ // Reset the RTC Service commands RTCServiceState = RTC_SEND_COMMAND; - setMibSPIBufferLength(GENERAL_NUM_OF_ITEMS_TO_READ); + if ( setMibSPIBufferLength(GENERAL_NUM_OF_ITEMS_TO_READ) ) + { + txBuffer[0] = RTC_READ_FROM_REG0; - txBuffer[0] = RTC_READ_FROM_REG0; - - U08 i; - for (i=1; i< GENERAL_NUM_OF_ITEMS_TO_READ; i++) + U08 i; + for (i=1; i< GENERAL_NUM_OF_ITEMS_TO_READ; i++) + { + txBuffer[i] = 0x0000; + } + result = RTC_EXEC_STATE_READ; + } + else { - txBuffer[i] = 0x0000; + result = RTC_EXEC_STATE_FAULT; } - result = RTC_EXEC_STATE_READ; } else { @@ -561,114 +684,96 @@ return result; } -static RTC_EXEC_STATE_T handleExecPrepRAMState( U16 address ) +static RTC_EXEC_STATE_T handleExecPrepRAMState() { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_PREP_RAM; - txBuffer[0] = RTC_PREP_RAM_READ_WRITE; - txBuffer[1] = ( address >> 8 ); - txBuffer[2] = ( address & 0x00FF ); - - setMibSPIBufferLength( RTC_RAM_PREP_BUFFER_LENGTH ); - - BOOL isStatusOk = serviceRTC( &txBuffer[0] ); - - if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) + // The transfer operations must be ok before moving on + if ( setMibSPIBufferLength( RTC_RAM_PREP_BUFFER_LENGTH ) ) { - if ( hasWriteToRAMRequested ) + BOOL isStatusOk = serviceRTC( &txBuffer[0] ); + + if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) { - result = RTC_EXEC_STATE_WRITE_TO_RAM; + if ( hasWriteToRAMRequested ) + { + result = RTC_EXEC_STATE_WRITE_TO_RAM; + } + else if ( hasReadFromRAMRequested ) + { + result = RTC_EXEC_STATE_READ_FROM_RAM; + } + + // Reset the RTC Service commands + RTCServiceState = RTC_SEND_COMMAND; } - else if ( hasReadFromRAMRequested ) + else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) { - result = RTC_EXEC_STATE_READ_FROM_RAM; + result = RTC_EXEC_STATE_FAULT; } - - // Reset the RTC Service commands - RTCServiceState = RTC_SEND_COMMAND; } - else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) + else { result = RTC_EXEC_STATE_FAULT; } return result; } -static RTC_EXEC_STATE_T handleExecWriteToRAMState( U08* data, U32 length ) +static RTC_EXEC_STATE_T handleExecWriteToRAMState() { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_WRITE_TO_RAM; - // Set the buffer once - if ( hasWriteToRAMRequested ) + if ( setMibSPIBufferLength( RAMBufferLength + 1 ) ) { - U08 i; + BOOL isStatusOk = serviceRTC( &txBuffer[3] ); - txBuffer[0] = RTC_WRITE_TO_RAM; + if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) + { + result = RTC_EXEC_STATE_IDLE; - for ( i = 0; i < length; i++ ) + // Reset the RTC Service commands + RTCServiceState = RTC_SEND_COMMAND; + + hasWriteToRAMRequested = FALSE; + } + else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) { - // The zeroth element of txBuffer - // is the RAM command - txBuffer[i + 1] = data[i]; + result = RTC_EXEC_STATE_FAULT; } - setMibSPIBufferLength( length + 1 ); - - // Set the buffer once and done - hasWriteToRAMRequested = FALSE; } - - BOOL isStatusOk = serviceRTC( &txBuffer[0] ); - - if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) + else { - result = RTC_EXEC_STATE_IDLE; - - // Reset the RTC Service commands - RTCServiceState = RTC_SEND_COMMAND; - } - else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) - { result = RTC_EXEC_STATE_FAULT; } return result; } -static RTC_EXEC_STATE_T handleExecReadFromRAMState( U32 length ) +static RTC_EXEC_STATE_T handleExecReadFromRAMState() { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_READ_FROM_RAM; - // Set the buffer once - if ( hasReadFromRAMRequested ) + if ( setMibSPIBufferLength( RAMBufferLength + 1 ) ) { - U08 i; + BOOL isStatusOk = serviceRTC( &txBuffer[3] ); - txBuffer[0] = RTC_READ_FROM_RAM; - - for ( i = 0; i < length; i++ ) + if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) { - txBuffer[i+1] = 0; - } + result = RTC_EXEC_STATE_IDLE; - setMibSPIBufferLength( length + 1 ); + hasReadFromRAMRequested = FALSE; - // Set the buffer to the maximum since - // we don't know how many buffer are in a - hasReadFromRAMRequested = FALSE; + // Reset the RTC Service commands + RTCServiceState = RTC_SEND_COMMAND; + } + else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) + { + result = RTC_EXEC_STATE_FAULT; + } } - - BOOL isStatusOk = serviceRTC( &txBuffer[0] ); - - if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) + else { - result = RTC_EXEC_STATE_IDLE; - - // Reset the RTC Service commands - RTCServiceState = RTC_SEND_COMMAND; - } - else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) - { result = RTC_EXEC_STATE_FAULT; } @@ -700,6 +805,9 @@ hasReadFromRTCRequested = FALSE; } result = RTC_EXEC_STATE_IDLE; + + // Reset the RTC Service commands + RTCServiceState = RTC_SEND_COMMAND; } } else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) @@ -715,18 +823,27 @@ { RTC_SELF_TEST_STATE_T result = RTC_SELF_TEST_STATE_START; - setMibSPIBufferLength(GENERAL_NUM_OF_ITEMS_TO_READ); + if ( setMibSPIBufferLength( GENERAL_NUM_OF_ITEMS_TO_READ ) ) + { + // Reset the states + RTCServiceState = RTC_SEND_COMMAND; - txBuffer[0] = RTC_READ_FROM_REG0; + txBuffer[0] = RTC_READ_FROM_REG0; - U08 i; - for (i=1; i< GENERAL_NUM_OF_ITEMS_TO_READ; i++) + U08 i; + for (i=1; i< GENERAL_NUM_OF_ITEMS_TO_READ; i++) + { + txBuffer[i] = 0x0000; + } + + result = RTC_SELF_TEST_STATE_CHECK_CTRL_REGS; + } + else { - txBuffer[i] = 0x0000; + RTCSelfTestResult = SELF_TEST_STATUS_FAILED; + result = RTC_SELF_TEST_STATE_COMPLETE; } - result = RTC_SELF_TEST_STATE_CHECK_CTRL_REGS; - return result; } @@ -806,73 +923,6 @@ return result; } -static BOOL setMibSPIBufferLength( U16 length ) -{ - BOOL transferStatus = FALSE; - // The max allowed buffer length in the - // MibSPI RAM is 127 - if ( length <= MIBSPI_MAX_BUFFER_LENGTH ) - { - U32 i = 0; - mibspiREG3->TGCTRL[0U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[1U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[1U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - - mibspiREG3->TGCTRL[2U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[2U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - - mibspiREG3->TGCTRL[3U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[3U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - - mibspiREG3->TGCTRL[4U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[4U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - - mibspiREG3->TGCTRL[5U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[5U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - - mibspiREG3->TGCTRL[6U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[6U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - - mibspiREG3->TGCTRL[7U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[7U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - - mibspiREG3->TGCTRL[8U] = (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT; - - mibspiREG3->LTGPEND = ( mibspiREG3->LTGPEND & 0xFFFF00FFU ) | - (uint32)( ((uint32)length - 1U) << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - - while ( i < ( length - 1U ) ) - { - mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT ) /* buffer mode */ - | (uint16)( (uint16)MIBSPI_CHIP_SELECT_ACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT ) /* chip select hold */ - | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT ) /* enable WDELAY */ - | (uint16)( (uint16)MIBSPI_LOCK_TG << MIBSPI_LOCK_TRANS_BIT_SHIFT ) /* lock transmission */ - | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT ) /* data format */ - /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ - i++; - } - mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT ) /* buffer mode */ - | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT ) /* chip select hold */ - | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT ) /* enable WDELAY */ - | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT ) /* data format */ - /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ - - - i++; - - transferStatus = TRUE; - } - else - { - transferStatus = FALSE; - } - - return transferStatus; -} - -