Index: firmware/App/Controllers/RTC.c =================================================================== diff -u -r72311accbea39c95b0ee1efbd28dfbcf9fea74d1 -r6a5885338e9dea0c33085788de0df2f05864591f --- firmware/App/Controllers/RTC.c (.../RTC.c) (revision 72311accbea39c95b0ee1efbd28dfbcf9fea74d1) +++ firmware/App/Controllers/RTC.c (.../RTC.c) (revision 6a5885338e9dea0c33085788de0df2f05864591f) @@ -44,15 +44,22 @@ #define RTC_YEARS_INDEX 10 // *************** MibSPI values ************* // -#define MIBSPI_MAX_BUFFER_LENGTH 127U -#define MIBSPI_PREP_RAM_BUFFER_LENGTH 3U -#define MIBSPI_CONTINUOUS_MODE 4U -#define MIBSPI_CHIP_SELECT_ACTIVE 1U -#define MIBSPI_CHIP_SELECT_DEACTIVE 0U -#define MIBSPI_NO_WDELAY 0U -#define MIBSPI_LOCK_TG 0U -#define MIBSPI_DATA_FORMAT_ZERO 0U +#define MIBSPI_MAX_BUFFER_LENGTH 127U +#define MIBSPI_CONTINUOUS_MODE 4U +#define MIBSPI_CHIP_SELECT_ACTIVE 1U +#define MIBSPI_CHIP_SELECT_DEACTIVE 0U +#define MIBSPI_NO_WDELAY 0U +#define MIBSPI_LOCK_TG 0U +#define MIBSPI_DATA_FORMAT_ZERO 0U +#define MIBSPI_BUFFER_MODE_BIT_SHIFT 13U +#define MIBSPI_CHIP_SELECT_BIT_SHIFT 12U +#define MIBSPI_NO_WDELAY_BIT_SHIT 10U +#define MIBSPI_LOCK_TRANS_BIT_SHIFT 11U +#define MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT 8U +#define MIBSPI_BUFFER_TRANS_BIT_SHIFT 8U +#define RTC_RAM_PREP_BUFFER_LENGTH 3U + // This command puts RTC into read mode from // address 0 #define RTC_READ_FROM_REG0 0x00A0 @@ -76,9 +83,9 @@ #define GENERAL_NUM_OF_ITEMS_TO_READ 11 -#define MAXIMUM_NUM_OF_BUFFER 129 + typedef enum RTC_Self_Test_States { RTC_SELF_TEST_STATE_START = 0, @@ -92,7 +99,7 @@ { RTC_SEND_COMMAND = 0, RTC_WAIT_FOR_TRANSFER_AND_READ, - RTC_READ_COMPLETE + RTC_SERVICE_COMPLETE } RTC_GET_DATA_STATE_T; typedef enum RTC_Exec_State @@ -141,12 +148,12 @@ static U32 numberOfFailedRTCTransfers = 0; static BOOL hasWriteToRTCRequested = FALSE; -static BOOL hasReadFromRTCRequested = TRUE; -static BOOL hasWriteToRAMRequested = FALSE; -static BOOL hasReadFromRAMRequested = TRUE; +static BOOL hasReadFromRTCRequested = FALSE; +static BOOL hasWriteToRAMRequested = TRUE; +static BOOL hasReadFromRAMRequested = FALSE; -static U16 rxBuffer[MAXIMUM_NUM_OF_BUFFER]; -static U16 txBuffer[MAXIMUM_NUM_OF_BUFFER]; +static U16 rxBuffer[MIBSPI_MAX_BUFFER_LENGTH + 1]; +static U16 txBuffer[MIBSPI_MAX_BUFFER_LENGTH + 1]; // ********** Private functions prototype ********* static BOOL serviceRTC( U16* buffer ); @@ -163,12 +170,12 @@ static RTC_EXEC_STATE_T handleExecIdleState(); static RTC_EXEC_STATE_T handleExecReadState(); -static RTC_EXEC_STATE_T handleExecPrepRAMState( U08* address ); +static RTC_EXEC_STATE_T handleExecPrepRAMState( U16 address ); static RTC_EXEC_STATE_T handleExecWriteToRAMState( U08* data, U32 length ); static RTC_EXEC_STATE_T handleExecReadFromRAMState( U32 length ); static RTC_EXEC_STATE_T handleExecWriteState(); -static BOOL setMibSPIBufferLength(U16 length); +static BOOL setMibSPIBufferLength( U16 length ); // ********** Public functions ********** void initRTC() @@ -273,7 +280,7 @@ case RTC_EXEC_STATE_PREP_RAM: - RTCExecState = handleExecPrepRAMState( &address ); + RTCExecState = handleExecPrepRAMState( address ); break; case RTC_EXEC_STATE_WRITE_TO_RAM: @@ -311,14 +318,14 @@ { hasReadFromRTCRequested = TRUE; - U32 timestamp = convertTime2Epoch() + U32 timestamp = convertTime2Epoch(); hasReadFromRTCRequested = FALSE; return timestamp; } -void writeToRAM( U08* address, U08* data, U32 length ) +void writeToRAM( U16 address, U08* data, U32 length ) { hasWriteToRAMRequested = TRUE; @@ -345,13 +352,13 @@ { mibspiGetData(mibspiREG3, 0, rxBuffer); - RTCServiceState = RTC_READ_COMPLETE; + RTCServiceState = RTC_SERVICE_COMPLETE; result = TRUE; } else if ( numberOfFailedRTCTransfers >= MAX_ALLOWED_FAILED_RTC_TRANSFERS ) { - RTCServiceState = RTC_READ_COMPLETE; + RTCServiceState = RTC_SERVICE_COMPLETE; } else { @@ -363,7 +370,7 @@ } break; - case RTC_READ_COMPLETE: + case RTC_SERVICE_COMPLETE: // Done with reading and transfer do nothing break; @@ -501,7 +508,7 @@ serviceRTC( ×tamp[0] ); - if ( RTCServiceState == RTC_READ_COMPLETE ) + if ( RTCServiceState == RTC_SERVICE_COMPLETE ) { // Reset the counter timeCounter = 1; @@ -520,10 +527,14 @@ { result = RTC_EXEC_STATE_WRITE; } - else if ( hasWriteToRAMRequested || hasReadFromRAMRequested ) + else if ( hasWriteToRAMRequested ) { result = RTC_EXEC_STATE_PREP_RAM; } + else if ( hasReadFromRAMRequested ) + { + result = RTC_EXEC_STATE_PREP_RAM; + } // If write to RTC has been requested, we don't have to read // write must be finished first else if ( timeCounter == TIMER_COUNTER_TO_REQUEST_READ || hasReadFromRTCRequested ) @@ -550,19 +561,19 @@ return result; } -static RTC_EXEC_STATE_T handleExecPrepRAMState( U08* address ) +static RTC_EXEC_STATE_T handleExecPrepRAMState( U16 address ) { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_PREP_RAM; txBuffer[0] = RTC_PREP_RAM_READ_WRITE; - txBuffer[1] = (U16)( *address / 10 ); - txBuffer[2] = (U16)( *address % 10 ); + txBuffer[1] = ( address >> 8 ); + txBuffer[2] = ( address & 0x00FF ); - setMibSPIBufferLength( MIBSPI_PREP_RAM_BUFFER_LENGTH ); + setMibSPIBufferLength( RTC_RAM_PREP_BUFFER_LENGTH ); BOOL isStatusOk = serviceRTC( &txBuffer[0] ); - if ( RTCServiceState == RTC_READ_COMPLETE && isStatusOk ) + if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) { if ( hasWriteToRAMRequested ) { @@ -576,7 +587,7 @@ // Reset the RTC Service commands RTCServiceState = RTC_SEND_COMMAND; } - else if ( RTCServiceState == RTC_READ_COMPLETE && ! isStatusOk ) + else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) { result = RTC_EXEC_STATE_FAULT; } @@ -609,11 +620,14 @@ BOOL isStatusOk = serviceRTC( &txBuffer[0] ); - if ( RTCServiceState == RTC_READ_COMPLETE && isStatusOk ) + if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) { result = RTC_EXEC_STATE_IDLE; + + // Reset the RTC Service commands + RTCServiceState = RTC_SEND_COMMAND; } - else if ( RTCServiceState == RTC_READ_COMPLETE && ! isStatusOk ) + else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) { result = RTC_EXEC_STATE_FAULT; } @@ -646,11 +660,14 @@ BOOL isStatusOk = serviceRTC( &txBuffer[0] ); - if ( RTCServiceState == RTC_READ_COMPLETE && isStatusOk ) + if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) { result = RTC_EXEC_STATE_IDLE; + + // Reset the RTC Service commands + RTCServiceState = RTC_SEND_COMMAND; } - else if ( RTCServiceState == RTC_READ_COMPLETE && ! isStatusOk ) + else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) { result = RTC_EXEC_STATE_FAULT; } @@ -664,7 +681,7 @@ BOOL isStatusOk = serviceRTC( &txBuffer[0] ); - if ( RTCServiceState == RTC_READ_COMPLETE && isStatusOk ) + if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) { if ( isRTCFunctional() ) { @@ -685,7 +702,7 @@ result = RTC_EXEC_STATE_IDLE; } } - else if ( RTCServiceState == RTC_READ_COMPLETE && ! isStatusOk ) + else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk ) { result = RTC_EXEC_STATE_FAULT; } @@ -719,7 +736,7 @@ serviceRTC( &txBuffer[0] ); - if ( RTCServiceState == RTC_READ_COMPLETE ) + if ( RTCServiceState == RTC_SERVICE_COMPLETE ) { // Reset the states RTCServiceState = RTC_SEND_COMMAND; @@ -744,7 +761,7 @@ serviceRTC( &txBuffer[0] ); - if ( RTCServiceState == RTC_READ_COMPLETE ) + if ( RTCServiceState == RTC_SERVICE_COMPLETE ) { // Reset the states RTCServiceState = RTC_SEND_COMMAND; @@ -791,61 +808,71 @@ static BOOL setMibSPIBufferLength( U16 length ) { - // TODO: Check for the length of the buffer - U32 i = 0; + BOOL transferStatus = FALSE; - mibspiREG3->TGCTRL[0U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); + // The max allowed buffer length in the + // MibSPI RAM is 127 + if ( length <= MIBSPI_MAX_BUFFER_LENGTH ) + { + U32 i = 0; - mibspiREG3->TGCTRL[1U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); - mibspiREG3->TGCTRL[1U] |= (uint32)((uint32)length << 8U); + mibspiREG3->TGCTRL[0U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[2U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); - mibspiREG3->TGCTRL[2U] |= (uint32)((uint32)(length+0U) << 8U); + mibspiREG3->TGCTRL[1U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[1U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[3U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); - mibspiREG3->TGCTRL[3U] |= (uint32)((uint32)(length+0U+0U) << 8U); + mibspiREG3->TGCTRL[2U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[2U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[4U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); - mibspiREG3->TGCTRL[4U] |= (uint32)((uint32)(length+0U+0U+0U) << 8U); + mibspiREG3->TGCTRL[3U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[3U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[5U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); - mibspiREG3->TGCTRL[5U] |= (uint32)((uint32)(length+0U+0U+0U+0U) << 8U); + mibspiREG3->TGCTRL[4U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[4U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[6U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); - mibspiREG3->TGCTRL[6U] |= (uint32)((uint32)(length+0U+0U+0U+0U+0U) << 8U); + mibspiREG3->TGCTRL[5U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[5U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[7U] &= ~(uint32)((uint32)MIBSPI_MAX_BUFFER_LENGTH << 8U); - mibspiREG3->TGCTRL[7U] |= (uint32)((uint32)(length+0U+0U+0U+0U+0U+0U) << 8U); + mibspiREG3->TGCTRL[6U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[6U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[8U] = (uint32)(length+0U+0U+0U+0U+0U+0U+0U) << 8U; + mibspiREG3->TGCTRL[7U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[7U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | - (uint32)(((uint32)(length+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); + mibspiREG3->TGCTRL[8U] = (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT; - while ( i < ( length - 1U ) ) - { - mibspiRAM3->tx[i].control = (uint16)((uint16)MIBSPI_CONTINUOUS_MODE << 13U) /* buffer mode */ - | (uint16)((uint16)MIBSPI_CHIP_SELECT_ACTIVE << 12U) /* chip select hold */ - | (uint16)((uint16)MIBSPI_NO_WDELAY << 10U) /* enable WDELAY */ - | (uint16)((uint16)MIBSPI_LOCK_TG << 11U) /* lock transmission */ - | (uint16)((uint16)MIBSPI_DATA_FORMAT_ZERO << 8U) /* data format */ - /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ - i++; - } - mibspiRAM3->tx[i].control = (uint16)((uint16)MIBSPI_CONTINUOUS_MODE << 13U) /* buffer mode */ - | (uint16)((uint16)MIBSPI_CHIP_SELECT_DEACTIVE << 12U) /* chip select hold */ - | (uint16)((uint16)MIBSPI_NO_WDELAY << 10U) /* enable WDELAY */ - | (uint16)((uint16)MIBSPI_DATA_FORMAT_ZERO << 8U) /* data format */ - /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + mibspiREG3->LTGPEND = ( mibspiREG3->LTGPEND & 0xFFFF00FFU ) | + (uint32)( ((uint32)length - 1U) << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + while ( i < ( length - 1U ) ) + { + mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT ) /* buffer mode */ + | (uint16)( (uint16)MIBSPI_CHIP_SELECT_ACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT ) /* chip select hold */ + | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT ) /* enable WDELAY */ + | (uint16)( (uint16)MIBSPI_LOCK_TG << MIBSPI_LOCK_TRANS_BIT_SHIFT ) /* lock transmission */ + | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ + i++; + } + mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT ) /* buffer mode */ + | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT ) /* chip select hold */ + | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT ) /* enable WDELAY */ + | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT ) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ - i++; + i++; + transferStatus = TRUE; + } + else + { + transferStatus = FALSE; + } - return TRUE; + return transferStatus; }