Index: firmware/App/Controllers/RTC.c
===================================================================
diff -u -rfdeda091d43e144eb63f62189c25b916b2eb5c57 -r23ebecb91f2a05526f691b611d6c1862426f171d
--- firmware/App/Controllers/RTC.c	(.../RTC.c)	(revision fdeda091d43e144eb63f62189c25b916b2eb5c57)
+++ firmware/App/Controllers/RTC.c	(.../RTC.c)	(revision 23ebecb91f2a05526f691b611d6c1862426f171d)
@@ -49,6 +49,12 @@
 #define RTC_MONTHS_INDEX   9
 #define RTC_YEARS_INDEX    10
 
+#define BUFFER_INDEX_0 0U
+#define BUFFER_INDEX_1 1U
+#define BUFFER_INDEX_2 2U
+#define BUFFER_INDEX_3 3U
+#define BUFFER_INDEX_4 4U
+
 // *************** MibSPI values ************* //
 
 #define MIBSPI_MAX_BUFFER_LENGTH          127U
@@ -76,19 +82,16 @@
 #define RTC_WRITE_TO_RAM                  0x003C  // RTC RAM write
 #define RTC_READ_FROM_RAM                 0x00BD  // RTC RAM read
 
-#define BUFFER_INDEX_0 0U
-#define BUFFER_INDEX_1 1U
-#define BUFFER_INDEX_2 2U
-#define BUFFER_INDEX_3 3U
-#define BUFFER_INDEX_4 4U
-
 #define RTC_ACCURACY_TIMEOUT              1000 // ms
 #define RTC_ACCURACY_TIMEOUT_TOLERANCE    1050 // ms
 
 #define TIMER_COUNTER_TO_REQUEST_READ     18
 
-#define MAX_ALLOWED_FAILED_RTC_TRANSFERS  2
+#define MAX_ALLOWED_FAILED_RTC_TRANSFERS  3
 
+#define MAX_ALLOWED_RTC_RAM_BYTES         100U
+#define MAX_ALLOWED_RTC_RAM_ADDRESS       512U
+
 typedef enum RTC_Self_Test_States
 {
     RTC_SELF_TEST_STATE_START = 0,
@@ -136,6 +139,7 @@
 static RTC_GET_DATA_STATE_T  RTCServiceState   = RTC_SEND_COMMAND;
 static RTC_EXEC_STATE_T      RTCExecState      = RTC_EXEC_STATE_WAIT_FOR_POST;
 static SELF_TEST_STATUS_T    RTCSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS;
+static RTC_RAM_STATUS_T      RTCRAMStatus      = RTC_RAM_READY;
 static RTC_TIMESTAMP_T       RTCTimestampStruct;
 
 static U32 RTCSelfTestTimer  = 0;
@@ -144,7 +148,7 @@
 static U32 lastEpochTime     = 0;
 
 static U32 timeCounter = 1;
-static U32 numberOfFailedRTCTransfers = 0;
+static U32 numberOfFailedRTCTransfers = 1;
 
 static BOOL hasWriteToRTCRequested    = FALSE;
 static BOOL hasWriteToRAMRequested    = FALSE;
@@ -300,69 +304,120 @@
     return lastEpochTime;
 }
 
-void writeToRAM( U16 address, U16* data, U32 length )
+RTC_RAM_STATUS_T writeToRAM( U16 address, U16* data, U32 length )
 {
-    hasWriteToRAMRequested = TRUE;
+    RTC_RAM_STATUS_T status = RTCRAMStatus;
 
-    RAMBufferLength = length;
+    if ( status == RTC_RAM_READY )
+    {
+        if ( address > MAX_ALLOWED_RTC_RAM_ADDRESS )
+        {
+            status = RTC_RAM_ILLEGAL_ADDRESS;
+        }
+        else if ( length > MAX_ALLOWED_RTC_RAM_BYTES )
+        {
+            status = RTC_RAM_BYTES_EXCEEDED;
+        }
+        else
+        {
+            RTCRAMStatus = status = RTC_RAM_IN_PROGRESS;
 
-    txBuffer[ BUFFER_INDEX_0 ] = RTC_PREP_RAM_READ_WRITE;
-    txBuffer[ BUFFER_INDEX_1 ] = ( address >> 8 );
-    txBuffer[ BUFFER_INDEX_2 ] = ( address & 0x00FF );
-    txBuffer[ BUFFER_INDEX_3 ] = RTC_WRITE_TO_RAM;
+            hasWriteToRAMRequested = TRUE;
 
-    U08 i;
-    for ( i = 0; i < RAMBufferLength; i++ )
+            RAMBufferLength = length;
+
+            txBuffer[ BUFFER_INDEX_0 ] = RTC_PREP_RAM_READ_WRITE;
+            txBuffer[ BUFFER_INDEX_1 ] = ( address >> 8 );
+            txBuffer[ BUFFER_INDEX_2 ] = ( address & 0x00FF );
+            txBuffer[ BUFFER_INDEX_3 ] = RTC_WRITE_TO_RAM;
+
+            U08 i;
+            for ( i = 0; i < RAMBufferLength; i++ )
+            {
+                // The first 3 elements in txBuffer are filled
+                txBuffer[ i + BUFFER_INDEX_4 ] = data[ i ];
+            }
+        }
+    }
+    else if ( status == RTC_RAM_IN_PROGRESS )
     {
-        // The first 3 elements in txBuffer
-        // are filled
-        txBuffer[ i + BUFFER_INDEX_4 ] = data[ i ];
+        U16 currentAddress = 0;
+        currentAddress = ( ~currentAddress & txBuffer[ BUFFER_INDEX_1 ] ) << 8;
+        currentAddress = ~currentAddress & txBuffer[ BUFFER_INDEX_2 ];
+
+        if ( currentAddress == address )
+        {
+            status = RTC_RAM_IN_PROGRESS;
+        }
+        else
+        {
+            status = RTC_RAM_BUSY;
+        }
     }
+
+    return status;
 }
 
-void readFromRAM( U16 address, U32 length )
+RTC_RAM_STATUS_T readFromRAM( U16 address, U32 length )
 {
-    hasReadFromRAMRequested = TRUE;
+    RTC_RAM_STATUS_T status = RTCRAMStatus;
 
-    RAMBufferLength = length;
+    if ( status == RTC_RAM_READY )
+    {
+       if ( address > MAX_ALLOWED_RTC_RAM_ADDRESS )
+       {
+           status = RTC_RAM_ILLEGAL_ADDRESS;
+       }
+       else if ( length > MAX_ALLOWED_RTC_RAM_BYTES )
+       {
+           status = RTC_RAM_BYTES_EXCEEDED;
+       }
+       else
+       {
+           status = RTCRAMStatus = RTC_RAM_BUSY;
 
-    txBuffer[ BUFFER_INDEX_0 ] = RTC_PREP_RAM_READ_WRITE;
-    txBuffer[ BUFFER_INDEX_1 ] = ( address >> 8 );
-    txBuffer[ BUFFER_INDEX_2 ] = ( address & 0x00FF );
-    txBuffer[ BUFFER_INDEX_3 ] = RTC_READ_FROM_RAM;
+           hasReadFromRAMRequested = TRUE;
 
-    U08 i;
-    for ( i = 0; i < length; i++ )
+           RAMBufferLength = length;
+
+           txBuffer[ BUFFER_INDEX_0 ] = RTC_PREP_RAM_READ_WRITE;
+           txBuffer[ BUFFER_INDEX_1 ] = ( address >> 8 );
+           txBuffer[ BUFFER_INDEX_2 ] = ( address & 0x00FF );
+           txBuffer[ BUFFER_INDEX_3 ] = RTC_READ_FROM_RAM;
+
+           U08 i;
+           for ( i = 0; i < length; i++ )
+           {
+               txBuffer[ i + BUFFER_INDEX_4 ] = 0x0000;
+           }
+       }
+    }
+    else if ( status == RTC_RAM_COMPLETE )
     {
-        txBuffer[ i + BUFFER_INDEX_4 ] = 0;
+        RTCRAMStatus = RTC_RAM_READY;
     }
+
+    return status;
 }
 
-U16* getDataFromRAM( U16 address, U32 length )
+RTC_RAM_STATUS_T getRTCRAMStatus()
 {
-    U16* pointer;
-
-    // The read operation must have been finished
-    if ( !hasReadFromRAMRequested )
+    if ( RTCRAMStatus == RTC_RAM_COMPLETE )
     {
-        if ( length == RAMBufferLength )
-        {
-            U08 i;
+        RTCRAMStatus = RTC_RAM_READY;
+    }
 
-            for ( i = 0; i < length; i++ )
-            {
-                RAMBuffer[ i ] = rxBuffer[ i + 1 ];
-            }
+    return RTCRAMStatus;
+}
 
-            pointer = &RAMBuffer[ 0 ];
-        }
-        else
-        {
-            pointer = 0;
-        }
-    }
+void getDataFromRAM( U16* externalBuffer, U32 length )
+{
+    U08 i;
 
-    return pointer;
+    for ( i = 0; i < length; i++ )
+    {
+        externalBuffer[ i ] = RAMBuffer[ i + 1 ];
+    }
 }
 
 // ********** Private functions *********
@@ -387,6 +442,8 @@
 
                 mibspiTransfer( mibspiREG3, MIBSPI_GROUP_ZEREO );
 
+                numberOfFailedRTCTransfers = 1;
+
                 RTCServiceState = RTC_WAIT_FOR_TRANSFER_AND_READ;
             }
             else
@@ -743,11 +800,17 @@
     {
         result = RTC_EXEC_STATE_IDLE;
 
+        RTCRAMStatus = RTC_RAM_COMPLETE;
+
         hasWriteToRAMRequested = FALSE;
     }
     else if ( RTCServiceState == RTC_SERVICE_COMPLETE && !isStatusOk )
     {
         result = RTC_EXEC_STATE_FAULT;
+
+        RTCRAMStatus = RTC_RAM_FAILED;
+
+        hasWriteToRAMRequested = FALSE;
     }
 
     return result;
@@ -772,6 +835,7 @@
 
     return result;
 }
+
 static RTC_EXEC_STATE_T handleExecReadState()
 {
     RTC_EXEC_STATE_T result = RTC_EXEC_STATE_READ;
@@ -788,7 +852,7 @@
 
             timeCounter = 1;
 
-             result = RTC_EXEC_STATE_IDLE;
+            result = RTC_EXEC_STATE_IDLE;
         }
     }
     else if ( RTCServiceState == RTC_SERVICE_COMPLETE && !isStatusOk )