Index: firmware/App/Modes/ModeInitPOST.c
===================================================================
diff -u -r626d9aabbab7db936cc0b2df47417db3692305d1 -r6623684ddacf5beebd15bce8a1dbd06a442fb38e
--- firmware/App/Modes/ModeInitPOST.c	(.../ModeInitPOST.c)	(revision 626d9aabbab7db936cc0b2df47417db3692305d1)
+++ firmware/App/Modes/ModeInitPOST.c	(.../ModeInitPOST.c)	(revision 6623684ddacf5beebd15bce8a1dbd06a442fb38e)
@@ -15,6 +15,7 @@
 *
 ***************************************************************************/
 
+#include "reg_crc.h"       // Used to hold reset reason code at startup before bits get cleared
 #include "reg_system.h"    // Used to access exception status registers for reset reason code at startup
 
 #include "Accel.h"
@@ -53,9 +54,6 @@
 /// Maximum wait time for UI to send its final POST result.
 #define POST_UI_MAX_WAIT_TIME       ( 2 * MS_PER_SECOND / TASK_GENERAL_INTERVAL )
 
-/// Reserved (manually) memory for saved processor reset reason code.
-#define RESET_REASON_CODE_SAVE      (*(volatile uint32 *)0x0802FFFCU)
-
 // ********** private data **********
 
 static HD_POST_STATE_T postState;                               ///< Current state of initialize and POST mode.
@@ -436,7 +434,7 @@
     // when the event data can be sent
     if ( ++startPOSTDelayCounter > START_POST_DELAY_COUNT )
     {
-        U32 resetReason = RESET_REASON_CODE_SAVE | systemREG1->SYSESR;
+        U32 resetReason = systemREG1->SYSESR | crcREG->PSA_SIGREGL1;                         // power-on reset bit preserved in an unused CRC register
 
         systemREG1->SYSESR = systemREG1->SYSESR;                                             // clear reset bit(s) after logging event so subsequent resets can be properly identified as not being power-on resets.