Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r242ad36c7a1ec4ee5012c9f009899f9e0bd87628 -r402885eda2ed755a079c854d1228ac5f76cbec7c
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 242ad36c7a1ec4ee5012c9f009899f9e0bd87628)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 402885eda2ed755a079c854d1228ac5f76cbec7c)
@@ -7,8 +7,8 @@
 *
 * @file    FPGA.c
 *
-* @author  (last)      Dara Navaei
-* @date    (last)      20-Jun-2022
+* @author  (last)      Dong Nguyen
+* @date    (last)      27-Sep-2022
 *
 * @author  (original)  Dara Navaei
 * @date    (original)  05-Nov-2019
@@ -245,8 +245,10 @@
     U16 bloodLeakRxFIFOCount;                   ///< Reg 448.  Blood leak receive FIFO count.
     U08 bloodLeakRxFIFODataOut;                 ///< Reg 450.  Blood leak receive FIFO data out.
     U08 dummyByte;                              ///< Reg 451.  Dummy byte to meet the even of the data.
+    U16 fpgaCompatibilityRev;                   ///< Reg 452.  Compatibility revisions
     U08 bloodLeakSelfTestErrorCounter;          ///< Reg 452.  Blood leak self test error counter.
     U08 bloodLeakZeroErrorCounter;              ///< Reg 453.  Blood leak zero error counter.
+
 } FPGA_SENSORS_T;
 
 /// Record structure for FPGA continuous priority writes.
@@ -931,25 +933,18 @@
 {
     SELF_TEST_STATUS_T result;
 
-    // Check FPGA reported correct ID
+    // check FPGA reported correct ID
     if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId )
     {
         // Check FPGA compatibility w/ firmware
-        if ( fpgaHeader.fpgaRevMajor > MIN_HD_FPGA_MAJOR )
+        if ( HD_FPGA_COMPATIBILITY_REV == fpgaSensorReadings.fpgaCompatibilityRev )
         {
             result = SELF_TEST_STATUS_PASSED;
         }
         else
         {
-            if ( fpgaHeader.fpgaRev >= MIN_HD_FPGA_MINOR )
-            {
-                result = SELF_TEST_STATUS_PASSED;
-            }
-            else
-            {
-                result = SELF_TEST_STATUS_FAILED;
-                SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaRevMajor, (U32)fpgaHeader.fpgaRev )
-            }
+            result = SELF_TEST_STATUS_FAILED;
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_POST_TEST_FAILED, (U32)HD_FPGA_COMPATIBILITY_REV, (U32)fpgaSensorReadings.fpgaCompatibilityRev )
         }
     }
     else
@@ -977,11 +972,14 @@
     U32 const diffFPGATimerCount = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms );
     U32 const diffTimerCount = u32DiffWithWrap( currentTimerCount_ms, newTimerCount_ms );
 
-    if ( getCurrentOperationMode() > MODE_INIT )
+    if ( getCurrentOperationMode() != MODE_INIT )
     {
         if ( abs( diffFPGATimerCount - diffTimerCount ) > PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE )
         {
-            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_CLOCK_SPEED_CHECK_FAILURE, diffFPGATimerCount, diffTimerCount );
+            if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR ) )
+            {
+                SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_CLOCK_SPEED_CHECK_FAILURE, diffFPGATimerCount, diffTimerCount );
+            }
         }
     }