Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 -rcb5c7321fae3036d7a3641ae49097b4b361270f5
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision cb5c7321fae3036d7a3641ae49097b4b361270f5)
@@ -42,6 +42,10 @@
 #define FPGA_PAGE_SIZE                  256
 #define FPGA_EXPECTED_ID                0x59
 
+#define FPGA_HEADER_START_ADDR          256     // update these after re-arranging w/ Randy
+#define FPGA_BULK_READ_START_ADDR       262
+#define FPGA_BULK_WRITE_START_ADDR      2
+
 #define FPGA_WRITE_CMD_BUFFER_LEN       (FPGA_PAGE_SIZE+8)
 #define FPGA_READ_CMD_BUFFER_LEN        8
 #define FPGA_WRITE_RSP_BUFFER_LEN       8
@@ -50,15 +54,14 @@
 #define FPGA_WRITE_CMD_CODE             0x55
 #define FPGA_READ_CMD_CODE              0x5A
 #define FPGA_WRITE_CMD_ACK              0xA5
-#define FPGA_WRITE_CMD_NAK              0xAE
 #define FPGA_READ_CMD_ACK               0xAA
-#define FPGA_READ_CMD_NAK               0xAF
+#define FPGA_CMD_NAK                    0xEE
 
 #define FPGA_CRC_LEN                    2
 #define FPGA_WRITE_CMD_HDR_LEN          4
 #define FPGA_READ_CMD_HDR_LEN           4
-#define FPGA_WRITE_RSP_HDR_LEN          1
-#define FPGA_READ_RSP_HDR_LEN           1
+#define FPGA_WRITE_RSP_HDR_LEN          3
+#define FPGA_READ_RSP_HDR_LEN           3
 
 #define SCI2_RECEIVE_DMA_REQUEST        28
 #define SCI2_TRANSMIT_DMA_REQUEST       29
@@ -71,13 +74,11 @@
 {
     U08 fpgaId;
     U08 fpgaRev;
-    U08 fpgaDiag;
-    U08 gap1;
-    U16 fpgaStatus;
     U16 fpgaControl;
-} FPGA_HEADER_T;
+    U16 fpgaStatus;
+} FPGA_HEADER_T;    // read only on FPGA
 
-typedef struct
+typedef struct  // TODO - add all sensor readings to this structure per FPGA register map
 {
     U16 bloodLeak;
     U32 adc1b;
@@ -90,8 +91,9 @@
     U32 dialysateTemp2;
 } FPGA_SENSORS_T;
 
-typedef struct
+typedef struct  // TODO - add all actuator set points to this structure per FPGA register map
 {
+    U08 bloodValveSetState;
 } FPGA_ACTUATORS_T;
 #pragma pack(pop)
 
@@ -481,12 +483,12 @@
             U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[crcPos+1], fpgaReadResponseBuffer[crcPos] );
 
             // does the FPGA response CRC check out?
-            if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
-//            if ( 1 ) // TODO - remove when FPGA CRCs are implemented
+//            if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
+            if ( 1 ) // TODO - remove when FPGA CRCs are implemented
             {
                 fpgaCommRetryCount = 0;
                 // capture the read values
-                memcpy( &fpgaHeader, &fpgaReadResponseBuffer[1], sizeof(FPGA_HEADER_T) );
+                memcpy( &fpgaHeader, &fpgaReadResponseBuffer[FPGA_READ_RSP_HDR_LEN], sizeof(FPGA_HEADER_T) );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else
@@ -545,7 +547,7 @@
     fpgaReadCmdBuffer[5] = GET_MSB_OF_WORD( crc );
     // prep DMA for sending the bulk write cmd and receiving its response
     setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + 1 + FPGA_CRC_LEN );  // TODO s/b sizeof(FPGA_ACTUATORS_T) instead of 1
-    setupDMAForWriteResp( FPGA_WRITE_RSP_HDR_LEN );
+    setupDMAForWriteResp( FPGA_WRITE_RSP_HDR_LEN + FPGA_CRC_LEN );
     // prep DMA for sending the bulk read cmd and receiving its response
     setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN );
     setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_T) + FPGA_CRC_LEN );
@@ -590,12 +592,12 @@
             U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[crcPos+1], fpgaReadResponseBuffer[crcPos] );
 
             // does the FPGA response CRC check out?
-            if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
-//            if ( 1 ) // TODO - remove when FPGA CRCs are implemented
+//            if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
+            if ( 1 ) // TODO - remove when FPGA CRCs are implemented
             {
                 fpgaCommRetryCount = 0;
                 // capture the read values
-                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[1], sizeof(FPGA_SENSORS_T) );
+                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[FPGA_READ_RSP_HDR_LEN], sizeof(FPGA_SENSORS_T) );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else // bad CRC
@@ -633,7 +635,7 @@
     SELF_TEST_STATUS_T result = SELF_TEST_STATUS_FAILED;
 
     // check FPGA reported correct ID
-    //if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId )
+    if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId )
     {
         result = SELF_TEST_STATUS_PASSED;
     }
@@ -832,21 +834,6 @@
 }
 
 /*************************************************************************
- * @brief getFPGADiag
- * The getFPGADiag function gets the version read from the diagnostic register \n
- * of the FPGA.
- * @details
- * Inputs : fpgaHeader
- * Outputs : none
- * @param none
- * @return fpgaDiag
- *************************************************************************/
-U08 getFPGADiag( void )
-{
-    return fpgaHeader.fpgaDiag;
-}
-
-/*************************************************************************
  * @brief getFPGAStatus
  * The getFPGAStatus function gets the version read from the diagnostic register \n
  * of the FPGA.