Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r739960711a13328f76f20accc65b9359e1feb2ac -r8bd1ae47aa13a843aa8abd6321ddc050deacb4a6
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 739960711a13328f76f20accc65b9359e1feb2ac)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 8bd1ae47aa13a843aa8abd6321ddc050deacb4a6)
@@ -1,17 +1,17 @@
 /**************************************************************************
 *
-* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved.
+* Copyright (c) 2019-2021 Diality Inc. - All Rights Reserved.
 *
 * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
 * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
 *
-* @file FPGA.c
+* @file    FPGA.c
 *
-* @author (last) Peman Montazemi
-* @date (last) 15-Feb-2021
+* @author  (last)      Quang Nguyen
+* @date    (last)      30-Aug-2021
 *
-* @author (original) Dara Navaei
-* @date (original) 05-Nov-2019
+* @author  (original)  Dara Navaei
+* @date    (original)  05-Nov-2019
 *
 ***************************************************************************/
 
@@ -23,8 +23,10 @@
 #include "Comm.h"
 #include "Compatible.h"
 #include "FPGA.h"
+#include "OperationModes.h"
 #include "PersistentAlarm.h"
 #include "SystemCommMessages.h"
+#include "Timers.h"
 #include "Utilities.h"
 
 /**
@@ -110,6 +112,8 @@
 #define FRONT_DOOR_SWITCH_MASK          0x0010                  ///< Front door switch bit mask. Bit 4 of the GPIO register.
 #define PUMP_TRACK_SWITCH_MASK          0x0020                  ///< Pump track switch bit mask. Bit 5 of the GPIO register.
 
+#define PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE      1              ///< Tolerance for processor clock speed check against FPGA clock.
+
 // FPGA Sensors Record
 #pragma pack(push,1)
 /// Record structure for FPGA header read.
@@ -299,6 +303,9 @@
 static FPGA_SENSORS_ASYNC_T  fpgaSensorReadingsAsync;                   ///< Record of last received async (as needed) FPGA sensor data.
 #endif
 
+static U16 currentFPGATimerCount_ms;                                       ///< Current FPGA timer count in ms.
+static U32 currentTimerCount_ms;                                           ///< Current processor timer count in ms.
+
 // ********** private function prototypes **********
 
 static FPGA_STATE_T handleFPGAReadHeaderState( void );
@@ -924,6 +931,33 @@
 
 /*********************************************************************//**
  * @brief
+ * The execFPGAClockSpeedTest function verifies the processor clock speed
+ * against the FPGA clock.
+ * @details Inputs: fpgaHeader
+ * @details Outputs: none
+ * @return passed, or failed
+ *************************************************************************/
+void execFPGAClockSpeedTest( void )
+{
+    U16 const newFPGATimerCount_ms = getFPGATimerCount();
+    U32 const newTimerCount_ms = getMSTimerCount();
+    U32 const diffFPGATimerCount = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms );
+    U32 const diffTimerCount = u32DiffWithWrap( currentTimerCount_ms, newTimerCount_ms );
+
+    if ( getCurrentOperationMode() > MODE_INIT )
+    {
+        if ( abs( diffFPGATimerCount - diffTimerCount ) > PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE )
+        {
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_CLOCK_SPEED_CHECK_FAILURE, diffFPGATimerCount, diffTimerCount );
+        }
+    }
+
+    currentFPGATimerCount_ms = newFPGATimerCount_ms;
+    currentTimerCount_ms = newTimerCount_ms;
+}
+
+/*********************************************************************//**
+ * @brief
  * The consumeUnexpectedData function checks to see if a byte is sitting in
  * the SCI2 received data register.
  * @details Inputs: fpgaHeader