Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r8b73263b38f449dacc0795c67a7cf6240cb79026 -r1c04924590760ca29e1c9fe19bca65ec5ce428fe --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 8b73263b38f449dacc0795c67a7cf6240cb79026) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 1c04924590760ca29e1c9fe19bca65ec5ce428fe) @@ -245,8 +245,10 @@ U16 bloodLeakRxFIFOCount; ///< Reg 448. Blood leak receive FIFO count. U08 bloodLeakRxFIFODataOut; ///< Reg 450. Blood leak receive FIFO data out. U08 dummyByte; ///< Reg 451. Dummy byte to meet the even of the data. + U16 fpgaCompatibilityRev; ///< Reg 452. Compatibility revisions U08 bloodLeakSelfTestErrorCounter; ///< Reg 452. Blood leak self test error counter. U08 bloodLeakZeroErrorCounter; ///< Reg 453. Blood leak zero error counter. + } FPGA_SENSORS_T; /// Record structure for FPGA continuous priority writes. @@ -931,25 +933,18 @@ { SELF_TEST_STATUS_T result; - // Check FPGA reported correct ID + // check FPGA reported correct ID if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId ) { // Check FPGA compatibility w/ firmware - if ( fpgaHeader.fpgaRevMajor > MIN_HD_FPGA_MAJOR ) + if ( HD_FPGA_COMPATIBILITY_REV == fpgaSensorReadings.fpgaCompatibilityRev ) { result = SELF_TEST_STATUS_PASSED; } else { - if ( fpgaHeader.fpgaRev >= MIN_HD_FPGA_MINOR ) - { - result = SELF_TEST_STATUS_PASSED; - } - else - { - result = SELF_TEST_STATUS_FAILED; - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaRevMajor, (U32)fpgaHeader.fpgaRev ) - } + result = SELF_TEST_STATUS_FAILED; + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_POST_TEST_FAILED, (U32)HD_FPGA_COMPATIBILITY_REV, (U32)fpgaSensorReadings.fpgaCompatibilityRev ) } } else