Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r9051b47d2d0e9f112d4ebc310a5572844b7528f4 -rf908e396e3ea2a08378d77089e6d6b8dd8da3cdc
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 9051b47d2d0e9f112d4ebc310a5572844b7528f4)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision f908e396e3ea2a08378d77089e6d6b8dd8da3cdc)
@@ -239,9 +239,14 @@
     U08 arterialPressureReadCount;              ///< Reg 444.  Arterial pressure sensor read count.
     U08 arterialPressureErrorCount;             ///< Reg 445.  Arterial pressure sensor error count.
     U08 bloodLeakTxFIFOCount;                   ///< Reg 446.  Blood leak transmit FIFO count.
-    U08 bloodLeakRxFIFOCount;                   ///< Reg 447.  Blood leak receive FIFO count.
-    U08 bloodLeakRxErrorCount;                  ///< Reg 448.  Blood leak receive error count.
-    U08 bloodLeakRxFIFODataOut;                 ///< Reg 449.  Blood leak receive FIFO data out.
+    U08 bloodLeakRxErrorCount;                  ///< Reg 447.  Blood leak receive error count.
+    U16 bloodLeakRxFIFOCount;                   ///< Reg 448.  Blood leak receive FIFO count.
+    U08 bloodLeakRxFIFODataOut;                 ///< Reg 450.  Blood leak receive FIFO data out.
+    U08 dummyByte;                              ///< Reg 451.  Dummy byte to meet the even of the data.
+    U16 fpgaCompatibilityRev;                   ///< Reg 452.  Compatibility revisions
+    U08 bloodLeakSelfTestErrorCounter;          ///< Reg 452.  Blood leak self test error counter.
+    U08 bloodLeakZeroErrorCounter;              ///< Reg 453.  Blood leak zero error counter.
+
 } FPGA_SENSORS_T;
 
 /// Record structure for FPGA continuous priority writes.
@@ -926,25 +931,18 @@
 {
     SELF_TEST_STATUS_T result;
 
-    // Check FPGA reported correct ID
+    // check FPGA reported correct ID
     if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId )
     {
         // Check FPGA compatibility w/ firmware
-        if ( fpgaHeader.fpgaRevMajor > MIN_HD_FPGA_MAJOR )
+        if ( HD_FPGA_COMPATIBILITY_REV == fpgaSensorReadings.fpgaCompatibilityRev )
         {
             result = SELF_TEST_STATUS_PASSED;
         }
         else
         {
-            if ( fpgaHeader.fpgaRev >= MIN_HD_FPGA_MINOR )
-            {
-                result = SELF_TEST_STATUS_PASSED;
-            }
-            else
-            {
-                result = SELF_TEST_STATUS_FAILED;
-                SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaRevMajor, (U32)fpgaHeader.fpgaRev )
-            }
+            result = SELF_TEST_STATUS_FAILED;
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_POST_TEST_FAILED, (U32)HD_FPGA_COMPATIBILITY_REV, (U32)fpgaSensorReadings.fpgaCompatibilityRev )
         }
     }
     else