Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r933a18d740285e70be9d00696ed0f5a5381bc8e4 -r911f6526ec3ba03ba0131681c7fb371c0abda6bb --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 933a18d740285e70be9d00696ed0f5a5381bc8e4) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 911f6526ec3ba03ba0131681c7fb371c0abda6bb) @@ -15,7 +15,7 @@ * ***************************************************************************/ -#include // for memset(), memcpy() +#include // For memset(), memcpy() #include "sci.h" #include "sys_dma.h" @@ -98,7 +98,7 @@ U08 accelCmd; ///< Reg 10. Command passed to accelerometer. U08 fpgaSensorTest; ///< Reg 11. Blood leak and bubble detector sensor test register. U16 fpgaPIDControl; ///< Reg 12. Valve PID enables. -} FPGA_HEADER_T; // read only on FPGA +} FPGA_HEADER_T; // Read only on FPGA /// Record structure for FPGA continuous priority reads. typedef struct // TODO - add all sensor readings to this structure per FPGA register map @@ -295,103 +295,104 @@ *************************************************************************/ void initFPGA( void ) { - // initialize fpga data structures + // Initialize fpga data structures memset( &fpgaHeader, 0, sizeof(FPGA_HEADER_T) ); memset( &fpgaSensorReadings, 0, sizeof(FPGA_SENSORS_T) ); memset( &fpgaActuatorSetPoints, 0, sizeof(FPGA_ACTUATORS_T) ); + fpgaActuatorSetPoints.AlarmControl = (U08)MIN_ALARM_VOLUME_ATTENUATION << 2; // Start alarm audio volume at maximum - // initialize fpga comm buffers + // Initialize fpga comm buffers memset( &fpgaWriteCmdBuffer, 0, FPGA_WRITE_CMD_BUFFER_LEN ); memset( &fpgaReadCmdBuffer, 0, FPGA_READ_CMD_BUFFER_LEN ); memset( &fpgaWriteResponseBuffer, 0, FPGA_WRITE_RSP_BUFFER_LEN ); memset( &fpgaReadResponseBuffer, 0, FPGA_READ_RSP_BUFFER_LEN ); - // enable interrupt notifications for FPGA serial port + // Enable interrupt notifications for FPGA serial port sciEnableNotification( scilinREG, SCI_OE_INT | SCI_FE_INT ); - // assign DMA channels to h/w DMA requests + // Assign DMA channels to h/w DMA requests dmaReqAssign( DMA_CH0, SCI2_RECEIVE_DMA_REQUEST ); dmaReqAssign( DMA_CH2, SCI2_TRANSMIT_DMA_REQUEST ); - // set DMA channel priorities + // Set DMA channel priorities dmaSetPriority( DMA_CH0, HIGHPRIORITY ); dmaSetPriority( DMA_CH2, LOWPRIORITY ); // Enable DMA block transfer complete interrupts dmaEnableInterrupt( DMA_CH0, BTC ); dmaEnableInterrupt( DMA_CH2, BTC ); - // initialize FPGA DMA Write Control Record - fpgaDMAWriteControlRecord.PORTASGN = 4; // port B (only choice per datasheet) - fpgaDMAWriteControlRecord.SADD = (U32)fpgaWriteCmdBuffer; // transfer source address - fpgaDMAWriteControlRecord.DADD = (U32)(&(scilinREG->TD)); // dest. is SCI2 xmit register - fpgaDMAWriteControlRecord.CHCTRL = 0; // no chaining - fpgaDMAWriteControlRecord.ELCNT = 1; // frame is 1 element - fpgaDMAWriteControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known - fpgaDMAWriteControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + // Initialize FPGA DMA Write Control Record + fpgaDMAWriteControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) + fpgaDMAWriteControlRecord.SADD = (U32)fpgaWriteCmdBuffer; // Transfer source address + fpgaDMAWriteControlRecord.DADD = (U32)(&(scilinREG->TD)); // Dest. is SCI2 xmit register + fpgaDMAWriteControlRecord.CHCTRL = 0; // No chaining + fpgaDMAWriteControlRecord.ELCNT = 1; // Frame is 1 element + fpgaDMAWriteControlRecord.FRCNT = 0; // Block is TBD frames - will be populated later when known + fpgaDMAWriteControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte fpgaDMAWriteControlRecord.WRSIZE = ACCESS_8_BIT; // - fpgaDMAWriteControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer - fpgaDMAWriteControlRecord.ADDMODERD = ADDR_INC1; // source addressing mode is post-increment - fpgaDMAWriteControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed - fpgaDMAWriteControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off - fpgaDMAWriteControlRecord.ELSOFFSET = 0; // not used - fpgaDMAWriteControlRecord.ELDOFFSET = 0; // not used - fpgaDMAWriteControlRecord.FRSOFFSET = 0; // not used - fpgaDMAWriteControlRecord.FRDOFFSET = 0; // not used + fpgaDMAWriteControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer + fpgaDMAWriteControlRecord.ADDMODERD = ADDR_INC1; // Source addressing mode is post-increment + fpgaDMAWriteControlRecord.ADDMODEWR = ADDR_FIXED; // Dest. addressing mode is fixed + fpgaDMAWriteControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off + fpgaDMAWriteControlRecord.ELSOFFSET = 0; // Not used + fpgaDMAWriteControlRecord.ELDOFFSET = 0; // Not used + fpgaDMAWriteControlRecord.FRSOFFSET = 0; // Not used + fpgaDMAWriteControlRecord.FRDOFFSET = 0; // Not used - // initialize FPGA DMA Write Response Control Record - fpgaDMAWriteRespControlRecord.PORTASGN = 4; // port B (only choice per datasheet) - fpgaDMAWriteRespControlRecord.SADD = (U32)(&(scilinREG->RD));// source is SCI2 recv register - fpgaDMAWriteRespControlRecord.DADD = (U32)fpgaWriteResponseBuffer; // transfer destination address - fpgaDMAWriteRespControlRecord.CHCTRL = 0; // no chaining - fpgaDMAWriteRespControlRecord.ELCNT = 1; // frame is 1 element - fpgaDMAWriteRespControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known - fpgaDMAWriteRespControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + // Initialize FPGA DMA Write Response Control Record + fpgaDMAWriteRespControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) + fpgaDMAWriteRespControlRecord.SADD = (U32)(&(scilinREG->RD));// Source is SCI2 recv register + fpgaDMAWriteRespControlRecord.DADD = (U32)fpgaWriteResponseBuffer; // Transfer destination address + fpgaDMAWriteRespControlRecord.CHCTRL = 0; // No chaining + fpgaDMAWriteRespControlRecord.ELCNT = 1; // Frame is 1 element + fpgaDMAWriteRespControlRecord.FRCNT = 0; // Block is TBD frames - will be populated later when known + fpgaDMAWriteRespControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte fpgaDMAWriteRespControlRecord.WRSIZE = ACCESS_8_BIT; // - fpgaDMAWriteRespControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer - fpgaDMAWriteRespControlRecord.ADDMODERD = ADDR_FIXED; // source addressing mode is fixed - fpgaDMAWriteRespControlRecord.ADDMODEWR = ADDR_INC1; // dest. addressing mode is post-increment - fpgaDMAWriteRespControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off - fpgaDMAWriteRespControlRecord.ELDOFFSET = 0; // not used - fpgaDMAWriteRespControlRecord.ELSOFFSET = 0; // not used - fpgaDMAWriteRespControlRecord.FRDOFFSET = 0; // not used - fpgaDMAWriteRespControlRecord.FRSOFFSET = 0; // not used + fpgaDMAWriteRespControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer + fpgaDMAWriteRespControlRecord.ADDMODERD = ADDR_FIXED; // Source addressing mode is fixed + fpgaDMAWriteRespControlRecord.ADDMODEWR = ADDR_INC1; // Dest. addressing mode is post-increment + fpgaDMAWriteRespControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off + fpgaDMAWriteRespControlRecord.ELDOFFSET = 0; // Not used + fpgaDMAWriteRespControlRecord.ELSOFFSET = 0; // Not used + fpgaDMAWriteRespControlRecord.FRDOFFSET = 0; // Not used + fpgaDMAWriteRespControlRecord.FRSOFFSET = 0; // Not used - // initialize FPGA DMA Read Control Record - fpgaDMAReadControlRecord.PORTASGN = 4; // port B (only choice per datasheet) - fpgaDMAReadControlRecord.SADD = (U32)fpgaReadCmdBuffer; // transfer source address - fpgaDMAReadControlRecord.DADD = (U32)(&(scilinREG->TD)); // dest. is SCI2 xmit register - fpgaDMAReadControlRecord.CHCTRL = 0; // no chaining - fpgaDMAReadControlRecord.ELCNT = 1; // frame is 1 element - fpgaDMAReadControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known - fpgaDMAReadControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + // Initialize FPGA DMA Read Control Record + fpgaDMAReadControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) + fpgaDMAReadControlRecord.SADD = (U32)fpgaReadCmdBuffer; // Transfer source address + fpgaDMAReadControlRecord.DADD = (U32)(&(scilinREG->TD)); // Dest. is SCI2 xmit register + fpgaDMAReadControlRecord.CHCTRL = 0; // No chaining + fpgaDMAReadControlRecord.ELCNT = 1; // Frame is 1 element + fpgaDMAReadControlRecord.FRCNT = 0; // Block is TBD frames - will be populated later when known + fpgaDMAReadControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte fpgaDMAReadControlRecord.WRSIZE = ACCESS_8_BIT; // - fpgaDMAReadControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer - fpgaDMAReadControlRecord.ADDMODERD = ADDR_INC1; // source addressing mode is post-increment - fpgaDMAReadControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed - fpgaDMAReadControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off - fpgaDMAReadControlRecord.ELSOFFSET = 0; // not used - fpgaDMAReadControlRecord.ELDOFFSET = 0; // not used - fpgaDMAReadControlRecord.FRSOFFSET = 0; // not used - fpgaDMAReadControlRecord.FRDOFFSET = 0; // not used + fpgaDMAReadControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer + fpgaDMAReadControlRecord.ADDMODERD = ADDR_INC1; // Source addressing mode is post-increment + fpgaDMAReadControlRecord.ADDMODEWR = ADDR_FIXED; // Dest. addressing mode is fixed + fpgaDMAReadControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off + fpgaDMAReadControlRecord.ELSOFFSET = 0; // Not used + fpgaDMAReadControlRecord.ELDOFFSET = 0; // Not used + fpgaDMAReadControlRecord.FRSOFFSET = 0; // Not used + fpgaDMAReadControlRecord.FRDOFFSET = 0; // Not used - // initialize FPGA DMA Read Response Control Record - fpgaDMAReadRespControlRecord.PORTASGN = 4; // port B (only choice per datasheet) - fpgaDMAReadRespControlRecord.SADD = (U32)(&(scilinREG->RD)); // source is SCI2 recv register - fpgaDMAReadRespControlRecord.DADD = (U32)fpgaReadResponseBuffer; // transfer destination address - fpgaDMAReadRespControlRecord.CHCTRL = 0; // no chaining - fpgaDMAReadRespControlRecord.ELCNT = 1; // frame is 1 element - fpgaDMAReadRespControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known - fpgaDMAReadRespControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + // Initialize FPGA DMA Read Response Control Record + fpgaDMAReadRespControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) + fpgaDMAReadRespControlRecord.SADD = (U32)(&(scilinREG->RD)); // Source is SCI2 recv register + fpgaDMAReadRespControlRecord.DADD = (U32)fpgaReadResponseBuffer; // Transfer destination address + fpgaDMAReadRespControlRecord.CHCTRL = 0; // No chaining + fpgaDMAReadRespControlRecord.ELCNT = 1; // Frame is 1 element + fpgaDMAReadRespControlRecord.FRCNT = 0; // Block is TBD frames - will be populated later when known + fpgaDMAReadRespControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte fpgaDMAReadRespControlRecord.WRSIZE = ACCESS_8_BIT; // - fpgaDMAReadRespControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer - fpgaDMAReadRespControlRecord.ADDMODERD = ADDR_FIXED; // source addressing mode is fixed - fpgaDMAReadRespControlRecord.ADDMODEWR = ADDR_INC1; // dest. addressing mode is post-increment - fpgaDMAReadRespControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off - fpgaDMAReadRespControlRecord.ELDOFFSET = 0; // not used - fpgaDMAReadRespControlRecord.ELSOFFSET = 0; // not used - fpgaDMAReadRespControlRecord.FRDOFFSET = 0; // not used - fpgaDMAReadRespControlRecord.FRSOFFSET = 0; // not used + fpgaDMAReadRespControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer + fpgaDMAReadRespControlRecord.ADDMODERD = ADDR_FIXED; // Source addressing mode is fixed + fpgaDMAReadRespControlRecord.ADDMODEWR = ADDR_INC1; // Dest. addressing mode is post-increment + fpgaDMAReadRespControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off + fpgaDMAReadRespControlRecord.ELDOFFSET = 0; // Not used + fpgaDMAReadRespControlRecord.ELSOFFSET = 0; // Not used + fpgaDMAReadRespControlRecord.FRDOFFSET = 0; // Not used + fpgaDMAReadRespControlRecord.FRSOFFSET = 0; // Not used - // there shouldn't be any data pending yet + // There should not be any data pending yet consumeUnexpectedData(); } @@ -425,7 +426,7 @@ void signalFPGAReceiptCompleted( void ) { fpgaReceiptCounter++; - // did FPGA Ack last command? + // Did FPGA Ack last command? if ( TRUE == fpgaWriteCommandInProgress ) { fpgaWriteCommandInProgress = FALSE; @@ -437,12 +438,12 @@ fpgaReadCommandResponseReceived = TRUE; } - // see if we want to follow up with a bulk read command + // See if we want to follow up with a bulk read command if ( TRUE == fpgaBulkWriteAndReadInProgress ) { fpgaBulkWriteAndReadInProgress = FALSE; fpgaReadCommandInProgress = TRUE; - // initiate bulk read command + // Initiate bulk read command startDMAReceiptOfReadResp(); startDMAReadCmd(); } @@ -494,7 +495,7 @@ #endif case FPGA_STATE_FAILED: - // do nothing - we'll be stuck here + // Do nothing - we will be stuck here break; default: @@ -504,18 +505,18 @@ } else { - // ok, some states handled in the outgoing state machine + // Ok, some states handled in the outgoing state machine } break; } - // if retries for commands exceeds limit, fault + // If retries for commands exceeds limit, fault if ( fpgaCommRetryCount > MAX_COMM_ERROR_RETRIES ) { - // TODO - FPGA comm fault + activateAlarmNoData( ALARM_ID_FPGA_COMM_TIMEOUT ); } - // reset comm flags after processing incoming responses + // Reset comm flags after processing incoming responses resetFPGACommFlags(); } @@ -542,7 +543,7 @@ break; case FPGA_STATE_FAILED: - // do nothing - we'll be stuck here + // Do nothing - we will be stuck here break; #ifdef READ_FPGA_ASYNC_DATA @@ -558,7 +559,7 @@ } else { - // ok, some states handled in the incoming state machine + // Ok, some states handled in the incoming state machine } break; } @@ -577,15 +578,15 @@ FPGA_STATE_T result = FPGA_STATE_RCV_HEADER; U16 crc; - // construct read command to read 3 registers starting at address 0 + // Construct read command to read 3 registers starting at address 0 fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_HEADER_START_ADDR ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_HEADER_START_ADDR ); fpgaReadCmdBuffer[ 3 ] = sizeof(FPGA_HEADER_T); crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc ); - // prep DMA for sending the read cmd and receiving the response + // Prep DMA for sending the read cmd and receiving the response fpgaReadCommandInProgress = TRUE; setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_HEADER_T) + FPGA_CRC_LEN ); setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN ); @@ -607,21 +608,21 @@ { FPGA_STATE_T result = FPGA_STATE_READ_HEADER; - // did we get an FPGA response? + // Did we get an FPGA response? if ( TRUE == fpgaReadCommandResponseReceived ) { - // did FPGA Ack the read command? + // Did FPGA Ack the read command? if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK ) { U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_HEADER_T); U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); - // does the FPGA response CRC check out? + // Does the FPGA response CRC check out? if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) { fpgaCommRetryCount = 0; - // capture the read values + // Capture the read values memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) ); result = FPGA_STATE_WRITE_ALL_ACTUATORS; } @@ -630,17 +631,17 @@ fpgaCommRetryCount++; } } - else // header read was NAK'd + else // Header read was NAK'd { fpgaCommRetryCount++; } } - else // no response to read command + else // No response to read command { fpgaCommRetryCount++; } - // shouldn't be any data received at this time + // Should not be any data received at this time consumeUnexpectedData(); return result; @@ -659,7 +660,7 @@ FPGA_STATE_T result = FPGA_STATE_RCV_ALL_SENSORS; U16 crc; - // construct bulk write command to write actuator data registers starting at address 3 (TODO - change address later) + // Construct bulk write command to write actuator data registers starting at address 3 (TODO - change address later) fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE; fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_WRITE_START_ADDR ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_WRITE_START_ADDR ); @@ -669,7 +670,7 @@ fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) ] = GET_MSB_OF_WORD( crc ); fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) + 1 ] = GET_LSB_OF_WORD( crc ); - // construct bulk read command to read sensor data registers starting at address 8 + // Construct bulk read command to read sensor data registers starting at address 8 fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_READ_START_ADDR ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_READ_START_ADDR ); @@ -678,16 +679,16 @@ fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc ); - // prep DMA for sending the bulk write cmd and receiving its response + // Prep DMA for sending the bulk write cmd and receiving its response setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) + FPGA_CRC_LEN ); setupDMAForWriteResp( FPGA_WRITE_RSP_HDR_LEN + FPGA_CRC_LEN ); - // prep DMA for sending the bulk read cmd and receiving its response + // Prep DMA for sending the bulk read cmd and receiving its response setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN ); setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof( FPGA_SENSORS_T ) + FPGA_CRC_LEN ); - // set fpga comm flags for bulk write cmd and follow-up bulk read command + // Set fpga comm flags for bulk write cmd and follow-up bulk read command fpgaWriteCommandInProgress = TRUE; fpgaBulkWriteAndReadInProgress = TRUE; - // initiate bulk write command and it's receipt - read will follow + // Initiate bulk write command and its receipt - read will follow startDMAReceiptOfWriteResp(); startDMAWriteCmd(); @@ -706,50 +707,50 @@ { FPGA_STATE_T result = FPGA_STATE_WRITE_ALL_ACTUATORS; - // check bulk write command success + // Check bulk write command success if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[ 0 ] != FPGA_WRITE_CMD_ACK ) ) { fpgaCommRetryCount++; } - // if bulk read command is ACK'd, collect the readings + // If bulk read command is ACK'd, collect the readings if ( TRUE == fpgaReadCommandResponseReceived ) { - // did FPGA Ack the read command? + // Did FPGA Ack the read command? if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK ) { U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_T); U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); - // does the FPGA response CRC check out? + // Does the FPGA response CRC check out? if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) { fpgaCommRetryCount = 0; - // capture the read values + // Capture the read values memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_SENSORS_T ) ); #ifndef READ_FPGA_ASYNC_DATA result = FPGA_STATE_WRITE_ALL_ACTUATORS; #else result = FPGA_STATE_READ_ALL_SENSORS_ASYNC; #endif } - else // bad CRC + else // Bad CRC { fpgaCommRetryCount++; } } - else // read command was NAK'd + else // Read command was NAK'd { fpgaCommRetryCount++; } } - else // no response to read command + else // No response to read command { fpgaCommRetryCount++; } - // shouldn't be any data received at this time + // Should not be any data received at this time consumeUnexpectedData(); return result; @@ -769,15 +770,15 @@ FPGA_STATE_T result = FPGA_STATE_RCV_ALL_SENSORS_ASYNC; U16 crc; - // construct read command to read low priority async registers starting at address 0x200 + // Construct read command to read low priority async registers starting at address 0x200 fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_ASYNC_READ_START_ADDR ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_ASYNC_READ_START_ADDR ); fpgaReadCmdBuffer[ 3 ] = sizeof(FPGA_SENSORS_ASYNC_T); crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc ); - // prep DMA for sending the read cmd and receiving the response + // Prep DMA for sending the read cmd and receiving the response fpgaReadCommandInProgress = TRUE; setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_ASYNC_T) + FPGA_CRC_LEN ); setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN ); @@ -799,40 +800,40 @@ { FPGA_STATE_T result = FPGA_STATE_READ_ALL_SENSORS_ASYNC; - // if bulk read command is ACK'd, collect the readings + // If bulk read command is ACK'd, collect the readings if ( TRUE == fpgaReadCommandResponseReceived ) { - // did FPGA Ack the read command? + // Did FPGA Ack the read command? if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK ) { U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_ASYNC_T); U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); - // does the FPGA response CRC check out? + // Does the FPGA response CRC check out? if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) { fpgaCommRetryCount = 0; - // capture the read values + // Capture the read values memcpy( &fpgaSensorReadingsAsync, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_SENSORS_ASYNC_T ) ); result = FPGA_STATE_WRITE_ALL_ACTUATORS; } - else // bad CRC + else // Bad CRC { fpgaCommRetryCount++; } } - else // read command was NAK'd + else // Read command was NAK'd { fpgaCommRetryCount++; } } - else // no response to read command + else // No response to read command { fpgaCommRetryCount++; } - // shouldn't be any data received at this time + // Should not be any data received at this time consumeUnexpectedData(); return result; @@ -850,12 +851,8 @@ { SELF_TEST_STATUS_T result; - // check FPGA reported correct ID -#ifndef RM46_EVAL_BOARD_TARGET + // Check FPGA reported correct ID if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId ) -#else - if ( 1 ) -#endif { result = SELF_TEST_STATUS_PASSED; } @@ -878,10 +875,10 @@ *************************************************************************/ static void consumeUnexpectedData( void ) { - // clear any errors + // Clear any errors sciRxError( scilinREG ); - // if a byte is pending read, read it + // If a byte is pending read, read it if ( sciIsRxReady( scilinREG ) != 0 ) { sciReceiveByte( scilinREG ); @@ -899,7 +896,7 @@ *************************************************************************/ static void setupDMAForWriteCmd( U32 bytes2Transmit ) { - // verify # of bytes does not exceed buffer length + // Verify # of bytes does not exceed buffer length if ( bytes2Transmit <= FPGA_WRITE_CMD_BUFFER_LEN ) { fpgaDMAWriteControlRecord.FRCNT = bytes2Transmit; @@ -936,7 +933,7 @@ *************************************************************************/ static void setupDMAForWriteResp( U32 bytes2Receive ) { - // verify # of bytes does not exceed buffer length + // Verify # of bytes does not exceed buffer length if ( bytes2Receive <= FPGA_WRITE_RSP_BUFFER_LEN ) { fpgaDMAWriteRespControlRecord.FRCNT = bytes2Receive; @@ -973,7 +970,7 @@ *************************************************************************/ static void setupDMAForReadCmd( U32 bytes2Transmit ) { - // verify # of bytes does not exceed buffer length + // Verify # of bytes does not exceed buffer length if ( bytes2Transmit <= FPGA_READ_CMD_BUFFER_LEN ) { fpgaDMAReadControlRecord.FRCNT = bytes2Transmit; @@ -1010,7 +1007,7 @@ *************************************************************************/ static void setupDMAForReadResp( U32 bytes2Receive ) { - // verify # of bytes does not exceed buffer length + // Verify # of bytes does not exceed buffer length if ( bytes2Receive <= FPGA_READ_RSP_BUFFER_LEN ) { fpgaDMAReadRespControlRecord.FRCNT = bytes2Receive; @@ -1053,6 +1050,47 @@ /*********************************************************************//** * @brief + * The setAlarmAudioState function sets the fpga audio control to the given + * state and volume. + * @details Inputs: none + * @details Outputs: alarm audio state and attenuation set + * @param state the state of alarm audio to command: + * 0 - No alarm tone + * 1 - Low priority alarm tone (c e) + * 2 - Medium priority alarm tone (c f# c) + * 3 - High priority alarm tone (c f# c - c f#) + * @param volumeLevel the level of attenuation to command (0..4) + * 4 - 3 dB gain + * 3 - 6 dB gain + * 2 - 9 dB gain + * 1 - 12 dB gain + * 0 - 15 dB gain + * @return none + *************************************************************************/ +void setAlarmAudioState( ALARM_PRIORITY_T state, U32 volumeLevel ) +{ + if ( ( state < NUM_OF_ALARM_PRIORITIES ) && ( volumeLevel <= MAX_ALARM_VOLUME_ATTENUATION ) ) + { + U08 audioCmd = (U08)state; + + audioCmd |= ( (U08)volumeLevel << 2 ); + fpgaActuatorSetPoints.AlarmControl = audioCmd; + } + else + { + U08 audioCmd = (U08)ALARM_PRIORITY_HIGH; + + // Set alarm audio to high priority, max volume for safety since s/w seems to be having trouble setting audio correctly + audioCmd |= ( (U08)MIN_ALARM_VOLUME_ATTENUATION << 2 ); + fpgaActuatorSetPoints.AlarmControl = audioCmd; + // S/w fault to indicate issue w/ s/w + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_ALARM_AUDIO_PARAM, volumeLevel ) + + } +} + +/*********************************************************************//** + * @brief * The getFPGABloodFlowSignalStrength function gets the latest blood flow * signal strength reading. * @details Inputs: fpgaSensorReadings2