Index: firmware/App/Services/FPGA.c =================================================================== diff -u -rb5756e5b5041288a2e95585990cce5a93756d693 -rd66d7110b82c3818713c42f201257cce0bec101a --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision b5756e5b5041288a2e95585990cce5a93756d693) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision d66d7110b82c3818713c42f201257cce0bec101a) @@ -52,7 +52,7 @@ #define FPGA_HEADER_START_ADDR 0x0000 ///< Start address for FPGA header data. #define FPGA_BULK_READ_START_ADDR 0x0100 ///< Start address for FPGA continuous priority reads. -#define FPGA_BULK_WRITE_START_ADDR 0x0008 ///< Start address for FPGA continuous priority writes. +#define FPGA_BULK_WRITE_START_ADDR 0x000C ///< Start address for FPGA continuous priority writes. #define FPGA_BULK_ASYNC_READ_START_ADDR 0x0200 ///< Start address for FPGA async reads. #define FPGA_WRITE_CMD_BUFFER_LEN (FPGA_PAGE_SIZE+8) ///< FPGA write command buffer byte length. @@ -77,15 +77,25 @@ #define MAX_COMM_ERROR_RETRIES 5 ///< Maximum consecutive FPGA communication error retries. +#define FPGA_ADC1_AUTO_READ_ENABLE 0x01 ///< Auto-read enable bit for ADC1 control register. + // FPGA Sensors Record #pragma pack(push,1) /// Record structure for FPGA header read. typedef struct { U08 fpgaId; ///< Reg 0. FPGA ID code. Checked against expected value at power up to verify basic FPGA communication and operation. U08 fpgaRev; ///< Reg 1. FPGA revision being reported. - U16 fpgaControl; ///< Reg 2,3. TBD. - U16 fpgaStatus; ///< Reg 4,5. TBD. + U16 fpgaStatus; ///< Reg 2. FPGA status register. + U08 fpgaDiag; ///< Reg 4. FPGA diagnostic (R/W) register. + U08 adc1Control; ///< Reg 5. ADC1 control register. Bit 0=auto read enable. + U08 flowDAQ1Cmd; ///< Reg 6. Command passed to flow DAQ #1. + U08 flowDAQ2Cmd; ///< Reg 7. Command passed to flow DAQ #2. + U08 accelCmd; ///< Reg 8. Command passed to accelerometer. + U08 fpgaRevMajor; ///< Reg 9. FPGA Major revision #. + U08 fpgaRevLab; ///< Reg 10. FPGA Lab revision #. + U08 fpgaSensorTest; ///< Reg 11. Blood leak and bubble detector sensor test register. + U16 fpgaPIDControl; ///< Reg 12. Valve PID enables. } FPGA_HEADER_T; // read only on FPGA /// Record structure for FPGA continuous priority reads. @@ -144,23 +154,34 @@ U16 fan1PulseTime; ///< Reg 352. Fan 1 pulse time in 2.5 uSec resolution. 0xFFFF if fan RPM < 500 RPM. U16 fan2PUlseTime; ///< Reg 354. Fan 2 pulse time in 2.5 uSec resolution. 0xFFFF if fan RPM < 500 RPM. U16 fpgaGPIO; ///< Reg 356. FPGA GPIO register. - S16 VBaPosition; ///< Reg 358. Encoder position from VBA pinch valve. 0 until PID interface is enabled. - S16 VBvPosition; ///< Reg 360. Encoder position from VBV pinch valve. 0 until PID interface is enabled. - S16 VDioPosition; ///< Reg 362. Encoder position from VDio pinch valve. 0 until PID interface is enabled. - S16 VDzrPosition; ///< Reg 364. Encoder position from VDZR pinch valve. 0 until PID interface is enabled. - S16 VDfPosition; ///< Reg 366. Encoder position from VDf pinch valve. 0 until PID interface is enabled. + S16 VBAPosition; ///< Reg 358. Encoder position from VBA pinch valve. 0 until PID interface is enabled. + S16 VBVPosition; ///< Reg 360. Encoder position from VBV pinch valve. 0 until PID interface is enabled. + S16 VDiPosition; ///< Reg 362. Encoder position from VDi pinch valve. 0 until PID interface is enabled. + S16 VDoPosition; ///< Reg 364. Encoder position from VDo pinch valve. 0 until PID interface is enabled. + S16 VSparePosition; ///< Reg 366. Encoder position from VSpare pinch valve. 0 until PID interface is enabled. U16 valveStatus; ///< Reg 368. Valve status register. - U16 VBaPWMTarget; ///< Reg 370. PWM target duty cycle for VBA pinch valve. - U16 VBvPWMTarget; ///< Reg 372. PWM target duty cycle for VBV pinch valve. - U16 VDioPWMTarget; ///< Reg 374. PWM target duty cycle for VDio pinch valve. - U16 VDzrPWMTarget; ///< Reg 376. PWM target duty cycle for VDZR pinch valve. - U16 VDfPWMTarget; ///< Reg 378. PWM target duty cycle for VDF pinch valve. + U16 VBAPWMTarget; ///< Reg 370. PWM target duty cycle for VBA pinch valve. + U16 VBVPWMTarget; ///< Reg 372. PWM target duty cycle for VBV pinch valve. + U16 VDiPWMTarget; ///< Reg 374. PWM target duty cycle for VDi pinch valve. + U16 VDoPWMTarget; ///< Reg 376. PWM target duty cycle for VDo pinch valve. + U16 VSparePWMTarget; ///< Reg 378. PWM target duty cycle for Vspare pinch valve. } FPGA_SENSORS_T; /// Record structure for FPGA continuous priority writes. typedef struct // TODO - add all actuator set points to this structure per FPGA register map { - U08 bloodValveSetState; ///< Reg 8. Set valve actuator states. + U16 fpgaPIDControl; ///< Reg 12. Valve PID enables. + U16 VBASetPoint; ///< Reg 14. VBA pinch valve is commanded to this set point position. + U16 VBVSetPoint; ///< Reg 16. VBV pinch valve is commanded to this set point position. + U16 VDiSetPoint; ///< Reg 18. VDi pinch valve is commanded to this set point position. + U16 VDoSetPoint; ///< Reg 20. VDo pinch valve is commanded to this set point position. + U16 VSpareSetPoint; ///< Reg 22. VSpare pinch valve is commanded to this set point position. + U16 VBAPWMFixed; ///< Reg 24. VBA PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction. + U16 VBVPWMFixed; ///< Reg 26. VBV PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction. + U16 VDiPWMFixed; ///< Reg 28. VDi PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction. + U16 VDoPWMFixed; ///< Reg 30. VDo PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction. + U16 VSparePWMFixed; ///< Reg 32. Vspare PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction. + U08 AlarmControl; ///< Reg 34. Alarm (audio) control register. } FPGA_ACTUATORS_T; /// Record structure for FPGA async (as needed) reads. @@ -1010,20 +1031,6 @@ /*********************************************************************//** * @brief - * The getFPGADiag function sets the diagnostic register of the FPGA. - * @details - * Inputs : fpgaHeader - * Outputs : none - * @param ctrl : value to write to diagnostic register - * @return none - *************************************************************************/ -void setFPGAControl( U16 ctrl ) -{ - fpgaHeader.fpgaControl = ctrl; -} - -/*********************************************************************//** - * @brief * The getFPGABloodFlowSignalStrength function gets the latest blood flow \n * signal strength reading. * @details