Index: firmware/App/Services/FPGA.c =================================================================== diff -u -reb877ae36c28eb83553ee11ccccf42e2c4a5b4d2 -reff7b1575f008f81b29ef906f6346fac6012d3ab --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision eb877ae36c28eb83553ee11ccccf42e2c4a5b4d2) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) @@ -63,6 +63,8 @@ #define SCI2_RECEIVE_DMA_REQUEST 28 #define SCI2_TRANSMIT_DMA_REQUEST 29 +#define MAX_COMM_ERROR_RETRIES 5 + // FPGA Sensors Record #pragma pack(push,1) typedef struct @@ -98,6 +100,7 @@ // FPGA state static FPGA_STATE_T fpgaState = FPGA_STATE_START; +static U32 fpgaCommRetryCount = 0; static U32 fpgaReceiptCounter = 0; static U32 fpgaTransmitCounter = 0; static BOOL fpgaWriteCommandInProgress = FALSE; @@ -158,6 +161,12 @@ memset( &fpgaSensorReadings, 0, sizeof(FPGA_SENSORS_T) ); memset( &fpgaActuatorSetPoints, 0, sizeof(FPGA_ACTUATORS_T) ); + // initialize fpga comm buffers + memset( &fpgaWriteCmdBuffer, 0, FPGA_WRITE_CMD_BUFFER_LEN ); + memset( &fpgaReadCmdBuffer, 0, FPGA_READ_CMD_BUFFER_LEN ); + memset( &fpgaWriteResponseBuffer, 0, FPGA_WRITE_RSP_BUFFER_LEN ); + memset( &fpgaReadResponseBuffer, 0, FPGA_READ_RSP_BUFFER_LEN ); + // enable interrupt notifications for FPGA serial port sciEnableNotification( scilinREG, SCI_OE_INT | SCI_FE_INT ); @@ -296,13 +305,11 @@ // see if we want to follow up with a bulk read command if ( TRUE == fpgaBulkWriteAndReadInProgress ) { - // first receipt? - if ( 1 == fpgaReceiptCounter ) - { - fpgaBulkWriteAndReadInProgress = FALSE; - fpgaReadCommandInProgress = TRUE; - // TODO - initiate bulk read command - } + fpgaBulkWriteAndReadInProgress = FALSE; + fpgaReadCommandInProgress = TRUE; + // initiate bulk read command + startDMAReceiptOfReadResp(); + startDMAReadCmd(); } } @@ -343,8 +350,8 @@ fpgaState = handleFPGAReceiveHeaderState(); break; + // TODO - sensor/ADC init/configuration states - case FPGA_STATE_RCV_ALL_SENSORS: fpgaState = handleFPGAReceiveAllSensorsState(); break; @@ -365,6 +372,12 @@ break; } + // if retries for commands exceeds limit, fault + if ( fpgaCommRetryCount > MAX_COMM_ERROR_RETRIES ) + { + // TODO - FPGA comm fault + } + // reset comm flags after processing incoming responses resetFPGACommFlags(); } @@ -387,8 +400,8 @@ fpgaState = handleFPGAReadHeaderState(); break; + // TODO - sensor/ADC init/configuration states - case FPGA_STATE_WRITE_ALL_ACTUATORS: fpgaState = handleFPGAWriteAllActuatorsState(); break; @@ -463,17 +476,32 @@ // did FPGA Ack the read command? if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK ) { + U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_HEADER_T); + U32 crcPos = rspSize; + U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[crcPos+1], fpgaReadResponseBuffer[crcPos] ); + // does the FPGA response CRC check out? - if ( 1 ) // TODO - check response CRC - { // capture the read values + if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) +// if ( 1 ) // TODO - remove when FPGA CRCs are implemented + { + fpgaCommRetryCount = 0; + // capture the read values memcpy( &fpgaHeader, &fpgaReadResponseBuffer[1], sizeof(FPGA_HEADER_T) ); result = FPGA_STATE_WRITE_ALL_ACTUATORS; } + else + { + fpgaCommRetryCount++; + } } + else // header read was NAK'd + { + fpgaCommRetryCount++; + } } - else // + else // no response to read command { - + fpgaCommRetryCount++; } // shouldn't be any data received at this time @@ -499,7 +527,7 @@ // construct bulk write command to write actuator data registers starting at address 3 (TODO - change address later) fpgaWriteCmdBuffer[0] = FPGA_WRITE_CMD_CODE; - fpgaWriteCmdBuffer[1] = 0x02; // start at FPGA address 8 + fpgaWriteCmdBuffer[1] = 0x08; // start at FPGA address 8 fpgaWriteCmdBuffer[2] = 0x00; fpgaWriteCmdBuffer[3] = 1; // TODO - replace 1 with sizeof(FPGA_ACTUATORS_T) // memcpy( &(fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN]), &fpgaActuatorSetPoints, sizeof(FPGA_ACTUATORS_T) ); @@ -548,7 +576,7 @@ // check bulk write command success if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[0] != FPGA_WRITE_CMD_ACK ) ) { - // TODO - ??? + fpgaCommRetryCount++; } // if bulk read command is ACK'd, collect the readings @@ -557,17 +585,32 @@ // did FPGA Ack the read command? if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK ) { + U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_T); + U32 crcPos = rspSize; + U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[crcPos+1], fpgaReadResponseBuffer[crcPos] ); + // does the FPGA response CRC check out? - if ( 1 ) // TODO - check response CRC - { // capture the read values - memcpy( &fpgaSensorReadings, fpgaReadResponseBuffer, sizeof(FPGA_SENSORS_T) ); + if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) +// if ( 1 ) // TODO - remove when FPGA CRCs are implemented + { + fpgaCommRetryCount = 0; + // capture the read values + memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[1], sizeof(FPGA_SENSORS_T) ); result = FPGA_STATE_WRITE_ALL_ACTUATORS; } + else // bad CRC + { + fpgaCommRetryCount++; + } } + else // read command was NAK'd + { + fpgaCommRetryCount++; + } } - else + else // no response to read command { - // TODO - ??? + fpgaCommRetryCount++; } // shouldn't be any data received at this time @@ -610,7 +653,15 @@ *************************************************************************/ static void setupDMAForWriteCmd( U32 bytes2Transmit ) { - fpgaDMAWriteControlRecord.FRCNT = bytes2Transmit; + // verify # of bytes does not exceed buffer length + if ( bytes2Transmit <= FPGA_WRITE_CMD_BUFFER_LEN ) + { + fpgaDMAWriteControlRecord.FRCNT = bytes2Transmit; + } + else + { + // TODO - s/w fault + } } /************************************************************************* @@ -642,7 +693,15 @@ *************************************************************************/ static void setupDMAForWriteResp( U32 bytes2Receive ) { - fpgaDMAWriteRespControlRecord.FRCNT = bytes2Receive; + // verify # of bytes does not exceed buffer length + if ( bytes2Receive <= FPGA_WRITE_RSP_BUFFER_LEN ) + { + fpgaDMAWriteRespControlRecord.FRCNT = bytes2Receive; + } + else + { + // TODO - s/w fault + } } /************************************************************************* @@ -674,7 +733,15 @@ *************************************************************************/ static void setupDMAForReadCmd( U32 bytes2Transmit ) { - fpgaDMAReadControlRecord.FRCNT = bytes2Transmit; + // verify # of bytes does not exceed buffer length + if ( bytes2Transmit <= FPGA_READ_CMD_BUFFER_LEN ) + { + fpgaDMAReadControlRecord.FRCNT = bytes2Transmit; + } + else + { + // TODO - s/w fault + } } /************************************************************************* @@ -706,7 +773,15 @@ *************************************************************************/ static void setupDMAForReadResp( U32 bytes2Receive ) { - fpgaDMAReadRespControlRecord.FRCNT = bytes2Receive; + // verify # of bytes does not exceed buffer length + if ( bytes2Receive <= FPGA_READ_RSP_BUFFER_LEN ) + { + fpgaDMAReadRespControlRecord.FRCNT = bytes2Receive; + } + else + { + // TODO - s/w fault + } } /*************************************************************************