Index: firmware/App/Services/SystemComm.c =================================================================== diff -u -r5bfaf341319b9fd763d07ad0a68a986028c37587 -re0af40e2557c9f9c4fd9f97e909b3cccdc2d15fe --- firmware/App/Services/SystemComm.c (.../SystemComm.c) (revision 5bfaf341319b9fd763d07ad0a68a986028c37587) +++ firmware/App/Services/SystemComm.c (.../SystemComm.c) (revision e0af40e2557c9f9c4fd9f97e909b3cccdc2d15fe) @@ -8,7 +8,7 @@ * @file SystemComm.c * * @author (last) Dara Navaei -* @date (last) 09-Nov-2021 +* @date (last) 07-Dec-2021 * * @author (original) Dara Navaei * @date (original) 05-Nov-2019 @@ -37,15 +37,8 @@ #define NUM_OF_CAN_OUT_BUFFERS 5 ///< Number of CAN buffers for transmit #define NUM_OF_CAN_IN_BUFFERS 7 ///< Number of CAN buffers for receiving -#ifndef DEBUG_ENABLED - #define NUM_OF_MSG_IN_BUFFERS 7 ///< Number of Msg buffers for receiving -#else - #define NUM_OF_MSG_IN_BUFFERS 8 - #define SCI1_RECEIVE_DMA_REQUEST 30 - #define SCI1_TRANSMIT_DMA_REQUEST 31 -#endif +#define NUM_OF_MSG_IN_BUFFERS 7 ///< Number of Msg buffers for receiving - #define CAN_XMIT_PACKET_TIMEOUT_MS 200 ///< If transmitted CAN frame does not cause a transmit complete interrupt within this time, re-send or move on #define MAX_XMIT_RETRIES 5 ///< Maximum number of retries on no transmit complete interrupt timeout @@ -56,12 +49,13 @@ #define MAX_COMM_CRC_FAILURE_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< CRC error window #define MSG_NOT_ACKED_TIMEOUT_MS 150 ///< Maximum time for a Denali message that requires ACK to be ACK'd +#define MSG_NOT_ACKED_TIMEOUT_MS_INIT 5000 ///< Maximum time for a Denali message that requires ACK to be ACK'd on the INIT state for the first (UI version request) message of the POST #define MSG_NOT_ACKED_MAX_RETRIES 3 ///< Maximum number of times a message that requires ACK that was not ACK'd can be re-sent before alarm #define PENDING_ACK_LIST_SIZE 25 ///< Maximum number of Denali messages that can be pending ACK at any given time #pragma pack(push, 1) -/// Record for transmitted message that is pending acknowledgement from receiver. +/// Record for transmitted message that is pending acknowledgment from receiver. typedef struct { BOOL used; @@ -97,9 +91,6 @@ COMM_BUFFER_IN_CAN_UI_2_HD, COMM_BUFFER_IN_CAN_UI_BROADCAST, COMM_BUFFER_IN_CAN_PC, -#ifdef DEBUG_ENABLED - COMM_BUFFER_IN_UART_PC -#endif }; static U08 lastCANPacketSent[ CAN_MESSAGE_PAYLOAD_SIZE ]; ///< Keep last packet sent on CAN bus in case we need to re-send. @@ -120,16 +111,6 @@ static U32 badCANCount; // Test code in support of EMC testing #endif -#ifdef DEBUG_ENABLED - // Debug buffers - static U08 pcXmitPacket[ 1024 ]; - static U08 pcRecvPacket[ PC_MESSAGE_PACKET_SIZE ] = { 0, 0, 0, 0, 0, 0, 0, 0 }; - - // DMA control records - static g_dmaCTRL pcDMAXmitControlRecord; - static g_dmaCTRL pcDMARecvControlRecord; -#endif - // ********** private function prototypes ********** static void clearCANXmitBuffers( void ); @@ -149,11 +130,6 @@ static BOOL matchACKtoPendingACKList( S16 seqNo ); static void checkPendingACKList( void ); -#ifdef DEBUG_ENABLED - static void initUARTAndDMA( void ); - static U32 transmitNextUARTPacket( void ); -#endif - /*********************************************************************//** * @brief * The initSystemComm function initializes the SystemComm module. @@ -165,11 +141,6 @@ { U32 i; -#ifdef DEBUG_ENABLED - // Initialize UART and DMA for PC communication - initUARTAndDMA(); -#endif - // Initialize bad message CRC time windowed count initTimeWindowedCount( TIME_WINDOWED_COUNT_BAD_MSG_CRC, MAX_COMM_CRC_FAILURES, MAX_COMM_CRC_FAILURE_WINDOW_MS ); @@ -339,14 +310,6 @@ } } } - -#ifdef DEBUG_ENABLED - // If UART transmitter is idle, start transmitting any pending packets - if ( FALSE == isSCI1DMATransmitInProgress() ) - { - transmitNextUARTPacket(); - } -#endif } /*********************************************************************//** @@ -399,113 +362,8 @@ } } -/*********************************************************************//*** - * @brief - * The handleUARTMsgRecvPacketInterrupt function handles a DMA UART receive - * packet completed interrupt. - * @details Inputs: none - * @details Outputs: UART received packet interrupt handled. - * @return none - *************************************************************************/ -#ifdef DEBUG_ENABLED -void handleUARTMsgRecvPacketInterrupt( void ) -{ - // Buffer received packet - addToCommBuffer( COMM_BUFFER_IN_UART_PC, pcRecvPacket, PC_MESSAGE_PACKET_SIZE ); - // Prepare to receive next packet - dmaSetCtrlPacket( DMA_CH1, pcDMARecvControlRecord ); - dmaSetChEnable( DMA_CH1, DMA_HW ); - setSCI1DMAReceiveInterrupt(); -} -#endif - /*********************************************************************//** * @brief - * The handleUARTMsgXmitPacketInterrupt function handles a DMA UART transmit - * packet completed interrupt. - * @details Inputs: none - * @details Outputs: UART transmit packet interrupt handled. - * @return none - *************************************************************************/ -#ifdef DEBUG_ENABLED -void handleUARTMsgXmitPacketInterrupt( void ) -{ - U32 bytesXmitted = transmitNextUARTPacket(); - - if ( 0 == bytesXmitted ) - { - signalSCI1XmitsCompleted(); - } -} -#endif - -/*********************************************************************//** - * @brief - * The initUARTAndDMA function initializes the SCI1 peripheral and the DMA - * to go with it for PC communication. - * @details Inputs: none - * @details Outputs: SCI1 and DMA initialized - * @return none - *************************************************************************/ -#ifdef DEBUG_ENABLED -static void initUARTAndDMA( void ) -{ - // Enable DMA block transfer complete interrupts - dmaEnableInterrupt( DMA_CH1, BTC ); - dmaEnableInterrupt( DMA_CH3, BTC ); - - // Assign DMA channels to h/w DMA requests - dmaReqAssign( DMA_CH1, SCI1_RECEIVE_DMA_REQUEST ); - dmaReqAssign( DMA_CH3, SCI1_TRANSMIT_DMA_REQUEST ); - // Set DMA channel priorities - dmaSetPriority( DMA_CH1, HIGHPRIORITY ); - dmaSetPriority( DMA_CH3, LOWPRIORITY ); - - // Initialize PC DMA Transmit Control Record - pcDMAXmitControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) - pcDMAXmitControlRecord.DADD = (U32)(&(sciREG->TD)); // Dest. is SCI2 xmit register - pcDMAXmitControlRecord.SADD = (U32)pcXmitPacket; // Source - pcDMAXmitControlRecord.CHCTRL = 0; // No chaining - pcDMAXmitControlRecord.ELCNT = 1; // Frame is 1 element - pcDMAXmitControlRecord.FRCNT = PC_MESSAGE_PACKET_SIZE; // Block is 8 frames - pcDMAXmitControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte - pcDMAXmitControlRecord.WRSIZE = ACCESS_8_BIT; // - pcDMAXmitControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer - pcDMAXmitControlRecord.ADDMODEWR = ADDR_FIXED; // Dest. addressing mode is fixed - pcDMAXmitControlRecord.ADDMODERD = ADDR_INC1; // Source addressing mode is post-increment - pcDMAXmitControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off - pcDMAXmitControlRecord.ELSOFFSET = 0; // Not used - pcDMAXmitControlRecord.ELDOFFSET = 0; // Not used - pcDMAXmitControlRecord.FRSOFFSET = 0; // Not used - pcDMAXmitControlRecord.FRDOFFSET = 0; // Not used - - // Initialize PC DMA Receipt Control Record - pcDMARecvControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) - pcDMARecvControlRecord.SADD = (U32)(&(sciREG->RD)); // Source is SCI2 recv register - pcDMARecvControlRecord.DADD = (U32)pcRecvPacket; // Transfer destination address - pcDMARecvControlRecord.CHCTRL = 0; // No chaining - pcDMARecvControlRecord.ELCNT = 1; // Frame is 1 element - pcDMARecvControlRecord.FRCNT = PC_MESSAGE_PACKET_SIZE; // Block is 8 frames - pcDMARecvControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte - pcDMARecvControlRecord.WRSIZE = ACCESS_8_BIT; // - pcDMARecvControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer - pcDMARecvControlRecord.ADDMODERD = ADDR_FIXED; // Source addressing mode is fixed - pcDMARecvControlRecord.ADDMODEWR = ADDR_INC1; // Dest. addressing mode is post-increment - pcDMARecvControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off - pcDMARecvControlRecord.ELDOFFSET = 0; // Not used - pcDMARecvControlRecord.ELSOFFSET = 0; // Not used - pcDMARecvControlRecord.FRDOFFSET = 0; // Not used - pcDMARecvControlRecord.FRSOFFSET = 0; // Not used - - // Initiate PC packet receiving readiness via DMA - dmaSetCtrlPacket( DMA_CH1, pcDMARecvControlRecord ); - dmaSetChEnable( DMA_CH1, DMA_HW ); - setSCI1DMAReceiveInterrupt(); -} -#endif - -/*********************************************************************//** - * @brief * The isCANBoxForXmit function determines whether a given CAN message box * is configured for transmit. * @details Inputs: CAN_OUT_BUFFERS[] @@ -654,39 +512,7 @@ return result; } -/*********************************************************************//** - * @brief - * The transmitNextUARTPacket function sets up and initiates a DMA transmit - * of the next packet pending transmit (if any) via UART. - * @details Inputs: Output UART Comm Buffer(s) - * @details Outputs: UART DMA transmit initiated. - * @return number of bytes transmitted - *************************************************************************/ -#ifdef DEBUG_ENABLED -static U32 transmitNextUARTPacket( void ) -{ - U32 result = 0; - U32 dataPend = numberOfBytesInCommBuffer( COMM_BUFFER_OUT_UART_PC ); - if ( dataPend > 0 ) - { - result = getFromCommBuffer( COMM_BUFFER_OUT_UART_PC, pcXmitPacket, dataPend ); - - // If there is data to transmit, transmit it - if ( result > 0 ) - { - signalSCI1XmitsInitiated(); - pcDMAXmitControlRecord.FRCNT = result; // Set DMA transfer size - dmaSetCtrlPacket( DMA_CH3, pcDMAXmitControlRecord ); - dmaSetChEnable( DMA_CH3, DMA_HW ); - setSCI1DMATransmitInterrupt(); - } - } - - return result; -} -#endif - /************************************************************************* ********************** RECEIVE SUPPORT FUNCTIONS ************************* *************************************************************************/ @@ -1046,8 +872,13 @@ // Find expired messages pending ACK for ( i = 0; i < PENDING_ACK_LIST_SIZE; i++ ) - { // Pending ACK expired? - if ( ( TRUE == pendingAckList[ i ].used ) && ( TRUE == didTimeout( pendingAckList[ i ].timeStamp, MSG_NOT_ACKED_TIMEOUT_MS ) ) ) + { // Pending ACK expired? + U32 timeoutPeriod = MSG_NOT_ACKED_TIMEOUT_MS; // set the timeout as default + if ( MODE_INIT == getCurrentOperationMode() ) + { // change it to longer timeout if the HD is in INIT state + timeoutPeriod = MSG_NOT_ACKED_TIMEOUT_MS_INIT; + } + if ( ( TRUE == pendingAckList[ i ].used ) && ( TRUE == didTimeout( pendingAckList[ i ].timeStamp, timeoutPeriod ) ) ) { // If retries left, reset and resend pending message if ( pendingAckList[ i ].retries > 0 ) { // Re-queue message for transmit @@ -1156,7 +987,7 @@ handleDGOpMode( message ); break; - case MSG_ID_DG_RESERVOIR_DATA: + case MSG_ID_DG_RESERVOIRS_DATA: handleDGReservoirData( message ); break; @@ -1304,6 +1135,10 @@ handleStopHDRTCClock( message ); break; + case MSG_ID_DG_CONCENTRATE_MIXING_RATIOS_DATA: + handleDGMixingRatios( message ); + break; + // NOTE: this always must be the last case case MSG_ID_TESTER_LOGIN_REQUEST: handleTesterLogInRequest( message );