Index: firmware/App/Tasks/TaskGeneral.c =================================================================== diff -u -r408e6e577818831b985f28e6bf777cd9f65b9849 -re20e8cd14d3965560e5ff38835270ef541e5abe6 --- firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision 408e6e577818831b985f28e6bf777cd9f65b9849) +++ firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision e20e8cd14d3965560e5ff38835270ef541e5abe6) @@ -53,37 +53,39 @@ // PLEASE DO NOT REVIEW THIS CODE // Used 120 and 200 so it will not read or write during POST static U16 test = 0; - static RTC_RAM_STATUS_T status; + RTC_RAM_STATUS_T status = getRTCRAMStatus(); + RTC_RAM_STATE_T state = getRTCRAMState(); static U16 returndata[5]; - if (test >= 120) + static BOOL readRAM = FALSE; + static U16 data[5]; + + if ( test >=120 && test%120 == 0 ) { - if ( status != RTC_RAM_STATUS_IN_PROGRESS ) + if ( state == RTC_RAM_STATE_READY ) { - static U16 data[5] = {17, 18, 19, 10, 22}; - status = writeToRAM(119, &data[0], 5); + U16 test1 = test/10; + data[0] = test1; + data[1] = test1+1; + data[2] = test1+2; + data[3] = test1+3; + data[4] = test1+4; + status = writeToRAM(122, &data[0], 5); } - else if ( status == RTC_RAM_STATUS_IN_PROGRESS ) + } + + if ( test >= 120 && test%133 == 0 ) + { + if ( state == RTC_RAM_STATE_READY ) { - status = getRTCRAMState(); + readFromRAM(122, 5); + readRAM = TRUE; } - else - { - test = 0; - //status = RTC_RAM_READY; - } } - if (test == 200) + else if ( status == RTC_RAM_STATUS_IDLE && readRAM) { - readFromRAM(9, 5); - } - if ( test == 220 ) - { getDataFromRAM(&returndata[0], 5); + readRAM = FALSE; } - /*if (test == 140) - { - setRTCTimestamp(0, 46, 13, 17, 12, 2019); - }*/ test++; // FOR DEBUGGING PURPOSES ONLY REMOVE // PLEASE DO NOT REVIEW THIS CODE