Index: firmware/source/etpwm.c
===================================================================
diff -u -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 -ref0b3f0ec00fadc50f95e0db1a6477fb4b076ea1
--- firmware/source/etpwm.c	(.../etpwm.c)	(revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3)
+++ firmware/source/etpwm.c	(.../etpwm.c)	(revision ef0b3f0ec00fadc50f95e0db1a6477fb4b076ea1)
@@ -177,13 +177,13 @@
     etpwmREG2->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG2->TBPRD = 1000U;
+    etpwmREG2->TBPRD = 25833U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG2->CMPA = 50U;
+    etpwmREG2->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG2->CMPB = 50U;
+    etpwmREG2->CMPB = 12917U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG2->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -202,7 +202,7 @@
                       | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                       | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                       | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                      | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                      | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                       | (uint16)((uint16)0U << 0U));   /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -217,7 +217,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG2->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
-                      | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                      | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                       | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                       | (uint16)((uint16)0U << 5U));  /* Chopping Clock Frequency */
 
@@ -272,13 +272,13 @@
     etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG3->TBPRD = 1000U;
+    etpwmREG3->TBPRD = 25833U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG3->CMPA = 50U;
+    etpwmREG3->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG3->CMPB = 50U;
+    etpwmREG3->CMPB = 12917U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG3->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -297,7 +297,7 @@
                       | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                       | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                       | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                      | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                      | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                       | (uint16)((uint16)0U << 0U));   /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -312,7 +312,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG3->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
-                      | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                      | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                       | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                       | (uint16)((uint16)0U << 5U));  /* Chopping Clock Frequency */