Index: firmware/source/etpwm.c
===================================================================
diff -u -ref0b3f0ec00fadc50f95e0db1a6477fb4b076ea1 -ra74a984a7059f75d86ad87d6d9499bd8f94cc976
--- firmware/source/etpwm.c	(.../etpwm.c)	(revision ef0b3f0ec00fadc50f95e0db1a6477fb4b076ea1)
+++ firmware/source/etpwm.c	(.../etpwm.c)	(revision a74a984a7059f75d86ad87d6d9499bd8f94cc976)
@@ -183,7 +183,7 @@
     etpwmREG2->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG2->CMPB = 12917U;
+    etpwmREG2->CMPB = 0U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG2->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -278,7 +278,7 @@
     etpwmREG3->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG3->CMPB = 12917U;
+    etpwmREG3->CMPB = 0U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG3->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -368,13 +368,13 @@
     etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG4->TBPRD = 1000U;
+    etpwmREG4->TBPRD = 102U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG4->CMPA = 50U;
+    etpwmREG4->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG4->CMPB = 50U;
+    etpwmREG4->CMPB = 0U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -393,7 +393,7 @@
                      | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                      | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                      | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                     | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                     | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                      | (uint16)((uint16)0U << 0U);    /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -408,7 +408,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U)  /* Enable/Disable chopper module */
-                     | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                     | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                      | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                      | (uint16)((uint16)0U << 5U);   /* Chopping Clock Frequency */
 
@@ -463,13 +463,13 @@
     etpwmREG6->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG6->TBPRD = 1000U;
+    etpwmREG6->TBPRD = 102U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG6->CMPA = 50U;
+    etpwmREG6->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG6->CMPB = 50U;
+    etpwmREG6->CMPB = 0U;
 
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
@@ -489,7 +489,7 @@
                      | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                      | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                      | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                     | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                     | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                      | (uint16)((uint16)0U << 0U);    /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -504,7 +504,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG6->PCCTL = (uint16)((uint16)0U << 0U)  /* Enable/Disable chopper module */
-                     | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                     | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                      | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                      | (uint16)((uint16)0U << 5U);   /* Chopping Clock Frequency */
 
@@ -561,13 +561,13 @@
     etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG7->TBPRD = 1000U;
+    etpwmREG7->TBPRD = 102U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG7->CMPA = 50U;
+    etpwmREG7->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG7->CMPB = 50U;
+    etpwmREG7->CMPB = 0U;
 
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
@@ -587,7 +587,7 @@
                      | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                      | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                      | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                     | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                     | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                      | (uint16)((uint16)0U << 0U);    /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -602,7 +602,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U)  /* Enable/Disable chopper module */
-                     | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                     | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                      | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                      | (uint16)((uint16)0U << 5U);   /* Chopping Clock Frequency */