Index: firmware/source/mibspi.c
===================================================================
diff -u -r172b320a1007769c7452fe3f1cc7ac85b016f89a -r7a34213f25ce25594311b77a3d003c1e65293a60
--- firmware/source/mibspi.c	(.../mibspi.c)	(revision 172b320a1007769c7452fe3f1cc7ac85b016f89a)
+++ firmware/source/mibspi.c	(.../mibspi.c)	(revision 7a34213f25ce25594311b77a3d003c1e65293a60)
@@ -1432,7 +1432,7 @@
                     | (uint32)((uint32)0U << 27U); /* SOMI[3] */
 
     /** - MIBSPI5 Port direction */
-    mibspiREG5->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+    mibspiREG5->PC1 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
                     | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)1U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)1U << 3U)  /* SCS[3] */
@@ -1496,7 +1496,7 @@
                     | (uint32)((uint32)0U << 27U); /* SOMI[3] */
 
     /* MIBSPI5 set all pins to functional */
-    mibspiREG5->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+    mibspiREG5->PC0 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
                     | (uint32)((uint32)0U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)0U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)0U << 3U)  /* SCS[3] */