Index: firmware/source/sys_link.cmd
===================================================================
diff -u -r161dc3734f29dcd986683008a01c30114279698b -r1a178aef78168ee358e1326f4fb1daf81df83c17
--- firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 161dc3734f29dcd986683008a01c30114279698b)
+++ firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 1a178aef78168ee358e1326f4fb1daf81df83c17)
@@ -47,6 +47,8 @@
 --retain="*(.intvecs)"
 
 /* USER CODE BEGIN (1) */
+/* IGNORE the generated Memory code, overridden below */
+#if 0
 /* USER CODE END */
 
 /*----------------------------------------------------------------------------*/
@@ -55,23 +57,52 @@
 MEMORY
 {
     VECTORS (X)  : origin=0x00000000 length=0x00000020
+    FLASH0  (RX) : origin=0x00000020 length=0x0013FFE0
+    STACKS  (RW) : origin=0x08000000 length=0x00003400
+    RAM     (RW) : origin=0x08003400 length=0x0002cc00
+
+/* USER CODE BEGIN (2) */
+#endif
+/* Override Memory Segments with CRC here */
+#if 1
+MEMORY
+{
+    VECTORS (X)  : origin=0x00000000 length=0x00000020
     CRCMEM  (RX) : origin=0x00000020 length=0x000001E0
     FLASH0  (RX) : origin=0x00000200 length=0x0013FE00
-    STACKS  (RW) : origin=0x08000000 length=0x00005800
-    RAM     (RW) : origin=0x08005800 length=0x0002a800
+    STACKS  (RW) : origin=0x08000000 length=0x00003400
+    RAM     (RW) : origin=0x08003400 length=0x0002cc00
 
-/* USER CODE BEGIN (2) */
+#endif
 /* USER CODE END */
 }
 
 /* USER CODE BEGIN (3) */
+/* IGNORE the generated Sections code, overridden below */
+#if 0
 /* USER CODE END */
 
 /*----------------------------------------------------------------------------*/
 /* Section Configuration                                                      */
 
 SECTIONS
 {
+    .intvecs : {} > VECTORS
+    .text    : {} > FLASH0 
+    .const   : {} > FLASH0 
+    .cinit   : {} > FLASH0 
+    .pinit   : {} > FLASH0 
+    .bss     : {} > RAM
+    .data    : {} > RAM
+    .sysmem  : {} > RAM
+    
+
+/* USER CODE BEGIN (4) */
+#endif
+/* Override Sections with CRCs here */
+#if 1
+SECTIONS
+{
     .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C )
     .text    : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
     .const   : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
@@ -80,10 +111,9 @@
     .bss     : {} > RAM
     .data    : {} > RAM
     .sysmem  : {} > RAM
-    
 
-/* USER CODE BEGIN (4) */
-	.TI.crctab : {} > CRCMEM
+    .TI.crctab : {} > CRCMEM
+#endif
 /* USER CODE END */
 }