Index: firmware/source/sys_link.cmd =================================================================== diff -u -r1a178aef78168ee358e1326f4fb1daf81df83c17 -r1addb5d7e52e17879db2c1f87b864cd5489b7ef7 --- firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 1a178aef78168ee358e1326f4fb1daf81df83c17) +++ firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 1addb5d7e52e17879db2c1f87b864cd5489b7ef7) @@ -1,129 +1,160 @@ -/*----------------------------------------------------------------------------*/ -/* sys_link.cmd */ -/* */ -/* -* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -/* */ -/*----------------------------------------------------------------------------*/ -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - - -/*----------------------------------------------------------------------------*/ -/* Linker Settings */ - ---retain="*(.intvecs)" - -/* USER CODE BEGIN (1) */ -/* IGNORE the generated Memory code, overridden below */ -#if 0 -/* USER CODE END */ - -/*----------------------------------------------------------------------------*/ -/* Memory Map */ - -MEMORY -{ - VECTORS (X) : origin=0x00000000 length=0x00000020 - FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 - STACKS (RW) : origin=0x08000000 length=0x00003400 - RAM (RW) : origin=0x08003400 length=0x0002cc00 - -/* USER CODE BEGIN (2) */ -#endif -/* Override Memory Segments with CRC here */ -#if 1 -MEMORY -{ - VECTORS (X) : origin=0x00000000 length=0x00000020 - CRCMEM (RX) : origin=0x00000020 length=0x000001E0 - FLASH0 (RX) : origin=0x00000200 length=0x0013FE00 - STACKS (RW) : origin=0x08000000 length=0x00003400 - RAM (RW) : origin=0x08003400 length=0x0002cc00 - -#endif -/* USER CODE END */ -} - -/* USER CODE BEGIN (3) */ -/* IGNORE the generated Sections code, overridden below */ -#if 0 -/* USER CODE END */ - -/*----------------------------------------------------------------------------*/ -/* Section Configuration */ - -SECTIONS -{ - .intvecs : {} > VECTORS - .text : {} > FLASH0 - .const : {} > FLASH0 - .cinit : {} > FLASH0 - .pinit : {} > FLASH0 - .bss : {} > RAM - .data : {} > RAM - .sysmem : {} > RAM - - -/* USER CODE BEGIN (4) */ -#endif -/* Override Sections with CRCs here */ -#if 1 -SECTIONS -{ - .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C ) - .text : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) - .const : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) - .cinit : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) - .pinit : {} > FLASH0 - .bss : {} > RAM - .data : {} > RAM - .sysmem : {} > RAM - - .TI.crctab : {} > CRCMEM -#endif -/* USER CODE END */ -} - -/* USER CODE BEGIN (5) */ -/* USER CODE END */ - - -/*----------------------------------------------------------------------------*/ -/* Misc */ - -/* USER CODE BEGIN (6) */ -/* USER CODE END */ -/*----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/* sys_link.cmd */ +/* */ +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/* */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + +/*----------------------------------------------------------------------------*/ +/* Linker Settings */ + +--retain="*(.intvecs)" + +/* USER CODE BEGIN (1) */ +/* IGNORE the generated Memory code, overridden below */ +#if 0 +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Memory Map */ + +MEMORY +{ + VECTORS (X) : origin=0x00000000 length=0x00000020 + FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 + STACKS (RW) : origin=0x08000000 length=0x00005800 + RAM (RW) : origin=0x08005800 length=0x0002a800 + +/* USER CODE BEGIN (2) */ +#endif +/* Override Memory Segments with CRC here */ +#if 1 +MEMORY +{ + VECTORS (X) : origin=0x00010000 + length=0x00000020 + vfill = 0xffffffff + + CRCMEM (RX) : origin=end(VECTORS) + length=0x000001E0 + vfill = 0xffffffff + + FLASH0 (RX) : origin=end(CRCMEM) + length=(0x0013FFFF - end(CRCMEM)) + vfill = 0xffffffff + + STACKS (RW) : origin=0x08000000 + length=0x00004c00 + + RAM (RW) : origin=0x08004c00 + length=0x0002b400 +#endif +#if 1 + ECC_VEC (R) : origin=(0xf0400000 + (start(VECTORS) >> 3)) + length=(size(VECTORS) >> 3) + ECC={algorithm=algoL2R4F021, input_range=VECTORS} + + ECC_CRC (R) : origin=(0xf0400000 + (start(CRCMEM) >> 3)) + length=(size(CRCMEM) >> 3) + ECC={algorithm=algoL2R4F021, input_range=CRCMEM } + + ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0) >> 3)) + length=(size(FLASH0) >> 3) + ECC={algorithm=algoL2R4F021, input_range=FLASH0 } +#endif +/* USER CODE END */ +} + +/* USER CODE BEGIN (3) */ +/* IGNORE the generated Sections code, overridden below */ +ECC +{ + algoL2R4F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */ + hamming_mask = R4 /* Use R4/R5 build in Mask */ + parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */ + mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */ +} +#if 0 +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Section Configuration */ + +SECTIONS +{ + .intvecs : {} > VECTORS + .text : {} > FLASH0 + .const : {} > FLASH0 + .cinit : {} > FLASH0 + .pinit : {} > FLASH0 + .bss : {} > RAM + .data : {} > RAM + .sysmem : {} > RAM + + +/* USER CODE BEGIN (4) */ +#endif +/* Override Sections with CRCs here */ +#if 1 +SECTIONS +{ + .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C ) + .text align(64) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .const align(64) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .cinit align(64) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .pinit align(64) : {} > FLASH0 + .bss : {} > RAM + .data : {} > RAM + .sysmem : {} > RAM + + .TI.crctab : {} > CRCMEM +#endif +/* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + +/*----------------------------------------------------------------------------*/ +/* Misc */ + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ +/*----------------------------------------------------------------------------*/