Index: firmware/source/sys_link.cmd
===================================================================
diff -u -r6311eb9b65fdeec7a285d25e07f3932ac0fb6cf1 -r1a178aef78168ee358e1326f4fb1daf81df83c17
--- firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 6311eb9b65fdeec7a285d25e07f3932ac0fb6cf1)
+++ firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 1a178aef78168ee358e1326f4fb1daf81df83c17)
@@ -47,6 +47,8 @@
 --retain="*(.intvecs)"
 
 /* USER CODE BEGIN (1) */
+/* IGNORE the generated Memory code, overridden below */
+#if 0
 /* USER CODE END */
 
 /*----------------------------------------------------------------------------*/
@@ -56,14 +58,28 @@
 {
     VECTORS (X)  : origin=0x00000000 length=0x00000020
     FLASH0  (RX) : origin=0x00000020 length=0x0013FFE0
-    STACKS  (RW) : origin=0x08000000 length=0x00003800
-    RAM     (RW) : origin=0x08003800 length=0x0002c800
+    STACKS  (RW) : origin=0x08000000 length=0x00003400
+    RAM     (RW) : origin=0x08003400 length=0x0002cc00
 
 /* USER CODE BEGIN (2) */
+#endif
+/* Override Memory Segments with CRC here */
+#if 1
+MEMORY
+{
+    VECTORS (X)  : origin=0x00000000 length=0x00000020
+    CRCMEM  (RX) : origin=0x00000020 length=0x000001E0
+    FLASH0  (RX) : origin=0x00000200 length=0x0013FE00
+    STACKS  (RW) : origin=0x08000000 length=0x00003400
+    RAM     (RW) : origin=0x08003400 length=0x0002cc00
+
+#endif
 /* USER CODE END */
 }
 
 /* USER CODE BEGIN (3) */
+/* IGNORE the generated Sections code, overridden below */
+#if 0
 /* USER CODE END */
 
 /*----------------------------------------------------------------------------*/
@@ -82,6 +98,22 @@
     
 
 /* USER CODE BEGIN (4) */
+#endif
+/* Override Sections with CRCs here */
+#if 1
+SECTIONS
+{
+    .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C )
+    .text    : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
+    .const   : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
+    .cinit   : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
+    .pinit   : {} > FLASH0
+    .bss     : {} > RAM
+    .data    : {} > RAM
+    .sysmem  : {} > RAM
+
+    .TI.crctab : {} > CRCMEM
+#endif
 /* USER CODE END */
 }