Index: firmware/source/sys_startup.c
===================================================================
diff -u -r6623684ddacf5beebd15bce8a1dbd06a442fb38e -rd2dfbe0338029375e84218c3f090f1971d9878ae
--- firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 6623684ddacf5beebd15bce8a1dbd06a442fb38e)
+++ firmware/source/sys_startup.c	(.../sys_startup.c)	(revision d2dfbe0338029375e84218c3f090f1971d9878ae)
@@ -120,19 +120,7 @@
      * by its ECC logic for accesses to program flash or data RAM.
      */
     _coreEnableEventBusExport_();
-/* USER CODE BEGIN (9) */
-/* USER CODE END */
 
-    /* Enable response to ECC errors indicated by CPU for accesses to flash */
-    flashWREG->FEDACCTRL1 = 0x000A060AU;
-
-/* USER CODE BEGIN (10) */
-/* USER CODE END */
-
-    /* Enable CPU ECC checking for ATCM (flash accesses) */
-    _coreEnableFlashEcc_();
-	
-
 /* USER CODE BEGIN (11) */
 /* USER CODE END */
 
@@ -253,6 +241,9 @@
     if ((esmREG->SR1[2]) != 0U)
     {
 /* USER CODE BEGIN (24) */
+        const uint32_t testVal = (esmREG->SR1[2]);
+        esmREG->EKR = 0x5;
+#if 1
 /* USER CODE END */
     /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
     /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
@@ -261,6 +252,7 @@
         { 
         }/* Wait */                 
 /* USER CODE BEGIN (25) */
+#endif
 /* USER CODE END */
     }
 
@@ -385,26 +377,6 @@
 /* USER CODE BEGIN (37) */
 /* USER CODE END */
 
-
-    /* Initialize CPU RAM.
-     * This function uses the system module's hardware for auto-initialization of memories and their
-     * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
-     * Hence the value 0x1 passed to the function.
-     * This function will initialize the entire CPU RAM and the corresponding ECC locations.
-     */
-    memoryInit(0x1U);
-
-/* USER CODE BEGIN (38) */
-/* USER CODE END */
-    
-    /* Enable ECC checking for TCRAM accesses.
-     * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
-     */
-    _coreEnableRamEcc_();
-
-/* USER CODE BEGIN (39) */
-/* USER CODE END */
-
     /* Start PBIST on all dual-port memories */
     /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
        PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
@@ -431,18 +403,6 @@
 
 /* USER CODE BEGIN (40) */
 /* USER CODE END */
-
-    /* Test the CPU ECC mechanism for RAM accesses.
-     * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
-     * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
-     * in the ECC causes a data abort exception. The data abort handler is written to look for
-     * deliberately caused exception and to return the code execution to the instruction
-     * following the one that caused the abort.
-     */
-    checkRAMECC();
-
-/* USER CODE BEGIN (41) */
-/* USER CODE END */
 /* USER CODE BEGIN (43) */
 /* USER CODE END */