Index: firmware/source/system.c
===================================================================
diff -u -reb877ae36c28eb83553ee11ccccf42e2c4a5b4d2 -r27eb0bf7706076503c31aa87d3f6fbc8cef39801
--- firmware/source/system.c	(.../system.c)	(revision eb877ae36c28eb83553ee11ccccf42e2c4a5b4d2)
+++ firmware/source/system.c	(.../system.c)	(revision 27eb0bf7706076503c31aa87d3f6fbc8cef39801)
@@ -104,7 +104,7 @@
                         |  (uint32)((uint32)0x1FU << 24U)
                         |  (uint32)0x00000000U
                         |  (uint32)((uint32)(6U - 1U)<< 16U)
-                        |  (uint32)(0x9A00U);
+                        |  (uint32)(0x9B00U);
 
     /**   - Setup pll control register 2
     *     - Setup spreading rate
@@ -305,7 +305,7 @@
 
     /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
     systemREG1->VCLKASRC = (uint32)((uint32)SYS_VCLK << 8U)
-                         | (uint32)((uint32)SYS_VCLK << 0U);
+                         | (uint32)((uint32)SYS_OSC << 0U);
 
     /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
     systemREG1->CLKCNTL  = (systemREG1->CLKCNTL & 0xF0FFFFFFU)