Index: source/sys_main.c =================================================================== diff -u -rcb47c5f896477ceae7597cb1a4191b3972e93f0d -r38ff7a6fbf82b86ab1bac3b7b24c4ea33d5419f9 --- source/sys_main.c (.../sys_main.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) +++ source/sys_main.c (.../sys_main.c) (revision 38ff7a6fbf82b86ab1bac3b7b24c4ea33d5419f9) @@ -127,6 +127,8 @@ canInit(); // CAN1 = CAN, re-purposing CAN2 and CAN3 Rx and Tx pins as GPIO sciInit(); // SCI1 used for PC serial interface, SCI2 used for FPGA serial interface dmaEnable(); // enable DMA +// sciEnableLoopback( sciREG, Digital_Lbk ); // TODO - for test only +// sciEnableLoopback( scilinREG, Digital_Lbk ); // TODO - for test only } /************************************************************************* @@ -184,58 +186,4 @@ _enable_IRQ(); } -void sciNotification(sciBASE_t *sci, uint32 flags) -{ - static U32 fErrorCnt = 0; - static U32 oErrorCnt = 0; - - if ( ( flags & SCI_FE_INT ) != 0 ) - { - fErrorCnt++; - } - if ( ( flags & SCI_OE_INT ) != 0 ) - { - oErrorCnt++; - } -} - -void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) -{ - if ( inttype == BTC ) - { - switch ( channel ) - { - case DMA_CH0: - // clear DMA receipt - scilinREG->CLEARINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ - scilinREG->CLEARINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ - break; - - case DMA_CH1: - // clear DMA receipt - sciREG->CLEARINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ - sciREG->CLEARINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ - // handle received packet from PC - handleUARTMsgRecvPacketInterrupt(); - break; - - case DMA_CH2: - // clear DMA xmit - scilinREG->CLEARINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ - break; - - case DMA_CH3: - // clear DMA xmit - sciREG->CLEARINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ - // send next pending packet to PC (if any) - handleUARTMsgXmitPacketInterrupt(); - break; - - default: - // TODO - ignore? - break; - } - } -} - /* USER CODE END */