- | FPGA | initFPGA | NominalPath | 01 NOV 2019 8:08:25 AM | PASS 107 / 107 |
- | | resetFPGACommFlags | NominalPath | 01 NOV 2019 8:08:25 AM | PASS 7 / 7 |
- | | signalFPGAReceiptCompleted | BulkWriteAndReadInProgressAfterWrite | 01 NOV 2019 8:08:25 AM | PASS 11 / 11 |
- | | | NothingInProgress | 01 NOV 2019 8:08:25 AM | PASS 7 / 7 |
- | | | ReadCmdInProgress | 01 NOV 2019 8:08:25 AM | PASS 7 / 7 |
- | | | WriteCmdInProgress | 01 NOV 2019 8:08:25 AM | PASS 7 / 7 |
- | | signalFPGATransmitCompleted | NominalPath | 01 NOV 2019 8:08:26 AM | PASS 7 / 7 |
- | | execFPGAIn | CommErrorTooManyRetries | 01 NOV 2019 8:08:26 AM | PASS 9 / 9 |
- | | | FailedState | 01 NOV 2019 8:08:26 AM | PASS 8 / 8 |
- | | | InvalidState | 01 NOV 2019 8:08:26 AM | PASS 8 / 8 |
- | | | OutgoingState | 01 NOV 2019 8:08:26 AM | PASS 8 / 8 |
- | | | RcvAllSensorsState | 01 NOV 2019 8:10:05 AM | PASS 19 / 19 |
- | | | RcvHeaderState | 01 NOV 2019 8:08:26 AM | PASS 15 / 15 |
- | | | StartState | 01 NOV 2019 8:08:26 AM | PASS 8 / 8 |
- | | execFPGAOut | FailedState | 01 NOV 2019 8:08:27 AM | PASS 1 / 1 |
- | | | IncomingState | 01 NOV 2019 8:08:27 AM | PASS 1 / 1 |
- | | | InvalidState | 01 NOV 2019 8:08:27 AM | PASS 1 / 1 |
- | | | ReadHeaderState | 01 NOV 2019 8:08:27 AM | PASS 19 / 19 |
- | | | WriteAllActuatorsState | 01 NOV 2019 8:08:27 AM | PASS 18 / 18 |
- | | handleFPGAReadHeaderState | NominalCase | 01 NOV 2019 8:08:27 AM | PASS 13 / 13 |
- | | handleFPGAReceiveHeaderState | BadCRC | 01 NOV 2019 8:08:27 AM | PASS 11 / 11 |
- | | | NAKResponse | 01 NOV 2019 8:08:27 AM | PASS 10 / 10 |
- | | | NoResponseReceived | 01 NOV 2019 8:08:28 AM | PASS 10 / 10 |
- | | | NominalCase | 01 NOV 2019 8:08:28 AM | PASS 11 / 11 |
- | | handleFPGAWriteAllActuatorsState | NominalPath | 01 NOV 2019 8:08:28 AM | PASS 25 / 25 |
- | | handleFPGAReceiveAllSensorsState | BadCRC | 01 NOV 2019 8:16:16 AM | PASS 15 / 15 |
- | | | NAKResponse | 01 NOV 2019 8:16:46 AM | PASS 14 / 14 |
- | | | NoResponseReceived | 01 NOV 2019 8:17:21 AM | PASS 14 / 14 |
- | | | NominalPath | 01 NOV 2019 8:08:28 AM | PASS 14 / 14 |
- | | | NoWriteResponseReceived | 01 NOV 2019 8:18:36 AM | PASS 14 / 14 |
- | | execFPGATest | TestFailed | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
- | | | TestPassed | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
- | | setupDMAForWriteCmd | LengthTooLarge | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
- | | | NominalPath | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
- | | startDMAWriteCmd | NominalPath | 01 NOV 2019 8:08:29 AM | PASS 20 / 20 |
- | | setupDMAForWriteResp | LengthTooLarge | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
- | | | NominalPath | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
- | | startDMAReceiptOfWriteResp | NominalPath | 01 NOV 2019 8:08:29 AM | PASS 20 / 20 |
- | | setupDMAForReadCmd | LengthTooLarge | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
- | | | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
- | | startDMAReadCmd | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 20 / 20 |
- | | setupDMAForReadResp | LengthTooLarge | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
- | | | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
- | | startDMAReceiptOfReadResp | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 20 / 20 |
- | | getFPGAId | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
- | | getFPGARev | NominalPath | 01 NOV 2019 8:08:31 AM | PASS 1 / 1 |
- | | getFPGADiag | NominalPath | 01 NOV 2019 8:08:31 AM | PASS 1 / 1 |
- | | getFPGAStatus | NominalPath | 01 NOV 2019 8:08:31 AM | PASS 1 / 1 |
- | | setFPGAControl | NominalPath | 01 NOV 2019 8:08:31 AM | PASS 1 / 1 |
- | | consumeUnexpectedData | DataBytePending | 01 NOV 2019 8:08:31 AM | PASS |
- | | | NoData | 01 NOV 2019 8:08:31 AM | PASS |
- | TOTALS | 25 | 51 | | PASS 51 / 51 |
+ | FPGA | initFPGA | NominalPath | 22 NOV 2019 7:44:48 AM | PASS 116 / 116 |
+ | | resetFPGACommFlags | NominalPath | 22 NOV 2019 7:44:48 AM | PASS 7 / 7 |
+ | | signalFPGAReceiptCompleted | BulkWriteAndReadInProgressAfterWrite | 22 NOV 2019 7:44:48 AM | PASS 11 / 11 |
+ | | | NothingInProgress | 22 NOV 2019 7:44:48 AM | PASS 7 / 7 |
+ | | | ReadCmdInProgress | 22 NOV 2019 7:44:48 AM | PASS 7 / 7 |
+ | | | WriteCmdInProgress | 22 NOV 2019 7:44:48 AM | PASS 7 / 7 |
+ | | signalFPGATransmitCompleted | NominalPath | 22 NOV 2019 7:44:48 AM | PASS 7 / 7 |
+ | | execFPGAIn | CommErrorTooManyRetries | 22 NOV 2019 7:44:48 AM | PASS 9 / 9 |
+ | | | FailedState | 22 NOV 2019 7:44:49 AM | PASS 8 / 8 |
+ | | | InvalidState | 22 NOV 2019 7:53:38 AM | PASS 9 / 9 |
+ | | | OutgoingState | 22 NOV 2019 7:44:49 AM | PASS 8 / 8 |
+ | | | RcvAllSensorsState | 22 NOV 2019 7:44:49 AM | PASS 13 / 13 |
+ | | | RcvHeaderState | 22 NOV 2019 7:44:49 AM | PASS 14 / 14 |
+ | | | StartState | 22 NOV 2019 7:44:49 AM | PASS 8 / 8 |
+ | | execFPGAOut | FailedState | 22 NOV 2019 7:44:49 AM | PASS 1 / 1 |
+ | | | IncomingState | 22 NOV 2019 7:44:50 AM | PASS 1 / 1 |
+ | | | InvalidState | 22 NOV 2019 7:53:57 AM | PASS 2 / 2 |
+ | | | ReadHeaderState | 22 NOV 2019 7:44:50 AM | PASS 19 / 19 |
+ | | | WriteAllActuatorsState | 22 NOV 2019 7:44:50 AM | PASS 18 / 18 |
+ | | handleFPGAReadHeaderState | NominalCase | 22 NOV 2019 7:44:50 AM | PASS 13 / 13 |
+ | | handleFPGAReceiveHeaderState | BadCRC | 22 NOV 2019 7:44:50 AM | PASS 9 / 9 |
+ | | | NAKResponse | 22 NOV 2019 7:44:50 AM | PASS 8 / 8 |
+ | | | NoResponseReceived | 22 NOV 2019 7:44:51 AM | PASS 8 / 8 |
+ | | | NominalCase | 22 NOV 2019 7:44:51 AM | PASS 9 / 9 |
+ | | handleFPGAWriteAllActuatorsState | NominalPath | 22 NOV 2019 7:44:51 AM | PASS 25 / 25 |
+ | | handleFPGAReceiveAllSensorsState | BadCRC | 22 NOV 2019 7:50:43 AM | PASS 6 / 6 |
+ | | | NAKResponse | 22 NOV 2019 7:44:51 AM | PASS 5 / 5 |
+ | | | NoResponseReceived | 22 NOV 2019 7:44:51 AM | PASS 5 / 5 |
+ | | | NoWriteResponseReceived | 22 NOV 2019 7:44:51 AM | PASS 5 / 5 |
+ | | | NominalPath | 22 NOV 2019 7:52:30 AM | PASS 5 / 5 |
+ | | execFPGATest | TestFailed | 22 NOV 2019 7:46:19 AM | PASS 4 / 4 |
+ | | | TestPassed | 22 NOV 2019 7:44:52 AM | PASS 1 / 1 |
+ | | setupDMAForWriteCmd | LengthTooLarge | 22 NOV 2019 7:44:52 AM | PASS 1 / 1 |
+ | | | NominalPath | 22 NOV 2019 7:44:52 AM | PASS 1 / 1 |
+ | | startDMAWriteCmd | NominalPath | 22 NOV 2019 7:44:52 AM | PASS 20 / 20 |
+ | | setupDMAForWriteResp | LengthTooLarge | 22 NOV 2019 7:44:52 AM | PASS 1 / 1 |
+ | | | NominalPath | 22 NOV 2019 7:44:52 AM | PASS 1 / 1 |
+ | | startDMAReceiptOfWriteResp | NominalPath | 22 NOV 2019 7:44:53 AM | PASS 20 / 20 |
+ | | setupDMAForReadCmd | LengthTooLarge | 22 NOV 2019 7:44:53 AM | PASS 1 / 1 |
+ | | | NominalPath | 22 NOV 2019 7:44:53 AM | PASS 1 / 1 |
+ | | startDMAReadCmd | NominalPath | 22 NOV 2019 7:44:53 AM | PASS 20 / 20 |
+ | | setupDMAForReadResp | LengthTooLarge | 22 NOV 2019 7:44:53 AM | PASS 1 / 1 |
+ | | | NominalPath | 22 NOV 2019 7:44:53 AM | PASS 1 / 1 |
+ | | startDMAReceiptOfReadResp | NominalPath | 22 NOV 2019 7:44:53 AM | PASS 20 / 20 |
+ | | getFPGAId | NominalPath | 22 NOV 2019 7:44:54 AM | PASS 1 / 1 |
+ | | getFPGARev | NominalPath | 22 NOV 2019 7:44:54 AM | PASS 1 / 1 |
+ | | getFPGAStatus | NominalPath | 22 NOV 2019 7:44:54 AM | PASS 1 / 1 |
+ | | setFPGAControl | NominalPath | 22 NOV 2019 7:44:54 AM | PASS 1 / 1 |
+ | | getFPGABloodFlow | getFPGABloodFlow_NominalPath | 22 NOV 2019 7:57:41 AM | PASS 1 / 1 |
+ | | getFPGADialysateFlow | getFPGADialysateFlow_NominalPath | 22 NOV 2019 7:58:13 AM | PASS 1 / 1 |
+ | | consumeUnexpectedData | DataBytePending | 22 NOV 2019 7:44:54 AM | PASS |
+ | | | NoData | 22 NOV 2019 7:44:54 AM | PASS |
+ | TOTALS | 26 | 52 | | PASS 52 / 52 |