Index: firmware/App/Controllers/RTC.c =================================================================== diff -u -rdc96b82b3e7b8acde804180b1c5da37bbdafd96d -r408e6e577818831b985f28e6bf777cd9f65b9849 --- firmware/App/Controllers/RTC.c (.../RTC.c) (revision dc96b82b3e7b8acde804180b1c5da37bbdafd96d) +++ firmware/App/Controllers/RTC.c (.../RTC.c) (revision 408e6e577818831b985f28e6bf777cd9f65b9849) @@ -20,6 +20,8 @@ #include "RTC.h" #include "mibspi.h" +// TODO: ADD FUNCTION HEADERS + // ********** Definitions ********** #define RTC_REG_1_12_HOUR_MODE 0X0004 // 12-hour or 24-hour mode @@ -38,23 +40,24 @@ #define RTC_REG_3_BF 0x0008 // RTC registers indices -#define RTC_REG_1_INDEX 1 -#define RTC_REG_2_INDEX 2 -#define RTC_REG_3_INDEX 3 -#define RTC_SECONDS_INDEX 4 -#define RTC_MINUTES_INDEX 5 -#define RTC_HOURS_INDEX 6 -#define RTC_DAYS_INDEX 7 -#define RTC_WEEKDAYS_INDEX 8 -#define RTC_MONTHS_INDEX 9 -#define RTC_YEARS_INDEX 10 -#define BUFFER_INDEX_0 0U -#define BUFFER_INDEX_1 1U -#define BUFFER_INDEX_2 2U -#define BUFFER_INDEX_3 3U -#define BUFFER_INDEX_4 4U +#define RTC_REG_1_INDEX 1U +#define RTC_REG_2_INDEX 2U +#define RTC_REG_3_INDEX 3U +#define RTC_SECONDS_INDEX 4U +#define RTC_MINUTES_INDEX 5U +#define RTC_HOURS_INDEX 6U +#define RTC_DAYS_INDEX 7U +#define RTC_WEEKDAYS_INDEX 8U +#define RTC_MONTHS_INDEX 9U +#define RTC_YEARS_INDEX 10U +#define BUFFER_INDEX_0 0U +#define BUFFER_INDEX_1 1U +#define BUFFER_INDEX_2 2U +#define BUFFER_INDEX_3 3U +#define BUFFER_INDEX_4 4U + // *************** MibSPI values ************* // #define MIBSPI_MAX_BUFFER_LENGTH 127U @@ -72,22 +75,31 @@ #define MIBSPI_LOCK_TRANS_BIT_SHIFT 11U #define MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT 8U #define MIBSPI_BUFFER_TRANS_BIT_SHIFT 8U + +// *************** RTC definitions ************* // + #define RTC_RAM_PREP_BUFFER_LENGTH 3U #define RTC_TIMESTAMP_BUFFER_LENGTH 8U #define RTC_GENERAL_BUFFER_LENGTH 11U +#define RTC_PREP_RAM_INDEX 0U +#define RTC_RAM_HIGH_ADDRESS_INDEX 1U +#define RTC_RAM_LOW_ADDRESS_INDEX 2U +#define RTC_RAM_COMMAND_INDEX 3U +#define RTC_RAM_HIGH_ADDRESS_BIT_SHIFT 8U + #define RTC_READ_FROM_REG0 0x00A0 // RTC read from address 0 #define RTC_WRITE_TO_REG3 0x0023 // Seconds register #define RTC_PREP_RAM_READ_WRITE 0x003A // RTC cmd prior to RAM ops #define RTC_WRITE_TO_RAM 0x003C // RTC RAM write #define RTC_READ_FROM_RAM 0x00BD // RTC RAM read -#define RTC_ACCURACY_TIMEOUT 1000 // ms -#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050 // ms +#define RTC_ACCURACY_TIMEOUT 1000U // ms +#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050U // ms -#define TIMER_COUNTER_TO_REQUEST_READ 18 +#define TIMER_COUNTER_TO_REQUEST_READ 18U -#define MAX_ALLOWED_FAILED_RTC_TRANSFERS 3 +#define MAX_ALLOWED_FAILED_RTC_TRANSFERS 3U #define MAX_ALLOWED_RTC_RAM_BYTES 100U #define MAX_ALLOWED_RTC_RAM_ADDRESS 512U @@ -141,7 +153,8 @@ static RTC_GET_DATA_STATE_T RTCServiceState = RTC_SEND_COMMAND; static RTC_EXEC_STATE_T RTCExecState = RTC_EXEC_STATE_WAIT_FOR_POST; static SELF_TEST_STATUS_T RTCSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; -static RTC_RAM_STATUS_T RTCRAMStatus = RTC_RAM_READY; +static RTC_RAM_STATUS_T RTCRAMStatus = RTC_RAM_STATUS_COMPLETE; +static RTC_RAM_STATE_T RTCRAMState = RTC_RAM_STATE_READY; static RTC_TIMESTAMP_T RTCTimestampStruct; static U32 RTCSelfTestTimer = 0; @@ -190,16 +203,34 @@ // ********** Public functions ********** +/************************************************************************* + * @brief initRTC + * The initRTC initializes the RTC + * @details + * Inputs : none + * Outputs : The function is empty for now + * @param none + * @return none + *************************************************************************/ void initRTC() { // Do nothing for now } +/************************************************************************* + * @brief setRTCTimestamp + * The setRTCTimestamp gets the timestamp values, converts them into BCD + * and inserts them into the txBuffer to be written into the RTC + * @details + * Inputs : seconds, minutes, hours, days, months, years + * Outputs : txBuffer will be prepared with the timestamp + * @param none + * @return none + *************************************************************************/ void setRTCTimestamp( U08 secs, U08 mins, U08 hours, U08 days, U08 months, U16 years ) { hasWriteToRTCRequested = TRUE; - // TODO: Remove these variables U16 decimalSeconds = convertDecimal2BCD( secs ); U16 decimalMins = convertDecimal2BCD( mins ); U16 decimalHours = convertDecimal2BCD( hours ); @@ -217,7 +248,16 @@ txBuffer[7] = convertDecimal2BCD( years - 2000 ); } -SELF_TEST_STATUS_T execRTCSelfTest( void ) +/************************************************************************* + * @brief execRTCSelfTest + * The execRTCSelfTest runs the RTC POST during the self test + * @details + * Inputs : none + * Outputs : SELF_TEST_STATUS_T + * @param none + * @return SELF_TEST_STATUS_T + *************************************************************************/ +SELF_TEST_STATUS_T execRTCSelfTest() { switch ( RTCSelfTestState ) { @@ -249,6 +289,7 @@ case RTC_SELF_TEST_STATE_COMPLETE: // Done with the state + // TODO: If POST failed, set the proper alarm break; default: @@ -261,6 +302,15 @@ return RTCSelfTestResult; } +/************************************************************************* + * @brief execRTC + * The execRTC runs the RTC during normal operations + * @details + * Inputs : none + * Outputs : none + * @param none + * @return none + *************************************************************************/ void execRTC() { switch ( RTCExecState ) @@ -311,6 +361,7 @@ } } +// TODO: Make this a const U32 getRTCTimestamp() { return lastEpochTime; @@ -320,28 +371,30 @@ { RTC_RAM_STATUS_T status = RTCRAMStatus; - if ( status == RTC_RAM_READY ) + if ( status == RTC_RAM_STATUS_IDLE ) { if ( address > MAX_ALLOWED_RTC_RAM_ADDRESS ) { - status = RTC_RAM_ILLEGAL_ADDRESS; + status = RTC_RAM_STATUS_ILLEGAL_ADDRESS; } else if ( length > MAX_ALLOWED_RTC_RAM_BYTES ) { - status = RTC_RAM_BYTES_EXCEEDED; + status = RTC_RAM_STATUS_BYTES_EXCEEDED; } else { - RTCRAMStatus = status = RTC_RAM_IN_PROGRESS; + RTCRAMStatus = status = RTC_RAM_STATUS_IN_PROGRESS; + RTCRAMState = RTC_RAM_STATE_BUSY; + hasWriteToRAMRequested = TRUE; RAMBufferLength = length; - txBuffer[ BUFFER_INDEX_0 ] = RTC_PREP_RAM_READ_WRITE; - txBuffer[ BUFFER_INDEX_1 ] = ( address >> 8 ); - txBuffer[ BUFFER_INDEX_2 ] = ( address & 0x00FF ); - txBuffer[ BUFFER_INDEX_3 ] = RTC_WRITE_TO_RAM; + txBuffer[ RTC_PREP_RAM_INDEX ] = RTC_PREP_RAM_READ_WRITE; + txBuffer[ RTC_RAM_HIGH_ADDRESS_INDEX ] = ( address >> RTC_RAM_HIGH_ADDRESS_BIT_SHIFT ); + txBuffer[ RTC_RAM_LOW_ADDRESS_INDEX ] = ( address & 0x00FF ); + txBuffer[ RTC_RAM_COMMAND_INDEX ] = RTC_WRITE_TO_RAM; U08 i; @@ -352,51 +405,36 @@ } } } - else if ( status == RTC_RAM_IN_PROGRESS ) - { - U16 currentAddress = 0; - currentAddress = ( ~currentAddress & txBuffer[ BUFFER_INDEX_1 ] ) << 8; - currentAddress = ~currentAddress & txBuffer[ BUFFER_INDEX_2 ]; - if ( currentAddress == address ) - { - status = RTC_RAM_IN_PROGRESS; - } - else - { - status = RTC_RAM_BUSY; - } - } - return status; } RTC_RAM_STATUS_T readFromRAM( U16 address, U32 length ) { RTC_RAM_STATUS_T status = RTCRAMStatus; - if ( status == RTC_RAM_READY ) + if ( status == RTC_RAM_STATUS_IDLE ) { if ( address > MAX_ALLOWED_RTC_RAM_ADDRESS ) { - status = RTC_RAM_ILLEGAL_ADDRESS; + status = RTC_RAM_STATUS_ILLEGAL_ADDRESS; } else if ( length > MAX_ALLOWED_RTC_RAM_BYTES ) { - status = RTC_RAM_BYTES_EXCEEDED; + status = RTC_RAM_STATUS_BYTES_EXCEEDED; } else { - status = RTCRAMStatus = RTC_RAM_BUSY; + status = RTCRAMStatus = RTC_RAM_STATUS_IN_PROGRESS; hasReadFromRAMRequested = TRUE; RAMBufferLength = length; - txBuffer[ BUFFER_INDEX_0 ] = RTC_PREP_RAM_READ_WRITE; - txBuffer[ BUFFER_INDEX_1 ] = ( address >> 8 ); - txBuffer[ BUFFER_INDEX_2 ] = ( address & 0x00FF ); - txBuffer[ BUFFER_INDEX_3 ] = RTC_READ_FROM_RAM; + txBuffer[ RTC_PREP_RAM_INDEX ] = RTC_PREP_RAM_READ_WRITE; + txBuffer[ RTC_RAM_HIGH_ADDRESS_INDEX ] = ( address >> RTC_RAM_HIGH_ADDRESS_BIT_SHIFT ); + txBuffer[ RTC_RAM_LOW_ADDRESS_INDEX ] = ( address & 0x00FF ); + txBuffer[ RTC_RAM_COMMAND_INDEX ] = RTC_READ_FROM_RAM; U08 i; @@ -406,21 +444,24 @@ } } } - else if ( status == RTC_RAM_COMPLETE ) + else if ( status == RTC_RAM_STATUS_COMPLETE ) { - RTCRAMStatus = RTC_RAM_READY; + RTCRAMStatus = RTC_RAM_STATUS_IDLE; } return status; } -RTC_RAM_STATUS_T getRTCRAMStatus() +RTC_RAM_STATE_T getRTCRAMState() { - if ( RTCRAMStatus == RTC_RAM_COMPLETE ) - { - RTCRAMStatus = RTC_RAM_READY; - } + RTC_RAM_STATE_T state = RTC_RAM_STATE_READY; + return RTCRAMState; +} + +// TODO: make this function a const +RTC_RAM_STATUS_T getRTCRAMStatus() +{ return RTCRAMStatus; } @@ -827,15 +868,15 @@ { result = RTC_EXEC_STATE_IDLE; - RTCRAMStatus = RTC_RAM_COMPLETE; + RTCRAMStatus = RTC_RAM_STATUS_COMPLETE; hasWriteToRAMRequested = FALSE; } else if ( RTCServiceState == RTC_SERVICE_COMPLETE && !isStatusOk ) { result = RTC_EXEC_STATE_FAULT; - RTCRAMStatus = RTC_RAM_FAILED; + RTCRAMStatus = RTC_RAM_STATUS_FAILED; hasWriteToRAMRequested = FALSE; } @@ -895,6 +936,7 @@ } // Private self test functions + static RTC_SELF_TEST_STATE_T handleSelfTestStart() { RTC_SELF_TEST_STATE_T result = RTC_SELF_TEST_STATE_START; Index: firmware/App/Controllers/RTC.h =================================================================== diff -u -rdc96b82b3e7b8acde804180b1c5da37bbdafd96d -r408e6e577818831b985f28e6bf777cd9f65b9849 --- firmware/App/Controllers/RTC.h (.../RTC.h) (revision dc96b82b3e7b8acde804180b1c5da37bbdafd96d) +++ firmware/App/Controllers/RTC.h (.../RTC.h) (revision 408e6e577818831b985f28e6bf777cd9f65b9849) @@ -31,22 +31,30 @@ typedef enum RTC_RAM_STATUS { - RTC_RAM_READY = 0, - RTC_RAM_BUSY, - RTC_RAM_IN_PROGRESS, - RTC_RAM_BYTES_EXCEEDED, - RTC_RAM_ILLEGAL_ADDRESS, - RTC_RAM_FAILED, - RTC_RAM_COMPLETE + RTC_RAM_STATUS_IDLE = 0, + RTC_RAM_STATUS_IN_PROGRESS, + RTC_RAM_STATUS_BYTES_EXCEEDED, + RTC_RAM_STATUS_ILLEGAL_ADDRESS, + RTC_RAM_STATUS_FAILED, + RTC_RAM_STATUS_COMPLETE } RTC_RAM_STATUS_T; +typedef enum RTC_RAM_STATE +{ + RTC_RAM_STATE_READY = 0, + RTC_RAM_STATE_BUSY + +} RTC_RAM_STATE_T; + RTC_RAM_STATUS_T writeToRAM( U16 address, U16* data, U32 length ); RTC_RAM_STATUS_T readFromRAM( U16 address, U32 length ); RTC_RAM_STATUS_T getRTCRAMStatus(); +RTC_RAM_STATE_T getRTCRAMState(); + void getDataFromRAM( U16* externalBuffer, U32 length ); #endif Index: firmware/App/Tasks/TaskGeneral.c =================================================================== diff -u -r23ebecb91f2a05526f691b611d6c1862426f171d -r408e6e577818831b985f28e6bf777cd9f65b9849 --- firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision 23ebecb91f2a05526f691b611d6c1862426f171d) +++ firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision 408e6e577818831b985f28e6bf777cd9f65b9849) @@ -50,26 +50,26 @@ //execSystemCommRx(); // FOR DEBUGGING PURPOSES ONLY REMOVE - // Used 120 and 200 so it will not read or - // write during POST + // PLEASE DO NOT REVIEW THIS CODE + // Used 120 and 200 so it will not read or write during POST static U16 test = 0; static RTC_RAM_STATUS_T status; static U16 returndata[5]; if (test >= 120) { - if ( status != RTC_RAM_IN_PROGRESS ) + if ( status != RTC_RAM_STATUS_IN_PROGRESS ) { static U16 data[5] = {17, 18, 19, 10, 22}; status = writeToRAM(119, &data[0], 5); } - else if ( status == RTC_RAM_IN_PROGRESS ) + else if ( status == RTC_RAM_STATUS_IN_PROGRESS ) { - status = getRTCRAMStatus(); + status = getRTCRAMState(); } else { test = 0; - status = RTC_RAM_READY; + //status = RTC_RAM_READY; } } if (test == 200) @@ -86,6 +86,7 @@ }*/ test++; // FOR DEBUGGING PURPOSES ONLY REMOVE + // PLEASE DO NOT REVIEW THIS CODE // Control RTC // After CommRx and and before execOperationModes()