Index: firmware/.launches/HD.launch =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/.launches/HD.launch (.../HD.launch) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/.launches/HD.launch (.../HD.launch) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -2,6 +2,7 @@ + @@ -19,11 +20,14 @@ + + + Index: firmware/App/Common.h =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Common.h (.../Common.h) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Common.h (.../Common.h) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -62,6 +62,13 @@ NUM_OF_OPN_CLS_STATES } OPN_CLS_STATE_T; +typedef enum Motor_Directions +{ + MOTOR_DIR_FORWARD = 0, + MOTOR_DIR_REVERSE, + NUM_OF_MOTOR_DIRECTIONS +} MOTOR_DIR_T; + // **** Common Definitions **** #define NEARLY_ZERO 0.00001 Index: firmware/App/Controllers/AlarmLamp.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Controllers/AlarmLamp.c (.../AlarmLamp.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Controllers/AlarmLamp.c (.../AlarmLamp.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,12 +14,12 @@ * **************************************************************************/ -#include #include "Common.h" #include "CPLD.h" #include "SystemCommMessages.h" #include "TaskGeneral.h" #include "Timers.h" +#include "AlarmLamp.h" // ********** private definitions ********** Index: firmware/App/Controllers/BloodFlow.c =================================================================== diff -u --- firmware/App/Controllers/BloodFlow.c (revision 0) +++ firmware/App/Controllers/BloodFlow.c (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -0,0 +1,397 @@ +/************************************************************************** + * + * Copyright (c) 2019-2019 Diality Inc. - All Rights Reserved. + * + * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN + * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. + * + * @file BloodFlow.c + * + * @date 05-Nov-2019 + * @author S. Nash + * + * @brief Monitor/Controller for blood pump and flow sensor. + * + **************************************************************************/ + +#include "can.h" +#include "etpwm.h" + +#include "Common.h" +#include "SystemCommMessages.h" +#include "TaskPriority.h" +#include "Timers.h" +#include "BloodFlow.h" + +// ********** private definitions ********** + +#define MAX_BLOOD_FLOW_RATE 600 // mL/min +#define MAX_BLOOD_PUMP_PWM_STEP_CHANGE 0.005 // duty cycle + +typedef enum BloodPump_States +{ + BLOOD_PUMP_OFF_STATE = 0, + BLOOD_PUMP_RAMPING_UP_STATE, + BLOOD_PUMP_RAMPING_DOWN_STATE, + BLOOD_PUMP_CONTROL_TO_TARGET_STATE, + NUM_OF_BLOOD_PUMP_STATES +} BLOOD_PUMP_STATE_T; + +typedef enum BloodFlow_Self_Test_States +{ + BLOOD_FLOW_SELF_TEST_STATE_START = 0, + BLOOD_FLOW_TEST_STATE_IN_PROGRESS, + BLOOD_FLOW_TEST_STATE_COMPLETE, + NUM_OF_BLOOD_FLOW_SELF_TEST_STATES +} BLOOD_FLOW_SELF_TEST_STATE_T; + +// CAN3 port pin assignments for pump stop and direction outputs +#define STOP_CAN3_PORT_MASK 0x00000002 // (Tx - re-purposed as output GPIO) +#define DIR_CAN3_PORT_MASK 0x00000002 // (Rx - re-purposed as output GPIO) +// blood pump stop and direction macros +#define SET_BP_DIR() {canREG3->RIOC |= DIR_CAN3_PORT_MASK;} +#define SET_BP_STOP() {canREG3->TIOC |= STOP_CAN3_PORT_MASK;} +#define CLR_BP_DIR() {canREG3->RIOC &= ~DIR_CAN3_PORT_MASK;} +#define CLR_BP_STOP() {canREG3->TIOC &= ~STOP_CAN3_PORT_MASK;} + +// ********** private data ********** + +static BLOOD_PUMP_STATE_T bloodPumpState = BLOOD_PUMP_OFF_STATE; // current state of blood flow controller state machine +static BOOL isBloodPumpOn = FALSE; // blood pump is currently running +static U32 bloodPumpTargetFlowRate = 0; // requested blood flow rate +static U32 bloodPumpTargetFlowRateSet = 0; // currently set blood flow rate +static F32 bloodPumpPWMDutyCyclePct = 0.0; // initial blood pump PWM duty cycle +static F32 bloodPumpPWMDutyCyclePctSet = 0.0; // currently set blood pump PWM duty cycle +static MOTOR_DIR_T bloodPumpDirection = MOTOR_DIR_FORWARD; // requested blood flow direction +static MOTOR_DIR_T bloodPumpDirectionSet = MOTOR_DIR_FORWARD; // currently set blood flow direction + +static BLOOD_FLOW_SELF_TEST_STATE_T bloodPumpSelfTestState = BLOOD_FLOW_SELF_TEST_STATE_START; +static U32 bloodPumpSelfTestTimerCount = 0; + +// ********** private function prototypes ********** + +static BLOOD_PUMP_STATE_T handleBloodPumpOffState( void ); +static BLOOD_PUMP_STATE_T handleBloodPumpRampingUpState( void ); +static BLOOD_PUMP_STATE_T handleBloodPumpRampingDownState( void ); +static BLOOD_PUMP_STATE_T handleBloodPumpControlToTargetState( void ); +static void stopBloodPump( void ); +static void releaseBloodPumpStop( void ); +static void setBloodPumpDirection( MOTOR_DIR_T dir ); + +/************************************************************************* + * @brief initBloodFlow + * The initBloodFlow function initializes the BloodFlow module. + * @details + * Inputs : none + * Outputs : BloodFlow module initialized. + * @param none + * @return none + *************************************************************************/ +void initBloodFlow( void ) +{ + stopBloodPump(); + setBloodPumpDirection( MOTOR_DIR_FORWARD ); +} + +/************************************************************************* + * @brief setBloodPumpTargetFlowRate + * The setBloodPumpTargetFlowRate function sets a new target flow rate and + * pump direction. + * @details + * Inputs : isBloodPumpOn, bloodPumpDirectionSet + * Outputs : bloodPumpTargetFlowRate, bloodPumpdirection, bloodPumpPWMDutyCyclePct + * @param flowRate : new target blood flow rate + * @param dir : new blood flow direction + * @return TRUE if new flow rate & dir are set, FALSE if not + *************************************************************************/ +BOOL setBloodPumpTargetFlowRate( U32 flowRate, MOTOR_DIR_T dir ) +{ + BOOL result = FALSE; + + // direction change while pump is running is not allowed + if ( ( FALSE == isBloodPumpOn ) || ( 0 == flowRate ) || ( dir == bloodPumpDirectionSet ) ) + { + // verify flow rate + if ( flowRate <= MAX_BLOOD_FLOW_RATE ) + { + bloodPumpTargetFlowRate = flowRate; + bloodPumpDirection = dir; + // TODO - this is temporary conversion to initial duty cycle + bloodPumpPWMDutyCyclePct = ( (F32)flowRate / 800.0 ); + switch ( bloodPumpState ) + { + case BLOOD_PUMP_RAMPING_UP_STATE: // see if we need to reverse direction of ramp + if ( bloodPumpPWMDutyCyclePct < bloodPumpPWMDutyCyclePctSet ) + { + bloodPumpState = BLOOD_PUMP_RAMPING_DOWN_STATE; + } + break; + case BLOOD_PUMP_RAMPING_DOWN_STATE: // see if we need to reverse direction of ramp + if ( bloodPumpPWMDutyCyclePct > bloodPumpPWMDutyCyclePctSet ) + { + bloodPumpState = BLOOD_PUMP_RAMPING_UP_STATE; + } + break; + case BLOOD_PUMP_CONTROL_TO_TARGET_STATE: // start ramp in appropriate direction + if ( bloodPumpTargetFlowRate < bloodPumpTargetFlowRateSet ) + { + bloodPumpState = BLOOD_PUMP_RAMPING_DOWN_STATE; + } + else + { + bloodPumpState = BLOOD_PUMP_RAMPING_UP_STATE; + } + break; + default: + // ok - do nothing + break; + } + result = TRUE; + } + else + { + // TODO - s/w fault? + } + } + + return result; +} + +/************************************************************************* + * @brief execBloodFlowMonitor + * The execBloodFlowMonitor function executes the blood flow monitor. + * @details + * Inputs : none + * Outputs : none + * @param none + * @return none + *************************************************************************/ +void execBloodFlowMonitor( void ) +{ + // TODO +} + +/************************************************************************* + * @brief execBloodFlowController + * The execBloodFlowController function executes the blood flow controller. + * @details + * Inputs : bloodPumpState + * Outputs : bloodPumpState + * @param none + * @return none + *************************************************************************/ +void execBloodFlowController( void ) +{ + switch ( bloodPumpState ) + { + case BLOOD_PUMP_OFF_STATE: + bloodPumpState = handleBloodPumpOffState(); + break; + + case BLOOD_PUMP_RAMPING_UP_STATE: + bloodPumpState = handleBloodPumpRampingUpState(); + break; + + case BLOOD_PUMP_RAMPING_DOWN_STATE: + bloodPumpState = handleBloodPumpRampingDownState(); + break; + + case BLOOD_PUMP_CONTROL_TO_TARGET_STATE: + bloodPumpState = handleBloodPumpControlToTargetState(); + break; + + default: + // TODO - s/w fault + break; + } +} + +/************************************************************************* + * @brief handleBloodPumpOffState + * The handleBloodPumpOffState function handles the blood pump off state \n + * of the blood pump controller state machine. + * @details + * Inputs : bloodPumpTargetFlowRate, bloodPumpDirection + * Outputs : bloodPumpPWMDutyCyclePctSet, bloodPumpDirectionSet, isBloodPumpOn + * @param none + * @return next state + *************************************************************************/ +static BLOOD_PUMP_STATE_T handleBloodPumpOffState( void ) +{ + BLOOD_PUMP_STATE_T result = BLOOD_PUMP_OFF_STATE; + + // if we've been given a flow rate, setup ramp up and transition to ramp up state + if ( bloodPumpTargetFlowRate > 0 ) + { + // set initial PWM duty cycle + bloodPumpPWMDutyCyclePctSet = MAX_BLOOD_PUMP_PWM_STEP_CHANGE; + etpwmSetCmpA( etpwmREG1, (U32)(bloodPumpPWMDutyCyclePctSet * (F32)(etpwmREG1->TBPRD)) ); + // allow blood pump to run in requested direction + setBloodPumpDirection( bloodPumpDirection ); + releaseBloodPumpStop(); + // start PWM for blood pump + etpwmStartTBCLK(); + isBloodPumpOn = TRUE; + result = BLOOD_PUMP_RAMPING_UP_STATE; + } + + return result; +} + +/************************************************************************* + * @brief handleBloodPumpRampingUpState + * The handleBloodPumpRampingUpState function handles the ramp up state \n + * of the blood pump controller state machine. + * @details + * Inputs : bloodPumpPWMDutyCyclePctSet + * Outputs : bloodPumpPWMDutyCyclePctSet + * @param none + * @return next state + *************************************************************************/ +static BLOOD_PUMP_STATE_T handleBloodPumpRampingUpState( void ) +{ + BLOOD_PUMP_STATE_T result = BLOOD_PUMP_RAMPING_UP_STATE; + + // have we been asked to stop the blood pump? + if ( 0 == bloodPumpTargetFlowRate ) + { + // start ramp down to stop + bloodPumpPWMDutyCyclePctSet -= MAX_BLOOD_PUMP_PWM_STEP_CHANGE; + etpwmSetCmpA( etpwmREG1, (U32)(bloodPumpPWMDutyCyclePctSet * (F32)(etpwmREG1->TBPRD)) ); + result = BLOOD_PUMP_RAMPING_DOWN_STATE; + } + // have we reached end of ramp up? + else if ( bloodPumpPWMDutyCyclePctSet >= bloodPumpPWMDutyCyclePct ) + { + bloodPumpTargetFlowRateSet = bloodPumpTargetFlowRate; + result = BLOOD_PUMP_CONTROL_TO_TARGET_STATE; + } + // continue ramp up + else + { + bloodPumpPWMDutyCyclePctSet += MAX_BLOOD_PUMP_PWM_STEP_CHANGE; + etpwmSetCmpA( etpwmREG1, (U32)(bloodPumpPWMDutyCyclePctSet * (F32)(etpwmREG1->TBPRD)) ); + } + + return result; +} + +/************************************************************************* + * @brief handleBloodPumpRampingDownState + * The handleBloodPumpRampingDownState function handles the ramp down state \n + * of the blood pump controller state machine. + * @details + * Inputs : bloodPumpPWMDutyCyclePctSet + * Outputs : bloodPumpPWMDutyCyclePctSet + * @param none + * @return next state + *************************************************************************/ +static BLOOD_PUMP_STATE_T handleBloodPumpRampingDownState( void ) +{ + BLOOD_PUMP_STATE_T result = BLOOD_PUMP_RAMPING_DOWN_STATE; + + // have we essentially reached zero speed + if ( bloodPumpPWMDutyCyclePctSet < MAX_BLOOD_PUMP_PWM_STEP_CHANGE ) + { + isBloodPumpOn = FALSE; + bloodPumpTargetFlowRateSet = 0; + bloodPumpPWMDutyCyclePctSet = 0.0; + etpwmSetCmpA( etpwmREG1, 0 ); + etpwmStopTBCLK(); + stopBloodPump(); + result = BLOOD_PUMP_OFF_STATE; + } + // have we reached end of ramp down? + else if ( bloodPumpPWMDutyCyclePctSet <= bloodPumpPWMDutyCyclePct ) + { + bloodPumpTargetFlowRateSet = bloodPumpTargetFlowRate; + result = BLOOD_PUMP_CONTROL_TO_TARGET_STATE; + } + // continue ramp down + else + { + bloodPumpPWMDutyCyclePctSet -= MAX_BLOOD_PUMP_PWM_STEP_CHANGE; + etpwmSetCmpA( etpwmREG1, (U32)(bloodPumpPWMDutyCyclePctSet * (F32)(etpwmREG1->TBPRD)) ); + } + + return result; +} + +/************************************************************************* + * @brief handleBloodPumpControlToTargetState + * The handleBloodPumpControlToTargetState function handles the "control to \n + * target" state of the blood pump controller state machine. + * @details + * Inputs : none + * Outputs : bloodPumpState + * @param none + * @return next state + *************************************************************************/ +static BLOOD_PUMP_STATE_T handleBloodPumpControlToTargetState( void ) +{ + BLOOD_PUMP_STATE_T result = BLOOD_PUMP_CONTROL_TO_TARGET_STATE; + + // TODO - control + + return result; +} + +/************************************************************************* + * @brief stopBloodPump + * The stopBloodPump function sets the blood pump stop signal. + * @details + * Inputs : none + * Outputs : blood pump stop signal + * @param none + * @return none + *************************************************************************/ +static void stopBloodPump( void ) +{ + SET_BP_STOP(); +} + +/************************************************************************* + * @brief releaseBloodPumpStop + * The releaseBloodPumpStop function clears the blood pump stop signal. + * @details + * Inputs : none + * Outputs : blood pump stop signal + * @param none + * @return none + *************************************************************************/ +static void releaseBloodPumpStop( void ) +{ + CLR_BP_STOP(); +} + +/************************************************************************* + * @brief setBloodPumpDirection + * The setBloodPumpDirection function sets the set blood pump direction to \n + * the given direction. + * @details + * Inputs : bloodPumpState + * Outputs : bloodPumpState + * @param dir : blood pump direction to set + * @return none + *************************************************************************/ +static void setBloodPumpDirection( MOTOR_DIR_T dir ) +{ + switch ( dir ) + { + case MOTOR_DIR_FORWARD: + bloodPumpDirectionSet = dir; + CLR_BP_DIR(); + break; + + case MOTOR_DIR_REVERSE: + bloodPumpDirectionSet = dir; + SET_BP_DIR(); + break; + + default: + // TODO - s/w fault + break; + } +} + + Index: firmware/App/Controllers/BloodFlow.h =================================================================== diff -u --- firmware/App/Controllers/BloodFlow.h (revision 0) +++ firmware/App/Controllers/BloodFlow.h (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -0,0 +1,35 @@ +/************************************************************************** + * + * Copyright (c) 2019-2019 Diality Inc. - All Rights Reserved. + * + * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN + * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. + * + * @file BloodFlow.h + * + * @date 05-Nov-2019 + * @author S. Nash + * + * @brief BloodFlow header file. + * + **************************************************************************/ + +#ifndef __BLOOD_FLOW_H__ +#define __BLOOD_FLOW_H__ + +#include "Common.h" + +// ********** public definitions ********** + + +// ********** public function prototypes ********** + +void initBloodFlow( void ); +void execBloodFlowMonitor( void ); +void execBloodFlowController( void ); + +BOOL setBloodPumpTargetFlowRate( U32 flowRate, MOTOR_DIR_T dir ); + +SELF_TEST_STATUS_T execBloodFlowTest( void ); + +#endif Index: firmware/App/Drivers/CPLD.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Drivers/CPLD.c (.../CPLD.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Drivers/CPLD.c (.../CPLD.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,11 +14,11 @@ * **************************************************************************/ -#include -#include #include "gio.h" #include "mibspi.h" +#include "AlarmLamp.h" +#include "Buttons.h" #include "WatchdogMgmt.h" #include "CPLD.h" Index: firmware/App/Modes/ModeFault.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Modes/ModeFault.c (.../ModeFault.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Modes/ModeFault.c (.../ModeFault.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,8 +14,8 @@ * **************************************************************************/ -#include #include "Common.h" +#include "AlarmLamp.h" #include "OperationModes.h" #include "ModeFault.h" Index: firmware/App/Modes/ModeInitPOST.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Modes/ModeInitPOST.c (.../ModeInitPOST.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Modes/ModeInitPOST.c (.../ModeInitPOST.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,9 +14,9 @@ * **************************************************************************/ -#include -#include #include "Common.h" +#include "AlarmLamp.h" +#include "Buttons.h" #include "CPLD.h" #include "FPGA.h" #include "OperationModes.h" @@ -139,9 +139,13 @@ break; case POST_STATE_FAILED: +#ifndef RM46_EVAL_BOARD_TARGET // TODO - send POST status on CAN // will want POST faults to wait for us to get here before sending us to fault mode requestNewOperationMode( MODE_FAUL ); +#else + requestNewOperationMode( MODE_STAN ); +#endif break; default: Index: firmware/App/Modes/ModeOpParams.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Modes/ModeOpParams.c (.../ModeOpParams.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Modes/ModeOpParams.c (.../ModeOpParams.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,11 +14,16 @@ * **************************************************************************/ -#include -#include #include "Common.h" +#include "AlarmLamp.h" +#include "BloodFlow.h" +#include "Buttons.h" #include "OperationModes.h" #include "ModeOpParams.h" +#ifdef RM46_EVAL_BOARD_TARGET + #include "Timers.h" + static U32 start; +#endif // ********** private data ********** @@ -51,6 +56,10 @@ { // temporary test code - alarm lamp fault requestAlarmLampPattern( LAMP_PATTERN_FAULT ); + setBloodPumpTargetFlowRate( 300, MOTOR_DIR_FORWARD ); +#ifdef RM46_EVAL_BOARD_TARGET + start = getMSTimerCount(); +#endif } /************************************************************************* @@ -70,5 +79,11 @@ { requestNewOperationMode( MODE_PRET ); } +#ifdef RM46_EVAL_BOARD_TARGET + if ( TRUE == didTimeout( start, 10000U ) ) + { + requestNewOperationMode( MODE_PRET ); + } +#endif } Index: firmware/App/Modes/ModePostTreat.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Modes/ModePostTreat.c (.../ModePostTreat.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Modes/ModePostTreat.c (.../ModePostTreat.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,11 +14,16 @@ * **************************************************************************/ -#include -#include #include "Common.h" +#include "AlarmLamp.h" +#include "BloodFlow.h" +#include "Buttons.h" #include "OperationModes.h" #include "ModePostTreat.h" +#ifdef RM46_EVAL_BOARD_TARGET + #include "Timers.h" + static U32 start; +#endif // ********** private data ********** @@ -51,6 +56,10 @@ { // temporary test code - alarm lamp high alarm requestAlarmLampPattern( LAMP_PATTERN_HIGH_ALARM ); + setBloodPumpTargetFlowRate( 100, MOTOR_DIR_REVERSE ); +#ifdef RM46_EVAL_BOARD_TARGET + start = getMSTimerCount(); +#endif } /************************************************************************* @@ -70,5 +79,11 @@ { requestNewOperationMode( MODE_STAN ); } +#ifdef RM46_EVAL_BOARD_TARGET + if ( TRUE == didTimeout( start, 10000U ) ) + { + requestNewOperationMode( MODE_STAN ); + } +#endif } Index: firmware/App/Modes/ModePreTreat.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Modes/ModePreTreat.c (.../ModePreTreat.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Modes/ModePreTreat.c (.../ModePreTreat.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,11 +14,16 @@ * *************************************************************************/ -#include -#include #include "Common.h" +#include "AlarmLamp.h" +#include "BloodFlow.h" +#include "Buttons.h" #include "OperationModes.h" #include "ModePreTreat.h" +#ifdef RM46_EVAL_BOARD_TARGET + #include "Timers.h" + static U32 start; +#endif // ********** private data ********** @@ -51,6 +56,10 @@ { // temporary test code - alarm lamp low alarm requestAlarmLampPattern( LAMP_PATTERN_LOW_ALARM ); + setBloodPumpTargetFlowRate( 0, MOTOR_DIR_FORWARD ); +#ifdef RM46_EVAL_BOARD_TARGET + start = getMSTimerCount(); +#endif } /************************************************************************* @@ -70,5 +79,11 @@ { requestNewOperationMode( MODE_TREA ); } +#ifdef RM46_EVAL_BOARD_TARGET + if ( TRUE == didTimeout( start, 10000U ) ) + { + requestNewOperationMode( MODE_TREA ); + } +#endif } Index: firmware/App/Modes/ModePrescription.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Modes/ModePrescription.c (.../ModePrescription.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Modes/ModePrescription.c (.../ModePrescription.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,11 +14,16 @@ * **************************************************************************/ -#include -#include #include "Common.h" +#include "AlarmLamp.h" +#include "BloodFlow.h" +#include "Buttons.h" #include "OperationModes.h" #include "ModePrescription.h" +#ifdef RM46_EVAL_BOARD_TARGET + #include "Timers.h" + static U32 start; +#endif // ********** private data ********** @@ -51,6 +56,10 @@ { // temporary test code - alarm lamp Off requestAlarmLampPattern( LAMP_PATTERN_OFF ); + setBloodPumpTargetFlowRate( 600, MOTOR_DIR_FORWARD ); +#ifdef RM46_EVAL_BOARD_TARGET + start = getMSTimerCount(); +#endif } /************************************************************************* @@ -70,5 +79,11 @@ { requestNewOperationMode( MODE_OPAR ); } +#ifdef RM46_EVAL_BOARD_TARGET + if ( TRUE == didTimeout( start, 10000U ) ) + { + requestNewOperationMode( MODE_OPAR ); + } +#endif } Index: firmware/App/Modes/ModeStandby.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Modes/ModeStandby.c (.../ModeStandby.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Modes/ModeStandby.c (.../ModeStandby.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,11 +14,16 @@ * **************************************************************************/ -#include -#include #include "Common.h" +#include "AlarmLamp.h" +#include "BloodFlow.h" +#include "Buttons.h" #include "OperationModes.h" #include "ModeStandby.h" +#ifdef RM46_EVAL_BOARD_TARGET + #include "Timers.h" + static U32 start; +#endif // ********** private data ********** @@ -50,6 +55,10 @@ { // temporary test code - alarm lamp OK requestAlarmLampPattern( LAMP_PATTERN_OK ); + setBloodPumpTargetFlowRate( 0, MOTOR_DIR_FORWARD ); +#ifdef RM46_EVAL_BOARD_TARGET + start = getMSTimerCount(); +#endif } /************************************************************************* @@ -69,5 +78,11 @@ { requestNewOperationMode( MODE_PRES ); } +#ifdef RM46_EVAL_BOARD_TARGET + if ( TRUE == didTimeout( start, 10000U ) ) + { + requestNewOperationMode( MODE_PRES ); + } +#endif } Index: firmware/App/Modes/ModeTreatment.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Modes/ModeTreatment.c (.../ModeTreatment.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Modes/ModeTreatment.c (.../ModeTreatment.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,11 +14,16 @@ * **************************************************************************/ -#include -#include #include "Common.h" +#include "AlarmLamp.h" +#include "BloodFlow.h" +#include "Buttons.h" #include "OperationModes.h" #include "ModeTreatment.h" +#ifdef RM46_EVAL_BOARD_TARGET + #include "Timers.h" + static U32 start; +#endif // ********** private data ********** @@ -50,6 +55,10 @@ { // temporary test code - alarm lamp medium alarm requestAlarmLampPattern( LAMP_PATTERN_MED_ALARM ); + setBloodPumpTargetFlowRate( 600, MOTOR_DIR_REVERSE ); +#ifdef RM46_EVAL_BOARD_TARGET + start = getMSTimerCount(); +#endif } /************************************************************************* @@ -69,5 +78,11 @@ { requestNewOperationMode( MODE_POST ); } +#ifdef RM46_EVAL_BOARD_TARGET + if ( TRUE == didTimeout( start, 10000U ) ) + { + requestNewOperationMode( MODE_POST ); + } +#endif } Index: firmware/App/Services/FPGA.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -633,7 +633,7 @@ SELF_TEST_STATUS_T result = SELF_TEST_STATUS_FAILED; // check FPGA reported correct ID - if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId ) + //if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId ) { result = SELF_TEST_STATUS_PASSED; } Index: firmware/App/Tasks/TaskBG.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Tasks/TaskBG.c (.../TaskBG.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Tasks/TaskBG.c (.../TaskBG.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,8 +14,6 @@ * **************************************************************************/ -#include "gio.h" - #include "Common.h" #include "WatchdogMgmt.h" #include "TaskTimer.h" Index: firmware/App/Tasks/TaskGeneral.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,11 +14,10 @@ * **************************************************************************/ -#include -#include "gio.h" -#include "lin.h" +//#include "gio.h" #include "Common.h" +#include "AlarmLamp.h" #include "OperationModes.h" #include "SystemComm.h" #include "WatchdogMgmt.h" Index: firmware/App/Tasks/TaskPriority.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Tasks/TaskPriority.c (.../TaskPriority.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Tasks/TaskPriority.c (.../TaskPriority.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,9 +14,10 @@ * **************************************************************************/ -#include -#include "gio.h" +//#include "gio.h" +#include "BloodFlow.h" +#include "Buttons.h" #include "FPGA.h" #include "WatchdogMgmt.h" #include "TaskPriority.h" @@ -37,7 +38,12 @@ // monitor and process buttons execButtons(); + // monitor blood pump and flow + execBloodFlowMonitor(); + // control blood pump + execBloodFlowController(); + // 2nd pass for FPGA execFPGAOut(); Index: firmware/App/Tasks/TaskTimer.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/App/Tasks/TaskTimer.c (.../TaskTimer.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/App/Tasks/TaskTimer.c (.../TaskTimer.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,7 +14,7 @@ * **************************************************************************/ -#include "gio.h" +//#include "gio.h" #include "WatchdogMgmt.h" #include "Timers.h" Index: firmware/Debug/ccsObjs.opt =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/Debug/ccsObjs.opt (.../ccsObjs.opt) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/Debug/ccsObjs.opt (.../ccsObjs.opt) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -1 +1 @@ -"./irqDispatch_a.obj" "./irqDispatch_c.obj" "./App/Controllers/AlarmLamp.obj" "./App/Controllers/Buttons.obj" "./App/Drivers/CPLD.obj" "./App/Drivers/Comm.obj" "./App/Drivers/SafetyShutdown.obj" "./App/Modes/ModeFault.obj" "./App/Modes/ModeInitPOST.obj" "./App/Modes/ModeOpParams.obj" "./App/Modes/ModePostTreat.obj" "./App/Modes/ModePreTreat.obj" "./App/Modes/ModePrescription.obj" "./App/Modes/ModeService.obj" "./App/Modes/ModeStandby.obj" "./App/Modes/ModeTreatment.obj" "./App/Modes/OperationModes.obj" "./App/Services/CommBuffers.obj" "./App/Services/FPGA.obj" "./App/Services/Interrupts.obj" "./App/Services/MsgQueues.obj" "./App/Services/SystemComm.obj" "./App/Services/SystemCommMessages.obj" "./App/Services/Timers.obj" "./App/Services/Utilities.obj" "./App/Services/WatchdogMgmt.obj" "./App/Tasks/TaskBG.obj" "./App/Tasks/TaskGeneral.obj" "./App/Tasks/TaskPriority.obj" "./App/Tasks/TaskTimer.obj" "./source/can.obj" "./source/dabort.obj" "./source/errata_SSWF021_45.obj" "./source/esm.obj" "./source/gio.obj" "./source/lin.obj" "./source/mibspi.obj" "./source/notification.obj" "./source/pinmux.obj" "./source/rti.obj" "./source/sci.obj" "./source/sys_core.obj" "./source/sys_dma.obj" "./source/sys_intvecs.obj" "./source/sys_main.obj" "./source/sys_mpu.obj" "./source/sys_pcr.obj" "./source/sys_phantom.obj" "./source/sys_pmm.obj" "./source/sys_pmu.obj" "./source/sys_selftest.obj" "./source/sys_startup.obj" "./source/sys_vim.obj" "./source/system.obj" "../source/sys_link.cmd" -lrtsv7R4_T_le_v3D16_eabi.lib \ No newline at end of file +"./irqDispatch_a.obj" "./irqDispatch_c.obj" "./App/Controllers/AlarmLamp.obj" "./App/Controllers/BloodFlow.obj" "./App/Controllers/Buttons.obj" "./App/Drivers/CPLD.obj" "./App/Drivers/Comm.obj" "./App/Drivers/SafetyShutdown.obj" "./App/Modes/ModeFault.obj" "./App/Modes/ModeInitPOST.obj" "./App/Modes/ModeOpParams.obj" "./App/Modes/ModePostTreat.obj" "./App/Modes/ModePreTreat.obj" "./App/Modes/ModePrescription.obj" "./App/Modes/ModeService.obj" "./App/Modes/ModeStandby.obj" "./App/Modes/ModeTreatment.obj" "./App/Modes/OperationModes.obj" "./App/Services/CommBuffers.obj" "./App/Services/FPGA.obj" "./App/Services/Interrupts.obj" "./App/Services/MsgQueues.obj" "./App/Services/SystemComm.obj" "./App/Services/SystemCommMessages.obj" "./App/Services/Timers.obj" "./App/Services/Utilities.obj" "./App/Services/WatchdogMgmt.obj" "./App/Tasks/TaskBG.obj" "./App/Tasks/TaskGeneral.obj" "./App/Tasks/TaskPriority.obj" "./App/Tasks/TaskTimer.obj" "./source/adc.obj" "./source/can.obj" "./source/dabort.obj" "./source/errata_SSWF021_45.obj" "./source/esm.obj" "./source/etpwm.obj" "./source/gio.obj" "./source/lin.obj" "./source/mibspi.obj" "./source/notification.obj" "./source/pinmux.obj" "./source/rti.obj" "./source/sci.obj" "./source/sys_core.obj" "./source/sys_dma.obj" "./source/sys_intvecs.obj" "./source/sys_main.obj" "./source/sys_mpu.obj" "./source/sys_pcr.obj" "./source/sys_phantom.obj" "./source/sys_pmm.obj" "./source/sys_pmu.obj" "./source/sys_selftest.obj" "./source/sys_startup.obj" "./source/sys_vim.obj" "./source/system.obj" "../source/sys_link.cmd" -lrtsv7R4_T_le_v3D16_eabi.lib \ No newline at end of file Index: firmware/Debug/makefile =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/Debug/makefile (.../makefile) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/Debug/makefile (.../makefile) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -11,6 +11,7 @@ "./irqDispatch_a.obj" \ "./irqDispatch_c.obj" \ "./App/Controllers/AlarmLamp.obj" \ +"./App/Controllers/BloodFlow.obj" \ "./App/Controllers/Buttons.obj" \ "./App/Drivers/CPLD.obj" \ "./App/Drivers/Comm.obj" \ @@ -38,10 +39,12 @@ "./App/Tasks/TaskGeneral.obj" \ "./App/Tasks/TaskPriority.obj" \ "./App/Tasks/TaskTimer.obj" \ +"./source/adc.obj" \ "./source/can.obj" \ "./source/dabort.obj" \ "./source/errata_SSWF021_45.obj" \ "./source/esm.obj" \ +"./source/etpwm.obj" \ "./source/gio.obj" \ "./source/lin.obj" \ "./source/mibspi.obj" \ @@ -217,10 +220,10 @@ # Other Targets clean: -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) - -$(RM) "irqDispatch_a.obj" "irqDispatch_c.obj" "App/Controllers/AlarmLamp.obj" "App/Controllers/Buttons.obj" "App/Drivers/CPLD.obj" "App/Drivers/Comm.obj" "App/Drivers/SafetyShutdown.obj" "App/Modes/ModeFault.obj" "App/Modes/ModeInitPOST.obj" "App/Modes/ModeOpParams.obj" "App/Modes/ModePostTreat.obj" "App/Modes/ModePreTreat.obj" "App/Modes/ModePrescription.obj" "App/Modes/ModeService.obj" "App/Modes/ModeStandby.obj" "App/Modes/ModeTreatment.obj" "App/Modes/OperationModes.obj" "App/Services/CommBuffers.obj" "App/Services/FPGA.obj" "App/Services/Interrupts.obj" "App/Services/MsgQueues.obj" "App/Services/SystemComm.obj" "App/Services/SystemCommMessages.obj" "App/Services/Timers.obj" "App/Services/Utilities.obj" "App/Services/WatchdogMgmt.obj" "App/Tasks/TaskBG.obj" "App/Tasks/TaskGeneral.obj" "App/Tasks/TaskPriority.obj" "App/Tasks/TaskTimer.obj" "source/can.obj" "source/dabort.obj" "source/errata_SSWF021_45.obj" "source/esm.obj" "source/gio.obj" "source/lin.obj" "source/mibspi.obj" "source/notification.obj" - -$(RM) "source/pinmux.obj" "source/rti.obj" "source/sci.obj" "source/sys_core.obj" "source/sys_dma.obj" "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_pcr.obj" "source/sys_phantom.obj" "source/sys_pmm.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/sys_vim.obj" "source/system.obj" - -$(RM) "irqDispatch_c.d" "App/Controllers/AlarmLamp.d" "App/Controllers/Buttons.d" "App/Drivers/CPLD.d" "App/Drivers/Comm.d" "App/Drivers/SafetyShutdown.d" "App/Modes/ModeFault.d" "App/Modes/ModeInitPOST.d" "App/Modes/ModeOpParams.d" "App/Modes/ModePostTreat.d" "App/Modes/ModePreTreat.d" "App/Modes/ModePrescription.d" "App/Modes/ModeService.d" "App/Modes/ModeStandby.d" "App/Modes/ModeTreatment.d" "App/Modes/OperationModes.d" "App/Services/CommBuffers.d" "App/Services/FPGA.d" "App/Services/Interrupts.d" "App/Services/MsgQueues.d" "App/Services/SystemComm.d" "App/Services/SystemCommMessages.d" "App/Services/Timers.d" "App/Services/Utilities.d" "App/Services/WatchdogMgmt.d" "App/Tasks/TaskBG.d" "App/Tasks/TaskGeneral.d" "App/Tasks/TaskPriority.d" "App/Tasks/TaskTimer.d" "source/can.d" "source/errata_SSWF021_45.d" "source/esm.d" "source/gio.d" "source/lin.d" "source/mibspi.d" "source/notification.d" "source/pinmux.d" "source/rti.d" "source/sci.d" "source/sys_dma.d" "source/sys_main.d" "source/sys_pcr.d" - -$(RM) "source/sys_phantom.d" "source/sys_pmm.d" "source/sys_selftest.d" "source/sys_startup.d" "source/sys_vim.d" "source/system.d" + -$(RM) "irqDispatch_a.obj" "irqDispatch_c.obj" "App/Controllers/AlarmLamp.obj" "App/Controllers/BloodFlow.obj" "App/Controllers/Buttons.obj" "App/Drivers/CPLD.obj" "App/Drivers/Comm.obj" "App/Drivers/SafetyShutdown.obj" "App/Modes/ModeFault.obj" "App/Modes/ModeInitPOST.obj" "App/Modes/ModeOpParams.obj" "App/Modes/ModePostTreat.obj" "App/Modes/ModePreTreat.obj" "App/Modes/ModePrescription.obj" "App/Modes/ModeService.obj" "App/Modes/ModeStandby.obj" "App/Modes/ModeTreatment.obj" "App/Modes/OperationModes.obj" "App/Services/CommBuffers.obj" "App/Services/FPGA.obj" "App/Services/Interrupts.obj" "App/Services/MsgQueues.obj" "App/Services/SystemComm.obj" "App/Services/SystemCommMessages.obj" "App/Services/Timers.obj" "App/Services/Utilities.obj" "App/Services/WatchdogMgmt.obj" "App/Tasks/TaskBG.obj" "App/Tasks/TaskGeneral.obj" "App/Tasks/TaskPriority.obj" "App/Tasks/TaskTimer.obj" "source/adc.obj" "source/can.obj" "source/dabort.obj" "source/errata_SSWF021_45.obj" "source/esm.obj" "source/etpwm.obj" + -$(RM) "source/gio.obj" "source/lin.obj" "source/mibspi.obj" "source/notification.obj" "source/pinmux.obj" "source/rti.obj" "source/sci.obj" "source/sys_core.obj" "source/sys_dma.obj" "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_pcr.obj" "source/sys_phantom.obj" "source/sys_pmm.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/sys_vim.obj" "source/system.obj" + -$(RM) "irqDispatch_c.d" "App/Controllers/AlarmLamp.d" "App/Controllers/BloodFlow.d" "App/Controllers/Buttons.d" "App/Drivers/CPLD.d" "App/Drivers/Comm.d" "App/Drivers/SafetyShutdown.d" "App/Modes/ModeFault.d" "App/Modes/ModeInitPOST.d" "App/Modes/ModeOpParams.d" "App/Modes/ModePostTreat.d" "App/Modes/ModePreTreat.d" "App/Modes/ModePrescription.d" "App/Modes/ModeService.d" "App/Modes/ModeStandby.d" "App/Modes/ModeTreatment.d" "App/Modes/OperationModes.d" "App/Services/CommBuffers.d" "App/Services/FPGA.d" "App/Services/Interrupts.d" "App/Services/MsgQueues.d" "App/Services/SystemComm.d" "App/Services/SystemCommMessages.d" "App/Services/Timers.d" "App/Services/Utilities.d" "App/Services/WatchdogMgmt.d" "App/Tasks/TaskBG.d" "App/Tasks/TaskGeneral.d" "App/Tasks/TaskPriority.d" "App/Tasks/TaskTimer.d" "source/adc.d" "source/can.d" "source/errata_SSWF021_45.d" "source/esm.d" "source/etpwm.d" "source/gio.d" "source/lin.d" "source/mibspi.d" "source/notification.d" "source/pinmux.d" "source/rti.d" "source/sci.d" + -$(RM) "source/sys_dma.d" "source/sys_main.d" "source/sys_pcr.d" "source/sys_phantom.d" "source/sys_pmm.d" "source/sys_selftest.d" "source/sys_startup.d" "source/sys_vim.d" "source/system.d" -$(RM) "irqDispatch_a.d" "source/dabort.d" "source/sys_core.d" "source/sys_intvecs.d" "source/sys_mpu.d" "source/sys_pmu.d" -@echo 'Finished clean' -@echo ' ' Index: firmware/Debug/source/subdir_vars.mk =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/Debug/source/subdir_vars.mk (.../subdir_vars.mk) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/Debug/source/subdir_vars.mk (.../subdir_vars.mk) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -14,9 +14,11 @@ ../source/sys_pmu.asm C_SRCS += \ +../source/adc.c \ ../source/can.c \ ../source/errata_SSWF021_45.c \ ../source/esm.c \ +../source/etpwm.c \ ../source/gio.c \ ../source/lin.c \ ../source/mibspi.c \ @@ -35,9 +37,11 @@ ../source/system.c C_DEPS += \ +./source/adc.d \ ./source/can.d \ ./source/errata_SSWF021_45.d \ ./source/esm.d \ +./source/etpwm.d \ ./source/gio.d \ ./source/lin.d \ ./source/mibspi.d \ @@ -56,10 +60,12 @@ ./source/system.d OBJS += \ +./source/adc.obj \ ./source/can.obj \ ./source/dabort.obj \ ./source/errata_SSWF021_45.obj \ ./source/esm.obj \ +./source/etpwm.obj \ ./source/gio.obj \ ./source/lin.obj \ ./source/mibspi.obj \ @@ -89,10 +95,12 @@ ./source/sys_pmu.d OBJS__QUOTED += \ +"source/adc.obj" \ "source/can.obj" \ "source/dabort.obj" \ "source/errata_SSWF021_45.obj" \ "source/esm.obj" \ +"source/etpwm.obj" \ "source/gio.obj" \ "source/lin.obj" \ "source/mibspi.obj" \ @@ -115,9 +123,11 @@ "source/system.obj" C_DEPS__QUOTED += \ +"source/adc.d" \ "source/can.d" \ "source/errata_SSWF021_45.d" \ "source/esm.d" \ +"source/etpwm.d" \ "source/gio.d" \ "source/lin.d" \ "source/mibspi.d" \ @@ -143,9 +153,11 @@ "source/sys_pmu.d" C_SRCS__QUOTED += \ +"../source/adc.c" \ "../source/can.c" \ "../source/errata_SSWF021_45.c" \ "../source/esm.c" \ +"../source/etpwm.c" \ "../source/gio.c" \ "../source/lin.c" \ "../source/mibspi.c" \ Index: firmware/HD.dil =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/HD.dil (.../HD.dil) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/HD.dil (.../HD.dil) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -1,4 +1,4 @@ -# RM46L852PGE 10/24/19 17:47:30 +# RM46L852PGE 11/06/19 07:57:31 # ARCH=RM46L852PGE # @@ -179,7 +179,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=103.335 DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0 @@ -443,7 +443,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=FIQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1 @@ -632,7 +632,7 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0802ffff DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK @@ -651,8 +651,8 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=165 DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0 DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080 @@ -838,7 +838,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1 @@ -859,7 +859,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00002000 DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x0008 DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt @@ -5552,13 +5552,13 @@ DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0 DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=3.338546 DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16 DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=2 DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16 DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.258 DRIVER.ADC.VAR.ADC2_PORT_BIT0_DIR.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000 @@ -5588,8 +5588,8 @@ DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 -DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=387.08 +DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.258 DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT @@ -5656,7 +5656,7 @@ DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00020000 DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005 DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=96.77 DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT @@ -5726,12 +5726,12 @@ DRIVER.ADC.VAR.ADC1_PORT_BIT0_PDR.VALUE=0 DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=300.00 DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.258 DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULL.VALUE=2 DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16 DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300 -DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=2 DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=387.08 DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000 @@ -5740,11 +5740,11 @@ DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000 DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 -DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=387.08 DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PSL.VALUE=1 -DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=387.08 DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16 DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000 @@ -5762,20 +5762,20 @@ DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100 DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00 DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000020 DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00 DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000 DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0 DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1 -DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000002 DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0 @@ -5810,7 +5810,7 @@ DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=387.08 -DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=48.386 DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 @@ -5821,7 +5821,7 @@ DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00010000 DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 @@ -7253,7 +7253,7 @@ DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.DMA_INTBTCEN_14.VALUE=1 DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=1 DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0 @@ -7272,7 +7272,7 @@ DRIVER.PINMUX.VAR.DMA_ENABLEINT_4.VALUE=1 DRIVER.PINMUX.VAR.PINMUX10.VALUE=PINMUX_PIN_86_AD1EVT DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=2 DRIVER.PINMUX.VAR.DMA_PRITY_11.VALUE=FIXED DRIVER.PINMUX.VAR.DMA_CHPR_10_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_PRITY_1_VALUE.VALUE=0x0001 @@ -7297,15 +7297,15 @@ DRIVER.PINMUX.VAR.DMA_PRITY_16.VALUE=FIXED DRIVER.PINMUX.VAR.PINMUX33.VALUE="PINMUX_PIN_36_HET1_04 | PINMUX_PIN_51_MIBSPI3SOMI | PINMUX_PIN_52_MIBSPI3SIMO | PINMUX_PIN_53_MIBSPI3CLK" DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_PIN_118_HET1_10 | PINMUX_PIN_124_HET1_12" -DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_HET1_18 | PINMUX_PIN_141_HET1_20" +DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_ETPWM6A | PINMUX_PIN_141_HET1_20" DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_PIN_125_HET1_14 | PINMUX_PIN_126_GIOB_0" DRIVER.PINMUX.VAR.DMA_ADDMR_26_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_CHANNEL_20_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ADDMR_18_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_CHANNEL_12_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.PINMUX35.VALUE=0 -DRIVER.PINMUX.VAR.PINMUX27.VALUE=PINMUX_PIN_32_MIBSPI5NCS_0 +DRIVER.PINMUX.VAR.PINMUX27.VALUE=PINMUX_PIN_32_ETPWM4A DRIVER.PINMUX.VAR.PINMUX19.VALUE=PINMUX_PIN_127_HET1_30 DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0 @@ -7694,7 +7694,7 @@ DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=2 DRIVER.PINMUX.VAR.DMA_ADDMR_27_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_CHANNEL_21_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ADDMR_19_VALUE.VALUE=0x0001 @@ -7714,7 +7714,7 @@ DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0 -DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=1 DRIVER.PINMUX.VAR.DMA_INTEN_13.VALUE=1 DRIVER.PINMUX.VAR.DMA_INTFTCEN_7.VALUE=1 DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0 @@ -7951,7 +7951,7 @@ DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0 DRIVER.PINMUX.VAR.DMA_BYP_13.VALUE=1 DRIVER.PINMUX.VAR.DMA_INTBTCEN_3.VALUE=1 -DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.MUX42_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX34_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX26_OPTION1.VALUE=0 @@ -8015,18 +8015,18 @@ DRIVER.PINMUX.VAR.DMA_PRITY_8.VALUE=FIXED DRIVER.PINMUX.VAR.MUX21_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.MUX13_CONFLICT.VALUE=0 -DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=1 DRIVER.PINMUX.VAR.PIN_MUX_51_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_43_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_35_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_27_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=4 DRIVER.PINMUX.VAR.DMA_TTYPE_3_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_PRITY_9.VALUE=FIXED DRIVER.PINMUX.VAR.MUX11_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.MUX11_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.ETPWM_TBCLK_SYNC_ENABLE.VALUE=0 -DRIVER.PINMUX.VAR.AD1.VALUE=0 +DRIVER.PINMUX.VAR.AD1.VALUE=1 DRIVER.PINMUX.VAR.MUX11_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.AD2.VALUE=0 DRIVER.PINMUX.VAR.MUX94_CONFLICT.VALUE=0 @@ -8198,7 +8198,7 @@ DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0 -DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_EIDXD_26.VALUE=0 @@ -8300,7 +8300,7 @@ DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=1 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_IET_COUNT_27.VALUE=0 @@ -8561,7 +8561,7 @@ DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=1 -DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=2 DRIVER.PINMUX.VAR.DMA_ADDMW_30_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ADDMW_22_VALUE.VALUE=0x0001 @@ -8641,7 +8641,7 @@ DRIVER.PINMUX.VAR.DMA_INTMP_5.VALUE=GROUP_A DRIVER.PINMUX.VAR.DMA_TRIG_3_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ACC_1.VALUE=ALL -DRIVER.PINMUX.VAR.ETPWM.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM.VALUE=1 DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.DMA_INTMP_6.VALUE=GROUP_A DRIVER.PINMUX.VAR.DMA_ACC_2.VALUE=ALL @@ -8685,7 +8685,7 @@ DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0 -DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=1 DRIVER.PINMUX.VAR.DMA_BASE.VALUE=0xFFFFF000 DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0 @@ -8732,7 +8732,7 @@ DRIVER.PINMUX.VAR.DMA_ADDMR_17_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_CHANNEL_11_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0 -DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0 @@ -8744,7 +8744,7 @@ DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0 -DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=1 DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0 @@ -8834,7 +8834,7 @@ DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_INTLFSEN_8.VALUE=1 -DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_GIOA_5" +DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_ETPWM1A" DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0 @@ -8851,19 +8851,19 @@ DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12.VALUE=8BIT DRIVER.PINMUX.VAR.ETPWM4_EQEPERR12.VALUE=EQEPERR12 -DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03" +DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_PIN_22_ETPWM2A | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03" DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT -DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_HET1_02 | PINMUX_PIN_31_HET1_05" +DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_HET1_05" DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_EIDXS_10.VALUE=0 DRIVER.PINMUX.VAR.DMA_CHANNEL_0.VALUE=CHANNEL0 -DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_HET1_09" +DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_ETPWM7A" DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23.VALUE=8BIT @@ -9374,23 +9374,23 @@ DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=500.000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0 DRIVER.ETPWM.VAR.ETPWM7_SOCB_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=50 DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1 @@ -9437,8 +9437,8 @@ DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=1000.000 DRIVER.ETPWM.VAR.ETPWM5_DCBEVT1.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=1000.000 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0 @@ -9492,7 +9492,7 @@ DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME_REG.VALUE=3 DRIVER.ETPWM.VAR.ETPWM2_OSHT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY.VALUE=50 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_INTERRUPT_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_OSHT2.VALUE=0x0000 @@ -9544,8 +9544,8 @@ DRIVER.ETPWM.VAR.ETPWM2_SOCA_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=77.418 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=500.000 DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000 @@ -9627,7 +9627,7 @@ DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_OSHT6.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=103.335 DRIVER.ETPWM.VAR.ETPWM5_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=50 DRIVER.ETPWM.VAR.ETPWM6_PWMB_POLARITY.VALUE=0 @@ -9637,7 +9637,7 @@ DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=1000 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000 DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 @@ -9701,7 +9701,7 @@ DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=500.000 DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000 @@ -9710,7 +9710,7 @@ DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000 @@ -9719,12 +9719,12 @@ DRIVER.ETPWM.VAR.ETPWM5_CBC3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY_NEW.VALUE=50.0 DRIVER.ETPWM.VAR.ETPWM3_PWMB_POLARITY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_OST.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_CBC4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_CBC5.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=50.000 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=38.709 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_CBC6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=100 @@ -9847,7 +9847,7 @@ DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=50 DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100 @@ -9878,7 +9878,7 @@ DRIVER.ETPWM.VAR.ETPWM6_DCAEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_RDELAY_SOURCE.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ECAP.VAR.ECAP1_PRESCALE_REG.VALUE=0 DRIVER.ECAP.VAR.ECAP2_ENA_PWM.VALUE=0 DRIVER.ECAP.VAR.ECAP4_PRD.VALUE=0x0000 Index: firmware/HD.hcg =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/HD.hcg (.../HD.hcg) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/HD.hcg (.../HD.hcg) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -269,7 +269,9 @@ adc.h - + + adc.c + @@ -401,7 +403,9 @@ etpwm.h - + + etpwm.c + reg_ecap.h @@ -571,7 +575,7 @@ include\adc.h - + source\adc.c @@ -763,7 +767,7 @@ include\etpwm.h - + source\etpwm.c Index: firmware/include/adc.h =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/include/adc.h (.../adc.h) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/include/adc.h (.../adc.h) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -229,8 +229,31 @@ uint32 CONFIG_PARCR; }adc_config_reg_t; +#define ADC1_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC1_CLOCKCR_CONFIGVALUE (9U) +#define ADC1_G0MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000020U | (uint32)0x00000002U) +#define ADC1_G1MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U) +#define ADC1_G2MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U) +#define ADC1_G0SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT) +#define ADC1_G1SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT) +#define ADC1_G2SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT) + +#define ADC1_BNDCR_CONFIGVALUE ((uint32)((uint32)8U << 16U)|(8U + 8U)) +#define ADC1_BNDEND_CONFIGVALUE (2U) + +#define ADC1_G0SAMP_CONFIGVALUE (2U) +#define ADC1_G1SAMP_CONFIGVALUE (2U) +#define ADC1_G2SAMP_CONFIGVALUE (2U) + +#define ADC1_G0SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) +#define ADC1_G1SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) +#define ADC1_G2SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) + +#define ADC1_PARCR_CONFIGVALUE (0x00000005U) + + /** * @defgroup ADC ADC * @brief Analog To Digital Converter Module. @@ -261,6 +284,8 @@ void adcSetEVTPin(adcBASE_t *adc, uint32 value); uint32 adcGetEVTPin(adcBASE_t *adc); +void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type); +void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type); /** @fn void adcNotification(adcBASE_t *adc, uint32 group) * @brief Group notification Index: firmware/include/etpwm.h =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/include/etpwm.h (.../etpwm.h) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/include/etpwm.h (.../etpwm.h) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -468,13 +468,13 @@ #define ETPWM1_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM1_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM1_TBPRD_CONFIGVALUE 1000U +#define ETPWM1_TBPRD_CONFIGVALUE 25833U #define ETPWM1_CMPCTL_CONFIGVALUE 0x00000000U -#define ETPWM1_CMPA_CONFIGVALUE 50U -#define ETPWM1_CMPB_CONFIGVALUE 50U +#define ETPWM1_CMPA_CONFIGVALUE 0U +#define ETPWM1_CMPB_CONFIGVALUE 0U #define ETPWM1_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM1_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM1_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM1_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM1_DBRED_CONFIGVALUE 1U #define ETPWM1_DBFED_CONFIGVALUE 1U #define ETPWM1_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -483,7 +483,7 @@ #define ETPWM1_TZEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U) #define ETPWM1_ETSEL_CONFIGVALUE ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U)) #define ETPWM1_ETPS_CONFIGVALUE ((uint16)1U | (uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)) -#define ETPWM1_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) +#define ETPWM1_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) #define ETPWM1_DCTRIPSEL_CONFIGVALUE 0x00000000U #define ETPWM1_DCACTL_CONFIGVALUE 0x00000000U #define ETPWM1_DCBCTL_CONFIGVALUE 0x00000000U Index: firmware/include/sys_vim.h =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/include/sys_vim.h (.../sys_vim.h) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/include/sys_vim.h (.../sys_vim.h) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -94,6 +94,7 @@ extern void rtiCompare1Interrupt(void); extern void rtiCompare3Interrupt(void); extern void linHighLevelInterrupt(void); +extern void adc1Group0Interrupt(void); extern void can1HighLevelInterrupt(void); extern void dmaBTCAInterrupt(void); extern void sciHighLevelInterrupt(void); @@ -143,7 +144,7 @@ | (uint32)((uint32)SYS_IRQ << 11U)\ | (uint32)((uint32)SYS_IRQ << 12U)\ | (uint32)((uint32)SYS_FIQ << 13U)\ - | (uint32)((uint32)SYS_IRQ << 14U)\ + | (uint32)((uint32)SYS_FIQ << 14U)\ | (uint32)((uint32)SYS_IRQ << 15U)\ | (uint32)((uint32)SYS_FIQ << 16U)\ | (uint32)((uint32)SYS_IRQ << 17U)\ @@ -275,7 +276,7 @@ | (uint32)((uint32)0U << 11U)\ | (uint32)((uint32)0U << 12U)\ | (uint32)((uint32)1U << 13U)\ - | (uint32)((uint32)0U << 14U)\ + | (uint32)((uint32)1U << 14U)\ | (uint32)((uint32)0U << 15U)\ | (uint32)((uint32)1U << 16U)\ | (uint32)((uint32)0U << 17U)\ Index: firmware/source/adc.c =================================================================== diff -u --- firmware/source/adc.c (revision 0) +++ firmware/source/adc.c (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -0,0 +1,1010 @@ +/** @file adc.c +* @brief ADC Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the ADC driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "adc.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + +/** @fn void adcInit(void) +* @brief Initializes ADC Driver +* +* This function initializes the ADC driver. +* +*/ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : ADC_SourceId_001 */ +/* DesignId : ADC_DesignId_001 */ +/* Requirements : HL_SR185 */ +void adcInit(void) +{ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + /** @b Initialize @b ADC1: */ + + /** - Reset ADC module */ + adcREG1->RSTCR = 1U; + adcREG1->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG1->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG1->CLOCKCR = 9U; + + /** - Setup memory boundaries */ + adcREG1->BNDCR = (uint32)((uint32)8U << 16U) | (8U + 8U); + adcREG1->BNDEND = (adcREG1->BNDEND & 0xFFFF0000U) | (2U); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[0U] = (uint32)ADC_12_BIT + | (uint32)0x00000020U + | (uint32)0x00000002U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->EVSRC = (uint32)0x00000000U + | (uint32)ADC1_EVENT; + + /** - Setup event group sample window */ + adcREG1->EVSAMP = 2U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->EVSAMPDISEN = (uint32)((uint32)0U << 8U) + | (uint32)0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[1U] = (uint32)ADC_12_BIT + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G1SRC = (uint32)0x00000000U + | (uint32)ADC1_EVENT; + + /** - Setup group 1 sample window */ + adcREG1->G1SAMP = 2U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G1SAMPDISEN = (uint32)((uint32)0U << 8U) + | (uint32)0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[2U] = (uint32)ADC_12_BIT + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G2SRC = (uint32)0x00000000U + | (uint32)ADC1_EVENT; + + /** - Setup group 2 sample window */ + adcREG1->G2SAMP = 2U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G2SAMPDISEN = (uint32)((uint32)0U << 8U) + | (uint32)0x00000000U; + + /** - ADC1 EVT pin output value */ + adcREG1->EVTOUT = 0U; + + /** - ADC1 EVT pin direction */ + adcREG1->EVTDIR = 0U; + + /** - ADC1 EVT pin open drain enable */ + adcREG1->EVTPDR = 0U; + + /** - ADC1 EVT pin pullup / pulldown selection */ + adcREG1->EVTPSEL = 1U; + + /** - ADC1 EVT pin pullup / pulldown enable*/ + adcREG1->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG1->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while (((adcREG1->BNDEND & 0xFFFF0000U) >> 16U ) != 0U) + { + } /* Wait */ + + /** - Setup parity */ + adcREG1->PARCR = 0x00000005U; + + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + +/** - s_adcSelect is used as constant table for channel selection */ +static const uint32 s_adcSelect[2U][3U] = +{ + {0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00010000U | + 0x00020000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U, + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U, + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U}, + {0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U , + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U, + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U | + 0x00000000U} +}; + +/** - s_adcFiFoSize is used as constant table for channel selection */ +static const uint32 s_adcFiFoSize[2U][3U] = +{ + {16U, + 16U, + 16U}, + {16U, + 16U, + 16U} +}; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group) +* @brief Starts an ADC conversion +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function starts a conversion of the ADC hardware group. +* +*/ +/* SourceId : ADC_SourceId_002 */ +/* DesignId : ADC_DesignId_002 */ +/* Requirements : HL_SR186 */ +void adcStartConversion(adcBASE_t *adc, uint32 group) +{ + uint32 index = (adc == adcREG1) ? 0U : 1U; + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + + /** - Setup FiFo size */ + adc->GxINTCR[group] = s_adcFiFoSize[index][group]; + + /** - Start Conversion */ + adc->GxSEL[group] = s_adcSelect[index][group]; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + +/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group) +* @brief Stops an ADC conversion +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function stops a conversion of the ADC hardware group. +* +*/ +/* SourceId : ADC_SourceId_003 */ +/* DesignId : ADC_DesignId_003 */ +/* Requirements : HL_SR187 */ +void adcStopConversion(adcBASE_t *adc, uint32 group) +{ +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + + /** - Stop Conversion */ + adc->GxSEL[group] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + + +/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group) +* @brief Resets FiFo read and write pointer. +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function resets the FiFo read and write pointers. +* +*/ +/* SourceId : ADC_SourceId_004 */ +/* DesignId : ADC_DesignId_004*/ +/* Requirements : HL_SR188 */ +void adcResetFiFo(adcBASE_t *adc, uint32 group) +{ +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + /** - Reset FiFo */ + adc->GxFIFORESETCR[group] = 1U; + + /** @note The function adcInit has to be called before this function can be used.\n + * the conversion should be stopped before calling this function. + */ + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + + +/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) +* @brief Gets converted a ADC values +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* @param[out] data Pointer to store ADC converted data +* @return The function will return the number of converted values copied into data buffer: +* +* This function writes a ADC message into a ADC message box. +* +*/ +/* SourceId : ADC_SourceId_005 */ +/* DesignId : ADC_DesignId_005 */ +/* Requirements : HL_SR189 */ +uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) +{ + uint32 i; + uint32 buf; + uint32 mode; + uint32 index = (adc == adcREG1) ? 0U : 1U; + + uint32 intcr_reg = adc->GxINTCR[group]; + uint32 count = (intcr_reg >= 256U) ? s_adcFiFoSize[index][group] : (s_adcFiFoSize[index][group] - (uint32)(intcr_reg & 0xFFU)); + adcData_t *ptr = data; + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + mode = (adc->OPMODECR & ADC_12_BIT_MODE); + + if(mode == ADC_12_BIT_MODE) + { + /** - Get conversion data and channel/pin id */ + for (i = 0U; i < count; i++) + { + buf = adc->GxBUF[group].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + ptr->value = (uint16)(buf & 0xFFFU); + ptr->id = (uint32)((buf >> 16U) & 0x1FU); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + else + { + /** - Get conversion data and channel/pin id */ + for (i = 0U; i < count; i++) + { + buf = adc->GxBUF[group].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + ptr->value = (uint16)(buf & 0x3FFU); + ptr->id = (uint32)((buf >> 10U) & 0x1FU); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + + + adc->GxINTFLG[group] = 9U; + + /** @note The function adcInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + return count; +} + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + + +/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) +* @brief Checks if FiFo buffer is full +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* @return The function will return: +* - 0: When FiFo buffer is not full +* - 1: When FiFo buffer is full +* - 3: When FiFo buffer overflow occurred +* +* This function checks FiFo buffer status. +* +*/ +/* SourceId : ADC_SourceId_006 */ +/* DesignId : ADC_DesignId_006 */ +/* Requirements : HL_SR190 */ +uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) +{ + uint32 flags; + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + + /** - Read FiFo flags */ + flags = adc->GxINTFLG[group] & 3U; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + +/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) +* @brief Checks if Conversion is complete +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* @return The function will return: +* - 0: When is not finished +* - 8: When conversion is complete +* +* This function checks if conversion is complete. +* +*/ +/* SourceId : ADC_SourceId_007 */ +/* DesignId : ADC_DesignId_007 */ +/* Requirements : HL_SR191 */ +uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) +{ + uint32 flags; + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + + /** - Read conversion flags */ + flags = adc->GxINTFLG[group] & 8U; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/** @fn void adcCalibration(adcBASE_t *adc) +* @brief Computes offset error using Calibration mode +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* This function computes offset error using Calibration mode +* +*/ +/* SourceId : ADC_SourceId_008 */ +/* DesignId : ADC_DesignId_010 */ +/* Requirements : HL_SR194 */ +void adcCalibration(adcBASE_t *adc) +{ +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + + uint32 conv_val[5U]={0U,0U,0U,0U,0U}; + uint32 loop_index=0U; + uint32 offset_error=0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[0U]=0x00U; + adc->GxSEL[1U]=0x00U; + adc->GxSEL[2U]=0x00U; + + for(loop_index=0U;loop_index<4U;loop_index++) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR=0x0U; + + switch(loop_index) + { + case 0U : /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR=0x0U; + break; + + case 1U : /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR=0x0100U; + break; + + case 2U : /* Test 1 : Bride En = 1 , HiLo =0 */ + adc->CALCR=0x0200U; + break; + + case 3U : /* Test 1 : Bride En = 1 , HiLo =1 */ + adc->CALCR=0x0300U; + break; + default : + break; + } + + /* Enable Calibration mode */ + adc->CALCR|=0x1U; + + /* Start calibration conversion */ + adc->CALCR|=0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((adc->CALCR & 0x00010000U)==0x00010000U) + { + } /* Wait */ + + /* Read converted value */ + conv_val[loop_index]= adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR=0x0U; + + /* Compute the Offset error correction value */ + conv_val[4U]=conv_val[0U]+ conv_val[1U] + conv_val[2U] + conv_val[3U]; + + conv_val[4U]=(conv_val[4U]/4U); + + offset_error=conv_val[4U]-0x7FFU; + + /*Write the offset error to the Calibration register */ + /* Load 2;s complement of the computed value to ADCALR register */ + offset_error=~offset_error; + offset_error=offset_error & 0xFFFU; + offset_error=offset_error+1U; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + /** @note The function adcInit has to be called before using this function. */ + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ +} + + +/** @fn void adcMidPointCalibration(adcBASE_t *adc) +* @brief Computes offset error using Mid Point Calibration mode +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @return This function will return offset error using Mid Point Calibration mode +* +* This function computes offset error using Mid Point Calibration mode +* +*/ +/* SourceId : ADC_SourceId_009 */ +/* DesignId : ADC_DesignId_011 */ +/* Requirements : HL_SR195 */ +uint32 adcMidPointCalibration(adcBASE_t *adc) +{ +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + + uint32 conv_val[3U]={0U,0U,0U}; + uint32 loop_index=0U; + uint32 offset_error=0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[0U]=0x00U; + adc->GxSEL[1U]=0x00U; + adc->GxSEL[2U]=0x00U; + + for(loop_index=0U;loop_index<2U;loop_index++) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR=0x0U; + + switch(loop_index) + { + case 0U : /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR=0x0U; + break; + + case 1U : /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR=0x0100U; + break; + + default : + break; + + } + + /* Enable Calibration mode */ + adc->CALCR|=0x1U; + + /* Start calibration conversion */ + adc->CALCR|=0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((adc->CALCR & 0x00010000U)==0x00010000U) + { + } /* Wait */ + + /* Read converted value */ + conv_val[loop_index]= adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR=0x0U; + + /* Compute the Offset error correction value */ + conv_val[2U]=(conv_val[0U])+ (conv_val[1U]); + + conv_val[2U]=(conv_val[2U]/2U); + + offset_error=conv_val[2U]-0x7FFU; + + /* Write the offset error to the Calibration register */ + /* Load 2's complement of the computed value to ADCALR register */ + offset_error=~offset_error; + offset_error=offset_error+1U; + offset_error=offset_error & 0xFFFU; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + return(offset_error); + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group) +* @brief Enable notification +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function will enable the notification of a conversion. +* In single conversion mode for conversion complete and +* in continuous conversion mode when the FiFo buffer is full. +* +*/ +/* SourceId : ADC_SourceId_010 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : HL_SR192 */ +void adcEnableNotification(adcBASE_t *adc, uint32 group) +{ + uint32 notif = (((uint32)(adc->GxMODECR[group]) & 2U) == 2U) ? 1U : 8U; + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + + adc->GxINTENA[group] = notif; + + /** @note The function adcInit has to be called before this function can be used.\n + * This function should be called before the conversion is started + */ + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + + +/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group) +* @brief Disable notification +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* - adcREG2: ADC2 module pointer +* @param[in] group Hardware group of ADC module: +* - adcGROUP0: ADC event group +* - adcGROUP1: ADC group 1 +* - adcGROUP2: ADC group 2 +* +* This function will disable the notification of a conversion. +*/ +/* SourceId : ADC_SourceId_011 */ +/* DesignId : ADC_DesignId_009 */ +/* Requirements : HL_SR193 */ +void adcDisableNotification(adcBASE_t *adc, uint32 group) +{ +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + + adc->GxINTENA[group] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ +} + +/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value) +* @brief Set ADCEVT pin +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* @param[in] value Value to be set: 0 or 1 +* +* This function will set the ADC EVT pin if configured as an output pin. +*/ +/* SourceId : ADC_SourceId_020 */ +/* DesignId : ADC_DesignId_014 */ +/* Requirements : HL_SR529 */ +void adcSetEVTPin(adcBASE_t *adc, uint32 value) +{ + adc->EVTOUT = value; +} + +/** @fn uint32 adcGetEVTPin(adcBASE_t *adc) +* @brief Set ADCEVT pin +* @param[in] adc Pointer to ADC module: +* - adcREG1: ADC1 module pointer +* @return Value of the ADC EVT pin: 0 or 1 +* +* This function will return the value of ADC EVT pin. +*/ +/* SourceId : ADC_SourceId_021 */ +/* DesignId : ADC_DesignId_015 */ +/* Requirements : HL_SR529 */ +uint32 adcGetEVTPin(adcBASE_t *adc) +{ + return adc->EVTIN; +} + +/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ADC_SourceId_012 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : HL_SR203 */ +void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[0U] = ADC1_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[1U] = ADC1_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[2U] = ADC1_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE; + } + else + { + config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR; + config_reg->CONFIG_GxMODECR[0U] = adcREG1->GxMODECR[0U]; + config_reg->CONFIG_GxMODECR[1U] = adcREG1->GxMODECR[1U]; + config_reg->CONFIG_GxMODECR[2U] = adcREG1->GxMODECR[2U]; + config_reg->CONFIG_G0SRC = adcREG1->EVSRC; + config_reg->CONFIG_G1SRC = adcREG1->G1SRC; + config_reg->CONFIG_G2SRC = adcREG1->G2SRC; + config_reg->CONFIG_BNDCR = adcREG1->BNDCR; + config_reg->CONFIG_BNDEND = adcREG1->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG1->PARCR; + } +} + + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + +/** @fn void adc1Group0Interrupt(void) +* @brief ADC1 Event Group Interrupt Handler +*/ +#pragma CODE_STATE(adc1Group0Interrupt, 32) +#pragma INTERRUPT(adc1Group0Interrupt, FIQ) + +/* SourceId : ADC_SourceId_014 */ +/* DesignId : ADC_DesignId_013 */ +/* Requirements : HL_SR197, HL_SR196 */ +void adc1Group0Interrupt(void) +{ +/* USER CODE BEGIN (36) */ +/* USER CODE END */ + + adcREG1->GxINTFLG[0U] = 9U; + + adcNotification(adcREG1, adcGROUP0); + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ +} + + + + + Index: firmware/source/etpwm.c =================================================================== diff -u --- firmware/source/etpwm.c (revision 0) +++ firmware/source/etpwm.c (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -0,0 +1,2134 @@ +/** @file etpwm.c +* @brief ETPWM Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the ETPWM driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +#include "etpwm.h" +#include "pinmux.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + +/** @fn void etpwmInit(void) +* @brief Initializes the eTPWM Driver +* +* This function initializes the eTPWM module. +* +* @note This function sets the time-base counters in up-count mode. +* Application can configure the module in a different mode using other functions in this driver.(Sample code provided in the examples folder) +* In that case, application need not call etpwmInit function. +* pinmuxInit needs to be called before this function. +* +*/ +/* SourceId : ETPWM_SourceId_001 */ +/* DesignId : ETPWM_DesignId_001 */ +/* Requirements : HL_EPWM_SR1 */ +void etpwmInit(void) +{ +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + /** @b initialize @b ETPWM1 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG1->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG1->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG1->TBPRD = 25833U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG1->CMPA = 0U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG1->CMPB = 0U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG1->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG1->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG1->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0u << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG1->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG1->DBFED = 1U ; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG1->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG1->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG1->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG1->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG1->ETSEL & 0x0007U) != 0U) + { + etpwmREG1->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG1->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG1->ETSEL |= ((uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U)); + + /** - Sets up the ADC SOC period */ + etpwmREG1->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM2 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG2->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG2->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG2->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG2->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG2->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG2->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG2->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG2->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG2->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG2->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG2->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG2->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG2->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG2->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG2->ETSEL & 0x0007U) != 0U) + { + etpwmREG2->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG2->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG2->ETSEL |= ((uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U)); + + /** - Sets up the ADC SOC period */ + etpwmREG2->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM3 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG3->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG3->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG3->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG3->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG3->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG3->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG3->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG3->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG3->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG3->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG3->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG3->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + + /** - Sets up the event for interrupt */ + etpwmREG3->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG3->ETSEL & 0x0007U) != 0U) + { + etpwmREG3->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG3->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG3->ETSEL |= ((uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U)); + + /** - Sets up the ADC SOC period */ + etpwmREG3->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM4 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG4->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG4->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG4->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG4->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG4->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG4->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG4->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG4->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG4->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG4->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG4->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG4->ETSEL & 0x0007U) != 0U) + { + etpwmREG4->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG4->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG4->ETSEL |= (uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U); + + /** - Sets up the ADC SOC period */ + etpwmREG4->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM6 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG6->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG6->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG6->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG6->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG6->CMPB = 50U; + + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG6->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG6->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG6->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG6->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG6->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG6->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ + + + /** - Set trip source enable */ + etpwmREG6->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG6->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + + /** - Sets up the event for interrupt */ + etpwmREG6->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG6->ETSEL & 0x0007U) != 0U) + { + etpwmREG6->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG6->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG6->ETSEL |= (uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U); + + /** - Sets up the ADC SOC period */ + etpwmREG6->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM7 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG7->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG7->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG7->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG7->CMPB = 50U; + + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG7->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG7->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG7->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG7->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG7->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ + + + /** - Set trip source enable */ + etpwmREG7->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG7->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG7->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG7->ETSEL & 0x0007U) != 0U) + { + etpwmREG7->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG7->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG7->ETSEL |= (uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U); + + /** - Sets up the ADC SOC period */ + etpwmREG7->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +} + +/** @fn void etpwmStartTBCLK() +* @brief Start the time-base clocks of all eTPWMx modules +* +* This function starts the time-base clocks of all eTPWMx modules. +*/ +/* SourceId : ETPWM_SourceId_002 */ +/* DesignId : ETPWM_DesignId_002 */ +/* Requirements : HL_EPWM_SR36 */ +void etpwmStartTBCLK(void) +{ + /* Enable Pin Muxing */ + kickerReg->KICKER0 = 0x83E70B13U; + kickerReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_ON); + + /* Disable Pin Muxing */ + kickerReg->KICKER0 = 0x00000000U; + kickerReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmStopTBCLK() +* @brief Stop the time-base clocks of all eTPWMx modules +* +* This function stops the time-base clocks of all eTPWMx modules. +*/ +/* SourceId : ETPWM_SourceId_003 */ +/* DesignId : ETPWM_DesignId_003 */ +/* Requirements : HL_EPWM_SR36 */ +void etpwmStopTBCLK(void) +{ + /* Enable Pin Muxing */ + kickerReg->KICKER0 = 0x83E70B13U; + kickerReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_OFF); + + /* Disable Pin Muxing */ + kickerReg->KICKER0 = 0x00000000U; + kickerReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t hspclkdiv) +* @brief Sets the Time-base Clock divider +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param clkdiv Time-base clock divider +* - ClkDiv_by_1 +* - ClkDiv_by_2 +* - ClkDiv_by_4 +* - ClkDiv_by_8 +* - ClkDiv_by_16 +* - ClkDiv_by_32 +* - ClkDiv_by_64 +* - ClkDiv_by_128 +* @param hspclkdiv High Speed Time-base clock divider +* - HspClkDiv_by_1 +* - HspClkDiv_by_2 +* - HspClkDiv_by_4 +* - HspClkDiv_by_6 +* - HspClkDiv_by_8 +* - HspClkDiv_by_10 +* - HspClkDiv_by_12 +* - HspClkDiv_by_14 +* +* This function sets the TimeBase Clock and the High Speed time base clock divider +* TBCLK = VCLK4 / (HSPCLKDIV � CLKDIV) +*/ +/* SourceId : ETPWM_SourceId_004 */ +/* DesignId : ETPWM_DesignId_004 */ +/* Requirements : HL_EPWM_SR2 */ +void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t hspclkdiv) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x1F80U; + etpwm->TBCTL |= (uint16)clkdiv | (uint16)hspclkdiv; +} + +/** @fn void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period) +* @brief Sets period of timebase counter +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param period 16-bit Time-base period +* +* This function sets period of timebase counter +*/ +/* SourceId : ETPWM_SourceId_005 */ +/* DesignId : ETPWM_DesignId_005 */ +/* Requirements : HL_EPWM_SR3 */ +void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period) +{ + etpwm->TBPRD = period; +} + +/** @fn void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count) +* @brief Sets timebase counter +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param count 16-bit Counter value +* +* This function sets the timebase counter +*/ +/* SourceId : ETPWM_SourceId_006 */ +/* DesignId : ETPWM_DesignId_006 */ +/* Requirements : HL_EPWM_SR4 */ +void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count) +{ + etpwm->TBCTR = count; +} + +/** @fn void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) +* @brief Disable shadow mode for time-base period register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables shadow mode for time-base period register +*/ +/* SourceId : ETPWM_SourceId_007 */ +/* DesignId : ETPWM_DesignId_007 */ +/* Requirements : HL_EPWM_SR5 */ +void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) +{ + etpwm->TBCTL |= 0x0008U; +} + +/** @fn void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) +* @brief Enable shadow mode for time-base period register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function enables shadow mode for time-base period register +*/ +/* SourceId : ETPWM_SourceId_008 */ +/* DesignId : ETPWM_DesignId_008 */ +/* Requirements : HL_EPWM_SR5 */ +void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x0008U; +} + +/** @fn void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 direction) +* @brief Enable counter register load from phase register when a sync event occurs +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param phase Counter value to be loaded when a sync event occurs +* @param direction Direction of the counter after the sync event (Applied only if counter is in updown-count mode, ignores otherwise) +* - COUNT_UP +* - COUNT_DOWN +* - Pass 0 if not applied +* +* This function enables counter register load from phase register when a sync event occurs +*/ +/* SourceId : ETPWM_SourceId_009 */ +/* DesignId : ETPWM_DesignId_009 */ +/* Requirements : HL_EPWM_SR6 */ +void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 direction) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x2000U; + etpwm->TBCTL |= 0x0004U | direction; + etpwm->TBPHS = phase; +} + +/** @fn void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm) +* @brief Disable counter register load from phase register when a sync event occurs +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables counter register load from phase register when a sync event occurs +*/ +/* SourceId : ETPWM_SourceId_010 */ +/* DesignId : ETPWM_DesignId_010 */ +/* Requirements : HL_EPWM_SR6 */ +void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x0004U; +} + +/** @fn void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncMode_t syncmode) +* @brief Set the source of EPWMxSYNCO signal +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param syncOutSrc Synchronization Output Select +* - SyncOut_EPWMxSYNCI +* - SyncOut_CtrEqZero +* - SyncOut_CtrEqCmpB +* - SyncOut_Disable +* +* This function sets the source of synchronization output signal +*/ +/* SourceId : ETPWM_SourceId_011 */ +/* DesignId : ETPWM_DesignId_011 */ +/* Requirements : HL_EPWM_SR7 */ +void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncOut_t syncOutSrc) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x0030U; + etpwm->TBCTL |= syncOutSrc; +} + +/** @fn void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode) +* @brief Set the time-base counter mode +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param countermode Counter Mode +* - CounterMode_Up +* - Countermode_Down +* - CounterMode_UpDown +* - CounterMode_Stop +* +* This function sets the time-base counter mode of operation. +*/ +/* SourceId : ETPWM_SourceId_012 */ +/* DesignId : ETPWM_DesignId_012 */ +/* Requirements : HL_EPWM_SR8 */ +void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x0003U; + etpwm->TBCTL |= countermode; +} + +/** @fn void etpwmTriggerSWSync(etpwmBASE_t *etpwm) +* @brief Trigger a software synchronization pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function triggers a software synchronization pulse. SWFSYNC is valid (operates) only when EPWMxSYNCI as SyncOut +*/ +/* SourceId : ETPWM_SourceId_013 */ +/* DesignId : ETPWM_DesignId_013 */ +/* Requirements : HL_EPWM_SR9 */ +void etpwmTriggerSWSync(etpwmBASE_t *etpwm) +{ + etpwm->TBCTL |= 0x0040U; +} + +/** @fn void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode) +* @brief Set the pulse width modulation (ETPWM) run mode +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param runmode Run mode +* - RunMode_SoftStopAfterIncr : Stop after the next time-base counter increment +* - RunMode_SoftStopAfterDecr : Stop after the next time-base counter decrement +* - RunMode_SoftStopAfterCycle : Stop when counter completes a whole cycle +* - RunMode_FreeRun : Free-run +* +* This function select the behaviour of the ePWM time-base counter during emulation events +*/ +/* SourceId : ETPWM_SourceId_014 */ +/* DesignId : ETPWM_DesignId_014 */ +/* Requirements : HL_EPWM_SR10 */ +void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode) +{ + etpwm->TBCTL &= (uint16)~(uint16)0xC000U; + etpwm->TBCTL |= runmode; +} + +/** @fn void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value) +* @brief Set the Compare A value +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param value 16-bit Compare A value +* +* This function sets the compare A value +*/ +/* SourceId : ETPWM_SourceId_015 */ +/* DesignId : ETPWM_DesignId_015 */ +/* Requirements : HL_EPWM_SR11 */ +void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value) +{ + etpwm->CMPA = value; +} + +/** @fn void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value) +* @brief Set the Compare B value +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param value 16-bit Compare B value +* +* This function sets the compare B register +*/ +/* SourceId : ETPWM_SourceId_016 */ +/* DesignId : ETPWM_DesignId_016 */ +/* Requirements : HL_EPWM_SR11 */ +void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value) +{ + etpwm->CMPB = value; +} + +/** @fn void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) +* @brief Enable shadow mode for Compare A register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param loadmode Active Counter-Compare A (CMPA) Load From Shadow Select Mode +* - LoadMode_CtrEqZero : Load on CTR = Zero +* - LoadMode_CtrEqPeriod : Load on CTR = PRD +* - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD +* - LoadMode_Freeze : Freeze (no loads possible) +* +* This function enables shadow mode for Compare A register +*/ +/* SourceId : ETPWM_SourceId_017 */ +/* DesignId : ETPWM_DesignId_017 */ +/* Requirements : HL_EPWM_SR12 */ +void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) +{ + etpwm->CMPCTL &= (uint16)~(uint16)0x0013U; + etpwm->CMPCTL |= loadmode; +} + +/** @fn void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm) +* @brief Disable shadow mode for Compare A register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables shadow mode for Compare A register +*/ +/* SourceId : ETPWM_SourceId_018 */ +/* DesignId : ETPWM_DesignId_018 */ +/* Requirements : HL_EPWM_SR12 */ +void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm) +{ + etpwm->CMPCTL |= 0x0010U; +} + +/** @fn void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) +* @brief Enable shadow mode for Compare B register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param loadmode Active Counter-Compare B (CMPB) Load From Shadow Select Mode +* - LoadMode_CtrEqZero : Load on CTR = Zero +* - LoadMode_CtrEqPeriod : Load on CTR = PRD +* - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD +* - LoadMode_Freeze : Freeze (no loads possible) +* +* This function enables shadow mode for Compare B register +*/ +/* SourceId : ETPWM_SourceId_019 */ +/* DesignId : ETPWM_DesignId_019 */ +/* Requirements : HL_EPWM_SR12 */ +void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) +{ + etpwm->CMPCTL &= (uint16)~(uint16)0x004CU; + etpwm->CMPCTL |= (uint16)((uint16)loadmode << 2U); +} + +/** @fn void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm) +* @brief Disable shadow mode for Compare B register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables shadow mode for Compare B register +*/ +/* SourceId : ETPWM_SourceId_020 */ +/* DesignId : ETPWM_DesignId_020 */ +/* Requirements : HL_EPWM_SR12 */ +void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm) +{ + etpwm->CMPCTL |= 0x0040U; +} + +/** @fn void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig) +* @brief Configure Action Qualifier submodule to generate PWMA +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param actionqualconfig Action Qualifier configuration +* +* Example usage (Removing semicolons to avoid MISRA warnings): +* etpwmActionQualConfig_t configA +* configA.CtrEqZero_Action = ActionQual_Set +* configA.CtrEqPeriod_Action = ActionQual_Disabled +* configA.CtrEqCmpAUp_Action = ActionQual_Clear +* configA.CtrEqCmpADown_Action = ActionQual_Disabled +* configA.CtrEqCmpBUp_Action = ActionQual_Disabled +* configA.CtrEqCmpBDown_Action = ActionQual_Disabled +* void etpwmSetActionQualPwmA(etpwmREG1, configA) +* +* This function configures Action Qualifier submodule to generate PWMA +*/ +/* SourceId : ETPWM_SourceId_021 */ +/* DesignId : ETPWM_DesignId_021 */ +/* Requirements : HL_EPWM_SR13 */ +void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig) +{ + etpwm->AQCTLA = ((uint16)((uint16)actionqualconfig.CtrEqZero_Action << 0U) | + (uint16)((uint16)actionqualconfig.CtrEqPeriod_Action << 2U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpAUp_Action << 4U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpADown_Action << 6U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpBUp_Action << 8U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpBDown_Action << 10U)); + +} + +/** @fn void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig) +* @brief Configure Action Qualifier submodule to generate PWMB +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param actionqualconfig Action Qualifier configuration +* +* Example usage (Removing semicolons to avoid MISRA warnings): +* etpwmActionQualConfig_t configB +* configB.CtrEqZero_Action = ActionQual_Set +* configB.CtrEqPeriod_Action = ActionQual_Disabled +* configB.CtrEqCmpAUp_Action = ActionQual_Disabled +* configB.CtrEqCmpADown_Action = ActionQual_Disabled +* configB.CtrEqCmpBUp_Action = ActionQual_Clear +* configB.CtrEqCmpBDown_Action = ActionQual_Disabled +* void etpwmSetActionQualPwmB(etpwmREG1, configB) +* +* This function configures Action Qualifier submodule to generate PWMB +*/ +/* SourceId : ETPWM_SourceId_022 */ +/* DesignId : ETPWM_DesignId_022 */ +/* Requirements : HL_EPWM_SR13 */ +void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig) +{ + etpwm->AQCTLB = ((uint16)((uint16)actionqualconfig.CtrEqZero_Action << 0U) | + (uint16)((uint16)actionqualconfig.CtrEqPeriod_Action << 2U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpAUp_Action << 4U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpADown_Action << 6U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpBUp_Action << 8U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpBDown_Action << 10U)); + +} + +/** @fn void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig) +* @brief Enable DeadBand module +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param deadbandconfig DeadBand configuration +* +* This function configures Action Qualifier submodule to generate PWMB +*/ +/* SourceId : ETPWM_SourceId_023 */ +/* DesignId : ETPWM_DesignId_023 */ +/* Requirements : HL_EPWM_SR14 */ +void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig) +{ + uint16 halfCycleMask = (uint16)((deadbandconfig.halfCycleEnable) ? 0x8000U : 0U); + etpwm->DBCTL = ((uint16)deadbandconfig.inputmode | + (uint16)deadbandconfig.outputmode | + (uint16)deadbandconfig.polarity | + halfCycleMask); +} + +/** @fn void etpwmDisableDeadband(etpwmBASE_t *etpwm) +* @brief Disable DeadBand module +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function bypasses the Deadband submodule +*/ +/* SourceId : ETPWM_SourceId_024 */ +/* DesignId : ETPWM_DesignId_024 */ +/* Requirements : HL_EPWM_SR14 */ +void etpwmDisableDeadband(etpwmBASE_t *etpwm) +{ + etpwm->DBCTL = 0U; +} + +/** @fn void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay) +* @brief Sets the rising and falling edge delay +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param Rdelay 16-bit rising edge delay in terms of TCLK ticks +* @param Fdelay 16-bit falling edge delay in terms of TCLK ticks +* +* This function sets the rising and falling edge delays in the DeadBand submodule +*/ +/* SourceId : ETPWM_SourceId_025 */ +/* DesignId : ETPWM_DesignId_025 */ +/* Requirements : HL_EPWM_SR14 */ +void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay) +{ + etpwm->DBRED = Rdelay; + etpwm->DBFED = Fdelay; +} + +/** @fn void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig) +* @brief Enable chopping +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param choppingconfig Chopper submodule configuration +* +* This function enables the chopper submodule with the given configuration +*/ +/* SourceId : ETPWM_SourceId_026 */ +/* DesignId : ETPWM_DesignId_026 */ +/* Requirements : HL_EPWM_SR15 */ +void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig) +{ + etpwm->PCCTL = ((uint16)0x0001U | + (uint16)choppingconfig.oswdth | + (uint16)choppingconfig.freq | + (uint16)choppingconfig.duty); +} + +/** @fn void etpwmDisableChopping(etpwmBASE_t *etpwm) +* @brief Disable chopping +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables the chopper submodule +*/ +/* SourceId : ETPWM_SourceId_027 */ +/* DesignId : ETPWM_DesignId_027 */ +/* Requirements : HL_EPWM_SR15 */ +void etpwmDisableChopping(etpwmBASE_t *etpwm) +{ + etpwm->PCCTL = 0U; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) +* @brief Select the tripzone zources +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param sources Trip zone sources (sources can be ORed) +* - CycleByCycle_TZ1 : Enable TZ1 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ2 : Enable TZ2 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ3 : Enable TZ3 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ4 : Enable TZ4 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ5 : Enable TZ5 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ6 : Enable TZ6 as a Cycle-by-cycle trip source +* - CycleByCycle_DCAEVT2 : Enable DCAEVT2 as a Cycle-by-cycle trip source +* - CycleByCycle_DCBEVT2 : Enable DCBEVT2 as a Cycle-by-cycle trip source +* - OneShot_TZ1 : Enable TZ1 as a One-shot trip source +* - OneShot_TZ2 : Enable TZ2 as a One-shot trip source +* - OneShot_TZ3 : Enable TZ3 as a One-shot trip source +* - OneShot_TZ4 : Enable TZ4 as a One-shot trip source +* - OneShot_TZ5 : Enable TZ5 as a One-shot trip source +* - OneShot_TZ6 : Enable TZ6 as a One-shot trip source +* - OneShot_DCAEVT1 : Enable DCAEVT1 as a One-shot trip source +* - OneShot_DCBEVT1 : Enable DCBEVT1 as a One-shot trip source +* +* This function selects the tripzone sources for cycle-by-cycle and one-shot trip +*/ +/* SourceId : ETPWM_SourceId_028 */ +/* DesignId : ETPWM_DesignId_028 */ +/* Requirements : HL_EPWM_SR16 */ +void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) +{ + etpwm->TZSEL |= sources; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) +* @brief Disable the tripzone zources +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param sources Trip zone sources (sources can be ORed) +* - CycleByCycle_TZ1 : Disable TZ1 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ2 : Disable TZ2 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ3 : Disable TZ3 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ4 : Disable TZ4 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ5 : Disable TZ5 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ6 : Disable TZ6 as a Cycle-by-cycle trip source +* - CycleByCycle_DCAEVT2 : Disable DCAEVT2 as a Cycle-by-cycle trip source +* - CycleByCycle_DCBEVT2 : Disable DCBEVT2 as a Cycle-by-cycle trip source +* - OneShot_TZ1 : Disable TZ1 as a One-shot trip source +* - OneShot_TZ2 : Disable TZ2 as a One-shot trip source +* - OneShot_TZ3 : Disable TZ3 as a One-shot trip source +* - OneShot_TZ4 : Disable TZ4 as a One-shot trip source +* - OneShot_TZ5 : Disable TZ5 as a One-shot trip source +* - OneShot_TZ6 : Disable TZ6 as a One-shot trip source +* - OneShot_DCAEVT1 : Disable DCAEVT1 as a One-shot trip source +* - OneShot_DCBEVT1 : Disable DCBEVT1 as a One-shot trip source +* +* This function disables the tripzone sources for cycle-by-cycle or one-shot trip +*/ +/* SourceId : ETPWM_SourceId_029 */ +/* DesignId : ETPWM_DesignId_029 */ +/* Requirements : HL_EPWM_SR16 */ +void etpwmDisableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) +{ + etpwm->TZSEL &= (uint16)~(uint16)sources; +} + +/** @fn void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t tripactionconfig) +* @brief Set the action for each trip event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param tripactionconfig Trip action configuration +* +* This function sets the action for each trip event +*/ +/* SourceId : ETPWM_SourceId_030 */ +/* DesignId : ETPWM_DesignId_030 */ +/* Requirements : HL_EPWM_SR17 */ +void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t tripactionconfig) +{ + etpwm->TZCTL = ((uint16)((uint16)tripactionconfig.TripEvent_ActionOnPWMA << 0U) | + (uint16)((uint16)tripactionconfig.TripEvent_ActionOnPWMB << 2U) | + (uint16)((uint16)tripactionconfig.DCAEVT1_ActionOnPWMA << 4U) | + (uint16)((uint16)tripactionconfig.DCAEVT2_ActionOnPWMA << 6U) | + (uint16)((uint16)tripactionconfig.DCBEVT1_ActionOnPWMB << 8U) | + (uint16)((uint16)tripactionconfig.DCBEVT2_ActionOnPWMB << 10U)); +} + +/** @fn void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) +* @brief Enables interrupt(EPWMx_TZINT) for the trip event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param interrupts Interrupts to be enabled (Interrupts can be ORed) +* - CycleByCycleTrip +* - OneShotTrip +* - DCAEVT1_inter +* - DCAEVT2_inter +* - DCBEVT1_inter +* - DCBEVT2_inter +* +* This function enables interrupt(EPWMx_TZINT) for the trip event +*/ +/* SourceId : ETPWM_SourceId_031 */ +/* DesignId : ETPWM_DesignId_031 */ +/* Requirements : HL_EPWM_SR18 */ +void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) +{ + etpwm->TZEINT |= interrupts; +} + +/** @fn void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) +* @brief Disables interrupt(EPWMx_TZINT) for the trip event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param interrupts Trip Interrupts to be disabled (Interrupts can be ORed) +* - CycleByCycleTrip +* - OneShotTrip +* - DCAEVT1_inter +* - DCAEVT2_inter +* - DCBEVT1_inter +* - DCBEVT2_inter +* +* This function disables interrupt(EPWMx_TZINT) for the trip event +*/ +/* SourceId : ETPWM_SourceId_032 */ +/* DesignId : ETPWM_DesignId_032 */ +/* Requirements : HL_EPWM_SR18 */ +void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) +{ + etpwm->TZEINT &= (uint16)~(uint16)interrupts; +} + +/** @fn void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips) +* @brief Clears the trip event flag +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param trips Trip events +* - CycleByCycleTrip +* - OneShotTrip +* - DCAEVT1_inter +* - DCAEVT2_inter +* - DCBEVT1_inter +* - DCBEVT2_inter +* +* This function clears the trip event / Digital Compare output event flag +*/ +/* SourceId : ETPWM_SourceId_033 */ +/* DesignId : ETPWM_DesignId_033 */ +/* Requirements : HL_EPWM_SR19 */ +void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips) +{ + etpwm->TZCLR = trips; +} + +/** @fn void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm) +* @brief Clears the trip interrupt flag +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function clears the trip interrupt flag +*/ +/* SourceId : ETPWM_SourceId_034 */ +/* DesignId : ETPWM_DesignId_034 */ +/* Requirements : HL_EPWM_SR19 */ +void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm) +{ + etpwm->TZCLR = 1U; +} + +/** @fn void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip) +* @brief Force a trip event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param trip Trip events +* - CycleByCycleTrip +* - OneShotTrip +* - DCAEVT1_inter +* - DCAEVT2_inter +* - DCBEVT1_inter +* - DCBEVT2_inter +* +* This function forces a trip event / Digital Compare trip event via software +*/ +/* SourceId : ETPWM_SourceId_035 */ +/* DesignId : ETPWM_DesignId_035 */ +/* Requirements : HL_EPWM_SR20 */ +void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip) +{ + etpwm->TZFRC = trip; +} + +/** @fn void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +* @brief Enable ADC Start of Conversion A pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param eventsource EPWMxSOCA Selection Options +* - DCAEVT1 : DCAEVT1.soc event +* - CTR_ZERO : Event CTR = Zero +* - CTR_PRD : Event CTR = PRD +* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD +* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing +* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing +* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing +* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing +* @param eventperiod EPWMxSOCA Period Select +* - EventPeriod_FirstEvent : Generate SOCA pulse on the first event +* - EventPeriod_SecondEvent : Generate SOCA pulse on the second event +* - EventPeriod_ThirdEvent : Generate SOCA pulse on the third event +* +* This function enables ADC Start of Conversion A pulse +*/ +/* SourceId : ETPWM_SourceId_036 */ +/* DesignId : ETPWM_DesignId_036 */ +/* Requirements : HL_EPWM_SR21 */ +void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +{ + etpwm->ETSEL &= 0xF0FFU; + etpwm->ETSEL |= (uint16)((uint16)1U << 11U) | (uint16)((uint16)eventsource << 8U); + + etpwm->ETPS &= 0xF0FFU; + etpwm->ETPS |= (uint16)((uint16)eventperiod << 8U); +} + +/** @fn void etpwmDisableSOCA(etpwmBASE_t *etpwm) +* @brief Disable ADC Start of Conversion A pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables ADC Start of Conversion A pulse +*/ +/* SourceId : ETPWM_SourceId_037 */ +/* DesignId : ETPWM_DesignId_037 */ +/* Requirements : HL_EPWM_SR21 */ +void etpwmDisableSOCA(etpwmBASE_t *etpwm) +{ + etpwm->ETSEL &= 0xF0FFU; +} + +/** @fn void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +* @brief Enable ADC Start of Conversion B pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param eventsource EPWMxSOCB Selection Options +* - DCBEVT1 : DCBEVT1.soc event +* - CTR_ZERO : Event CTR = Zero +* - CTR_PRD : Event CTR = PRD +* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD +* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing +* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing +* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing +* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing +* @param eventperiod EPWMxSOCB Period Select +* - EventPeriod_FirstEvent : Generate SOCB pulse on the first event +* - EventPeriod_SecondEvent : Generate SOCB pulse on the second event +* - EventPeriod_ThirdEvent : Generate SOCB pulse on the third event +* +* This function enables ADC Start of Conversion B pulse +*/ +/* SourceId : ETPWM_SourceId_038 */ +/* DesignId : ETPWM_DesignId_038 */ +/* Requirements : HL_EPWM_SR21 */ +void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +{ + etpwm->ETSEL &= 0x0FFFU; + etpwm->ETSEL |= (uint16)((uint16)1U << 15U) | (uint16)((uint16)eventsource << 12U); + + etpwm->ETPS &= 0x0FFFU; + etpwm->ETPS |= (uint16)((uint16)eventperiod << 12U); +} + +/** @fn void etpwmDisableSOCB(etpwmBASE_t *etpwm) +* @brief Disable ADC Start of Conversion B pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables ADC Start of Conversion B pulse +*/ +/* SourceId : ETPWM_SourceId_039 */ +/* DesignId : ETPWM_DesignId_039 */ +/* Requirements : HL_EPWM_SR21 */ +void etpwmDisableSOCB(etpwmBASE_t *etpwm) +{ + etpwm->ETSEL &= 0x0FFFU; +} + +/** @fn void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +* @brief Enable ePWM Interrupt +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param eventsource EPWMx_INT Selection Options +* - CTR_ZERO : Event CTR = Zero +* - CTR_PRD : Event CTR = PRD +* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD +* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing +* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing +* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing +* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing +* @param eventperiod EPWMx_INT Period Select +* - EventPeriod_FirstEvent : Generate interrupt on the first event +* - EventPeriod_SecondEvent : Generate interrupt on the second event +* - EventPeriod_ThirdEvent : Generate interrupt on the third event +* +* This function enables EPWMx_INT generation +*/ +/* SourceId : ETPWM_SourceId_040 */ +/* DesignId : ETPWM_DesignId_040 */ +/* Requirements : HL_EPWM_SR22 */ +void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +{ + etpwm->ETSEL &= 0xFFF0U; + etpwm->ETSEL |= (uint16)((uint16)1U << 3U) | (uint16)((uint16)eventsource << 0U); + + etpwm->ETPS &= 0xFFF0U; + etpwm->ETPS |= (uint16)((uint16)eventperiod << 0U); +} + +/** @fn void etpwmDisableInterrupt(etpwmBASE_t *etpwm) +* @brief Disable ePWM Interrupt +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables EPWMx_INT generation +*/ +/* SourceId : ETPWM_SourceId_041 */ +/* DesignId : ETPWM_DesignId_041 */ +/* Requirements : HL_EPWM_SR22 */ +void etpwmDisableInterrupt(etpwmBASE_t *etpwm) +{ + etpwm->ETSEL &= 0xFFF0U; +} + +/** @fn uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm) +* @brief Return event status flag +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @return event status flag +* Bit 0: ePWM Interrupt(EPWMx_INT) Status Flag +* Bit 2: ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag +* Bit 3: ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag +* +* This function returns the event status flags +*/ +/* SourceId : ETPWM_SourceId_042 */ +/* DesignId : ETPWM_DesignId_042 */ +/* Requirements : HL_EPWM_SR23 */ +uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm) +{ + return etpwm->ETFLG; +} + +/** @fn void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events) +* @brief Clear event status flag +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param events status flag (flags can be ORed) +* - Event_Interrupt +* - Event_SOCA +* - Event_SOCB +* +* This function clears the event status flags +*/ +/* SourceId : ETPWM_SourceId_043 */ +/* DesignId : ETPWM_DesignId_043 */ +/* Requirements : HL_EPWM_SR24 */ +void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events) +{ + etpwm->ETCLR = events; +} + +/** @fn void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events) +* @brief Force an event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @return events (events can be ORed) +* - Event_Interrupt +* - Event_SOCA +* - Event_SOCB +* +* This function forces an event +*/ +/* SourceId : ETPWM_SourceId_044 */ +/* DesignId : ETPWM_DesignId_044 */ +/* Requirements : HL_EPWM_SR25 */ +void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events) +{ + etpwm->ETFRC = events; +} + +/** @fn void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, etpwmDigitalCompareConfig_t digitalcompareconfig) +* @brief Enable and configure digital compare events +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param digitalcompareconfig Digital Compare modue configuration +* +* Example usage (Removing semicolons to avoid MISRA warnings): +* etpwmDigitalCompareConfig_t config1 +* config1.DCAH_src = TZ1 +* config1.DCAL_src = TZ2 +* config1.DCBH_src = TZ1 +* config1.DCBL_src = TZ3 +* config1.DCAEVT1_event = DCAH_High +* config1.DCAEVT2_event = DCAL_High +* config1.DCBEVT1_event = DCBL_High +* config1.DCBEVT2_event = DCBL_High_DCBH_low +* etpwmEnableDigitalCompareEvents(etpwmREG1, config1) +* +* This function enbales and configures the digital compare events. HTis function can also be used to disable digital compare events +*/ +/* SourceId : ETPWM_SourceId_045 */ +/* DesignId : ETPWM_DesignId_045 */ +/* Requirements : HL_EPWM_SR26 */ +void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, etpwmDigitalCompareConfig_t digitalcompareconfig) +{ + etpwm->DCTRIPSEL = ((uint16)((uint16)digitalcompareconfig.DCAH_src << 0U) | + (uint16)((uint16)digitalcompareconfig.DCAL_src << 4U) | + (uint16)((uint16)digitalcompareconfig.DCBH_src << 8U) | + (uint16)((uint16)digitalcompareconfig.DCBL_src << 12U)); + + etpwm->TZDCSEL = ((uint16)((uint16)digitalcompareconfig.DCAEVT1_event << 0U) | + (uint16)((uint16)digitalcompareconfig.DCAEVT2_event << 3U) | + (uint16)((uint16)digitalcompareconfig.DCBEVT1_event << 6U) | + (uint16)((uint16)digitalcompareconfig.DCBEVT2_event << 9U)); +} + +/** @fn void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_046 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM1_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM1_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM1_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM1_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM1_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM1_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM1_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM1_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM1_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM1_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM1_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM1_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM1_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM1_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM1_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM1_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM1_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM1_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM1_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM1_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM1_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM1_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM1_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM1_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG1->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG1->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG1->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG1->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG1->CMPA; + config_reg->CONFIG_CMPB = etpwmREG1->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG1->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG1->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG1->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG1->DBRED; + config_reg->CONFIG_DBFED = etpwmREG1->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG1->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG1->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG1->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG1->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG1->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG1->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG1->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG1->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG1->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG1->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG1->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG1->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG1->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG1->DCFWINDOWCNT; + } +} + +/** @fn void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_47 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM2_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM2_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM2_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM2_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM2_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM2_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM2_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM2_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM2_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM2_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM2_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM2_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM2_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM2_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM2_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM2_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM2_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM2_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM2_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM2_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM2_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM2_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM2_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM2_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM2_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG2->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG2->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG2->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG2->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG2->CMPA; + config_reg->CONFIG_CMPB = etpwmREG2->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG2->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG2->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG2->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG2->DBRED; + config_reg->CONFIG_DBFED = etpwmREG2->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG2->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG2->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG2->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG2->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG2->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG2->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG2->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG2->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG2->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG2->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG2->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG2->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG2->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG2->DCFWINDOWCNT; + } +} + +/** @fn void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_048 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM3_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM3_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM3_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM3_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM3_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM3_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM3_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM3_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM3_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM3_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM3_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM3_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM3_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM3_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM3_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM3_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM3_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM3_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM3_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM3_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM3_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM3_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM3_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM3_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM3_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG3->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG3->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG3->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG3->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG3->CMPA; + config_reg->CONFIG_CMPB = etpwmREG3->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG3->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG3->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG3->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG3->DBRED; + config_reg->CONFIG_DBFED = etpwmREG3->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG3->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG3->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG3->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG3->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG3->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG3->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG3->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG3->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG3->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG3->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG3->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG3->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG3->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG3->DCFWINDOWCNT; + } +} + +/** @fn void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_049 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM4_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM4_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM4_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM4_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM4_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM4_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM4_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM4_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM4_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM4_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM4_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM4_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM4_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM4_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM4_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM4_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM4_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM4_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM4_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM4_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM4_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM4_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM4_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM4_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM4_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG4->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG4->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG4->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG4->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG4->CMPA; + config_reg->CONFIG_CMPB = etpwmREG4->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG4->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG4->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG4->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG4->DBRED; + config_reg->CONFIG_DBFED = etpwmREG4->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG4->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG4->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG4->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG4->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG4->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG4->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG4->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG4->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG4->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG4->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG4->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG4->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG4->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG4->DCFWINDOWCNT; + } +} + +/** @fn void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_050 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR3232 */ +void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM5_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM5_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM5_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM5_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM5_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM5_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM5_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM5_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM5_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM5_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM5_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM5_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM5_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM5_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM5_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM5_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM5_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM5_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM5_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM5_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM5_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM5_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM5_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM5_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM5_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG5->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG5->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG5->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG5->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG5->CMPA; + config_reg->CONFIG_CMPB = etpwmREG5->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG5->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG5->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG5->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG5->DBRED; + config_reg->CONFIG_DBFED = etpwmREG5->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG5->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG5->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG5->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG5->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG5->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG5->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG5->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG5->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG5->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG5->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG5->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG5->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG5->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG5->DCFWINDOWCNT; + } +} + +/** @fn void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_051 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM6_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM6_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM6_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM6_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM6_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM6_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM6_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM6_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM6_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM6_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM6_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM6_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM6_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM6_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM6_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM6_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM6_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM6_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM6_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM6_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM6_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM6_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM6_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM6_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM6_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG6->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG6->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG6->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG6->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG6->CMPA; + config_reg->CONFIG_CMPB = etpwmREG6->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG6->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG6->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG6->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG6->DBRED; + config_reg->CONFIG_DBFED = etpwmREG6->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG6->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG6->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG6->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG6->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG6->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG6->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG6->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG6->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG6->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG6->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG6->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG6->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG6->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG6->DCFWINDOWCNT; + } +} + +/** @fn void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_052 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM7_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM7_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM7_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM7_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM7_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM7_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM7_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM7_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM7_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM7_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM7_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM7_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM7_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM7_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM7_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM7_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM7_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM7_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM7_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM7_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM7_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM7_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM7_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM7_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG7->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG7->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG7->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG7->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG7->CMPA; + config_reg->CONFIG_CMPB = etpwmREG7->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG7->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG7->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG7->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG7->DBRED; + config_reg->CONFIG_DBFED = etpwmREG7->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG7->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG7->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG7->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG7->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG7->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG7->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG7->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG7->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG7->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG7->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG7->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG7->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG7->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG7->DCFWINDOWCNT; + } +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ Index: firmware/source/notification.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/source/notification.c (.../notification.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/source/notification.c (.../notification.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -50,11 +50,13 @@ #include "esm.h" #include "sys_selftest.h" +#include "adc.h" #include "can.h" #include "gio.h" #include "mibspi.h" #include "sci.h" #include "rti.h" +#include "etpwm.h" #include "sys_dma.h" /* USER CODE BEGIN (0) */ @@ -109,6 +111,16 @@ /* USER CODE BEGIN (10) */ /* USER CODE END */ +#pragma WEAK(adcNotification) +void adcNotification(adcBASE_t *adc, uint32 group) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ #pragma WEAK(canErrorNotification) void canErrorNotification(canBASE_t *node, uint32 notification) { @@ -181,7 +193,24 @@ /* USER CODE BEGIN (43) */ /* USER CODE END */ +#pragma WEAK(etpwmNotification) +void etpwmNotification(etpwmBASE_t *node) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (44) */ +/* USER CODE END */ +} +#pragma WEAK(etpwmTripNotification) +void etpwmTripNotification(etpwmBASE_t *node,uint16 flags) +{ +/* enter user code between the USER CODE BEGIN and USER CODE END. */ +/* USER CODE BEGIN (45) */ +/* USER CODE END */ +} +/* USER CODE BEGIN (46) */ +/* USER CODE END */ + /* USER CODE BEGIN (47) */ /* USER CODE END */ Index: firmware/source/pinmux.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/source/pinmux.c (.../pinmux.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/source/pinmux.c (.../pinmux.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -172,15 +172,15 @@ pinMuxReg->PINMMR1 = PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_HET1_11; - pinMuxReg->PINMMR2 = PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_GIOA_5; + pinMuxReg->PINMMR2 = PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_ETPWM1A; pinMuxReg->PINMMR3 = PINMUX_PIN_15_HET1_22 | PINMUX_PIN_16_GIOA_6; - pinMuxReg->PINMMR4 = PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03; + pinMuxReg->PINMMR4 = PINMUX_PIN_22_ETPWM2A | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03; - pinMuxReg->PINMMR5 = PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_HET1_02 | PINMUX_PIN_31_HET1_05; + pinMuxReg->PINMMR5 = PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_HET1_05; - pinMuxReg->PINMMR6 = PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_HET1_09; + pinMuxReg->PINMMR6 = PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_ETPWM7A; pinMuxReg->PINMMR7 = PINMUX_PIN_37_MIBSPI3NCS_1 | PINMUX_PIN_38_SCIRX; @@ -224,7 +224,7 @@ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ pinMuxReg->PINMMR26 = ((~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U); - pinMuxReg->PINMMR27 = PINMUX_PIN_32_MIBSPI5NCS_0; + pinMuxReg->PINMMR27 = PINMUX_PIN_32_ETPWM4A; pinMuxReg->PINMMR29 = 0x01010101U; @@ -236,7 +236,7 @@ pinMuxReg->PINMMR33 = PINMUX_PIN_36_HET1_04 | PINMUX_PIN_51_MIBSPI3SOMI | PINMUX_PIN_52_MIBSPI3SIMO | PINMUX_PIN_53_MIBSPI3CLK; - pinMuxReg->PINMMR34 = PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_HET1_18 | PINMUX_PIN_141_HET1_20; + pinMuxReg->PINMMR34 = PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_ETPWM6A | PINMUX_PIN_141_HET1_20; /* USER CODE BEGIN (3) */ Index: firmware/source/sys_main.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/source/sys_main.c (.../sys_main.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/source/sys_main.c (.../sys_main.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -53,13 +53,15 @@ #include "system.h" #include "sys_dma.h" #include "can.h" +#include "etpwm.h" #include "gio.h" #include "mibspi.h" #include "sci.h" #include "rti.h" #include "Common.h" #include "AlarmLamp.h" +#include "BloodFlow.h" #include "Buttons.h" #include "CommBuffers.h" #include "CPLD.h" @@ -124,6 +126,7 @@ { gioInit(); // configure GPIO pins mibspiInit(); // re-purposing MIBSPI5 I/O/C pins as GPIO + etpwmInit(); // configure PWMs canInit(); // CAN1 = CAN, re-purposing CAN2 and CAN3 Rx and Tx pins as GPIO sciInit(); // SCI1 used for PC serial interface, SCI2 used for FPGA serial interface dmaEnable(); // enable DMA @@ -142,6 +145,7 @@ initTimers(); initSafetyShutdown(); initCPLD(); + initBloodFlow(); initAlarmLamp(); initButtons(); initWatchdogMgmt(); Index: firmware/source/sys_vim.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3 --- firmware/source/sys_vim.c (.../sys_vim.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/source/sys_vim.c (.../sys_vim.c) (revision 40bcef6aa65af6c93ce937c6c4aa2de13e8a78d3) @@ -83,7 +83,7 @@ &phantomInterrupt, /* Channel 11 */ &phantomInterrupt, /* Channel 12 */ &linHighLevelInterrupt, /* Channel 13 */ - &phantomInterrupt, /* Channel 14 */ + &adc1Group0Interrupt, /* Channel 14 */ &phantomInterrupt, /* Channel 15 */ &can1HighLevelInterrupt, /* Channel 16 */ &phantomInterrupt, /* Channel 17 */ @@ -241,7 +241,7 @@ | (uint32)((uint32)SYS_IRQ << 11U) | (uint32)((uint32)SYS_IRQ << 12U) | (uint32)((uint32)SYS_FIQ << 13U) - | (uint32)((uint32)SYS_IRQ << 14U) + | (uint32)((uint32)SYS_FIQ << 14U) | (uint32)((uint32)SYS_IRQ << 15U) | (uint32)((uint32)SYS_FIQ << 16U) | (uint32)((uint32)SYS_IRQ << 17U) @@ -376,7 +376,7 @@ | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 12U) | (uint32)((uint32)1U << 13U) - | (uint32)((uint32)0U << 14U) + | (uint32)((uint32)1U << 14U) | (uint32)((uint32)0U << 15U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 17U)