Index: App/Services/CommInterrupts.c =================================================================== diff -u -r6c8c486d26306662402945537c5acaea2709d85b -r447eb904c9deb9536c04c9cc0e009a0b26b55573 --- App/Services/CommInterrupts.c (.../CommInterrupts.c) (revision 6c8c486d26306662402945537c5acaea2709d85b) +++ App/Services/CommInterrupts.c (.../CommInterrupts.c) (revision 447eb904c9deb9536c04c9cc0e009a0b26b55573) @@ -25,6 +25,7 @@ // ********** private definitions ********** +#define DMA_CH_STATUS_BIT(ch) ((U32)1U << (ch)) // ********** private data ********** @@ -250,9 +251,10 @@ *************************************************************************/ BOOL isSCI1DMATransmitInProgress( void ) { - BOOL transmitterBusy = ( ( sciREG->FLR & (uint32)SCI_TX_INT ) == 0U ? TRUE : FALSE ); - BOOL dmaTransmitterBusy = ( ( sciREG->CLEARINT & SCI_DMA_RECEIVE_INT ) != 0 ? TRUE : FALSE ); + BOOL transmitterBusy = ( ( sciREG->FLR & (U32)SCI_TX_INT ) == 0U ? TRUE : FALSE ); + BOOL dmaTransmitterBusy = ( ( dmaREG->PEND & DMA_CH_STATUS_BIT(DMA_CH3) ) != 0U ? TRUE : FALSE ); + return ( ( transmitterBusy == TRUE ) || ( dmaTransmitterBusy == TRUE ) ? TRUE : FALSE ); } @@ -268,8 +270,8 @@ *************************************************************************/ BOOL isSCI2DMATransmitInProgress( void ) { - BOOL transmitterBusy = ( ( scilinREG->FLR & (uint32)SCI_TX_INT ) == 0U ? TRUE : FALSE ); - BOOL dmaTransmitterBusy = ( ( scilinREG->CLEARINT & SCI_DMA_RECEIVE_INT ) != 0 ? TRUE : FALSE ); + BOOL transmitterBusy = ( ( scilinREG->FLR & (U32)SCI_TX_INT ) == 0U ? TRUE : FALSE ); + BOOL dmaTransmitterBusy = ( ( dmaREG->PEND & DMA_CH_STATUS_BIT(DMA_CH2) ) != 0U ? TRUE : FALSE ); return ( ( transmitterBusy == TRUE ) || ( dmaTransmitterBusy == TRUE ) ? TRUE : FALSE ); } Index: App/Services/FPGA.c =================================================================== diff -u -r8ca991f9c04d8d301ada71eabc297f514b0d6cf8 -r447eb904c9deb9536c04c9cc0e009a0b26b55573 --- App/Services/FPGA.c (.../FPGA.c) (revision 8ca991f9c04d8d301ada71eabc297f514b0d6cf8) +++ App/Services/FPGA.c (.../FPGA.c) (revision 447eb904c9deb9536c04c9cc0e009a0b26b55573) @@ -564,7 +564,7 @@ FPGA_STATE_T result = FPGA_STATE_WRITE_ALL_ACTUATORS; // check bulk write command success - if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[0] != FPGA_WRITE_CMD_ACK ) + if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[0] != FPGA_WRITE_CMD_ACK ) ) { // TODO - ??? } @@ -588,7 +588,6 @@ // TODO - ??? } - return result; } @@ -777,9 +776,7 @@ *************************************************************************/ U16 getFPGAStatus( void ) { - U16 result = MAKE_WORD_OF_BYTES(fpgaHeader.fpgaStatusHigh,fpgaHeader.fpgaStatusLow); - - return result; + return fpgaHeader.fpgaStatus; } /************************************************************************* @@ -794,7 +791,6 @@ *************************************************************************/ void setFPGAControl( U16 ctrl ) { - fpgaHeader.fpgaControlHigh = GET_MSB_OF_WORD( ctrl ); - fpgaHeader.fpgaControlLow = GET_MSB_OF_WORD( ctrl ); + fpgaHeader.fpgaControl = ctrl; } Index: App/Services/SystemComm.c =================================================================== diff -u -r6c8c486d26306662402945537c5acaea2709d85b -r447eb904c9deb9536c04c9cc0e009a0b26b55573 --- App/Services/SystemComm.c (.../SystemComm.c) (revision 6c8c486d26306662402945537c5acaea2709d85b) +++ App/Services/SystemComm.c (.../SystemComm.c) (revision 447eb904c9deb9536c04c9cc0e009a0b26b55573) @@ -141,7 +141,7 @@ } // if UART transmitter is idle, start transmitting any pending packets -// if ( FALSE == isSCI1DMATransmitInProgress() ) + if ( FALSE == isSCI1DMATransmitInProgress() ) { transmitNextUARTPacket(); } @@ -278,7 +278,7 @@ pcDMARecvControlRecord.FRDOFFSET = 0; // not used pcDMARecvControlRecord.FRSOFFSET = 0; // not used - // initiate UART packet receiving readiness via DMA + // initiate PC packet receiving readiness via DMA dmaSetCtrlPacket( DMA_CH1, pcDMARecvControlRecord ); dmaSetChEnable( DMA_CH1, DMA_HW ); setSCI1DMAReceiveInterrupt(); @@ -554,11 +554,12 @@ U32 pos = i + 1; // skip past sync byte implemented U32 remSize = len - pos; - // if a minimum sized msg would fit in remaining + // if a minimum sized msg would fit in remaining, continue if ( remSize >= MESSAGE_OVERHEAD_SIZE ) { cargoSize = data[pos+sizeof(U16)]; msgSize = MESSAGE_OVERHEAD_SIZE + cargoSize; + // we now know the size of the message - we can now know if full message is contained in buffer if ( msgSize <= remSize ) { result = msgSize; // we found a complete message of this size @@ -646,6 +647,10 @@ { switch ( msgID ) { + case MSG_ID_HD_MESSAGE: + handleTestHDMessageRequest( message ); + break; + case MSG_ID_OFF_BUTTON_STATE_OVERRIDE: handleTestOffButtonStateOverrideRequest( message ); break; Index: source/sys_main.c =================================================================== diff -u -r38ff7a6fbf82b86ab1bac3b7b24c4ea33d5419f9 -r447eb904c9deb9536c04c9cc0e009a0b26b55573 --- source/sys_main.c (.../sys_main.c) (revision 38ff7a6fbf82b86ab1bac3b7b24c4ea33d5419f9) +++ source/sys_main.c (.../sys_main.c) (revision 447eb904c9deb9536c04c9cc0e009a0b26b55573) @@ -127,8 +127,6 @@ canInit(); // CAN1 = CAN, re-purposing CAN2 and CAN3 Rx and Tx pins as GPIO sciInit(); // SCI1 used for PC serial interface, SCI2 used for FPGA serial interface dmaEnable(); // enable DMA -// sciEnableLoopback( sciREG, Digital_Lbk ); // TODO - for test only -// sciEnableLoopback( scilinREG, Digital_Lbk ); // TODO - for test only } /*************************************************************************