Index: firmware/App/HDCommon.h =================================================================== diff -u -r1addb5d7e52e17879db2c1f87b864cd5489b7ef7 -r4d03f00c00c89c41e7364a23e22d31c6a5d6c811 --- firmware/App/HDCommon.h (.../HDCommon.h) (revision 1addb5d7e52e17879db2c1f87b864cd5489b7ef7) +++ firmware/App/HDCommon.h (.../HDCommon.h) (revision 4d03f00c00c89c41e7364a23e22d31c6a5d6c811) @@ -22,10 +22,10 @@ // ********** version ********** -#define HD_VERSION_MAJOR 0 -#define HD_VERSION_MINOR 9 -#define HD_VERSION_MICRO 0 -#define HD_VERSION_BUILD 350 +#define HD_VERSION_MAJOR 15 +#define HD_VERSION_MINOR 81 +#define HD_VERSION_MICRO 14 +#define HD_VERSION_BUILD 200 // ********** development build switches ********** Index: firmware/HD.dil =================================================================== diff -u -r1a178aef78168ee358e1326f4fb1daf81df83c17 -r4d03f00c00c89c41e7364a23e22d31c6a5d6c811 --- firmware/HD.dil (.../HD.dil) (revision 1a178aef78168ee358e1326f4fb1daf81df83c17) +++ firmware/HD.dil (.../HD.dil) (revision 4d03f00c00c89c41e7364a23e22d31c6a5d6c811) @@ -1,4 +1,4 @@ -# RM46L852PGE 05/02/24 13:54:03 +# RM46L852PGE 08/14/24 09:47:08 # ARCH=RM46L852PGE # @@ -105,7 +105,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18 DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATEVALUE.VALUE=0x5 DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0 @@ -240,7 +240,7 @@ DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=etpwm6Interrupt DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1 -DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_RAMPARITYCHECK_ENA.VALUE=0 @@ -707,7 +707,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1 -DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=0 DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=104.000 DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=165.0 Index: firmware/source/sys_link.cmd =================================================================== diff -u -r1addb5d7e52e17879db2c1f87b864cd5489b7ef7 -r4d03f00c00c89c41e7364a23e22d31c6a5d6c811 --- firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 1addb5d7e52e17879db2c1f87b864cd5489b7ef7) +++ firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 4d03f00c00c89c41e7364a23e22d31c6a5d6c811) @@ -1,67 +1,67 @@ -/*----------------------------------------------------------------------------*/ -/* sys_link.cmd */ -/* */ -/* -* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -*/ - -/* */ -/*----------------------------------------------------------------------------*/ -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - - -/*----------------------------------------------------------------------------*/ -/* Linker Settings */ - ---retain="*(.intvecs)" - -/* USER CODE BEGIN (1) */ +/*----------------------------------------------------------------------------*/ +/* sys_link.cmd */ +/* */ +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/* */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + +/*----------------------------------------------------------------------------*/ +/* Linker Settings */ + +--retain="*(.intvecs)" + +/* USER CODE BEGIN (1) */ /* IGNORE the generated Memory code, overridden below */ #if 0 -/* USER CODE END */ - -/*----------------------------------------------------------------------------*/ -/* Memory Map */ - -MEMORY -{ - VECTORS (X) : origin=0x00000000 length=0x00000020 - FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 - STACKS (RW) : origin=0x08000000 length=0x00005800 - RAM (RW) : origin=0x08005800 length=0x0002a800 - -/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Memory Map */ + +MEMORY +{ + VECTORS (X) : origin=0x00000000 length=0x00000020 + FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 + STACKS (RW) : origin=0x08000000 length=0x00003400 + RAM (RW) : origin=0x08003400 length=0x0002cc00 + +/* USER CODE BEGIN (2) */ #endif /* Override Memory Segments with CRC here */ #if 1 @@ -80,9 +80,9 @@ vfill = 0xffffffff STACKS (RW) : origin=0x08000000 - length=0x00004c00 + length=0x00003400 - RAM (RW) : origin=0x08004c00 + RAM (RW) : origin=0x08003400 length=0x0002b400 #endif #if 1 @@ -98,10 +98,10 @@ length=(size(FLASH0) >> 3) ECC={algorithm=algoL2R4F021, input_range=FLASH0 } #endif -/* USER CODE END */ -} - -/* USER CODE BEGIN (3) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (3) */ /* IGNORE the generated Sections code, overridden below */ ECC { @@ -111,24 +111,24 @@ mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */ } #if 0 -/* USER CODE END */ - -/*----------------------------------------------------------------------------*/ -/* Section Configuration */ - -SECTIONS -{ - .intvecs : {} > VECTORS - .text : {} > FLASH0 - .const : {} > FLASH0 - .cinit : {} > FLASH0 - .pinit : {} > FLASH0 - .bss : {} > RAM - .data : {} > RAM - .sysmem : {} > RAM - - -/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Section Configuration */ + +SECTIONS +{ + .intvecs : {} > VECTORS + .text : {} > FLASH0 + .const : {} > FLASH0 + .cinit : {} > FLASH0 + .pinit : {} > FLASH0 + .bss : {} > RAM + .data : {} > RAM + .sysmem : {} > RAM + + +/* USER CODE BEGIN (4) */ #endif /* Override Sections with CRCs here */ #if 1 @@ -145,16 +145,16 @@ .TI.crctab : {} > CRCMEM #endif -/* USER CODE END */ -} - -/* USER CODE BEGIN (5) */ -/* USER CODE END */ - - -/*----------------------------------------------------------------------------*/ -/* Misc */ - -/* USER CODE BEGIN (6) */ -/* USER CODE END */ -/*----------------------------------------------------------------------------*/ +/* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + +/*----------------------------------------------------------------------------*/ +/* Misc */ + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ +/*----------------------------------------------------------------------------*/ Index: firmware/source/sys_startup.c =================================================================== diff -u -r6623684ddacf5beebd15bce8a1dbd06a442fb38e -r4d03f00c00c89c41e7364a23e22d31c6a5d6c811 --- firmware/source/sys_startup.c (.../sys_startup.c) (revision 6623684ddacf5beebd15bce8a1dbd06a442fb38e) +++ firmware/source/sys_startup.c (.../sys_startup.c) (revision 4d03f00c00c89c41e7364a23e22d31c6a5d6c811) @@ -120,19 +120,7 @@ * by its ECC logic for accesses to program flash or data RAM. */ _coreEnableEventBusExport_(); -/* USER CODE BEGIN (9) */ -/* USER CODE END */ - /* Enable response to ECC errors indicated by CPU for accesses to flash */ - flashWREG->FEDACCTRL1 = 0x000A060AU; - -/* USER CODE BEGIN (10) */ -/* USER CODE END */ - - /* Enable CPU ECC checking for ATCM (flash accesses) */ - _coreEnableFlashEcc_(); - - /* USER CODE BEGIN (11) */ /* USER CODE END */ @@ -385,26 +373,6 @@ /* USER CODE BEGIN (37) */ /* USER CODE END */ - - /* Initialize CPU RAM. - * This function uses the system module's hardware for auto-initialization of memories and their - * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. - * Hence the value 0x1 passed to the function. - * This function will initialize the entire CPU RAM and the corresponding ECC locations. - */ - memoryInit(0x1U); - -/* USER CODE BEGIN (38) */ -/* USER CODE END */ - - /* Enable ECC checking for TCRAM accesses. - * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. - */ - _coreEnableRamEcc_(); - -/* USER CODE BEGIN (39) */ -/* USER CODE END */ - /* Start PBIST on all dual-port memories */ /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories. PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. @@ -431,18 +399,6 @@ /* USER CODE BEGIN (40) */ /* USER CODE END */ - - /* Test the CPU ECC mechanism for RAM accesses. - * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses - * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error - * in the ECC causes a data abort exception. The data abort handler is written to look for - * deliberately caused exception and to return the code execution to the instruction - * following the one that caused the abort. - */ - checkRAMECC(); - -/* USER CODE BEGIN (41) */ -/* USER CODE END */ /* USER CODE BEGIN (43) */ /* USER CODE END */