Index: source/can.c =================================================================== diff -u --- source/can.c (revision 0) +++ source/can.c (revision 7de64c199413a3f74d69efbdd1424b37c6f607c9) @@ -0,0 +1,1357 @@ +/** @file can.c +* @brief CAN Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the CAN driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + +/* Include Files */ + +#include "can.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + +/* Global and Static Variables */ + +#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) +#else + static const uint32 s_canByteOrder[8U] = {3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U}; +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + +/** @fn void canInit(void) +* @brief Initializes CAN Driver +* +* This function initializes the CAN driver. +* +*/ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +/* SourceId : CAN_SourceId_001 */ +/* DesignId : CAN_DesignId_001 */ +/* Requirements : HL_SR207 */ +void canInit(void) +{ +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + /** @b Initialize @b CAN1: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG1->CTL = (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)((uint32)0x00000005U << 10U) + | (uint32)0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG1->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG1->INTMUXx[0U] = (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U; + + canREG1->INTMUXx[1U] = (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U + | (uint32)0x00000000U; + + /** - Setup auto bus on timer period */ + canREG1->ABOTR = (uint32)0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + canREG1->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ + canREG1->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG1->BTR = (uint32)((uint32)0U << 16U) | + (uint32)((uint32)(3U - 1U) << 12U) | + (uint32)((uint32)((4U + 3U) - 1U) << 8U) | + (uint32)((uint32)(3U - 1U) << 6U) | + (uint32)19U; + + + /** - CAN1 Port output values */ + canREG1->TIOC = (uint32)((uint32)1U << 18U ) + | (uint32)((uint32)0U << 17U ) + | (uint32)((uint32)0U << 16U ) + | (uint32)((uint32)1U << 3U ) + | (uint32)((uint32)1U << 2U ) + | (uint32)((uint32)1U << 1U ); + + canREG1->RIOC = (uint32)((uint32)1U << 18U ) + | (uint32)((uint32)0U << 17U ) + | (uint32)((uint32)0U << 16U ) + | (uint32)((uint32)1U << 3U ) + | (uint32)((uint32)0U << 2U ) + | (uint32)((uint32)0U <<1U ); + + /** - Leave configuration and initialization mode */ + canREG1->CTL &= ~(uint32)(0x00000041U); + + + /** @b Initialize @b CAN2: */ + + + /** - Setup control register + * - Enter initialization mode + */ + canREG2->CTL = 0x00000001U; + + /** - CAN2 Port output values */ + canREG2->TIOC = (uint32)((uint32)1U << 18U ) + | (uint32)((uint32)0U << 17U ) + | (uint32)((uint32)0U << 16U ) + | (uint32)((uint32)0U << 3U ) + | (uint32)((uint32)1U << 2U ) + | (uint32)((uint32)1U << 1U ); + + canREG2->RIOC = (uint32)((uint32)1U << 18U ) + | (uint32)((uint32)0U << 17U ) + | (uint32)((uint32)0U << 16U ) + | (uint32)((uint32)0U << 3U ) + | (uint32)((uint32)1U << 2U ) + | (uint32)((uint32)0U <<1U ); + + + /** @b Initialize @b CAN3: */ + + + /** - Setup control register + * - Enter initialization mode + */ + canREG3->CTL = 0x00000001U; + + /** - CAN3 Port output values */ + canREG3->TIOC = (uint32)((uint32)1U << 18U ) + | (uint32)((uint32)0U << 17U ) + | (uint32)((uint32)0U << 16U ) + | (uint32)((uint32)0U << 3U ) + | (uint32)((uint32)1U << 2U ) + | (uint32)((uint32)1U << 1U ); + + canREG3->RIOC = (uint32)((uint32)1U << 18U ) + | (uint32)((uint32)0U << 17U ) + | (uint32)((uint32)0U << 16U ) + | (uint32)((uint32)0U << 3U ) + | (uint32)((uint32)1U << 2U ) + | (uint32)((uint32)0U << 1U ); + + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/** @fn uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data) +* @brief Transmits a CAN message +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @param[in] data Pointer to CAN TX data +* @return The function will return: +* - 0: When the setup of the TX message box wasn't successful +* - 1: When the setup of the TX message box was successful +* +* This function writes a CAN message into a CAN message box. +* This function is not reentrant. However, if a CAN interrupt occurs, the values of +* the IF registers are backup up and restored at the end of the ISR, since these are a shared resource. +* +*/ +/* SourceId : CAN_SourceId_002 */ +/* DesignId : CAN_DesignId_002 */ +/* Requirements : HL_SR208 */ +uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = (messageBox - 1U) >> 5U; + uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU); + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if ((node->TXRQx[regIndex] & bitIndex) != 0U) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((node->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + * - Start Transmission + */ + node->IF1CMD = 0x87U; + + /** - Copy TX data into IF1 */ + for (i = 0U; i < 8U; i++) + { +#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + node->IF1DATx[i] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + node->IF1DATx[s_canByteOrder[i]] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#endif + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = (uint8) messageBox; + + success = 1U; + } + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + + return success; +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/** @fn uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data) +* @brief Gets received a CAN message +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @param[out] data Pointer to store CAN RX data +* @return The function will return: +* - 0: When RX message box hasn't received new data +* - 1: When RX data are stored in the data buffer +* - 3: When RX data are stored in the data buffer and a message was lost +* +* This function writes a CAN message into a CAN message box. +* +*/ +/* SourceId : CAN_SourceId_003 */ +/* DesignId : CAN_DesignId_003 */ +/* Requirements : HL_SR209 */ +uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data) +{ + uint32 i; + uint32 size; + uint8 * pData = data; + uint32 success = 0U; + uint32 regIndex = (messageBox - 1U) >> 5U; + uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU); + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + + /** - Check if new data have been arrived: + * - no new data, return 0 + * - new data, get received message + */ + if ((node->NWDATx[regIndex] & bitIndex) == 0U) + { + success = 0U; + } + + else + { + /** - Wait until IF2 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((node->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x17U; + + /** - Copy data into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = (uint8) messageBox; + + /** - Wait until data are copied into IF2 */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((node->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + /** - Get number of received bytes + * - Value from 0x8 to 0xF equals length 8. + */ + size = node->IF2MCTL & 0xFU; + if(size > 0x8U) + { + size = 0x8U; + } + + /** - Copy RX data into destination buffer */ + for (i = 0U; i < size; i++) + { +#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + *pData = node->IF2DATx[i]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + *pData = node->IF2DATx[s_canByteOrder[i]]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData++; +#endif + } + + success = 1U; + } + /** - Check if data have been lost: + * - no data lost, return 1 + * - data lost, return 3 + */ + if ((node->IF2MCTL & 0x4000U) == 0x4000U) + { + success = 3U; + } + + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + return success; +} + + +/** @fn uint32 canGetID(canBASE_t *node, uint32 messageBox) +* @brief Gets the Message Box's ID +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @param[out] data Pointer to store CAN RX data +* @return The function will return the ID of the message box. +* +* This function gets the identifier of a CAN message box. +* +*/ +/* SourceId : CAN_SourceId_026 */ +/* DesignId : CAN_DesignId_020 */ +/* Requirements : HL_SR537 */ +uint32 canGetID(canBASE_t *node, uint32 messageBox) +{ + uint32 msgBoxID = 0U; + + + /** - Wait until IF2 is ready for use */ + while ((node->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x20U; + + /** - Copy message box number into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = (uint8) messageBox; + + /** - Wait until data are copied into IF2 */ + while ((node->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + /* Read Message Box ID from Arbitration register. */ + msgBoxID = (node->IF2ARB & 0x1FFFFFFFU); + + return msgBoxID; + +} + +/** @fn uint32 canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal) +* @brief Change CAN Message Box ID. +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @param[in] msgBoxArbitVal (32 bit value): +* Bit 31 - Not used. +* Bit 30 - 0 - The 11-bit ("standard") identifier is used for this message object. +* 1 - The 29-bit ("extended") identifier is used for this message object. +* Bit 29 - 0 - Direction = Receive +* 1 - Direction = Transmit +* Bit 28:0 - Message Identifier. +* @return + +* +* This function changes the Identifier and other arbitration parameters of a CAN Message Box. +* +*/ +/* SourceId : CAN_SourceId_027 */ +/* DesignId : CAN_DesignId_021 */ +/* Requirements : HL_SR538 */ +void canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal) +{ + + /** - Wait until IF2 is ready for use */ + while ((node->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0xA0U; + /* Copy passed value into the arbitration register. */ + node->IF2ARB &= 0x80000000U; + node->IF2ARB |= (msgBoxArbitVal & 0x7FFFFFFFU); + + /** - Update message box number. */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = (uint8) messageBox; + + /** - Wait until data are copied into IF2 */ + while ((node->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ + +} + + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/** @fn uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox) +* @brief Transmits a CAN Remote Frame. +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @param[in] data Pointer to CAN TX data +* @return The function will return: +* - 0: When the setup of Send Remote Frame from message box wasn't successful +* - 1: When the setup of Send Remote Frame from message box was successful +* +* This function triggers Remote Frame Transmission from CAN message box. +* Note : Enable RTR must be set in the Message x Configuration in the GUI( x: 1 - 64) +* +*/ +/* SourceId : CAN_SourceId_028 */ +/* DesignId : CAN_DesignId_022 */ +/* Requirements : HL_SR531 */ +uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox) +{ + + uint32 success = 0U; + uint32 regIndex = (messageBox - 1U) >> 5U; + uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if ((node->TXRQx[regIndex] & bitIndex) != 0U) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((node->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + /** - Request Transmission by setting TxRqst in message box */ + node->IF1CMD = (uint8) 0x84U; + + /** - Trigger Remote Frame Transmit from message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = (uint8) messageBox; + + success = 1U; + } + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + return success; +} + +/** @fn uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * data) +* @brief Fills the Message Object with the data but does not initiate transmission. +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @return The function will return: +* - 0: When the Fill up of the TX message box wasn't successful +* - 1: When the Fill up of the TX message box was successful +* +* This function fills the Message Object with the data but does not initiate transmission. +* +*/ +/* SourceId : CAN_SourceId_029 */ +/* DesignId : CAN_DesignId_023 */ +/* Requirements : HL_SR532 */ +uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * data) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = (messageBox - 1U) >> 5U; + uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if ((node->TXRQx[regIndex] & bitIndex) != 0U) + { + success = 0U; + } + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((node->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + */ + node->IF1CMD = 0x83U; + + /** - Copy TX data into IF1 */ + for (i = 0U; i < 8U; i++) + { +#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + node->IF1DATx[i] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + node->IF1DATx[s_canByteOrder[i]] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#endif + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = (uint8) messageBox; + + success = 1U; + } + + return success; + +} + +/** @fn uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox) +* @brief Gets Tx message box transmission status +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @return The function will return the tx request flag +* +* Checks to see if the Tx message box has a pending Tx request, returns +* 0 is flag not set otherwise will return the Tx request flag itself. +*/ +/* SourceId : CAN_SourceId_004 */ +/* DesignId : CAN_DesignId_004 */ +/* Requirements : HL_SR210 */ +uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox) +{ + uint32 flag; + uint32 regIndex = (messageBox - 1U) >> 5U; + uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU); + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + /** - Read Tx request register */ + flag = node->TXRQx[regIndex] & bitIndex; + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + + return flag; +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/** @fn uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox) +* @brief Gets Rx message box reception status +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @return The function will return the new data flag +* +* Checks to see if the Rx message box has pending Rx data, returns +* 0 is flag not set otherwise will return the Tx request flag itself. +*/ +/* SourceId : CAN_SourceId_005 */ +/* DesignId : CAN_DesignId_005 */ +/* Requirements : HL_SR211 */ +uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox) +{ + uint32 flag; + uint32 regIndex = (messageBox - 1U) >> 5U; + uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU); + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + /** - Read Tx request register */ + flag = node->NWDATx[regIndex] & bitIndex; + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + return flag; +} + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/** @fn uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox) +* @brief Checks if message box is valid +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @return The function will return the new data flag +* +* Checks to see if the message box is valid for operation, returns +* 0 is flag not set otherwise will return the validation flag itself. +*/ +/* SourceId : CAN_SourceId_006 */ +/* DesignId : CAN_DesignId_006 */ +/* Requirements : HL_SR212 */ +uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox) +{ + uint32 flag; + uint32 regIndex = (messageBox - 1U) >> 5U; + uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU); + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + + /** - Read Tx request register */ + flag = node->MSGVALx[regIndex] & bitIndex; + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + return flag; +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/** @fn uint32 canGetLastError(canBASE_t *node) +* @brief Gets last RX/TX-Error of CAN message traffic +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @return The function will return: +* - canERROR_OK (0): When no CAN error occurred +* - canERROR_STUFF (1): When a stuff error occurred on RX message +* - canERROR_FORMAT (2): When a form/format error occurred on RX message +* - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged +* - canERROR_BIT1 (4): When a TX message monitored dominant level where recessive is expected +* - canERROR_BIT0 (5): When a TX message monitored recessive level where dominant is expected +* - canERROR_CRC (6): When a RX message has wrong CRC value +* - canERROR_NO (7): When no error occurred since last call of this function +* +* This function returns the last occurred error code of an RX or TX message, +* since the last call of this function. +* +*/ +/* SourceId : CAN_SourceId_007 */ +/* DesignId : CAN_DesignId_007 */ +/* Requirements : HL_SR213 */ +uint32 canGetLastError(canBASE_t *node) +{ + uint32 errorCode; + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + + /** - Get last error code */ + errorCode = node->ES & 7U; + + /** @note The function canInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + return errorCode; +} + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/** @fn uint32 canGetErrorLevel(canBASE_t *node) +* @brief Gets error level of a CAN node +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @return The function will return: +* - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96 +* - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127 +* - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and 255 +* - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 +* +* This function returns the current error level of a CAN node. +* +*/ +/* SourceId : CAN_SourceId_008 */ +/* DesignId : CAN_DesignId_008 */ +/* Requirements : HL_SR214 */ +uint32 canGetErrorLevel(canBASE_t *node) +{ + uint32 errorLevel; + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + + /** - Get error level */ + errorLevel = node->ES & 0xE0U; + + /** @note The function canInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + + return errorLevel; +} + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + +/** @fn void canEnableErrorNotification(canBASE_t *node) +* @brief Enable error notification +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* +* This function will enable the notification for the reaching the error levels warning, passive and bus off. +*/ +/* SourceId : CAN_SourceId_009 */ +/* DesignId : CAN_DesignId_009 */ +/* Requirements : HL_SR215 */ +void canEnableErrorNotification(canBASE_t *node) +{ +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + + node->CTL |= 8U; + + /** @note The function canInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ +} + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + +/** @fn void canEnableStatusChangeNotification(canBASE_t *node) +* @brief Enable Status Change notification +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* +* This function will enable the notification for the status change RxOK, TxOK, PDA, WakeupPnd Interrupt. +*/ +/* SourceId : CAN_SourceId_030 */ +/* DesignId : CAN_DesignId_024 */ +/* Requirements : HL_SR533 */ +void canEnableStatusChangeNotification(canBASE_t *node) +{ + + node->CTL |= 4U; + + /** @note The function canInit has to be called before this function can be used. */ + +} + +/** @fn void canDisableStatusChangeNotification(canBASE_t *node) +* @brief Disable Status Change notification +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* +* This function will disable the notification for the status change RxOK, TxOK, PDA, WakeupPnd Interrupt. +*/ +/* SourceId : CAN_SourceId_031 */ +/* DesignId : CAN_DesignId_025 */ +/* Requirements : HL_SR534 */ +void canDisableStatusChangeNotification(canBASE_t *node) +{ + node->CTL &= ~(uint32)(4U); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +/** @fn void canDisableErrorNotification(canBASE_t *node) +* @brief Disable error notification +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* +* This function will disable the notification for the reaching the error levels warning, passive and bus off. +*/ +/* SourceId : CAN_SourceId_010 */ +/* DesignId : CAN_DesignId_010 */ +/* Requirements : HL_SR216 */ +void canDisableErrorNotification(canBASE_t *node) +{ +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + + node->CTL &= ~(uint32)(8U); + + /** @note The function canInit has to be called before this function can be used. */ + +/* USER CODE BEGIN (33) */ +/* USER CODE END */ +} + +/** @fn void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype) +* @brief Disable error notification +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] Loopbacktype Type of Loopback: +* - Internal_Lbk: Internal Loop Back +* - External_Lbk: External Loop Back +* - Internal_Silent_Lbk: Internal Loop Back with Silent mode. +* +* This function will enable can loopback mode +*/ +/* SourceId : CAN_SourceId_011 */ +/* DesignId : CAN_DesignId_011 */ +/* Requirements : HL_SR521 */ +void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype) +{ + /* Enter Test Mode */ + node->CTL |= (uint32)((uint32)1U << 7U); + + /* Configure Loopback */ + node->TEST |= (uint32)Loopbacktype; + + /** @note The function canInit has to be called before this function can be used. */ +} + + +/** @fn void canDisableloopback(canBASE_t *node) +* @brief Disable error notification +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* +* This function will disable can loopback mode +*/ +/* SourceId : CAN_SourceId_012 */ +/* DesignId : CAN_DesignId_012 */ +/* Requirements : HL_SR522 */ +void canDisableloopback(canBASE_t *node) +{ + + + node->TEST &= ~(uint32)(0x00000118U); + + /* Exit Test Mode */ + node->CTL &= ~(uint32)((uint32)1U << 7U); + + /** @note The function canInit has to be called before this function can be used. */ +} + + +/** @fn void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir) +* @brief Set Port Direction +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] TxDir - TX Pin direction +* @param[in] RxDir - RX Pin direction +* +* Set the direction of CAN pins at runtime when configured as IO pins. +*/ +/* SourceId : CAN_SourceId_013 */ +/* DesignId : CAN_DesignId_013 */ +/* Requirements : HL_SR217 */ +void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir) +{ +/* USER CODE BEGIN (34) */ +/* USER CODE END */ + + node->TIOC = ((node->TIOC & 0xFFFFFFFBU) | (TxDir << 2U)); + node->RIOC = ((node->RIOC & 0xFFFFFFFBU) | (RxDir << 2U)); + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ +} + +/** @fn void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue) +* @brief Write Port Value +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* @param[in] TxValue - TX Pin value 0 or 1 +* @param[in] RxValue - RX Pin value 0 or 1 +* +* Writes a value to TX and RX pin of a given CAN module when configured as IO pins. +*/ +/* SourceId : CAN_SourceId_014 */ +/* DesignId : CAN_DesignId_014 */ +/* Requirements : HL_SR218 */ +void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue) +{ +/* USER CODE BEGIN (36) */ +/* USER CODE END */ + + node->TIOC = ((node->TIOC & 0xFFFFFFFDU) | (TxValue << 1U)); + node->RIOC = ((node->RIOC & 0xFFFFFFFDU) | (RxValue << 1U)); + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ +} + +/** @fn uint32 canIoTxGetBit(canBASE_t *node) +* @brief Read TX Bit +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* +* Reads a the current value from the TX pin of the given CAN port +*/ +/* SourceId : CAN_SourceId_015 */ +/* DesignId : CAN_DesignId_015 */ +/* Requirements : HL_SR219 */ +uint32 canIoTxGetBit(canBASE_t *node) +{ +/* USER CODE BEGIN (38) */ +/* USER CODE END */ + + return (node->TIOC & 1U); +} + +/** @fn uint32 canIoRxGetBit(canBASE_t *node) +* @brief Read RX Bit +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* +* Reads a the current value from the RX pin of the given CAN port +*/ +/* SourceId : CAN_SourceId_016 */ +/* DesignId : CAN_DesignId_016 */ +/* Requirements : HL_SR220 */ +uint32 canIoRxGetBit(canBASE_t *node) +{ +/* USER CODE BEGIN (39) */ +/* USER CODE END */ + + return (node->RIOC & 1U); +} + + +/** @fn void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the CAN1 configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : CAN_SourceId_017 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : HL_SR224 */ +void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTL = CAN1_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN1_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN1_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN1_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN1_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN1_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN1_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN1_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN1_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_CTL = canREG1->CTL; + config_reg->CONFIG_ES = canREG1->ES; + config_reg->CONFIG_BTR = canREG1->BTR; + config_reg->CONFIG_TEST = canREG1->TEST; + config_reg->CONFIG_ABOTR = canREG1->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG1->INTMUXx[0]; + config_reg->CONFIG_INTMUX1 = canREG1->INTMUXx[1]; + config_reg->CONFIG_INTMUX2 = canREG1->INTMUXx[2]; + config_reg->CONFIG_INTMUX3 = canREG1->INTMUXx[3]; + config_reg->CONFIG_TIOC = canREG1->TIOC; + config_reg->CONFIG_RIOC = canREG1->RIOC; + } +} +/** @fn void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the CAN2 configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : CAN_SourceId_018 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : HL_SR224 */ +void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTL = CAN2_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN2_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN2_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN2_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN2_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN2_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN2_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN2_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN2_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_CTL = canREG2->CTL; + config_reg->CONFIG_ES = canREG2->ES; + config_reg->CONFIG_BTR = canREG2->BTR; + config_reg->CONFIG_TEST = canREG2->TEST; + config_reg->CONFIG_ABOTR = canREG2->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG2->INTMUXx[0]; + config_reg->CONFIG_INTMUX1 = canREG2->INTMUXx[1]; + config_reg->CONFIG_INTMUX2 = canREG2->INTMUXx[2]; + config_reg->CONFIG_INTMUX3 = canREG2->INTMUXx[3]; + config_reg->CONFIG_TIOC = canREG2->TIOC; + config_reg->CONFIG_RIOC = canREG2->RIOC; + } +} +/** @fn void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the CAN3 configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : CAN_SourceId_019 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : HL_SR224 */ +void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTL = CAN3_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN3_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN3_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN3_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN3_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN3_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN3_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN3_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN3_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_CTL = canREG3->CTL; + config_reg->CONFIG_ES = canREG3->ES; + config_reg->CONFIG_BTR = canREG3->BTR; + config_reg->CONFIG_TEST = canREG3->TEST; + config_reg->CONFIG_ABOTR = canREG3->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG3->INTMUXx[0]; + config_reg->CONFIG_INTMUX1 = canREG3->INTMUXx[1]; + config_reg->CONFIG_INTMUX2 = canREG3->INTMUXx[2]; + config_reg->CONFIG_INTMUX3 = canREG3->INTMUXx[3]; + config_reg->CONFIG_TIOC = canREG3->TIOC; + config_reg->CONFIG_RIOC = canREG3->RIOC; + } +} + + + + + + + Index: source/mibspi.c =================================================================== diff -u --- source/mibspi.c (revision 0) +++ source/mibspi.c (revision 7de64c199413a3f74d69efbdd1424b37c6f607c9) @@ -0,0 +1,942 @@ +/** @file mibspi.c +* @brief MIBSPI Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "mibspi.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void mibspiInit(void) +* @brief Initializes the MIBSPI Driver +* +* This function initializes the MIBSPI module. +*/ +/* SourceId : MIBSPI_SourceId_001 */ +/* DesignId : MIBSPI_DesignId_001 */ +/* Requirements : HL_SR153 */ +void mibspiInit(void) +{ +uint32 i ; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + + + + /** @b initialize @b MIBSPI5 */ + + /** bring MIBSPI out of reset */ + mibspiREG5->GCR0 = 0U; + mibspiREG5->GCR0 = 1U; + + /** enable MIBSPI5 multibuffered mode and enable buffer RAM */ + mibspiREG5->MIBSPIE = (mibspiREG5->MIBSPIE & 0xFFFFFFFEU) | 1U; + + /** MIBSPI5 master mode and clock configuration */ + mibspiREG5->GCR1 = (mibspiREG5->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */ + | 1U); /* MASTER */ + + /** MIBSPI5 enable pin configuration */ + mibspiREG5->INT0 = (mibspiREG5->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */ + + /** - Delays */ + mibspiREG5->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */ + | (uint32)((uint32)0U << 16U) /* T2CDELAY */ + | (uint32)((uint32)0U << 8U) /* T2EDELAY */ + | (uint32)((uint32)0U << 0U); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG5->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 1 */ + mibspiREG5->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 2 */ + mibspiREG5->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 3 */ + mibspiREG5->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Default Chip Select */ + mibspiREG5->DEF = (uint32)(0xFFU); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while ((mibspiREG5->FLG & 0x01000000U) != 0U) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG5->UERRCTRL = (mibspiREG5->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U); + + /** - initialize transfer groups */ + mibspiREG5->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)0U << 8U); /* start buffer */ + + mibspiREG5->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)8U << 8U); /* start buffer */ + + mibspiREG5->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U) << 8U); /* start buffer */ + + mibspiREG5->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U) << 8U); /* start buffer */ + + mibspiREG5->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG5->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG5->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG5->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + + mibspiREG5->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U; + + mibspiREG5->LTGPEND = (mibspiREG5->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); + + /** - initialize buffer ram */ + { + i = 0U; + +#if (8U > 0U) + { + +#if (8U > 1U) + + while (i < (8U-1U)) + { + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U)-1U)) + { + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U)-1U)) + { + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U)-1U)) + { + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U)-1U)) + { + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG5->LVL = (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG5->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG5->INT0 = (mibspiREG5->INT0 & 0xFFFF0000U) + | (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** @b initialize @b MIBSPI5 @b Port */ + + /** - MIBSPI5 Port output values */ + mibspiREG5->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 17U) /* SIMO[1] */ + | (uint32)((uint32)0U << 18U) /* SIMO[2] */ + | (uint32)((uint32)0U << 19U) /* SIMO[3] */ + | (uint32)((uint32)0U << 25U) /* SOMI[1] */ + | (uint32)((uint32)0U << 26U) /* SOMI[2] */ + | (uint32)((uint32)0U << 27U); /* SOMI[3] */ + + /** - MIBSPI5 Port direction */ + mibspiREG5->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO[0] */ + | (uint32)((uint32)1U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 17U) /* SIMO[1] */ + | (uint32)((uint32)0U << 18U) /* SIMO[2] */ + | (uint32)((uint32)0U << 19U) /* SIMO[3] */ + | (uint32)((uint32)0U << 25U) /* SOMI[1] */ + | (uint32)((uint32)0U << 26U) /* SOMI[2] */ + | (uint32)((uint32)0U << 27U); /* SOMI[3] */ + + /** - MIBSPI5 Port open drain enable */ + mibspiREG5->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 17U) /* SIMO[1] */ + | (uint32)((uint32)0U << 18U) /* SIMO[2] */ + | (uint32)((uint32)0U << 19U) /* SIMO[3] */ + | (uint32)((uint32)0U << 25U) /* SOMI[1] */ + | (uint32)((uint32)0U << 26U) /* SOMI[2] */ + | (uint32)((uint32)0U << 27U); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown selection */ + mibspiREG5->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO[0] */ + | (uint32)((uint32)1U << 11U) /* SOMI[0] */ + | (uint32)((uint32)1U << 17U) /* SIMO[1] */ + | (uint32)((uint32)1U << 18U) /* SIMO[2] */ + | (uint32)((uint32)1U << 19U) /* SIMO[3] */ + | (uint32)((uint32)1U << 25U) /* SOMI[1] */ + | (uint32)((uint32)1U << 26U) /* SOMI[2] */ + | (uint32)((uint32)1U << 27U); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown enable*/ + mibspiREG5->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 17U) /* SIMO[1] */ + | (uint32)((uint32)0U << 18U) /* SIMO[2] */ + | (uint32)((uint32)0U << 19U) /* SIMO[3] */ + | (uint32)((uint32)0U << 25U) /* SOMI[1] */ + | (uint32)((uint32)0U << 26U) /* SOMI[2] */ + | (uint32)((uint32)0U << 27U); /* SOMI[3] */ + + /* MIBSPI5 set all pins to functional */ + mibspiREG5->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)1U << 17U) /* SIMO[1] */ + | (uint32)((uint32)1U << 18U) /* SIMO[2] */ + | (uint32)((uint32)1U << 19U) /* SIMO[3] */ + | (uint32)((uint32)1U << 25U) /* SOMI[1] */ + | (uint32)((uint32)1U << 26U) /* SOMI[2] */ + | (uint32)((uint32)1U << 27U); /* SOMI[3] */ + + /** - Finally start MIBSPI5 */ + mibspiREG5->GCR1 = (mibspiREG5->GCR1 & 0xFEFFFFFFU) | 0x01000000U; + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +} + + +/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port) +* @brief Change functional behavior of pins at runtime. +* @param[in] mibspi - mibspi module base address +* @param[in] port - Value to write to PC0 register +* +* Change the value of the PC0 register at runtime, this allows to +* dynamically change the functionality of the MIBSPI pins between functional +* and GIO mode. +*/ +/* SourceId : MIBSPI_SourceId_002 */ +/* DesignId : MIBSPI_DesignId_002 */ +/* Requirements : HL_SR154 */ +void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port) +{ +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + mibspi->PC0 = port; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ +} + + +/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) +* @brief Set Buffer Data +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* @param[in] data - new data for transfer group +* +* This function updates the data for the specified transfer group, +* the length of the data must match the length of the transfer group. +*/ +/* SourceId : MIBSPI_SourceId_003 */ +/* DesignId : MIBSPI_DesignId_003 */ +/* Requirements : HL_SR155 */ +void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) +{ +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + mibspiRAM_t *ram = (mibspi == mibspiREG1) ? mibspiRAM1 : ((mibspi == mibspiREG3) ? mibspiRAM3 : mibspiRAM5); + uint32 start = (mibspi->TGCTRL[group] >> 8U) & 0xFFU; + uint32 end = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU); + + if (end == 0U) {end = 128U;} + + while (start < end) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + ram->tx[start].data = *data; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + start++; + } +/* USER CODE BEGIN (7) */ +/* USER CODE END */ +} + + +/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) +* @brief Retrieves Buffer Data from receive buffer +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* @param[out] data - pointer to data array +* +* @return error flags from data buffer, if there was a receive error on +* one of the buffers this will be reflected in the return value. +* +* This function transfers the data from the specified transfer group receive +* buffers to the data array, the length of the data must match the length +* of the transfer group. +*/ +/* SourceId : MIBSPI_SourceId_004 */ +/* DesignId : MIBSPI_DesignId_004 */ +/* Requirements : HL_SR156 */ +uint32 mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) +{ +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + + mibspiRAM_t *ram = (mibspi == mibspiREG1) ? mibspiRAM1 : ((mibspi == mibspiREG3) ? mibspiRAM3 : mibspiRAM5); + uint32 start = (mibspi->TGCTRL[group] >> 8U) & 0xFFU; + uint32 end = (group == 7U) ? (((mibspi->LTGPEND & 0x00007F00U) >> 8U) + 1U) : ((mibspi->TGCTRL[group+1U] >> 8U) & 0xFFU); + uint16 mibspiFlags = 0U; + uint32 ret; + if (end == 0U) {end = 128U;} + + while (start < end) + { + mibspiFlags |= ram->rx[start].flags; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + *data = ram->rx[start].data; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + start++; + } + + ret = ((uint32)mibspiFlags >> 8U) & 0x5FU; +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + return ret; +} + + +/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group) +* @brief Transmit Transfer Group +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* +* Initiates a transfer for the specified transfer group. +*/ +/* SourceId : MIBSPI_SourceId_005 */ +/* DesignId : MIBSPI_DesignId_005 */ +/* Requirements : HL_SR157 */ +void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group) +{ +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + + mibspi->TGCTRL[group] |= 0x80000000U; + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +} + + +/** @fn boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group) +* @brief Check for Transfer Group Ready +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* +* @return TRUE is transfer complete, otherwise FALSE. +* +* Checks to see if the transfer for the specified transfer group +* has finished. +*/ +/* SourceId : MIBSPI_SourceId_006 */ +/* DesignId : MIBSPI_DesignId_006 */ +/* Requirements : HL_SR158 */ +boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group) +{ + boolean status; + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + + if(((((mibspi->TGINTFLG & 0xFFFF0000U) >> 16U)>> group) & 1U) == 1U) + { + mibspi->TGINTFLG = (mibspi->TGINTFLG & 0x0000FFFFU) | ((uint32)((uint32)1U << group) << 16U); + status = TRUE; + } + else + { + status = FALSE; + } + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + return (status); +} + + +/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype) +* @brief Enable Loopback mode for self test +* @param[in] mibspi - Mibspi module base address +* @param[in] Loopbacktype - Digital or Analog +* +* This function enables the Loopback mode for self test. +*/ +/* SourceId : MIBSPI_SourceId_007 */ +/* DesignId : MIBSPI_DesignId_009 */ +/* Requirements : HL_SR161 */ +void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype) +{ +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + + /* Clear Loopback incase enabled already */ + mibspi->IOLPKTSTCR = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + mibspi->IOLPKTSTCR = (uint32)0x00000A00U + | (uint32)((uint32)Loopbacktype << 1U); + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ +} + +/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi) +* @brief Enable Loopback mode for self test +* @param[in] mibspi - Mibspi module base address +* +* This function disable the Loopback mode. +*/ +/* SourceId : MIBSPI_SourceId_008 */ +/* DesignId : MIBSPI_DesignId_010 */ +/* Requirements : HL_SR162 */ +void mibspiDisableLoopback(mibspiBASE_t *mibspi) +{ +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + /* Disable Loopback Mode */ + mibspi->IOLPKTSTCR = 0x00000500U; + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ +} + +/** @fn void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT) +* @brief Set the Pmode for the selected Data Format register +* @param[in] mibspi - Mibspi module base address +* @param[in] Pmode - Mibspi Parellel mode +* PMODE_NORMAL +* PMODE_2_DATALINE +* PMODE_4_DATALINE +* PMODE_8_DATALINE +* @param[in] DFMT - Mibspi Data Format register +* DATA_FORMAT0 +* DATA_FORMAT1 +* DATA_FORMAT2 +* DATA_FORMAT3 +* +* This function sets the Pmode for the selected Data Format register. +*/ +/* SourceId : MIBSPI_SourceId_009 */ +/* DesignId : MIBSPI_DesignId_011 */ +/* Requirements : HL_SR524 */ +void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT) +{ + uint32 pmctrl_reg; + /* Set the Pmode for the selected Data Format register */ + pmctrl_reg = (mibspi->PMCTRL & (~(uint32)((uint32)0xFFU << (8U * DFMT)))); + mibspi->PMCTRL = (pmctrl_reg | (uint32)((uint32)Pmode << ((8U * DFMT)))); + +} + +/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level) +* @brief Enable Transfer Group interrupt +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* @param[in] level - Interrupt level +* +* This function enables the transfer group finished interrupt. +*/ +/* SourceId : MIBSPI_SourceId_010 */ +/* DesignId : MIBSPI_DesignId_007 */ +/* Requirements : HL_SR159 */ +void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level) +{ +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + + if (level != 0U) + { + mibspi->TGITLVST = (mibspi->TGITLVST & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U); + } + else + { + mibspi->TGITLVCR = (mibspi->TGITLVCR & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U); + } + mibspi->TGITENST = (mibspi->TGITENST & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U); + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ +} + + +/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group) +* @brief Disable Transfer Group interrupt +* @param[in] mibspi - Spi module base address +* @param[in] group - Transfer group (0..7) +* +* This function disables the transfer group finished interrupt. +*/ +/* SourceId : MIBSPI_SourceId_011 */ +/* DesignId : MIBSPI_DesignId_008 */ +/* Requirements : HL_SR160 */ +void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group) +{ +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + mibspi->TGITENCR = (mibspi->TGITENCR & 0x0000FFFFU) | (uint32)((uint32)((uint32)1U << group) << 16U); + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ +} + + + +/** @fn void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : MIBSPI_SourceId_014 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : HL_SR166 */ +void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR1 = MIBSPI5_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI5_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI5_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI5_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI5_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI5_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI5_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI5_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI5_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI5_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI5_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI5_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI5_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI5_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI5_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[0U] = MIBSPI5_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[1U] = MIBSPI5_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[2U] = MIBSPI5_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[3U] = MIBSPI5_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[4U] = MIBSPI5_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[5U] = MIBSPI5_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[6U] = MIBSPI5_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[7U] = MIBSPI5_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_UERRCTRL = MIBSPI5_UERRCTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = mibspiREG5->GCR1; + config_reg->CONFIG_INT0 = mibspiREG5->INT0; + config_reg->CONFIG_LVL = mibspiREG5->LVL; + config_reg->CONFIG_PCFUN = mibspiREG5->PC0; + config_reg->CONFIG_PCDIR = mibspiREG5->PC1; + config_reg->CONFIG_PCPDR = mibspiREG5->PC6; + config_reg->CONFIG_PCDIS = mibspiREG5->PC7; + config_reg->CONFIG_PCPSL = mibspiREG5->PC8; + config_reg->CONFIG_DELAY = mibspiREG5->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG5->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG5->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG5->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG5->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG5->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG5->LTGPEND; + config_reg->CONFIG_TGCTRL[0U] = mibspiREG5->TGCTRL[0U]; + config_reg->CONFIG_TGCTRL[1U] = mibspiREG5->TGCTRL[1U]; + config_reg->CONFIG_TGCTRL[2U] = mibspiREG5->TGCTRL[2U]; + config_reg->CONFIG_TGCTRL[3U] = mibspiREG5->TGCTRL[3U]; + config_reg->CONFIG_TGCTRL[4U] = mibspiREG5->TGCTRL[4U]; + config_reg->CONFIG_TGCTRL[5U] = mibspiREG5->TGCTRL[5U]; + config_reg->CONFIG_TGCTRL[6U] = mibspiREG5->TGCTRL[6U]; + config_reg->CONFIG_TGCTRL[7U] = mibspiREG5->TGCTRL[7U]; + config_reg->CONFIG_UERRCTRL = mibspiREG5->UERRCTRL; + } +} + + + + + Index: source/sci.c =================================================================== diff -u --- source/sci.c (revision 0) +++ source/sci.c (revision 7de64c199413a3f74d69efbdd1424b37c6f607c9) @@ -0,0 +1,668 @@ +/** @file sci.c +* @brief SCI Driver Implementation File +* @date 11-Dec-2018 +* @version 04.07.01 +* +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sci.h" +#include "sys_vim.h" +#include "math.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ +/** @struct g_sciTransfer +* @brief Interrupt mode globals +* +*/ +static volatile struct g_sciTransfer +{ + uint32 mode; /* Used to check for TX interrupt Enable */ + uint32 tx_length; /* Transmit data length in number of Bytes */ + uint32 rx_length; /* Receive data length in number of Bytes */ + uint8 * tx_data; /* Transmit data pointer */ + uint8 * rx_data; /* Receive data pointer */ +} g_sciTransfer_t[2U]; + + +/** @fn void sciInit(void) +* @brief Initializes the SCI Driver +* +* This function initializes the SCI module. +*/ +/* SourceId : SCI_SourceId_001 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : HL_SR230 */ +void sciInit(void) +{ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + /** @b initialize @b SCI */ + + /** - bring SCI out of reset */ + sciREG->GCR0 = 0U; + sciREG->GCR0 = 1U; + + /** - Disable all interrupts */ + sciREG->CLEARINT = 0xFFFFFFFFU; + sciREG->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + sciREG->GCR1 = (uint32)((uint32)1U << 25U) /* enable transmit */ + | (uint32)((uint32)1U << 24U) /* enable receive */ + | (uint32)((uint32)1U << 5U) /* internal clock (device has no clock pin) */ + | (uint32)((uint32)(2U-1U) << 4U) /* number of stop bits */ + | (uint32)((uint32)0U << 3U) /* even parity, otherwise odd */ + | (uint32)((uint32)0U << 2U) /* enable parity */ + | (uint32)((uint32)1U << 1U); /* asynchronous timing mode */ + + /** - set baudrate */ + sciREG->BRS = 715U; /* baudrate */ + + /** - transmission length */ + sciREG->FORMAT = 8U - 1U; /* length */ + + /** - set SCI pins functional mode */ + sciREG->PIO0 = (uint32)((uint32)1U << 2U) /* tx pin */ + | (uint32)((uint32)1U << 1U); /* rx pin */ + + /** - set SCI pins default output value */ + sciREG->PIO3 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + /** - set SCI pins output direction */ + sciREG->PIO1 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + /** - set SCI pins open drain enable */ + sciREG->PIO6 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + /** - set SCI pins pullup/pulldown enable */ + sciREG->PIO7 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + /** - set SCI pins pullup/pulldown select */ + sciREG->PIO8 = (uint32)((uint32)1U << 2U) /* tx pin */ + | (uint32)((uint32)1U << 1U); /* rx pin */ + + /** - set interrupt level */ + sciREG->SETINTLVL = (uint32)((uint32)0U << 26U) /* Framing error */ + | (uint32)((uint32)0U << 25U) /* Overrun error */ + | (uint32)((uint32)0U << 24U) /* Parity error */ + | (uint32)((uint32)0U << 9U) /* Receive */ + | (uint32)((uint32)0U << 8U) /* Transmit */ + | (uint32)((uint32)0U << 1U) /* Wakeup */ + | (uint32)((uint32)0U << 0U); /* Break detect */ + + /** - set interrupt enable */ + sciREG->SETINT = (uint32)((uint32)0U << 26U) /* Framing error */ + | (uint32)((uint32)0U << 25U) /* Overrun error */ + | (uint32)((uint32)0U << 24U) /* Parity error */ + | (uint32)((uint32)0U << 9U) /* Receive */ + | (uint32)((uint32)0U << 1U) /* Wakeup */ + | (uint32)((uint32)0U << 0U); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[0U].mode = (uint32)0U << 8U; + g_sciTransfer_t[0U].tx_length = 0U; + g_sciTransfer_t[0U].rx_length = 0U; + + /** - Finaly start SCI */ + sciREG->GCR1 |= 0x80U; + + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +} + + +/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port) +* @brief Change functional behavior of pins at runtime. +* @param[in] sci - sci module base address +* @param[in] port - Value to write to PIO0 register +* +* Change the value of the PCPIO0 register at runtime, this allows to +* dynamically change the functionality of the SCI pins between functional +* and GIO mode. +*/ +/* SourceId : SCI_SourceId_002 */ +/* DesignId : SCI_DesignId_002 */ +/* Requirements : HL_SR231 */ +void sciSetFunctional(sciBASE_t *sci, uint32 port) +{ +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + sci->PIO0 = port; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ +} + + +/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud) +* @brief Change baudrate at runtime. +* @param[in] sci - sci module base address +* @param[in] baud - baudrate in Hz +* +* Change the SCI baudrate at runtime. +*/ +/* SourceId : SCI_SourceId_003 */ +/* DesignId : SCI_DesignId_003 */ +/* Requirements : HL_SR232 */ +void sciSetBaudrate(sciBASE_t *sci, uint32 baud) +{ + float64 vclk = 110.000 * 1000000.0; + uint32 f = ((sci->GCR1 & 2U) == 2U) ? 16U : 1U; + uint32 temp; + float64 temp2; +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + /*SAFETYMCUSW 96 S MR:6.1 "Calculations including int and float cannot be avoided" */ + temp = (f*(baud)); + temp2 = ((vclk)/((float64)temp))-1U; + temp2 = floor(temp2 + 0.5); /* Rounding-off to the closest integer */ + sci->BRS = (uint32)((uint32)temp2 & 0x00FFFFFFU); + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ +} + + +/** @fn uint32 sciIsTxReady(sciBASE_t *sci) +* @brief Check if Tx buffer empty +* @param[in] sci - sci module base address +* +* @return The TX ready flag +* +* Checks to see if the Tx buffer ready flag is set, returns +* 0 is flags not set otherwise will return the Tx flag itself. +*/ +/* SourceId : SCI_SourceId_004 */ +/* DesignId : SCI_DesignId_004 */ +/* Requirements : HL_SR233 */ +uint32 sciIsTxReady(sciBASE_t *sci) +{ +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + + return sci->FLR & (uint32)SCI_TX_INT; +} + + +/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte) +* @brief Send Byte +* @param[in] sci - sci module base address +* @param[in] byte - byte to transfer +* +* Sends a single byte in polling mode, will wait in the +* routine until the transmit buffer is empty before sending +* the byte. Use sciIsTxReady to check for Tx buffer empty +* before calling sciSendByte to avoid waiting. +*/ +/* SourceId : SCI_SourceId_005 */ +/* DesignId : SCI_DesignId_005 */ +/* Requirements : HL_SR234 */ +void sciSendByte(sciBASE_t *sci, uint8 byte) +{ +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((sci->FLR & (uint32)SCI_TX_INT) == 0U) + { + } /* Wait */ + sci->TD = byte; + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ +} + + +/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) +* @brief Send Data +* @param[in] sci - sci module base address +* @param[in] length - number of data words to transfer +* @param[in] data - pointer to data to send +* +* Send a block of data pointed to by 'data' and 'length' bytes +* long. If interrupts have been enabled the data is sent using +* interrupt mode, otherwise polling mode is used. In interrupt +* mode transmission of the first byte is started and the routine +* returns immediately, sciSend must not be called again until the +* transfer is complete, when the sciNotification callback will +* be called. In polling mode, sciSend will not return until +* the transfer is complete. +* +* @note if data word is less than 8 bits, then the data must be left +* aligned in the data byte. +*/ +/* SourceId : SCI_SourceId_006 */ +/* DesignId : SCI_DesignId_006 */ +/* Requirements : HL_SR235 */ +void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) +{ + uint32 index = (sci == sciREG) ? 0U : 1U; + uint8 txdata; + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +/*SAFETYMCUSW 139 S MR:13.7 "Mode variable is configured in sciEnableNotification()" */ + if ((g_sciTransfer_t[index].mode & (uint32)SCI_TX_INT) != 0U) + { + /* we are in interrupt mode */ + + g_sciTransfer_t[index].tx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + g_sciTransfer_t[index].tx_data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + txdata = *g_sciTransfer_t[index].tx_data; + sci->TD = (uint32)(txdata); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[index].tx_data++; + sci->SETINT = (uint32)SCI_TX_INT; + } + else + { + /* send the data */ + while (length > 0U) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((sci->FLR & (uint32)SCI_TX_INT) == 0U) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + txdata = *data; + sci->TD = (uint32)(txdata); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +} + + +/** @fn uint32 sciIsRxReady(sciBASE_t *sci) +* @brief Check if Rx buffer full +* @param[in] sci - sci module base address +* +* @return The Rx ready flag +* +* Checks to see if the Rx buffer full flag is set, returns +* 0 is flags not set otherwise will return the Rx flag itself. +*/ +/* SourceId : SCI_SourceId_007 */ +/* DesignId : SCI_DesignId_007 */ +/* Requirements : HL_SR236 */ +uint32 sciIsRxReady(sciBASE_t *sci) +{ +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + return sci->FLR & (uint32)SCI_RX_INT; +} + +/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci) +* @brief Check if Idle Period is Detected +* @param[in] sci - sci module base address +* +* @return The Idle flag +* +* Checks to see if the SCI Idle flag is set, returns 0 if idle +* period has been detected and SCI is ready to receive, otherwise returns the Idle flag itself. +*/ +/* SourceId : SCI_SourceId_008 */ +/* DesignId : SCI_DesignId_008 */ +/* Requirements : HL_SR237 */ +uint32 sciIsIdleDetected(sciBASE_t *sci) +{ +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + + return sci->FLR & (uint32)SCI_IDLE; +} + + +/** @fn uint32 sciRxError(sciBASE_t *sci) +* @brief Return Rx Error flags +* @param[in] sci - sci module base address +* +* @return The Rx error flags +* +* Returns the Rx framing, overrun and parity errors flags, +* also clears the error flags before returning. +*/ +/* SourceId : SCI_SourceId_009 */ +/* DesignId : SCI_DesignId_009 */ +/* Requirements : HL_SR238 */ +uint32 sciRxError(sciBASE_t *sci) +{ + uint32 status = (sci->FLR & ((uint32)SCI_FE_INT | (uint32)SCI_OE_INT |(uint32)SCI_PE_INT)); + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + + sci->FLR = ((uint32)SCI_FE_INT | (uint32)SCI_OE_INT | (uint32)SCI_PE_INT); + return status; +} + + +/** @fn uint32 sciReceiveByte(sciBASE_t *sci) +* @brief Receive Byte +* @param[in] sci - sci module base address +* +* @return Received byte +* +* Receives a single byte in polling mode. If there is +* not a byte in the receive buffer the routine will wait +* until one is received. Use sciIsRxReady to check to +* see if the buffer is full to avoid waiting. +*/ +/* SourceId : SCI_SourceId_010 */ +/* DesignId : SCI_DesignId_010 */ +/* Requirements : HL_SR239 */ +uint32 sciReceiveByte(sciBASE_t *sci) +{ +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((sci->FLR & (uint32)SCI_RX_INT) == 0U) + { + } /* Wait */ + + return (sci->RD & (uint32)0x000000FFU); +} + + +/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) +* @brief Receive Data +* @param[in] sci - sci module base address +* @param[in] length - number of data words to transfer +* @param[in] data - pointer to data buffer to receive data +* +* Receive a block of 'length' bytes long and place it into the +* data buffer pointed to by 'data'. If interrupts have been +* enabled the data is received using interrupt mode, otherwise +* polling mode is used. In interrupt mode receive is setup and +* the routine returns immediately, sciReceive must not be called +* again until the transfer is complete, when the sciNotification +* callback will be called. In polling mode, sciReceive will not +* return until the transfer is complete. +*/ +/* SourceId : SCI_SourceId_011 */ +/* DesignId : SCI_DesignId_011 */ +/* Requirements : HL_SR240 */ +void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) +{ +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + if ((sci->SETINT & (uint32)SCI_RX_INT) == (uint32)SCI_RX_INT) + { + /* we are in interrupt mode */ + uint32 index = (sci == sciREG) ? 0U : 1U; + + /* clear error flags */ + sci->FLR = ((uint32) SCI_FE_INT | (uint32) SCI_OE_INT | (uint32) SCI_PE_INT); + + g_sciTransfer_t[index].rx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + g_sciTransfer_t[index].rx_data = data; + } + else + { + while (length > 0U) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((sci->FLR & (uint32)SCI_RX_INT) == 0U) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + *data = (uint8)(sci->RD & 0x000000FFU); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } +/* USER CODE BEGIN (18) */ +/* USER CODE END */ +} + +/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) +* @brief Enable Loopback mode for self test +* @param[in] sci - sci module base address +* @param[in] Loopbacktype - Digital or Analog +* +* This function enables the Loopback mode for self test. +*/ +/* SourceId : SCI_SourceId_012 */ +/* DesignId : SCI_DesignId_014 */ +/* Requirements : HL_SR243 */ +void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) +{ +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + + /* Clear Loopback incase enabled already */ + sci->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + sci->IODFTCTRL = (uint32)0x00000A00U + | (uint32)((uint32)Loopbacktype << 1U); + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ +} + +/** @fn void sciDisableLoopback(sciBASE_t *sci) +* @brief Enable Loopback mode for self test +* @param[in] sci - sci module base address +* +* This function disable the Loopback mode. +*/ +/* SourceId : SCI_SourceId_013 */ +/* DesignId : SCI_DesignId_015 */ +/* Requirements : HL_SR244 */ +void sciDisableLoopback(sciBASE_t *sci) +{ +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + /* Disable Loopback Mode */ + sci->IODFTCTRL = 0x00000500U; + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ +} + +/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags) +* @brief Enable interrupts +* @param[in] sci - sci module base address +* @param[in] flags - Interrupts to be enabled, can be ored value of: +* SCI_FE_INT - framing error, +* SCI_OE_INT - overrun error, +* SCI_PE_INT - parity error, +* SCI_RX_INT - receive buffer ready, +* SCI_TX_INT - transmit buffer ready, +* SCI_WAKE_INT - wakeup, +* SCI_BREAK_INT - break detect +*/ +/* SourceId : SCI_SourceId_014 */ +/* DesignId : SCI_DesignId_012 */ +/* Requirements : HL_SR241 */ +void sciEnableNotification(sciBASE_t *sci, uint32 flags) +{ + uint32 index = (sci == sciREG) ? 0U : 1U; + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + g_sciTransfer_t[index].mode |= (flags & (uint32)SCI_TX_INT); + sci->SETINT = (flags & (uint32)(~(uint32)(SCI_TX_INT))); + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ +} + + +/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags) +* @brief Disable interrupts +* @param[in] sci - sci module base address +* @param[in] flags - Interrupts to be disabled, can be ored value of: +* SCI_FE_INT - framing error, +* SCI_OE_INT - overrun error, +* SCI_PE_INT - parity error, +* SCI_RX_INT - receive buffer ready, +* SCI_TX_INT - transmit buffer ready, +* SCI_WAKE_INT - wakeup, +* SCI_BREAK_INT - break detect +*/ +/* SourceId : SCI_SourceId_015 */ +/* DesignId : SCI_DesignId_013 */ +/* Requirements : HL_SR242 */ +void sciDisableNotification(sciBASE_t *sci, uint32 flags) +{ + uint32 index = (sci == sciREG) ? 0U : 1U; + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + + g_sciTransfer_t[index].mode &= (uint32)(~(flags & (uint32)SCI_TX_INT)); + sci->CLEARINT = (flags & (uint32)(~(uint32)(SCI_TX_INT))); + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ +} + +/** @fn sciEnterResetState(sciBASE_t *sci) +* @brief Enter reset state +* @param[in] sci - sci module base address +* @note The SCI should only be configured while in reset state +*/ +/* SourceId : SCI_SourceId_022 */ +/* DesignId : SCI_DesignId_018 */ +/* Requirements : HL_SR548 */ +void sciEnterResetState(sciBASE_t *sci) +{ + sci->GCR1 &= 0xFFFFFF7FU; +} + +/** @fn scixitResetState(sciBASE_t *sci) +* @brief Exit reset state +* @param[in] sci - sci module base address +* @note The SCI should only be configured while in reset state +*/ +/* SourceId : SCI_SourceId_023 */ +/* DesignId : SCI_DesignId_018 */ +/* Requirements : HL_SR548 */ +void sciExitResetState(sciBASE_t *sci) +{ + sci->GCR1 |= 0x00000080U; +} + +/** @fn void sciGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the SCI configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SCI_SourceId_016 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : HL_SR247 */ +void sciGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR0 = SCI_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCI_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCI_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCI_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCI_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCI_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCI_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCI_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCI_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCI_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCI_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR0 = sciREG->GCR0; + config_reg->CONFIG_GCR1 = sciREG->GCR1; + config_reg->CONFIG_SETINT = sciREG->SETINT; + config_reg->CONFIG_SETINTLVL = sciREG->SETINTLVL; + config_reg->CONFIG_FORMAT = sciREG->FORMAT; + config_reg->CONFIG_BRS = sciREG->BRS; + config_reg->CONFIG_PIO0 = sciREG->PIO0; + config_reg->CONFIG_PIO1 = sciREG->PIO1; + config_reg->CONFIG_PIO6 = sciREG->PIO6; + config_reg->CONFIG_PIO7 = sciREG->PIO7; + config_reg->CONFIG_PIO8 = sciREG->PIO8; + } +} + + + +/* USER CODE BEGIN (37) */ +/* USER CODE END */ +