Index: firmware/.launches/HD.launch =================================================================== diff -u -r636c8e7083577ed918d06255423784ca47271a88 -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/.launches/HD.launch (.../HD.launch) (revision 636c8e7083577ed918d06255423784ca47271a88) +++ firmware/.launches/HD.launch (.../HD.launch) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -2,6 +2,7 @@ + @@ -20,13 +21,16 @@ + + + Index: firmware/.settings/org.eclipse.core.resources.prefs =================================================================== diff -u -r4fc76c20dc4d515a391ef510da9360d633be8924 -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/.settings/org.eclipse.core.resources.prefs (.../org.eclipse.core.resources.prefs) (revision 4fc76c20dc4d515a391ef510da9360d633be8924) +++ firmware/.settings/org.eclipse.core.resources.prefs (.../org.eclipse.core.resources.prefs) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -1,6 +1,4 @@ eclipse.preferences.version=1 -encoding//Debug/App/Contollers/subdir_rules.mk=UTF-8 -encoding//Debug/App/Contollers/subdir_vars.mk=UTF-8 encoding//Debug/App/Controllers/subdir_rules.mk=UTF-8 encoding//Debug/App/Controllers/subdir_vars.mk=UTF-8 encoding//Debug/App/Drivers/subdir_rules.mk=UTF-8 @@ -18,3 +16,20 @@ encoding//Debug/sources.mk=UTF-8 encoding//Debug/subdir_rules.mk=UTF-8 encoding//Debug/subdir_vars.mk=UTF-8 +encoding//Release/App/Controllers/subdir_rules.mk=UTF-8 +encoding//Release/App/Controllers/subdir_vars.mk=UTF-8 +encoding//Release/App/Drivers/subdir_rules.mk=UTF-8 +encoding//Release/App/Drivers/subdir_vars.mk=UTF-8 +encoding//Release/App/Modes/subdir_rules.mk=UTF-8 +encoding//Release/App/Modes/subdir_vars.mk=UTF-8 +encoding//Release/App/Services/subdir_rules.mk=UTF-8 +encoding//Release/App/Services/subdir_vars.mk=UTF-8 +encoding//Release/App/Tasks/subdir_rules.mk=UTF-8 +encoding//Release/App/Tasks/subdir_vars.mk=UTF-8 +encoding//Release/makefile=UTF-8 +encoding//Release/objects.mk=UTF-8 +encoding//Release/source/subdir_rules.mk=UTF-8 +encoding//Release/source/subdir_vars.mk=UTF-8 +encoding//Release/sources.mk=UTF-8 +encoding//Release/subdir_rules.mk=UTF-8 +encoding//Release/subdir_vars.mk=UTF-8 Index: firmware/App/Common.h =================================================================== diff -u -r3417fd56afc9b21fb4c2d86c75dd33ac31fbd9f1 -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/App/Common.h (.../Common.h) (revision 3417fd56afc9b21fb4c2d86c75dd33ac31fbd9f1) +++ firmware/App/Common.h (.../Common.h) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -22,7 +22,7 @@ // ********** build switches ********** #ifndef _VECTORCAST_ -// #define RM46_EVAL_BOARD_TARGET 1 + #define RM46_EVAL_BOARD_TARGET 1 // #define SIMULATE_UI 1 // #define DEBUG_ENABLED 1 Index: firmware/App/Controllers/RTC.c =================================================================== diff -u --- firmware/App/Controllers/RTC.c (revision 0) +++ firmware/App/Controllers/RTC.c (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -0,0 +1,232 @@ +/************************************************************************** + * + * Copyright (c) 2019-2019 Diality Inc. - All Rights Reserved. + * + * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN + * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. + * + * @file RTC.c + * + * @date 27-Nov-2019 + * @author D. Navaei + * + * @brief Monitor/Controller Real Time Clock + * + **************************************************************************/ + +#include "Common.h" +#include "RTC.h" +#include "mibspi.h" + + +// ********** private definitions ********** +// TODO: Add the definition of all the registers +#define RTC_REG_1_12_HOUR_MODE 0X0004 +#define RTC_REG_1_PORO 0X0008 +#define RTC_REG_1_CLK_STOPPED 0X0020 +#define RTC_REG_1_UNUSED 0X0040 +#define RTC_REG_1_EXT_CLK_MODE 0X0080 + +#define RTC_REG_2_MASK 0X0000 + +#define RTC_REG_3_MASK 0X0008 + +// RTC registers indices +#define RTC_REG_1_INDEX 1 +#define RTC_REG_2_INDEX 2 +#define RTC_REG_3_INDEX 3 +#define RTC_SECONDS_INDEX 4 +#define RTC_MINUTES_INDEX 5 +#define RTC_HOURS_INDEX 6 +#define RTC_DAYS_INDEX 7 +#define RTC_WEEKDAYS_INDEX 8 +#define RTC_MONTHS_INDEX 9 +#define RTC_YEARS_INDEX 10 + +// This command puts RTC into read mode from +// address 0 +#define RTC_READ_ALL 0x00A0 + +typedef enum RTC_Self_Test_States +{ + RTC_SELF_TEST_STATE_START = 0, + RTC_SELF_TEST_STATE_CHECK_CTRL_REGS, + RTC_SELF_TEST_STATE_IN_PROGRESS, + RTC_SELF_TEST_STATE_COMPLETE +} RTC_SELF_TEST_STATE_T; + +typedef enum RTC_read_data +{ + RTC_SEND_COMMAND = 0, + RTC_WAIT_FOR_TRANSFER_AND_READ, + RTC_READ_COMPLETE +} RTC_GET_DATA_STATE_T; + + +static RTC_SELF_TEST_STATE_T RTCSelfTestState = RTC_SELF_TEST_STATE_START; +static RTC_GET_DATA_STATE_T RTCGetDataState = RTC_SEND_COMMAND; +static U32 RTCTestTimer = 0; + +// TODO: Increase the size of the buffer +static U16 rxBuffer[11]; +static U16 txBuffer[] = {RTC_READ_ALL, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}; + +// TODO: add the pointer to the buffers in the input arguments +void getRTCData() +{ + switch ( RTCGetDataState ) + { + case RTC_SEND_COMMAND: + + mibspiSetData(mibspiREG3, 0, txBuffer); + + mibspiTransfer(mibspiREG3, 0); + + RTCGetDataState = RTC_WAIT_FOR_TRANSFER_AND_READ; + break; + + case RTC_WAIT_FOR_TRANSFER_AND_READ: + + if ( mibspiIsTransferComplete(mibspiREG3, 0) ) + { + mibspiGetData(mibspiREG3, 0, rxBuffer); + + RTCGetDataState = RTC_READ_COMPLETE; + } + break; + + case RTC_READ_COMPLETE: + // Done with reading and transfer do nothing + break; + + default: + // TODO: Set an alarm or try multiple times (3 times) before failing + break; + } +} + +BOOL isRTCFunctional() +{ + BOOL hasTestPassed = TRUE; + + U16 controlReg1 = rxBuffer[RTC_REG_1_INDEX]; + U16 controlReg2 = rxBuffer[RTC_REG_2_INDEX]; + U16 controlReg3 = rxBuffer[RTC_REG_2_INDEX]; + + if ( ! controlReg1 & RTC_REG_1_12_HOUR_MODE ) + { + // Set the alarm for 24 hour mode + hasTestPassed = FALSE; + } + if ( ! controlReg1 & RTC_REG_1_PORO ) + { + // Set the alarm for PORO low mode + hasTestPassed = FALSE; + } + if ( ! controlReg1 & RTC_REG_1_CLK_STOPPED ) + { + // Set the alarm for clock stopped mode + hasTestPassed = FALSE; + } + if ( ! controlReg1 & RTC_REG_1_UNUSED ) + { + // Set the alarm for unused bit set to 1 mode + hasTestPassed = FALSE; + } + if ( ! controlReg1 & RTC_REG_1_EXT_CLK_MODE ) + { + // Set the alarm for clock set on external mode + hasTestPassed = FALSE; + } + if ( ! controlReg2 & RTC_REG_2_MASK ) + { + // Set the alarm for register 2 + hasTestPassed = FALSE; + } + if ( ! controlReg3 & RTC_REG_3_MASK ) + { + // Set the alarm for register 3 + hasTestPassed = FALSE; + } + return hasTestPassed; +} + +SELF_TEST_STATUS_T execRTCSelfTest( void ) +{ + SELF_TEST_STATUS_T result = SELF_TEST_STATUS_IN_PROGRESS; + + switch ( RTCSelfTestState ) + { + case RTC_SELF_TEST_STATE_START: + + getRTCData(); + + RTCSelfTestState = RTC_SELF_TEST_STATE_CHECK_CTRL_REGS; + + + case RTC_SELF_TEST_STATE_CHECK_CTRL_REGS: + + getRTCData(); + + if ( RTCGetDataState == RTC_READ_COMPLETE ) + { + // Reset the states + RTCGetDataState = RTC_SEND_COMMAND; + + if ( isRTCFunctional() ) + { + result = SELF_TEST_STATUS_PASSED; + RTCSelfTestState = RTC_SELF_TEST_STATE_IN_PROGRESS; + } + else + { + result = SELF_TEST_STATUS_FAILED; + RTCSelfTestState = RTC_SELF_TEST_STATE_COMPLETE; + } + } + break; + + case RTC_SELF_TEST_STATE_IN_PROGRESS: + + + break; + + case RTC_SELF_TEST_STATE_COMPLETE: + break; + + default: + // TODO: Add the alarms + result = SELF_TEST_STATUS_FAILED; + break; + } + + return result; +} + + + +BOOL readRTCData() +{ + BOOL transferStatus = mibspiIsTransferComplete(mibspiREG3, 0); + + if ( transferStatus ) + { + mibspiGetData(mibspiREG3, 0, rxBuffer); + } + + return transferStatus; +} + +void initRTC() +{ +} + +void execRTC() +{ + + + +} + + + Index: firmware/App/Controllers/RTC.h =================================================================== diff -u --- firmware/App/Controllers/RTC.h (revision 0) +++ firmware/App/Controllers/RTC.h (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -0,0 +1,30 @@ +/************************************************************************** + * + * Copyright (c) 2019-2019 Diality Inc. - All Rights Reserved. + * + * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN + * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. + * + * @file RTC.h + * + * @date 27-NOV-2019 + * @author D. Navaei + * + * @brief RTC header file. + * + **************************************************************************/ + +#ifndef _RTC_H_ +#define _RTC_H_ + +#include "Common.h" + +void initRTC( void ); + +void execRTC( void ); +BOOL setTimeStamp( void ); + +SELF_TEST_STATUS_T execRTCSelfTest( void ); + + +#endif Index: firmware/App/Drivers/CPLD.c =================================================================== diff -u -r90f6438e80dbe0a32472a076a0d1bc54db65d15a -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/App/Drivers/CPLD.c (.../CPLD.c) (revision 90f6438e80dbe0a32472a076a0d1bc54db65d15a) +++ firmware/App/Drivers/CPLD.c (.../CPLD.c) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -234,6 +234,10 @@ { PIN_SIGNAL_STATE_T level = GET_OFF(); +#ifdef RM46_EVAL_BOARD_TARGET + level = (level == PIN_SIGNAL_LOW ? PIN_SIGNAL_HIGH : PIN_SIGNAL_LOW); +#endif + return level; } @@ -251,6 +255,10 @@ { PIN_SIGNAL_STATE_T level = GET_STOP(); +#ifdef RM46_EVAL_BOARD_TARGET + level = (level == PIN_SIGNAL_LOW ? PIN_SIGNAL_HIGH : PIN_SIGNAL_LOW); +#endif + return level; } Index: firmware/App/Modes/ModeInitPOST.c =================================================================== diff -u -r1f3647830e9de0a1f0a4e445ce8d72d5525f51fb -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/App/Modes/ModeInitPOST.c (.../ModeInitPOST.c) (revision 1f3647830e9de0a1f0a4e445ce8d72d5525f51fb) +++ firmware/App/Modes/ModeInitPOST.c (.../ModeInitPOST.c) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -20,6 +20,7 @@ #include "CPLD.h" #include "FPGA.h" #include "OperationModes.h" +#include "RTC.h" #include "WatchdogMgmt.h" #include "ModeInitPOST.h" @@ -31,6 +32,7 @@ POST_STATE_ALARM_LAMP, POST_STATE_STUCK_BUTTON, POST_STATE_FPGA, + POST_STATE_RTC, POST_STATE_WATCHDOG, POST_STATE_COMPLETED, POST_STATE_FAILED, @@ -93,6 +95,8 @@ { SELF_TEST_STATUS_T testStatus = SELF_TEST_STATUS_IN_PROGRESS; + BOOL stop = isStopButtonPressed(); + // execute current POST state switch ( postState ) { @@ -115,6 +119,11 @@ postState = handlePOSTStatus( testStatus ); break; + case POST_STATE_RTC: + testStatus = execRTCSelfTest(); + postState = handlePOSTStatus( testStatus ); + break; + case POST_STATE_WATCHDOG: testStatus = execWatchdogTest(); handlePOSTStatus( testStatus ); // ignoring return value because last test Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r3417fd56afc9b21fb4c2d86c75dd33ac31fbd9f1 -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 3417fd56afc9b21fb4c2d86c75dd33ac31fbd9f1) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -639,9 +639,12 @@ SELF_TEST_STATUS_T execFPGATest( void ) { SELF_TEST_STATUS_T result; - +#ifndef RM46_EVAL_BOARD_TARGET // check FPGA reported correct ID if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId ) +#else + if ( 1 ) +#endif { result = SELF_TEST_STATUS_PASSED; } Index: firmware/App/Tasks/TaskGeneral.c =================================================================== diff -u -r51c6a24b30643c8ce296ebfe1d703f289ffafe97 -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision 51c6a24b30643c8ce296ebfe1d703f289ffafe97) +++ firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -22,6 +22,7 @@ #include "SystemComm.h" #include "WatchdogMgmt.h" #include "TaskGeneral.h" +#include "RTC.h" #ifdef RM46_EVAL_BOARD_TARGET #include "CPLD.h" @@ -48,6 +49,10 @@ // manage data received from other sub-systems execSystemCommRx(); + // Control RTC + // After CommRx and and before execOperationModes() + execRTC(); + // run operation mode state machine execOperationModes(); Index: firmware/HD.dil =================================================================== diff -u -r6c801cb0b32cba0e754cb6b1b57c1a8bd4e2bcf7 -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/HD.dil (.../HD.dil) (revision 6c801cb0b32cba0e754cb6b1b57c1a8bd4e2bcf7) +++ firmware/HD.dil (.../HD.dil) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -1,4 +1,4 @@ -# RM46L852PGE 11/13/19 13:30:04 +# RM46L852PGE 12/03/19 15:47:31 # ARCH=RM46L852PGE # @@ -1109,7 +1109,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_DP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x0013FFE0 DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00180000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16 @@ -1855,7 +1855,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0 @@ -1932,7 +1932,7 @@ DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=20 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=9.677 @@ -1960,7 +1960,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18 @@ -2086,7 +2086,7 @@ DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0 @@ -2152,7 +2152,7 @@ DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2 @@ -2175,7 +2175,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG3_USE_CS_ENCODE.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG7_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0 @@ -2311,7 +2311,7 @@ DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG5_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED @@ -2336,7 +2336,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=11 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_CS_ENCODE.VALUE=0xFF @@ -2411,7 +2411,7 @@ DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0 @@ -2439,7 +2439,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0 @@ -2511,7 +2511,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=19.355 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0 @@ -2558,7 +2558,7 @@ DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=102 -DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=8 DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1003.252 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=102 @@ -7207,7 +7207,7 @@ DRIVER.PINMUX.VAR.DMA_IFT_COUNT_24.VALUE=0 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_16.VALUE=0 DRIVER.PINMUX.VAR.DMA_INTLFSEN_12.VALUE=1 -DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.DMA_FIDXD_29.VALUE=0 @@ -7424,7 +7424,7 @@ DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0 @@ -7670,7 +7670,7 @@ DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.DMA_ADDMW_7.VALUE=CONSTANT @@ -7945,7 +7945,7 @@ DRIVER.PINMUX.VAR.MUX50_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX42_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX34_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX18_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX4_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0 @@ -8350,7 +8350,7 @@ DRIVER.PINMUX.VAR.DMA_BYP_9.VALUE=1 DRIVER.PINMUX.VAR.MIBSPI1.VALUE=0 DRIVER.PINMUX.VAR.MUX103_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MIBSPI3.VALUE=0 +DRIVER.PINMUX.VAR.MIBSPI3.VALUE=1 DRIVER.PINMUX.VAR.MUX103_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.OHCI0.VALUE=0 DRIVER.PINMUX.VAR.MUX103_OPTION2.VALUE=0 Index: firmware/include/mibspi.h =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/include/mibspi.h (.../mibspi.h) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/include/mibspi.h (.../mibspi.h) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -190,7 +190,37 @@ +#define MIBSPI3_GCR1_CONFIGVALUE (0x01000000U | (uint32)((uint32)1U << 1U) | 1U) +#define MIBSPI3_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) +#define MIBSPI3_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) +#define MIBSPI3_PCFUN_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U)) +#define MIBSPI3_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) +#define MIBSPI3_PCPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) +#define MIBSPI3_PCDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) +#define MIBSPI3_PCPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U)) + +#define MIBSPI3_DELAY_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U)) + +#define MIBSPI3_FMT0_CONFIGVALUE ((uint32)((uint32)20U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)8U << 0U)) +#define MIBSPI3_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI3_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI3_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U)) + +#define MIBSPI3_MIBSPIE_CONFIGVALUE 1U +#define MIBSPI3_LTGPEND_CONFIGVALUE ((uint32)((uint32)((11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U)) + +#define MIBSPI3_TGCTRL0_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)0U << 8U))) +#define MIBSPI3_TGCTRL1_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)11U << 8U))) +#define MIBSPI3_TGCTRL2_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U) << 8U))) +#define MIBSPI3_TGCTRL3_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL4_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL5_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL6_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL7_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U))) + +#define MIBSPI3_UERRCTRL_CONFIGVALUE (0x00000005U) + #define MIBSPI5_GCR1_CONFIGVALUE (0x01000000U | (uint32)((uint32)1U << 1U) | 1U) #define MIBSPI5_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) #define MIBSPI5_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) @@ -251,6 +281,7 @@ void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype); void mibspiDisableLoopback(mibspiBASE_t *mibspi); void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT); +void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type); void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type); /** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags) Index: firmware/source/mibspi.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -ra635fc9674913460c74831add7886c85d8aaf8f1 --- firmware/source/mibspi.c (.../mibspi.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/source/mibspi.c (.../mibspi.c) (revision a635fc9674913460c74831add7886c85d8aaf8f1) @@ -65,7 +65,480 @@ + /** @b initialize @b MIBSPI3 */ + /** bring MIBSPI out of reset */ + mibspiREG3->GCR0 = 0U; + mibspiREG3->GCR0 = 1U; + + /** enable MIBSPI3 multibuffered mode and enable buffer RAM */ + mibspiREG3->MIBSPIE = (mibspiREG3->MIBSPIE & 0xFFFFFFFEU) | 1U; + + /** MIBSPI3 master mode and clock configuration */ + mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */ + | 1U); /* MASTER */ + + /** MIBSPI3 enable pin configuration */ + mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */ + + /** - Delays */ + mibspiREG3->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */ + | (uint32)((uint32)0U << 16U) /* T2CDELAY */ + | (uint32)((uint32)0U << 8U) /* T2EDELAY */ + | (uint32)((uint32)0U << 0U); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG3->FMT0 = (uint32)((uint32)20U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)1U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)8U << 0U); /* data word length */ + + /** - Data Format 1 */ + mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 2 */ + mibspiREG3->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 3 */ + mibspiREG3->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Default Chip Select */ + mibspiREG3->DEF = (uint32)(0xFFU); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while ((mibspiREG3->FLG & 0x01000000U) != 0U) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U); + + /** - initialize transfer groups */ + mibspiREG3->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)0U << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)11U << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + + mibspiREG3->TGCTRL[8U] = (uint32)(11U+0U+0U+0U+0U+0U+0U+0U) << 8U; + + mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); + + /** - initialize buffer ram */ + { + i = 0U; + +#if (11U > 0U) + { + +#if (11U > 1U) + + while (i < (11U-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)1U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG3->LVL = (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG3->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U) + | (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** @b initialize @b MIBSPI3 @b Port */ + + /** - MIBSPI3 Port output values */ + mibspiREG3->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + /** - MIBSPI3 Port direction */ + mibspiREG3->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + /** - MIBSPI3 Port open drain enable */ + mibspiREG3->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + + /** - MIBSPI3 Port pullup / pulldown selection */ + mibspiREG3->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)1U << 11U); /* SOMI */ + + + /** - MIBSPI3 Port pullup / pulldown enable*/ + mibspiREG3->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + + /* MIBSPI3 set all pins to functional */ + mibspiREG3->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)1U << 11U); /* SOMI */ + + /** - Finally start MIBSPI3 */ + mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U; + + + /** @b initialize @b MIBSPI5 */ /** bring MIBSPI out of reset */ @@ -858,6 +1331,82 @@ } +/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : MIBSPI_SourceId_013 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : HL_SR166 */ +void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR1 = MIBSPI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI3_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI3_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI3_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI3_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI3_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI3_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI3_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI3_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI3_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI3_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI3_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI3_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI3_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI3_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[0U] = MIBSPI3_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[1U] = MIBSPI3_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[2U] = MIBSPI3_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[3U] = MIBSPI3_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[4U] = MIBSPI3_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[5U] = MIBSPI3_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[6U] = MIBSPI3_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[7U] = MIBSPI3_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_UERRCTRL = MIBSPI3_UERRCTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = mibspiREG3->GCR1; + config_reg->CONFIG_INT0 = mibspiREG3->INT0; + config_reg->CONFIG_LVL = mibspiREG3->LVL; + config_reg->CONFIG_PCFUN = mibspiREG3->PC0; + config_reg->CONFIG_PCDIR = mibspiREG3->PC1; + config_reg->CONFIG_PCPDR = mibspiREG3->PC6; + config_reg->CONFIG_PCDIS = mibspiREG3->PC7; + config_reg->CONFIG_PCPSL = mibspiREG3->PC8; + config_reg->CONFIG_DELAY = mibspiREG3->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG3->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG3->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG3->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG3->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG3->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG3->LTGPEND; + config_reg->CONFIG_TGCTRL[0U] = mibspiREG3->TGCTRL[0U]; + config_reg->CONFIG_TGCTRL[1U] = mibspiREG3->TGCTRL[1U]; + config_reg->CONFIG_TGCTRL[2U] = mibspiREG3->TGCTRL[2U]; + config_reg->CONFIG_TGCTRL[3U] = mibspiREG3->TGCTRL[3U]; + config_reg->CONFIG_TGCTRL[4U] = mibspiREG3->TGCTRL[4U]; + config_reg->CONFIG_TGCTRL[5U] = mibspiREG3->TGCTRL[5U]; + config_reg->CONFIG_TGCTRL[6U] = mibspiREG3->TGCTRL[6U]; + config_reg->CONFIG_TGCTRL[7U] = mibspiREG3->TGCTRL[7U]; + config_reg->CONFIG_UERRCTRL = mibspiREG3->UERRCTRL; + } +} /** @fn void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) * @brief Get the initial or current values of the configuration registers @@ -940,3 +1489,4 @@ +