Index: firmware/.launches/HD.launch
===================================================================
diff -u -re3e3dca356ca4938e62f742225f4bace2aaf1b57 -ra713d5cd8b39f13482ce13750dabdf1569d6d95d
--- firmware/.launches/HD.launch (.../HD.launch) (revision e3e3dca356ca4938e62f742225f4bace2aaf1b57)
+++ firmware/.launches/HD.launch (.../HD.launch) (revision a713d5cd8b39f13482ce13750dabdf1569d6d95d)
@@ -11,6 +11,7 @@
+
@@ -35,6 +36,7 @@
+
@@ -44,6 +46,7 @@
+
@@ -54,6 +57,7 @@
+
Index: firmware/HD.dil
===================================================================
diff -u -ra8451b47c75daac4189cf58bfaa007606d559376 -ra713d5cd8b39f13482ce13750dabdf1569d6d95d
--- firmware/HD.dil (.../HD.dil) (revision a8451b47c75daac4189cf58bfaa007606d559376)
+++ firmware/HD.dil (.../HD.dil) (revision a713d5cd8b39f13482ce13750dabdf1569d6d95d)
@@ -1,4 +1,4 @@
-# RM46L852PGE 02/04/20 17:48:12
+# RM46L852PGE 02/27/20 08:55:20
#
ARCH=RM46L852PGE
#
@@ -2431,7 +2431,7 @@
DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1
DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000
DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED
-DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=0
DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
DRIVER.MIBSPI.VAR.MIBSPI3_TG0_CS_ENCODE.VALUE=0xFF
DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0
@@ -2477,7 +2477,7 @@
DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS
DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=1
DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0
DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0
DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF
Index: firmware/include/mibspi.h
===================================================================
diff -u -rfe01fd0124c0c43737474781730608d55d0f0bda -ra713d5cd8b39f13482ce13750dabdf1569d6d95d
--- firmware/include/mibspi.h (.../mibspi.h) (revision fe01fd0124c0c43737474781730608d55d0f0bda)
+++ firmware/include/mibspi.h (.../mibspi.h) (revision a713d5cd8b39f13482ce13750dabdf1569d6d95d)
@@ -194,7 +194,7 @@
#define MIBSPI3_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 0U))
#define MIBSPI3_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
-#define MIBSPI3_PCFUN_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
+#define MIBSPI3_PCFUN_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
#define MIBSPI3_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
#define MIBSPI3_PCPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
#define MIBSPI3_PCDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
Index: firmware/source/mibspi.c
===================================================================
diff -u -ra8451b47c75daac4189cf58bfaa007606d559376 -ra713d5cd8b39f13482ce13750dabdf1569d6d95d
--- firmware/source/mibspi.c (.../mibspi.c) (revision a8451b47c75daac4189cf58bfaa007606d559376)
+++ firmware/source/mibspi.c (.../mibspi.c) (revision a713d5cd8b39f13482ce13750dabdf1569d6d95d)
@@ -523,8 +523,8 @@
/* MIBSPI3 set all pins to functional */
- mibspiREG3->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */
- | (uint32)((uint32)0U << 1U) /* SCS[1] */
+ mibspiREG3->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */
+ | (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)0U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */