Index: App/Common.h =================================================================== diff -u -r3470940824d26e0c43cb59ffdacfa4d9854096ae -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- App/Common.h (.../Common.h) (revision 3470940824d26e0c43cb59ffdacfa4d9854096ae) +++ App/Common.h (.../Common.h) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -55,6 +55,13 @@ NUM_OF_SELF_TEST_STATUS } SELF_TEST_STATUS_T; +typedef enum Two_Way_States +{ + STATE_CLOSED = 0, + STATE_OPEN, + NUM_OF_TWO_WAY_STATES +} TWO_WAY_STATE_T; + // **** Common Definitions **** #define NEARLY_ZERO 0.00001 @@ -65,6 +72,47 @@ #define MAX(a,b) ((a) < (b) ? (b) : (a)) #define MIN(a,b) ((a) > (b) ? (b) : (a)) +// **** Script Support Definitions **** + +#define OVERRIDE_KEY 0xCCC33C33 +#define OVERRIDE_RESET 0x00000000 + +// DATA_DECL - declares an overrideable data variable +// t = data's type +// t_name = name for data's structure type +// d_name = name for data's variable +// i_val = data's initial value +// o_val = data's initial override value +#define DATA_DECL( t, t_name, d_name, i_val, o_val ) \ +struct t_name \ +{ \ + t data; \ + t ovInitData; \ + t ovData; \ + U32 override; \ +}; \ +static struct t_name d_name = { i_val, o_val, o_val, OVERRIDE_RESET } + +// DATA_GET_PROTOTYPE - declares a function prototype for a DATA getter function +// t = data's type +// f_name = name for DATA getter function +#define DATA_GET_PROTOTYPE( t, f_name ) t f_name( void ) + +// DATA_GET - creates a getter function for a DATA +// t = data's type +// f_name = name for DATA getter function +// d_name = name of data's variable +#define DATA_GET( t, f_name, d_name ) \ +t f_name( void ) \ +{ \ + t result = d_name.data; \ + if ( OVERRIDE_KEY == d_name.override ) \ + { \ + result = d_name.ovData; \ + } \ + return result; \ +} + // **** VectorCAST Definitions **** #ifdef _VECTORCAST_ Index: App/Services/CommBuffers.h =================================================================== diff -u -ra87b6b9e253c6c0fcc84bca6f5de71959ce18bcc -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- App/Services/CommBuffers.h (.../CommBuffers.h) (revision a87b6b9e253c6c0fcc84bca6f5de71959ce18bcc) +++ App/Services/CommBuffers.h (.../CommBuffers.h) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -34,8 +34,6 @@ COMM_BUFFER_IN_CAN_DG_BROADCAST, COMM_BUFFER_IN_CAN_UI_2_HD, COMM_BUFFER_IN_CAN_UI_BROADCAST, - COMM_BUFFER_IN_FPGA, - COMM_BUFFER_OUT_FPGA, COMM_BUFFER_IN_DBG, COMM_BUFFER_OUT_DBG, NUM_OF_COMM_BUFFERS Index: App/Services/FPGA.c =================================================================== diff -u --- App/Services/FPGA.c (revision 0) +++ App/Services/FPGA.c (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -0,0 +1,311 @@ +/************************************************************************** + * + * Copyright (c) 2019-2019 Diality Inc. - All Rights Reserved. + * + * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN + * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. + * + * @file FPGA.c + * + * @date 21-Oct-2019 + * @author S. Nash + * + * @brief FPGA interface service module. Provides an interface to the FPGA. \n + * Various sensor readings are gathered and get functions provided for them. \n + * Various actuator settings are sent and set functions provided for them. + * + **************************************************************************/ + +#include // for memcpy() + +#include "sci.h" +#include "sys_dma.h" + +#include "Common.h" + +// ********** private definitions ********** + +#define FPGA_WRITE_CMD_BUFFER_LEN 16 +#define FPGA_READ_CMD_BUFFER_LEN 8 +#define FPGA_WRITE_RSP_BUFFER_LEN 10 +#define FPGA_READ_RSP_BUFFER_LEN 100 + +#define SCI2_RECEIVE_DMA_REQUEST 28 +#define SCI2_TRANSMIT_DMA_REQUEST 29 + +// FPGA Sensors Record +#pragma pack(push,1) +typedef struct +{ + U08 artBloodValveState; // arterial blood valve state + U08 venBloodValveState; // venous blood valve state +} FPGA_SENSORS_T; + +typedef struct +{ + U08 artBloodValveState; // arterial blood valve set state +} FPGA_ACTUATORS_T; +#pragma pack(pop) + +// ********** private data ********** + +// FPGA received sensor data from DMA bulk read +static FPGA_SENSORS_T fpgaSensors; + +// FPGA comm buffers +static U08 fpgaWriteCmdBuffer[FPGA_WRITE_CMD_BUFFER_LEN] = {1,2,3,4,5,6,7,8,0,0,0,0,0,0,0,0}; +static U08 fpgaReadCmdBuffer[FPGA_READ_CMD_BUFFER_LEN] = {0,0,0,0,0,0,0,0}; +static U08 fpgaWriteResponseBuffer[FPGA_WRITE_RSP_BUFFER_LEN] = {0,0,0,0,0,0,0,0,0,0}; +static U08 fpgaReadResponseBuffer[FPGA_READ_RSP_BUFFER_LEN]; + +// DMA control records +static g_dmaCTRL fpgaDMAWriteControlRecord; +static g_dmaCTRL fpgaDMAWriteRespControlRecord; +static g_dmaCTRL fpgaDMAReadControlRecord; +static g_dmaCTRL fpgaDMAReadRespControlRecord; + +// FPGA data + +U08 version; // FPGA version +U08 diagnostic; // FPGA diagnostic register + +DATA_DECL( TWO_WAY_STATE_T, BloodValveState, dataArterialBloodValveState, STATE_CLOSED, STATE_CLOSED ); + +// ********** private function prototypes ********** + +static void setupDMAForWriteCmd( U32 bytes2Transmit ); +static void startDMAWriteCmd( void ); +static void setupDMAForWriteResp( U32 bytes2Receive ); +static void startDMAReceiptOfWriteResp( void ); +static void setupDMAForReadCmd( U32 bytes2Transmit ); +static void startDMAReadCmd( void ); +static void setupDMAForReadResp( U32 bytes2Receive ); + +/************************************************************************* + * @brief initFPGA + * The initFPGA function initializes the FPGA module. + * @details + * Inputs : none + * Outputs : FPGA module initialized. + * @param none + * @return none + *************************************************************************/ +void initFPGA( void ) +{ + sciEnableLoopback( scilinREG, Digital_Lbk ); // TODO - for test only + + // enable interrupt notifications for FPGA serial port + //sciEnableNotification( scilinREG, SCI_TX_INT | SCI_RX_INT | SCI_OE_INT | SCI_FE_INT ); + //sciEnableNotification( scilinREG, SCI_RX_INT | SCI_OE_INT | SCI_FE_INT ); + sciEnableNotification( scilinREG, SCI_OE_INT | SCI_FE_INT ); + + // Enable DMA block transfer complete interrupts + dmaEnableInterrupt( DMA_CH0, BTC ); + dmaEnableInterrupt( DMA_CH2, BTC ); + // assign DMA channels to h/w DMA requests + dmaReqAssign( DMA_CH0, SCI2_RECEIVE_DMA_REQUEST ); + dmaReqAssign( DMA_CH2, SCI2_TRANSMIT_DMA_REQUEST ); + // set DMA channel priorities + dmaSetPriority( DMA_CH0, HIGHPRIORITY ); + dmaSetPriority( DMA_CH2, LOWPRIORITY ); + + // initialize FPGA DMA Write Control Record + fpgaDMAWriteControlRecord.PORTASGN = 4; // port B (only choice per datasheet) + fpgaDMAWriteControlRecord.DADD = (U32)(&(scilinREG->TD)); // dest. is SCI2 xmit register + fpgaDMAWriteControlRecord.SADD = (U32)fpgaWriteResponseBuffer; // transfer source address + fpgaDMAWriteControlRecord.CHCTRL = 0; // no chaining + fpgaDMAWriteControlRecord.ELCNT = 1; // frame is 1 element + fpgaDMAWriteControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known + fpgaDMAWriteControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + fpgaDMAWriteControlRecord.WRSIZE = ACCESS_8_BIT; // + fpgaDMAWriteControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer + fpgaDMAWriteControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed + fpgaDMAWriteControlRecord.ADDMODERD = ADDR_INC1; // source addressing mode is post-increment + fpgaDMAWriteControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off + fpgaDMAWriteControlRecord.ELSOFFSET = 0; // # of bytes to advance at source memory after each element + fpgaDMAWriteControlRecord.ELDOFFSET = 0; // not used + fpgaDMAWriteControlRecord.FRSOFFSET = 0; // # of bytes to advance at source memory after each frame + fpgaDMAWriteControlRecord.FRDOFFSET = 0; // not used + + // initialize FPGA DMA Write Response Control Record + fpgaDMAWriteRespControlRecord.PORTASGN = 4; // port B (only choice per datasheet) + fpgaDMAWriteRespControlRecord.SADD = (U32)(&(scilinREG->RD));// source is SCI2 recv register + fpgaDMAWriteRespControlRecord.DADD = (U32)fpgaWriteResponseBuffer; // transfer destination address + fpgaDMAWriteRespControlRecord.CHCTRL = 0; // no chaining + fpgaDMAWriteRespControlRecord.ELCNT = 1; // frame is 1 element + fpgaDMAWriteRespControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known + fpgaDMAWriteRespControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + fpgaDMAWriteRespControlRecord.WRSIZE = ACCESS_8_BIT; // + fpgaDMAWriteRespControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer + fpgaDMAWriteRespControlRecord.ADDMODERD = ADDR_FIXED; // source addressing mode is fixed + fpgaDMAWriteRespControlRecord.ADDMODEWR = ADDR_INC1; // dest. addressing mode is post-increment + fpgaDMAWriteRespControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off + fpgaDMAWriteRespControlRecord.ELDOFFSET = 0; // # of bytes to advance at destination memory after each element + fpgaDMAWriteRespControlRecord.ELSOFFSET = 0; // not used + fpgaDMAWriteRespControlRecord.FRDOFFSET = 0; // # of bytes to advance at destination memory after each frame + fpgaDMAWriteRespControlRecord.FRSOFFSET = 0; // not used + + // initialize FPGA DMA Read Control Record + fpgaDMAReadControlRecord.PORTASGN = 4; // port B (only choice per datasheet) + fpgaDMAReadControlRecord.DADD = (U32)(&(scilinREG->TD)); // dest. is SCI2 xmit register + fpgaDMAReadControlRecord.SADD = (U32)fpgaWriteResponseBuffer;// transfer source address + fpgaDMAReadControlRecord.CHCTRL = 0; // no chaining + fpgaDMAReadControlRecord.ELCNT = 1; // frame is 1 element + fpgaDMAReadControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known + fpgaDMAReadControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + fpgaDMAReadControlRecord.WRSIZE = ACCESS_8_BIT; // + fpgaDMAReadControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer + fpgaDMAReadControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed + fpgaDMAReadControlRecord.ADDMODERD = ADDR_INC1; // source addressing mode is post-increment + fpgaDMAReadControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off + fpgaDMAReadControlRecord.ELSOFFSET = 0; // # of bytes to advance at source memory after each element + fpgaDMAReadControlRecord.ELDOFFSET = 0; // not used + fpgaDMAReadControlRecord.FRSOFFSET = 0; // # of bytes to advance at source memory after each frame + fpgaDMAReadControlRecord.FRDOFFSET = 0; // not used + + // initialize FPGA DMA Read Response Control Record + fpgaDMAReadRespControlRecord.PORTASGN = 4; // port B (only choice per datasheet) + fpgaDMAReadRespControlRecord.SADD = (U32)(&(scilinREG->RD)); // source is SCI2 recv register + fpgaDMAReadRespControlRecord.DADD = (U32)fpgaWriteResponseBuffer; // transfer destination address + fpgaDMAReadRespControlRecord.CHCTRL = 0; // no chaining + fpgaDMAReadRespControlRecord.ELCNT = 1; // frame is 1 element + fpgaDMAReadRespControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known + fpgaDMAReadRespControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + fpgaDMAReadRespControlRecord.WRSIZE = ACCESS_8_BIT; // + fpgaDMAReadRespControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer + fpgaDMAReadRespControlRecord.ADDMODERD = ADDR_FIXED; // source addressing mode is fixed + fpgaDMAReadRespControlRecord.ADDMODEWR = ADDR_INC1; // dest. addressing mode is post-increment + fpgaDMAReadRespControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off + fpgaDMAReadRespControlRecord.ELDOFFSET = 0; // # of bytes to advance at destination memory after each element + fpgaDMAReadRespControlRecord.ELSOFFSET = 0; // not used + fpgaDMAReadRespControlRecord.FRDOFFSET = 0; // # of bytes to advance at destination memory after each frame + fpgaDMAReadRespControlRecord.FRSOFFSET = 0; // not used + + // TODO - this is a DMA xmit and recv via loopback test + setupDMAForWriteResp( 8 ); + startDMAReceiptOfWriteResp(); + setupDMAForWriteCmd( 8 ); + startDMAWriteCmd(); +} + +/************************************************************************* + * @brief execFPGA + * The execFPGA function manages data exchanges with the FPGA. + * @details + * Inputs : none + * Outputs : none + * @param none + * @return none + *************************************************************************/ +void execFPGA( void ) +{ + U08 x; + x = fpgaWriteResponseBuffer[0]; +} + + + + + +static void setupDMAForWriteCmd( U32 bytes2Transmit ) +{ + fpgaDMAWriteControlRecord.FRCNT = bytes2Transmit; +} + +static void startDMAWriteCmd( void ) +{ + dmaSetCtrlPacket( DMA_CH2, fpgaDMAWriteControlRecord ); + dmaSetChEnable( DMA_CH2, DMA_HW ); + scilinREG->SETINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ +} + +static void setupDMAForWriteResp( U32 bytes2Receive ) +{ + fpgaDMAWriteRespControlRecord.FRCNT = bytes2Receive; +} + +static void startDMAReceiptOfWriteResp( void ) +{ + dmaSetCtrlPacket( DMA_CH0, fpgaDMAWriteRespControlRecord ); + dmaSetChEnable( DMA_CH0, DMA_HW ); + scilinREG->SETINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ + scilinREG->SETINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ +} + +static void setupDMAForReadCmd( U32 bytes2Transmit ) +{ + fpgaDMAReadControlRecord.FRCNT = bytes2Transmit; +} + +static void startDMAReadCmd( void ) +{ + dmaSetCtrlPacket( DMA_CH2, fpgaDMAReadControlRecord ); + dmaSetChEnable( DMA_CH2, DMA_HW ); + scilinREG->SETINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ +} + +static void setupDMAForReadResp( U32 bytes2Receive ) +{ + fpgaDMAReadRespControlRecord.FRCNT = bytes2Receive; +} + +static void startDMAReceiptOfReadResp( void ) +{ + dmaSetCtrlPacket( DMA_CH0, fpgaDMAReadRespControlRecord ); + dmaSetChEnable( DMA_CH0, DMA_HW ); + scilinREG->SETINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ + scilinREG->SETINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ +} + + + +U08 getFPGAVersion( void ) +{ + +} + +U08 getFPGADiag( void ) +{ + U08 result = 0; + + return result; +} + +void setFPGADiag( void ) +{ + +} + +DATA_GET( TWO_WAY_STATE_T, getArterialBloodValveState, dataArterialBloodValveState ) + +BOOL dialinSetArterialBloodValveStateOverride( TWO_WAY_STATE_T state ) +{ + BOOL result = FALSE; + + // verify dialin login successfully completed before executing override + if ( 1 ) // TODO - call function to check login + { + result = TRUE; + dataArterialBloodValveState.ovData = state; + dataArterialBloodValveState.override = OVERRIDE_KEY; + } + + return result; +} + +BOOL dialinResetArterialBloodValveStateOverride( void ) +{ + BOOL result = FALSE; + + // verify dialin login successfully completed before executing override reset + if ( 1 ) // TODO - call function to check login + { + result = TRUE; + dataArterialBloodValveState.override = OVERRIDE_RESET; + dataArterialBloodValveState.ovData = dataArterialBloodValveState.ovInitData; + } + + return result; +} + + Index: App/Services/FPGA.h =================================================================== diff -u --- App/Services/FPGA.h (revision 0) +++ App/Services/FPGA.h (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -0,0 +1,39 @@ +/************************************************************************** + * + * Copyright (c) 2019-2019 Diality Inc. - All Rights Reserved. + * + * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN + * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. + * + * @file FPGA.h + * + * @date 21-Oct-2019 + * @author S. Nash + * + * @brief header file for FPGA Interface service . + * + **************************************************************************/ + +#ifndef __FPGA_H__ +#define __FPGA_H__ + +#include "Common.h" + +// ********** public definitions ********** + + +// ********** public function prototypes ********** + +void initFPGA( void ); +void execFPGA( void ); + +U08 getFPGAVersion( void ); +U08 getFPGADiag( void ); +void setFPGADiag( void ); + +DATA_GET_PROTOTYPE( TWO_WAY_STATE_T, getArterialBloodValveState ); + +BOOL dialinSetArterialBloodValveStateOverride( TWO_WAY_STATE_T state ); +BOOL dialinResetArterialBloodValveStateOverride( void ); + +#endif Index: App/Services/SystemComm.c =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- App/Services/SystemComm.c (.../SystemComm.c) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ App/Services/SystemComm.c (.../SystemComm.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -16,10 +16,11 @@ * **************************************************************************/ -#include #include // for memcpy() #include "can.h" +#include "sci.h" +#include "sys_dma.h" #include "Common.h" #include "MsgQueues.h" @@ -35,6 +36,9 @@ #define NUM_OF_CAN_OUT_BUFFERS 4 // # of CAN buffers for transmit #define NUM_OF_CAN_IN_BUFFERS 6 // # of CAN buffers for receiving +#define SCI1_RECEIVE_DMA_REQUEST 30 +#define SCI1_TRANSMIT_DMA_REQUEST 31 + // ********** private data ********** const COMM_BUFFER_T CAN_OUT_BUFFERS[NUM_OF_CAN_OUT_BUFFERS] = @@ -55,16 +59,24 @@ COMM_BUFFER_IN_CAN_UI_BROADCAST }; +static U08 pcXmitPacket[PC_MESSAGE_PACKET_SIZE]; +static U08 pcRecvPacket[PC_MESSAGE_PACKET_SIZE]; + +// DMA control records +static g_dmaCTRL pcDMAXmitControlRecord; +static g_dmaCTRL pcDMARecvControlRecord; + // ********** private function prototypes ********** static void handleCANPacketReceivedInt( CAN_MESSAGE_BOX_T srcCANBox ); static void handleCANXmitCompleteInt( void ); +static void handleUARTXmitCompleteInt( void ); static BOOL isCANBoxForXmit( CAN_MESSAGE_BOX_T srcCANBox ); static BOOL isCANBoxForRecv( CAN_MESSAGE_BOX_T srcCANBox ); static COMM_BUFFER_T findNextHighestPriorityCANPacketToTransmit( void ); static void transmitNextCANPacket( void ); -static void transmitPendingUARTData( void ); +static void transmitNextUARTPacket( void ); static void processIncomingData( void ); static U32 parseMessageFromBuffer( U08 *data, U32 len ); @@ -83,7 +95,53 @@ *************************************************************************/ void initSystemComm( void ) { - // currently nothing to initialize + sciEnableLoopback( sciREG, Digital_Lbk ); // TODO - for test only + + // Enable DMA block transfer complete interrupts + dmaEnableInterrupt( DMA_CH1, BTC ); + dmaEnableInterrupt( DMA_CH3, BTC ); + // assign DMA channels to h/w DMA requests + dmaReqAssign( DMA_CH1, SCI1_RECEIVE_DMA_REQUEST ); + dmaReqAssign( DMA_CH3, SCI1_TRANSMIT_DMA_REQUEST ); + // set DMA channel priorities + dmaSetPriority( DMA_CH1, HIGHPRIORITY ); + dmaSetPriority( DMA_CH3, LOWPRIORITY ); + + // initialize PC DMA Transmit Control Record + pcDMAXmitControlRecord.PORTASGN = 4; // port B (only choice per datasheet) + pcDMAXmitControlRecord.DADD = (U32)(&(sciREG->TD)); // dest. is SCI2 xmit register + pcDMAXmitControlRecord.SADD = (U32)pcXmitPacket; // source + pcDMAXmitControlRecord.CHCTRL = 0; // no chaining + pcDMAXmitControlRecord.ELCNT = 1; // frame is 1 element + pcDMAXmitControlRecord.FRCNT = PC_MESSAGE_PACKET_SIZE; // block is 8 frames + pcDMAXmitControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + pcDMAXmitControlRecord.WRSIZE = ACCESS_8_BIT; // + pcDMAXmitControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer + pcDMAXmitControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed + pcDMAXmitControlRecord.ADDMODERD = ADDR_INC1; // source addressing mode is post-increment + pcDMAXmitControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off + pcDMAXmitControlRecord.ELSOFFSET = 0; // # of bytes to advance at source memory after each element + pcDMAXmitControlRecord.ELDOFFSET = 0; // not used + pcDMAXmitControlRecord.FRSOFFSET = 0; // # of bytes to advance at source memory after each frame + pcDMAXmitControlRecord.FRDOFFSET = 0; // not used + + // initialize PC DMA Receipt Control Record + pcDMARecvControlRecord.PORTASGN = 4; // port B (only choice per datasheet) + pcDMARecvControlRecord.SADD = (U32)(&(sciREG->RD));// source is SCI2 recv register + pcDMARecvControlRecord.DADD = (U32)pcRecvPacket; // transfer destination address + pcDMARecvControlRecord.CHCTRL = 0; // no chaining + pcDMARecvControlRecord.ELCNT = 1; // frame is 1 element + pcDMARecvControlRecord.FRCNT = PC_MESSAGE_PACKET_SIZE;// block is 8 frames + pcDMARecvControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte + pcDMARecvControlRecord.WRSIZE = ACCESS_8_BIT; // + pcDMARecvControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer + pcDMARecvControlRecord.ADDMODERD = ADDR_FIXED; // source addressing mode is fixed + pcDMARecvControlRecord.ADDMODEWR = ADDR_INC1; // dest. addressing mode is post-increment + pcDMARecvControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off + pcDMARecvControlRecord.ELDOFFSET = 0; // # of bytes to advance at destination memory after each element + pcDMARecvControlRecord.ELSOFFSET = 0; // not used + pcDMARecvControlRecord.FRDOFFSET = 0; // # of bytes to advance at destination memory after each frame + pcDMARecvControlRecord.FRSOFFSET = 0; // not used } /************************************************************************* @@ -125,11 +183,26 @@ // TODO - check to see if UART transmitter is idle first if ( 1 ) // for now, assume it's idle { - transmitPendingUARTData(); + transmitNextUARTPacket(); } } /************************************************************************* + * @brief canMessageNotification + * The canMessageNotification function handles CAN message notifications. + * @details + * Inputs : none + * Outputs : CAN message notification handled. + * @param node : which CAN controller + * @param messageBox : which message box triggered the message notification + * @return none + *************************************************************************/ +void canMessageNotification(canBASE_t *node, uint32 messageBox) +{ + handleCANMsgInterrupt( (CAN_MESSAGE_BOX_T)messageBox ); +} + +/************************************************************************* * @brief handleCANMsgInterrupt * The handleCANMsgInterrupt function handles a CAN message interrupt. \n * This may have occurred because a CAN packet transmission has completed \n @@ -159,6 +232,23 @@ } } +void handleUARTMsgRecvPacketInterrupt( void ) +{ + // buffer received packet + addToCommBuffer( COMM_BUFFER_IN_DBG, pcRecvPacket, PC_MESSAGE_PACKET_SIZE ); + // prepare to receive next packet + dmaSetCtrlPacket( DMA_CH1, pcDMARecvControlRecord ); + dmaSetChEnable( DMA_CH1, DMA_HW ); + sciREG->SETINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ + sciREG->SETINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ +} + +void handleUARTMsgXmitPacketInterrupt( void ) +{ + handleUARTXmitCompleteInt(); +} + + /************************************************************************* * @brief isCANBoxForXmit * The isCANBoxForXmit function determines whether a given CAN message box \n @@ -236,6 +326,11 @@ transmitNextCANPacket(); } +static void handleUARTXmitCompleteInt( void ) +{ + transmitNextUARTPacket(); +} + /************************************************************************* * @brief findNextHighestPriorityCANPacketToTransmit * The findNextHighestPriorityCANPacketToTransmit function gets the next \n @@ -286,6 +381,7 @@ U32 dataSize = getFromCommBuffer( buffer, data, CAN_MESSAGE_CARGO_SIZE ); CAN_MESSAGE_BOX_T mBox = buffer; // CAN message boxes and comm buffers are aligned + // if there's another CAN packet to send, send it if ( dataSize == CAN_MESSAGE_CARGO_SIZE ) { canTransmit( canREG1, mBox, data ); @@ -294,18 +390,27 @@ } /************************************************************************* - * @brief transmitPendingUARTData - * The transmitPendingUARTData function sets up and initiates a DMA transmit \n - * of any data currently pending transmit via UART. + * @brief transmitNextUARTPacket + * The transmitNextUARTPacket function sets up and initiates a DMA transmit \n + * of the next packet pending transmit (if any) via UART. * @details * Inputs : Output UART Comm Buffer(s) * Outputs : UART DMA transmit initiated. * @param msg : none * @return none *************************************************************************/ -static void transmitPendingUARTData( void ) +static void transmitNextUARTPacket( void ) { - // TODO - implement + U08 data[PC_MESSAGE_PACKET_SIZE]; + U32 dataSize = getFromCommBuffer( COMM_BUFFER_OUT_DBG, data, PC_MESSAGE_PACKET_SIZE ); + + // if there's another UART packet to send, send it + if ( dataSize == PC_MESSAGE_PACKET_SIZE ) + { + dmaSetCtrlPacket( DMA_CH3, pcDMAXmitControlRecord ); + dmaSetChEnable( DMA_CH3, DMA_HW ); + sciREG->SETINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ + } } Index: App/Services/SystemComm.h =================================================================== diff -u -r29f1ba03faefd982327916590818a260a3e4aa48 -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- App/Services/SystemComm.h (.../SystemComm.h) (revision 29f1ba03faefd982327916590818a260a3e4aa48) +++ App/Services/SystemComm.h (.../SystemComm.h) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -25,6 +25,7 @@ #define MESSAGE_SYNC_BYTE 0xA5 #define CAN_MESSAGE_CARGO_SIZE 8 +#define PC_MESSAGE_PACKET_SIZE 8 typedef COMM_BUFFER_T CAN_MESSAGE_BOX_T; // the first 10 comm buffers align with the 10 active CAN message boxes @@ -34,5 +35,7 @@ void execSystemCommRx( void ); void execSystemCommTx( void ); void handleCANMsgInterrupt( CAN_MESSAGE_BOX_T srcCANBox ); +void handleUARTMsgRecvPacketInterrupt( void ); +void handleUARTMsgXmitPacketInterrupt( void ); #endif Index: App/Tasks/TaskPriority.c =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- App/Tasks/TaskPriority.c (.../TaskPriority.c) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ App/Tasks/TaskPriority.c (.../TaskPriority.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -17,6 +17,7 @@ #include #include "gio.h" +#include "FPGA.h" #include "WatchdogMgmt.h" #include "TaskPriority.h" @@ -30,6 +31,9 @@ *************************************************************************/ void taskPriority( void ) { + // 1st pass for FPGA + execFPGA(); + // monitor and process buttons execButtons(); Index: Debug/ccsObjs.opt =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- Debug/ccsObjs.opt (.../ccsObjs.opt) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ Debug/ccsObjs.opt (.../ccsObjs.opt) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -1 +1 @@ -"./irqDispatch_a.obj" "./irqDispatch_c.obj" "./App/Controllers/AlarmLamp.obj" "./App/Controllers/Buttons.obj" "./App/Drivers/CPLD.obj" "./App/Drivers/SafetyShutdown.obj" "./App/Modes/ModeFault.obj" "./App/Modes/ModeInitPOST.obj" "./App/Modes/ModeOpParams.obj" "./App/Modes/ModePostTreat.obj" "./App/Modes/ModePreTreat.obj" "./App/Modes/ModePrescription.obj" "./App/Modes/ModeService.obj" "./App/Modes/ModeStandby.obj" "./App/Modes/ModeTreatment.obj" "./App/Modes/OperationModes.obj" "./App/Services/CommBuffers.obj" "./App/Services/MsgQueues.obj" "./App/Services/SystemComm.obj" "./App/Services/SystemCommMessages.obj" "./App/Services/Timers.obj" "./App/Services/WatchdogMgmt.obj" "./App/Tasks/TaskBG.obj" "./App/Tasks/TaskGeneral.obj" "./App/Tasks/TaskPriority.obj" "./App/Tasks/TaskTimer.obj" "./source/can.obj" "./source/dabort.obj" "./source/errata_SSWF021_45.obj" "./source/esm.obj" "./source/gio.obj" "./source/lin.obj" "./source/mibspi.obj" "./source/notification.obj" "./source/pinmux.obj" "./source/rti.obj" "./source/sci.obj" "./source/sys_core.obj" "./source/sys_dma.obj" "./source/sys_intvecs.obj" "./source/sys_main.obj" "./source/sys_mpu.obj" "./source/sys_pcr.obj" "./source/sys_phantom.obj" "./source/sys_pmm.obj" "./source/sys_pmu.obj" "./source/sys_selftest.obj" "./source/sys_startup.obj" "./source/sys_vim.obj" "./source/system.obj" "../source/sys_link.cmd" -lrtsv7R4_T_le_v3D16_eabi.lib \ No newline at end of file +"./irqDispatch_a.obj" "./irqDispatch_c.obj" "./App/Controllers/AlarmLamp.obj" "./App/Controllers/Buttons.obj" "./App/Drivers/CPLD.obj" "./App/Drivers/SafetyShutdown.obj" "./App/Modes/ModeFault.obj" "./App/Modes/ModeInitPOST.obj" "./App/Modes/ModeOpParams.obj" "./App/Modes/ModePostTreat.obj" "./App/Modes/ModePreTreat.obj" "./App/Modes/ModePrescription.obj" "./App/Modes/ModeService.obj" "./App/Modes/ModeStandby.obj" "./App/Modes/ModeTreatment.obj" "./App/Modes/OperationModes.obj" "./App/Services/CommBuffers.obj" "./App/Services/FPGA.obj" "./App/Services/MsgQueues.obj" "./App/Services/SystemComm.obj" "./App/Services/SystemCommMessages.obj" "./App/Services/Timers.obj" "./App/Services/WatchdogMgmt.obj" "./App/Tasks/TaskBG.obj" "./App/Tasks/TaskGeneral.obj" "./App/Tasks/TaskPriority.obj" "./App/Tasks/TaskTimer.obj" "./source/can.obj" "./source/dabort.obj" "./source/errata_SSWF021_45.obj" "./source/esm.obj" "./source/gio.obj" "./source/lin.obj" "./source/mibspi.obj" "./source/notification.obj" "./source/pinmux.obj" "./source/rti.obj" "./source/sci.obj" "./source/sys_core.obj" "./source/sys_dma.obj" "./source/sys_intvecs.obj" "./source/sys_main.obj" "./source/sys_mpu.obj" "./source/sys_pcr.obj" "./source/sys_phantom.obj" "./source/sys_pmm.obj" "./source/sys_pmu.obj" "./source/sys_selftest.obj" "./source/sys_startup.obj" "./source/sys_vim.obj" "./source/system.obj" "../source/sys_link.cmd" -lrtsv7R4_T_le_v3D16_eabi.lib \ No newline at end of file Index: Debug/makefile =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- Debug/makefile (.../makefile) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ Debug/makefile (.../makefile) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -25,6 +25,7 @@ "./App/Modes/ModeTreatment.obj" \ "./App/Modes/OperationModes.obj" \ "./App/Services/CommBuffers.obj" \ +"./App/Services/FPGA.obj" \ "./App/Services/MsgQueues.obj" \ "./App/Services/SystemComm.obj" \ "./App/Services/SystemCommMessages.obj" \ @@ -213,10 +214,10 @@ # Other Targets clean: -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) - -$(RM) "irqDispatch_a.obj" "irqDispatch_c.obj" "App/Controllers/AlarmLamp.obj" "App/Controllers/Buttons.obj" "App/Drivers/CPLD.obj" "App/Drivers/SafetyShutdown.obj" "App/Modes/ModeFault.obj" "App/Modes/ModeInitPOST.obj" "App/Modes/ModeOpParams.obj" "App/Modes/ModePostTreat.obj" "App/Modes/ModePreTreat.obj" "App/Modes/ModePrescription.obj" "App/Modes/ModeService.obj" "App/Modes/ModeStandby.obj" "App/Modes/ModeTreatment.obj" "App/Modes/OperationModes.obj" "App/Services/CommBuffers.obj" "App/Services/MsgQueues.obj" "App/Services/SystemComm.obj" "App/Services/SystemCommMessages.obj" "App/Services/Timers.obj" "App/Services/WatchdogMgmt.obj" "App/Tasks/TaskBG.obj" "App/Tasks/TaskGeneral.obj" "App/Tasks/TaskPriority.obj" "App/Tasks/TaskTimer.obj" "source/can.obj" "source/dabort.obj" "source/errata_SSWF021_45.obj" "source/esm.obj" "source/gio.obj" "source/lin.obj" "source/mibspi.obj" "source/notification.obj" "source/pinmux.obj" "source/rti.obj" "source/sci.obj" "source/sys_core.obj" "source/sys_dma.obj" - -$(RM) "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_pcr.obj" "source/sys_phantom.obj" "source/sys_pmm.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/sys_vim.obj" "source/system.obj" - -$(RM) "irqDispatch_c.d" "App/Controllers/AlarmLamp.d" "App/Controllers/Buttons.d" "App/Drivers/CPLD.d" "App/Drivers/SafetyShutdown.d" "App/Modes/ModeFault.d" "App/Modes/ModeInitPOST.d" "App/Modes/ModeOpParams.d" "App/Modes/ModePostTreat.d" "App/Modes/ModePreTreat.d" "App/Modes/ModePrescription.d" "App/Modes/ModeService.d" "App/Modes/ModeStandby.d" "App/Modes/ModeTreatment.d" "App/Modes/OperationModes.d" "App/Services/CommBuffers.d" "App/Services/MsgQueues.d" "App/Services/SystemComm.d" "App/Services/SystemCommMessages.d" "App/Services/Timers.d" "App/Services/WatchdogMgmt.d" "App/Tasks/TaskBG.d" "App/Tasks/TaskGeneral.d" "App/Tasks/TaskPriority.d" "App/Tasks/TaskTimer.d" "source/can.d" "source/errata_SSWF021_45.d" "source/esm.d" "source/gio.d" "source/lin.d" "source/mibspi.d" "source/notification.d" "source/pinmux.d" "source/rti.d" "source/sci.d" "source/sys_dma.d" "source/sys_main.d" "source/sys_pcr.d" "source/sys_phantom.d" "source/sys_pmm.d" "source/sys_selftest.d" "source/sys_startup.d" "source/sys_vim.d" - -$(RM) "source/system.d" + -$(RM) "irqDispatch_a.obj" "irqDispatch_c.obj" "App/Controllers/AlarmLamp.obj" "App/Controllers/Buttons.obj" "App/Drivers/CPLD.obj" "App/Drivers/SafetyShutdown.obj" "App/Modes/ModeFault.obj" "App/Modes/ModeInitPOST.obj" "App/Modes/ModeOpParams.obj" "App/Modes/ModePostTreat.obj" "App/Modes/ModePreTreat.obj" "App/Modes/ModePrescription.obj" "App/Modes/ModeService.obj" "App/Modes/ModeStandby.obj" "App/Modes/ModeTreatment.obj" "App/Modes/OperationModes.obj" "App/Services/CommBuffers.obj" "App/Services/FPGA.obj" "App/Services/MsgQueues.obj" "App/Services/SystemComm.obj" "App/Services/SystemCommMessages.obj" "App/Services/Timers.obj" "App/Services/WatchdogMgmt.obj" "App/Tasks/TaskBG.obj" "App/Tasks/TaskGeneral.obj" "App/Tasks/TaskPriority.obj" "App/Tasks/TaskTimer.obj" "source/can.obj" "source/dabort.obj" "source/errata_SSWF021_45.obj" "source/esm.obj" "source/gio.obj" "source/lin.obj" "source/mibspi.obj" "source/notification.obj" "source/pinmux.obj" "source/rti.obj" "source/sci.obj" "source/sys_core.obj" + -$(RM) "source/sys_dma.obj" "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_pcr.obj" "source/sys_phantom.obj" "source/sys_pmm.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/sys_vim.obj" "source/system.obj" + -$(RM) "irqDispatch_c.d" "App/Controllers/AlarmLamp.d" "App/Controllers/Buttons.d" "App/Drivers/CPLD.d" "App/Drivers/SafetyShutdown.d" "App/Modes/ModeFault.d" "App/Modes/ModeInitPOST.d" "App/Modes/ModeOpParams.d" "App/Modes/ModePostTreat.d" "App/Modes/ModePreTreat.d" "App/Modes/ModePrescription.d" "App/Modes/ModeService.d" "App/Modes/ModeStandby.d" "App/Modes/ModeTreatment.d" "App/Modes/OperationModes.d" "App/Services/CommBuffers.d" "App/Services/FPGA.d" "App/Services/MsgQueues.d" "App/Services/SystemComm.d" "App/Services/SystemCommMessages.d" "App/Services/Timers.d" "App/Services/WatchdogMgmt.d" "App/Tasks/TaskBG.d" "App/Tasks/TaskGeneral.d" "App/Tasks/TaskPriority.d" "App/Tasks/TaskTimer.d" "source/can.d" "source/errata_SSWF021_45.d" "source/esm.d" "source/gio.d" "source/lin.d" "source/mibspi.d" "source/notification.d" "source/pinmux.d" "source/rti.d" "source/sci.d" "source/sys_dma.d" "source/sys_main.d" "source/sys_pcr.d" "source/sys_phantom.d" "source/sys_pmm.d" "source/sys_selftest.d" "source/sys_startup.d" + -$(RM) "source/sys_vim.d" "source/system.d" -$(RM) "irqDispatch_a.d" "source/dabort.d" "source/sys_core.d" "source/sys_intvecs.d" "source/sys_mpu.d" "source/sys_pmu.d" -@echo 'Finished clean' -@echo ' ' Index: HD.dil =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- HD.dil (.../HD.dil) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ HD.dil (.../HD.dil) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -1,4 +1,4 @@ -# RM46L852PGE 10/18/19 14:00:36 +# RM46L852PGE 10/21/19 18:51:54 # ARCH=RM46L852PGE # @@ -208,7 +208,7 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=1 @@ -369,11 +369,11 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=FIQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=1 @@ -509,7 +509,7 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0x0843ffff DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=FIQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=0 @@ -806,7 +806,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=FIQ DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=103.335 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0010 @@ -856,7 +856,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00002000 DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=0 @@ -951,7 +951,7 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803ffff DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=FIQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=FIQ @@ -974,7 +974,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_RAMPARITYCHECK_ENA.VALUE=1 @@ -1003,7 +1003,7 @@ DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_DP_PBISTCHECK_ENA.VALUE=0x00000400 @@ -1062,7 +1062,7 @@ DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=_svc DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_RAMPARITYCHECK_ENA.VALUE=0 @@ -1354,7 +1354,7 @@ DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_LEVEL.VALUE=0 -DRIVER.ESM.VAR.ESM_LOW_TIME.VALUE=148.945 +DRIVER.ESM.VAR.ESM_LOW_TIME.VALUE=158.552 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_ENABLE.VALUE=0 @@ -1390,7 +1390,7 @@ DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_INT_LEVEL.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_INT_LEVEL.VALUE=0 -DRIVER.ESM.VAR.ESM_VCLK_FREQ.VALUE=110 +DRIVER.ESM.VAR.ESM_VCLK_FREQ.VALUE=103.335 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_ENABLE.VALUE=0 @@ -1673,7 +1673,7 @@ DRIVER.SCI.VAR.SCI_PORT_BIT2_PULL.VALUE=2 DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DIR.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT0_DIR.VALUE=0 -DRIVER.SCI.VAR.SCI_ACTUALBAUDRATE.VALUE=115329 +DRIVER.SCI.VAR.SCI_ACTUALBAUDRATE.VALUE=922634 DRIVER.SCI.VAR.SCI_EVENPARITY.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_FUN.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DIR.VALUE=1 @@ -1709,17 +1709,17 @@ DRIVER.SCI.VAR.SCI_FEINTENA.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DOUT.VALUE=0 DRIVER.SCI.VAR.SCI_OEINTLVL.VALUE=0 -DRIVER.SCI.VAR.SCI_TXINTENA.VALUE=1 +DRIVER.SCI.VAR.SCI_TXINTENA.VALUE=0 DRIVER.SCI.VAR.SCILIN_PARITYENA.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DOUT.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT0_DOUT.VALUE=0 -DRIVER.SCI.VAR.SCI_BAUDRATE.VALUE=115200 +DRIVER.SCI.VAR.SCI_BAUDRATE.VALUE=921600 DRIVER.SCI.VAR.SCILIN_BREAKINTLVL.VALUE=0 DRIVER.SCI.VAR.SCI_WAKEINTLVL.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PULDIS.VALUE=0 DRIVER.SCI.VAR.SCI_BREAKINTLVL.VALUE=0 DRIVER.SCI.VAR.SCI_STOPBITS.VALUE=1 -DRIVER.SCI.VAR.SCI_RXINTENA.VALUE=1 +DRIVER.SCI.VAR.SCI_RXINTENA.VALUE=0 DRIVER.SCI.VAR.SCI_FEINTLVL.VALUE=0 DRIVER.SCI.VAR.SCILIN_EVENPARITY.VALUE=0 DRIVER.SCI.VAR.SCI_TXINTLVL.VALUE=0 @@ -1734,7 +1734,7 @@ DRIVER.SCI.VAR.SCILIN_BASE.VALUE=0xFFF7E400 DRIVER.SCI.VAR.SCI_RXINTLVL.VALUE=0 DRIVER.SCI.VAR.SCILIN_FEINTENA.VALUE=1 -DRIVER.SCI.VAR.SCI_PRESCALE.VALUE=55 +DRIVER.SCI.VAR.SCI_PRESCALE.VALUE=6 DRIVER.SCI.VAR.SCILIN_OEINTLVL.VALUE=0 DRIVER.SCI.VAR.SCILIN_TXINTENA.VALUE=1 DRIVER.SCI.VAR.SCI_PORT_BIT2_PULDIS.VALUE=0 @@ -7090,7 +7090,7 @@ DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792 DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00 DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0 -DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=220.00 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=206.67 DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0 DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5 @@ -7104,7 +7104,7 @@ DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1 DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0 -DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=544500 +DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=511508 DRIVER.PINMUX.VAR.DMA_EIDXS_28.VALUE=0 DRIVER.PINMUX.VAR.DMA_FIDXD_20.VALUE=0 DRIVER.PINMUX.VAR.DMA_FIDXD_12.VALUE=0 Index: HD.hcg =================================================================== diff -u -rad8ad611c910747eef92336a30b6520a83409532 -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- HD.hcg (.../HD.hcg) (revision ad8ad611c910747eef92336a30b6520a83409532) +++ HD.hcg (.../HD.hcg) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -237,8 +237,7 @@ lin.h - lin.c - + reg_mibspi.h @@ -520,7 +519,7 @@ include\lin.h - source\lin.c + Index: include/sci.h =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- include/sci.h (.../sci.h) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ include/sci.h (.../sci.h) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -133,12 +133,12 @@ #define SCI_SETINT_CONFIGVALUE ((uint32)((uint32)1U << 26U) \ |(uint32)((uint32)1U << 25U) \ |(uint32)((uint32)0U << 24U) \ - |(uint32)((uint32)1U << 9U) \ + |(uint32)((uint32)0U << 9U) \ |(uint32)((uint32)0U << 1U) \ |(uint32)((uint32)0U << 0U)) #define SCI_FORMAT_CONFIGVALUE (8U - 1U) -#define SCI_BRS_CONFIGVALUE (55U) +#define SCI_BRS_CONFIGVALUE (6U) #define SCI_PIO0_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)1U << 1U)) #define SCI_PIO1_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)0U << 1U)) #define SCI_PIO6_CONFIGVALUE ((uint32)((uint32)0U << 2U ) | (uint32)((uint32)0U << 1U)) Index: include/sys_vim.h =================================================================== diff -u -r29f1ba03faefd982327916590818a260a3e4aa48 -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- include/sys_vim.h (.../sys_vim.h) (revision 29f1ba03faefd982327916590818a260a3e4aa48) +++ include/sys_vim.h (.../sys_vim.h) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -93,8 +93,10 @@ extern void rtiCompare0Interrupt(void); extern void rtiCompare1Interrupt(void); extern void rtiCompare3Interrupt(void); +extern void linHighLevelInterrupt(void); extern void can1HighLevelInterrupt(void); -extern void can1LowLevelInterrupt(void); +extern void dmaBTCAInterrupt(void); +extern void sciHighLevelInterrupt(void); /* USER CODE BEGIN (3) */ /* USER CODE END */ @@ -140,7 +142,7 @@ | (uint32)((uint32)SYS_IRQ << 10U)\ | (uint32)((uint32)SYS_IRQ << 11U)\ | (uint32)((uint32)SYS_IRQ << 12U)\ - | (uint32)((uint32)SYS_IRQ << 13U)\ + | (uint32)((uint32)SYS_FIQ << 13U)\ | (uint32)((uint32)SYS_IRQ << 14U)\ | (uint32)((uint32)SYS_IRQ << 15U)\ | (uint32)((uint32)SYS_FIQ << 16U)\ @@ -168,7 +170,7 @@ | (uint32)((uint32)SYS_IRQ << 5U)\ | (uint32)((uint32)SYS_IRQ << 6U)\ | (uint32)((uint32)SYS_IRQ << 7U)\ - | (uint32)((uint32)SYS_IRQ << 8U)\ + | (uint32)((uint32)SYS_FIQ << 8U)\ | (uint32)((uint32)SYS_IRQ << 9U)\ | (uint32)((uint32)SYS_IRQ << 10U)\ | (uint32)((uint32)SYS_IRQ << 11U)\ @@ -193,7 +195,7 @@ | (uint32)((uint32)SYS_IRQ << 30U)\ | (uint32)((uint32)SYS_IRQ << 31U)) -#define VIM_FIRQPR2_CONFIGVALUE ( (uint32)((uint32)SYS_IRQ << 0U)\ +#define VIM_FIRQPR2_CONFIGVALUE ( (uint32)((uint32)SYS_FIQ << 0U)\ | (uint32)((uint32)SYS_IRQ << 1U)\ | (uint32)((uint32)SYS_IRQ << 2U)\ | (uint32)((uint32)SYS_IRQ << 3U)\ @@ -272,7 +274,7 @@ | (uint32)((uint32)0U << 10U)\ | (uint32)((uint32)0U << 11U)\ | (uint32)((uint32)0U << 12U)\ - | (uint32)((uint32)0U << 13U)\ + | (uint32)((uint32)1U << 13U)\ | (uint32)((uint32)0U << 14U)\ | (uint32)((uint32)0U << 15U)\ | (uint32)((uint32)1U << 16U)\ @@ -288,7 +290,7 @@ | (uint32)((uint32)0U << 26U)\ | (uint32)((uint32)0U << 27U)\ | (uint32)((uint32)0U << 28U)\ - | (uint32)((uint32)1U << 29U)\ + | (uint32)((uint32)0U << 29U)\ | (uint32)((uint32)0U << 30U)\ | (uint32)((uint32)0U << 31U)) @@ -300,7 +302,7 @@ | (uint32)((uint32)0U << 5U)\ | (uint32)((uint32)0U << 6U)\ | (uint32)((uint32)0U << 7U)\ - | (uint32)((uint32)0U << 8U)\ + | (uint32)((uint32)1U << 8U)\ | (uint32)((uint32)0U << 9U)\ | (uint32)((uint32)0U << 10U)\ | (uint32)((uint32)0U << 11U)\ @@ -325,7 +327,7 @@ | (uint32)((uint32)0U << 30U)\ | (uint32)((uint32)0U << 31U)) -#define VIM_REQMASKSET2_CONFIGVALUE ( (uint32)((uint32)0U << 0U)\ +#define VIM_REQMASKSET2_CONFIGVALUE ( (uint32)((uint32)1U << 0U)\ | (uint32)((uint32)0U << 1U)\ | (uint32)((uint32)0U << 2U)\ | (uint32)((uint32)0U << 3U)\ Index: source/can.c =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- source/can.c (.../can.c) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ source/can.c (.../can.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -1601,49 +1601,8 @@ } -/* USER CODE BEGIN (43) */ -/* USER CODE END */ -/** @fn void can1LowLevelInterrupt(void) -* @brief CAN1 Level 1 Interrupt Handler -*/ -#pragma CODE_STATE(can1LowLevelInterrupt, 32) -#pragma INTERRUPT(can1LowLevelInterrupt, FIQ) -/* SourceId : CAN_SourceId_021 */ -/* DesignId : CAN_DesignId_019 */ -/* Requirements : HL_SR221, HL_SR223 */ -void can1LowLevelInterrupt(void) -{ - uint32 messageBox = canREG1->INT >> 16U; -/* USER CODE BEGIN (44) */ -/* USER CODE END */ - /** - Setup IF1 for clear pending interrupt flag */ - /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG1->IF1STAT & 0x80U) ==0x80U) - { - } /* Wait */ - canREG1->IF1CMD = 0x08U; - /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ - canREG1->IF1NO = (uint8) messageBox; - - /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG1->IF1STAT & 0x80U) ==0x80U) - { - } /* Wait */ - canREG1->IF1CMD = 0x87U; - - canMessageNotification(canREG1, messageBox); - -/* USER CODE BEGIN (45) */ -/* USER CODE END */ - -} - - - - - Index: source/sci.c =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- source/sci.c (.../sci.c) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ source/sci.c (.../sci.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -96,7 +96,7 @@ | (uint32)((uint32)1U << 1U); /* asynchronous timing mode */ /** - set baudrate */ - sciREG->BRS = 55U; /* baudrate */ + sciREG->BRS = 6U; /* baudrate */ /** - transmission length */ sciREG->FORMAT = 8U - 1U; /* length */ @@ -138,12 +138,12 @@ sciREG->SETINT = (uint32)((uint32)1U << 26U) /* Framing error */ | (uint32)((uint32)1U << 25U) /* Overrun error */ | (uint32)((uint32)0U << 24U) /* Parity error */ - | (uint32)((uint32)1U << 9U) /* Receive */ + | (uint32)((uint32)0U << 9U) /* Receive */ | (uint32)((uint32)0U << 1U) /* Wakeup */ | (uint32)((uint32)0U << 0U); /* Break detect */ /** - initialize global transfer variables */ - g_sciTransfer_t[0U].mode = (uint32)1U << 8U; + g_sciTransfer_t[0U].mode = (uint32)0U << 8U; g_sciTransfer_t[0U].tx_length = 0U; g_sciTransfer_t[0U].rx_length = 0U; @@ -793,7 +793,165 @@ } } +/* USER CODE BEGIN (27) */ +/* USER CODE END */ +/** @fn void sciHighLevelInterrupt(void) +* @brief Level 0 Interrupt for SCI +*/ +#pragma CODE_STATE(sciHighLevelInterrupt, 32) +#pragma INTERRUPT(sciHighLevelInterrupt, FIQ) + +/* SourceId : SCI_SourceId_018 */ +/* DesignId : SCI_DesignId_017 */ +/* Requirements : HL_SR245, HL_SR246 */ +void sciHighLevelInterrupt(void) +{ + uint32 vec = sciREG->INTVECT0; + uint8 byte; +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + + switch (vec) + { + case 1U: + sciNotification(sciREG, (uint32)SCI_WAKE_INT); + break; + case 3U: + sciNotification(sciREG, (uint32)SCI_PE_INT); + break; + case 6U: + sciNotification(sciREG, (uint32)SCI_FE_INT); + break; + case 7U: + sciNotification(sciREG, (uint32)SCI_BREAK_INT); + break; + case 9U: + sciNotification(sciREG, (uint32)SCI_OE_INT); + break; + + case 11U: + /* receive */ + byte = (uint8)(sciREG->RD & 0x000000FFU); + + if (g_sciTransfer_t[0U].rx_length > 0U) + { + *g_sciTransfer_t[0U].rx_data = byte; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[0U].rx_data++; + g_sciTransfer_t[0U].rx_length--; + if (g_sciTransfer_t[0U].rx_length == 0U) + { + sciNotification(sciREG, (uint32)SCI_RX_INT); + } + } + break; + + case 12U: + /* transmit */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in Transmit/Receive polling and Interrupt mode" */ + --g_sciTransfer_t[0U].tx_length; + if (g_sciTransfer_t[0U].tx_length > 0U) + { + uint8 txdata = *g_sciTransfer_t[0U].tx_data; + sciREG->TD = (uint32)(txdata); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[0U].tx_data++; + } + else + { + sciREG->CLEARINT = (uint32)SCI_TX_INT; + sciNotification(sciREG, (uint32)SCI_TX_INT); + } + break; + + default: + /* phantom interrupt, clear flags and return */ + sciREG->FLR = ~sciREG->SETINTLVL & 0x07000303U; + break; + } +/* USER CODE BEGIN (29) */ +/* USER CODE END */ +} + + +/** @fn void linHighLevelInterrupt(void) +* @brief Level 0 Interrupt for SCILIN +*/ +#pragma CODE_STATE(linHighLevelInterrupt, 32) +#pragma INTERRUPT(linHighLevelInterrupt, FIQ) + +/* SourceId : SCI_SourceId_021 */ +/* DesignId : SCI_DesignId_017 */ +/* Requirements : HL_SR245, HL_SR246 */ +void linHighLevelInterrupt(void) +{ + uint32 vec = scilinREG->INTVECT0; + uint8 byte; +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + + switch (vec) + { + case 1U: + sciNotification(scilinREG, (uint32)SCI_WAKE_INT); + break; + case 3U: + sciNotification(scilinREG, (uint32)SCI_PE_INT); + break; + case 6U: + sciNotification(scilinREG, (uint32)SCI_FE_INT); + break; + case 7U: + sciNotification(scilinREG, (uint32)SCI_BREAK_INT); + break; + case 9U: + sciNotification(scilinREG, (uint32)SCI_OE_INT); + break; + + case 11U: + /* receive */ + byte = (uint8)(scilinREG->RD & 0x000000FFU); + + if (g_sciTransfer_t[1U].rx_length > 0U) + { + *g_sciTransfer_t[1U].rx_data = byte; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[1U].rx_data++; + g_sciTransfer_t[1U].rx_length--; + if (g_sciTransfer_t[1U].rx_length == 0U) + { + sciNotification(scilinREG, (uint32)SCI_RX_INT); + } + } + break; + + case 12U: + /* transmit */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in Transmit/Receive polling and Interrupt mode" */ + --g_sciTransfer_t[1U].tx_length; + if (g_sciTransfer_t[1U].tx_length > 0U) + { + uint8 txdata = *g_sciTransfer_t[1U].tx_data; + scilinREG->TD = (uint32)(txdata); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[1U].tx_data++; + } + else + { + scilinREG->CLEARINT = (uint32)SCI_TX_INT; + sciNotification(scilinREG, (uint32)SCI_TX_INT); + } + break; + + default: + /* phantom interrupt, clear flags and return */ + scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U; + break; + } +/* USER CODE BEGIN (36) */ +/* USER CODE END */ +} /* USER CODE BEGIN (37) */ /* USER CODE END */ Index: source/sys_dma.c =================================================================== diff -u -r765d2c35118e202444e737c66c77faf9678cc87e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- source/sys_dma.c (.../sys_dma.c) (revision 765d2c35118e202444e737c66c77faf9678cc87e) +++ source/sys_dma.c (.../sys_dma.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -447,3 +447,32 @@ + +/** @fn void dmaBTCAInterrupt(void) +* @brief DMA Interrupt Handler +* +* Frame transfer complete Interrupt handler for DMA channel routed to Group A +* +*/ +#pragma CODE_STATE(dmaBTCAInterrupt, 32) +#pragma INTERRUPT(dmaBTCAInterrupt, FIQ) + +/* SourceId : DMA_SourceId_019 */ +/* DesignId : DMA_DesignId_016 */ +/* Requirements: HL_SR181, HL_SR182 */ +void dmaBTCAInterrupt(void) +{ + uint32 offset = dmaREG->BTCAOFFSET; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + if (offset != 0U) + { + dmaGroupANotification(BTC, offset - 1U); + } + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +} Index: source/sys_main.c =================================================================== diff -u -r3323966fe741edbb36dffc78317ccf06ed93a68e -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- source/sys_main.c (.../sys_main.c) (revision 3323966fe741edbb36dffc78317ccf06ed93a68e) +++ source/sys_main.c (.../sys_main.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -47,20 +47,23 @@ /* Include Files */ -#include -#include #include "sys_common.h" /* USER CODE BEGIN (1) */ #include "system.h" +#include "sys_dma.h" +#include "can.h" #include "gio.h" #include "mibspi.h" -#include "can.h" +#include "sci.h" #include "rti.h" #include "Common.h" +#include "AlarmLamp.h" +#include "Buttons.h" #include "CommBuffers.h" #include "CPLD.h" +#include "FPGA.h" #include "MsgQueues.h" #include "OperationModes.h" #include "SafetyShutdown.h" @@ -122,6 +125,8 @@ gioInit(); // configure GPIO pins mibspiInit(); // re-purposing MIBSPI5 I/O/C pins as GPIO canInit(); // CAN1 = CAN, re-purposing CAN2 and CAN3 Rx and Tx pins as GPIO + sciInit(); // SCI1 used for PC serial interface, SCI2 used for FPGA serial interface + dmaEnable(); // enable DMA } /************************************************************************* @@ -141,6 +146,7 @@ initAlarmLamp(); initButtons(); initWatchdogMgmt(); + initFPGA(); initCommBuffers(); initMsgQueues(); initSystemComm(); @@ -178,20 +184,58 @@ _enable_IRQ(); } -/************************************************************************* - * @brief canMessageNotification - * The canMessageNotification function handles CAN message notifications. - * @details - * Inputs : none - * Outputs : CAN message notification handled. - * @param node : which CAN controller - * @param messageBox : which message box triggered the message notification - * @return none - *************************************************************************/ -void canMessageNotification(canBASE_t *node, uint32 messageBox) +void sciNotification(sciBASE_t *sci, uint32 flags) { - handleCANMsgInterrupt( (CAN_MESSAGE_BOX_T)messageBox ); + static U32 fErrorCnt = 0; + static U32 oErrorCnt = 0; + + if ( ( flags & SCI_FE_INT ) != 0 ) + { + fErrorCnt++; + } + if ( ( flags & SCI_OE_INT ) != 0 ) + { + oErrorCnt++; + } } +void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) +{ + if ( inttype == BTC ) + { + switch ( channel ) + { + case DMA_CH0: + // clear DMA receipt + scilinREG->CLEARINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ + scilinREG->CLEARINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ + break; + case DMA_CH1: + // clear DMA receipt + sciREG->CLEARINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ + sciREG->CLEARINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ + // handle received packet from PC + handleUARTMsgRecvPacketInterrupt(); + break; + + case DMA_CH2: + // clear DMA xmit + scilinREG->CLEARINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ + break; + + case DMA_CH3: + // clear DMA xmit + sciREG->CLEARINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ + // send next pending packet to PC (if any) + handleUARTMsgXmitPacketInterrupt(); + break; + + default: + // TODO - ignore? + break; + } + } +} + /* USER CODE END */ Index: source/sys_vim.c =================================================================== diff -u -r29f1ba03faefd982327916590818a260a3e4aa48 -rcb47c5f896477ceae7597cb1a4191b3972e93f0d --- source/sys_vim.c (.../sys_vim.c) (revision 29f1ba03faefd982327916590818a260a3e4aa48) +++ source/sys_vim.c (.../sys_vim.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) @@ -82,7 +82,7 @@ &phantomInterrupt, /* Channel 10 */ &phantomInterrupt, /* Channel 11 */ &phantomInterrupt, /* Channel 12 */ - &phantomInterrupt, /* Channel 13 */ + &linHighLevelInterrupt, /* Channel 13 */ &phantomInterrupt, /* Channel 14 */ &phantomInterrupt, /* Channel 15 */ &can1HighLevelInterrupt, /* Channel 16 */ @@ -98,7 +98,7 @@ &phantomInterrupt, /* Channel 26 */ &phantomInterrupt, /* Channel 27 */ &phantomInterrupt, /* Channel 28 */ - &can1LowLevelInterrupt, /* Channel 29 */ + &phantomInterrupt, /* Channel 29 */ &phantomInterrupt, /* Channel 30 */ &phantomInterrupt, /* Channel 31 */ &phantomInterrupt, /* Channel 32 */ @@ -109,7 +109,7 @@ &phantomInterrupt, /* Channel 37 */ &phantomInterrupt, /* Channel 38 */ &phantomInterrupt, /* Channel 39 */ - &phantomInterrupt, /* Channel 40 */ + &dmaBTCAInterrupt, /* Channel 40 */ &phantomInterrupt, /* Channel 41 */ &phantomInterrupt, /* Channel 42 */ &phantomInterrupt, /* Channel 43 */ @@ -133,7 +133,7 @@ &phantomInterrupt, /* Channel 61 */ &phantomInterrupt, /* Channel 62 */ &phantomInterrupt, /* Channel 63 */ - &phantomInterrupt, /* Channel 64 */ + &sciHighLevelInterrupt, /* Channel 64 */ &phantomInterrupt, /* Channel 65 */ &phantomInterrupt, /* Channel 66 */ &phantomInterrupt, /* Channel 67 */ @@ -240,7 +240,7 @@ | (uint32)((uint32)SYS_IRQ << 10U) | (uint32)((uint32)SYS_IRQ << 11U) | (uint32)((uint32)SYS_IRQ << 12U) - | (uint32)((uint32)SYS_IRQ << 13U) + | (uint32)((uint32)SYS_FIQ << 13U) | (uint32)((uint32)SYS_IRQ << 14U) | (uint32)((uint32)SYS_IRQ << 15U) | (uint32)((uint32)SYS_FIQ << 16U) @@ -268,7 +268,7 @@ | (uint32)((uint32)SYS_IRQ << 5U) | (uint32)((uint32)SYS_IRQ << 6U) | (uint32)((uint32)SYS_IRQ << 7U) - | (uint32)((uint32)SYS_IRQ << 8U) + | (uint32)((uint32)SYS_FIQ << 8U) | (uint32)((uint32)SYS_IRQ << 9U) | (uint32)((uint32)SYS_IRQ << 10U) | (uint32)((uint32)SYS_IRQ << 11U) @@ -294,7 +294,7 @@ | (uint32)((uint32)SYS_IRQ << 31U); - vimREG->FIRQPR2 = (uint32)((uint32)SYS_IRQ << 0U) + vimREG->FIRQPR2 = (uint32)((uint32)SYS_FIQ << 0U) | (uint32)((uint32)SYS_IRQ << 1U) | (uint32)((uint32)SYS_IRQ << 2U) | (uint32)((uint32)SYS_IRQ << 3U) @@ -375,7 +375,7 @@ | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 12U) - | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)1U << 13U) | (uint32)((uint32)0U << 14U) | (uint32)((uint32)0U << 15U) | (uint32)((uint32)1U << 16U) @@ -391,7 +391,7 @@ | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U) | (uint32)((uint32)0U << 28U) - | (uint32)((uint32)1U << 29U) + | (uint32)((uint32)0U << 29U) | (uint32)((uint32)0U << 30U) | (uint32)((uint32)0U << 31U); @@ -403,7 +403,7 @@ | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U) - | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)1U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 11U) @@ -428,7 +428,7 @@ | (uint32)((uint32)0U << 30U) | (uint32)((uint32)0U << 31U); - vimREG->REQMASKSET2 = (uint32)((uint32)0U << 0U) + vimREG->REQMASKSET2 = (uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U)