Index: AlarmDefs.h
===================================================================
diff -u -r16067a34bbe2f63c78340dc92c6416bc849fcc81 -rae2a434072551837645764125d1d7cfa994e0786
--- AlarmDefs.h	(.../AlarmDefs.h)	(revision 16067a34bbe2f63c78340dc92c6416bc849fcc81)
+++ AlarmDefs.h	(.../AlarmDefs.h)	(revision ae2a434072551837645764125d1d7cfa994e0786)
@@ -53,6 +53,7 @@
     ALARM_ID_DD_FPGA_CLOCK_SPEED_CHECK_FAILURE = 22,                        ///< DD processor clock speed checks against FPGA clock failure
     ALARM_ID_DD_FPGA_COMM_TIMEOUT = 23,                                     ///< DG FPGA communication down for too long
     ALARM_ID_TD_ALARM_AUDIO_SELF_TEST_FAILURE = 24,                         ///< TD alarm audio failed POST
+    ALARM_ID_DD_VALVE_CONTROL_FAILURE = 25,                                 ///< DD FPGA not accepting commanded valve states
     NUM_OF_ALARM_IDS                                                        ///< Total number of alarms
 };
 typedef enum Alarm_List ALARM_ID_T;                                         ///< Type for alarm list enumeration
@@ -210,6 +211,8 @@
     { ALARM_PRIORITY_HIGH,   110,  FALSE, TRUE , TRUE , TRUE , FALSE, TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, TRUE , FALSE, FALSE, ALARM_ID_DD_FPGA_CLOCK_SPEED_CHECK_FAILURE                   },
     { ALARM_PRIORITY_HIGH,   110,  FALSE, TRUE , TRUE , TRUE , FALSE, TRUE , FALSE, FALSE, TRUE , FALSE, FALSE, TRUE , FALSE, FALSE, ALARM_ID_DD_FPGA_COMM_TIMEOUT                                },
     { ALARM_PRIORITY_HIGH,     1,  TRUE , FALSE, TRUE , TRUE , TRUE , TRUE , TRUE , TRUE , FALSE, FALSE, TRUE , TRUE , FALSE, FALSE, ALARM_ID_TD_ALARM_AUDIO_SELF_TEST_FAILURE                    },
+    { ALARM_PRIORITY_HIGH,   110,  FALSE, TRUE , TRUE , TRUE , FALSE, TRUE , FALSE, FALSE, FALSE, FALSE, FALSE, TRUE , FALSE, FALSE, ALARM_ID_DD_VALVE_CONTROL_FAILURE                            },
+
 };  //   Priority            Rank  Fault DGFault Stops  ClrIm  NoClr  NoRes  NoRin  NoEnd  BlkRB  BlkET  NoBRcr NoDRcr ClrOnly TxLog  ID
 
 /// Table of alarms and their rank.
@@ -235,6 +238,7 @@
     { 110, ALARM_ID_DD_FPGA_POST_TEST_FAILED },
     { 110, ALARM_ID_DD_FPGA_CLOCK_SPEED_CHECK_FAILURE },
     { 110, ALARM_ID_DD_FPGA_COMM_TIMEOUT },
+    { 110, ALARM_ID_DD_VALVE_CONTROL_FAILURE },
     { 111, ALARM_ID_TD_DD_COMM_TIMEOUT },
     { 111, ALARM_ID_TD_CAN_MESSAGE_NOT_ACKED_BY_DD },
     { 111, ALARM_ID_DD_CAN_MESSAGE_NOT_ACKED_BY_RO },
@@ -287,6 +291,7 @@
  { 22  , ALARM_ID_DD_FPGA_CLOCK_SPEED_CHECK_FAILURE                    , "DD    | Service Required: Dialysate Device      | A problem was detected with the dialysate device. \n- Treatment must be terminated.\n- Locate the ID code found in the bottom left corner\nof the alarm screen.\n- Call service to report the issue and schedule a repair.                                                                                                                                                                                            | DD Fault: Proc- FPGA Clock               | FPGA clock speed failure                                                                                                                  | If the FPGA clock speed is relatively close to the processor clock for a certain period of time.                                                                                                                                                                                 | "},
  { 23  , ALARM_ID_DD_FPGA_COMM_TIMEOUT                                 , "DD    | Service Required: Dialysate Device      | A problem was detected with the dialysate device. \n- Treatment must be terminated.\n- Locate the ID code found in the bottom left corner\nof the alarm screen.\n- Call service to report the issue and schedule a repair.                                                                                                                                                                                            | DD Fault: FPGA Com                       | DD FPGA communication down for too long                                                                                                   | If retries for commands exceeds limit or FPGA reports comm error.                                                                                                                                                                                                                | "},
  { 24  , ALARM_ID_HD_ALARM_AUDIO_SELF_TEST_FAILURE                     , "TD    | Service Required: Hemodialysis Device   | A problem was detected with the hemodialysis device.\n- Locate the ID code found in the bottom left corner\nof the alarm screen.\n- Call service to report the issue and schedule a repair.                                                                                                                                                                                                                           | HD POST: Primary Alarm Current           | HD alarm audio failed POST                                                                                                                | If alarm audio current is NOT in expected range for than 1 second while alarm tone is being output                                                                                                                                                                               | "},
+ { 25  , ALARM_ID_DD_VALVE_CONTROL_FAILURE                             , "DD    | Service Required: Dialysate Device      | A problem was detected with the dialysate device. \n- Treatment must be terminated.\n- Locate the ID code found in the bottom left corner\nof the alarm screen.\n- Call service to report the issue and schedule a repair.                                                                                                                                                                                            | DD Fault: Valve Control                  | DD FPGA not accepting commanded valve states                                                                                              | If the read back FPGA valve states does not match the commanded valve states for a certain amount of time.                                                                                                                                                                       | "},
  // Num   Alarm ID                                                        Device  Display Title                                                 Instructions                                                                                                                                                                                                                                                                                                  Alarm List Title                           Description                                                                                                                                 Trigger Condition
 };