Index: FPGA.c
===================================================================
diff -u -rbef458bc1e66a2c753f7bf0fda5dae5f097cf39d -r37885be23e7e81383d91c7b20cc01c0da141f286
--- FPGA.c	(.../FPGA.c)	(revision bef458bc1e66a2c753f7bf0fda5dae5f097cf39d)
+++ FPGA.c	(.../FPGA.c)	(revision 37885be23e7e81383d91c7b20cc01c0da141f286)
@@ -56,20 +56,18 @@
     NUM_OF_FPGA_STATES                                                  ///< Number of FPGA states.
 } FPGA_STATE_T;
 
-#ifdef _TD_
-#define FPGA_PAGE_SIZE                  256                             ///< FPGA register pages are 256 bytes.
-#endif
 #ifdef _DD_
 #define FPGA_PAGE_SIZE                  512                             ///< FPGA register pages are 512 bytes.
+#else
+#define FPGA_PAGE_SIZE                  256                             ///< FPGA register pages are 256 bytes.
 #endif
 
 #define FPGA_HEADER_START_ADDR          0x0000                          ///< Start address for FPGA header data.
 #define FPGA_BULK_WRITE_START_ADDR      0x0004                          ///< Start address for FPGA continuous priority writes.
-#ifdef _TD_
-#define FPGA_BULK_READ_START_ADDR       0x0100                          ///< Start address for FPGA continuous priority reads.
-#endif
 #ifdef _DD_
 #define FPGA_BULK_READ_START_ADDR       0x0200                          ///< Start address for FPGA continuous priority reads.
+#else
+#define FPGA_BULK_READ_START_ADDR       0x0100                          ///< Start address for FPGA continuous priority reads.
 #endif
 
 #define FPGA_WRITE_CMD_BUFFER_LEN       (FPGA_PAGE_SIZE+8)              ///< FPGA write command buffer byte length.
@@ -84,8 +82,13 @@
 #define FPGA_CMD_NAK                    0xEE                            ///< FPGA command NAK code.
 
 #define FPGA_CRC_LEN                    2                               ///< FPGA CRC byte length.
+#ifdef _DD_
+#define FPGA_WRITE_CMD_HDR_LEN          5                               ///< FPGA write command header byte length.
+#define FPGA_READ_CMD_HDR_LEN           5                               ///< FPGA read command header byte length.
+#else
 #define FPGA_WRITE_CMD_HDR_LEN          4                               ///< FPGA write command header byte length.
 #define FPGA_READ_CMD_HDR_LEN           4                               ///< FPGA read command header byte length.
+#endif
 #define FPGA_WRITE_RSP_HDR_LEN          3                               ///< FPGA write command response header byte length.
 #define FPGA_READ_RSP_HDR_LEN           3                               ///< FPGA read command response header byte length.
 
@@ -415,10 +418,20 @@
     fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE;
     fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_HEADER_START_ADDR );
     fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_HEADER_START_ADDR );
+#ifdef _DD_
+    fpgaReadCmdBuffer[ 3 ] = GET_LSB_OF_WORD( fpgaHeaderSize );
+    fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( fpgaHeaderSize );
+#else
     fpgaReadCmdBuffer[ 3 ] = fpgaHeaderSize;
+#endif
     crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN );
+#ifdef _DD_
+    fpgaReadCmdBuffer[ 5 ] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 6 ] = GET_LSB_OF_WORD( crc );
+#else
     fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc );
     fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );
+#endif
     // Prep DMA for sending the read cmd and receiving the response
     fpgaReadCommandInProgress = TRUE;
     setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + fpgaHeaderSize + FPGA_CRC_LEN );
@@ -497,24 +510,35 @@
     fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE;
     fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_WRITE_START_ADDR );
     fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_WRITE_START_ADDR );
+#ifdef _DD_
+    fpgaWriteCmdBuffer[ 3 ] = GET_LSB_OF_WORD( fpgaActuatorSetPointsSize );
+    fpgaWriteCmdBuffer[ 4 ] = GET_MSB_OF_WORD( fpgaActuatorSetPointsSize );
+#else
     fpgaWriteCmdBuffer[ 3 ] = fpgaActuatorSetPointsSize;
+#endif
     memcpy( &( fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ] ), fpgaActuatorSetPointsPtr, fpgaActuatorSetPointsSize );
     crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + fpgaActuatorSetPointsSize );
     fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + fpgaActuatorSetPointsSize ] = GET_MSB_OF_WORD( crc );
     fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + fpgaActuatorSetPointsSize + 1 ] = GET_LSB_OF_WORD( crc );
-#ifdef _TD_
-    // reset transitory commands once they're copied to buffer for transmit to FPGA
-    fpgaResetTransitoryCmds();
-#endif
 
     // Construct bulk read command to read sensor data registers starting at address 8
     fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE;
     fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_READ_START_ADDR );
     fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_READ_START_ADDR );
+#ifdef _DD_
+    fpgaReadCmdBuffer[ 3 ] = GET_LSB_OF_WORD( fpgaSensorReadingsSize );
+    fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( fpgaSensorReadingsSize );
+#else
     fpgaReadCmdBuffer[ 3 ] = fpgaSensorReadingsSize;
+#endif
     crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN );
+#ifdef _DD_
+    fpgaReadCmdBuffer[ 5 ] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 6 ] = GET_LSB_OF_WORD( crc );
+#else
     fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc );
     fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );
+#endif
 
     // Prep DMA for sending the bulk write cmd and receiving its response
     setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + fpgaActuatorSetPointsSize + FPGA_CRC_LEN );