Index: FPGA.c =================================================================== diff -u -rcc8db062292cdcbdb29e4174af5976ccf150d0c0 -r37885be23e7e81383d91c7b20cc01c0da141f286 --- FPGA.c (.../FPGA.c) (revision cc8db062292cdcbdb29e4174af5976ccf150d0c0) +++ FPGA.c (.../FPGA.c) (revision 37885be23e7e81383d91c7b20cc01c0da141f286) @@ -30,9 +30,6 @@ #ifdef _DD_ #include "FpgaDD.h" #include "OperationModes.h" -#endif -#ifdef _RO_ -#include "FpgaFP.h" #include "FPOperationModes.h" #endif #include "Messaging.h" @@ -59,11 +56,19 @@ NUM_OF_FPGA_STATES ///< Number of FPGA states. } FPGA_STATE_T; +#ifdef _DD_ +#define FPGA_PAGE_SIZE 512 ///< FPGA register pages are 512 bytes. +#else #define FPGA_PAGE_SIZE 256 ///< FPGA register pages are 256 bytes. +#endif #define FPGA_HEADER_START_ADDR 0x0000 ///< Start address for FPGA header data. #define FPGA_BULK_WRITE_START_ADDR 0x0004 ///< Start address for FPGA continuous priority writes. +#ifdef _DD_ +#define FPGA_BULK_READ_START_ADDR 0x0200 ///< Start address for FPGA continuous priority reads. +#else #define FPGA_BULK_READ_START_ADDR 0x0100 ///< Start address for FPGA continuous priority reads. +#endif #define FPGA_WRITE_CMD_BUFFER_LEN (FPGA_PAGE_SIZE+8) ///< FPGA write command buffer byte length. #define FPGA_READ_CMD_BUFFER_LEN 8 ///< FPGA read command buffer byte length. @@ -77,8 +82,13 @@ #define FPGA_CMD_NAK 0xEE ///< FPGA command NAK code. #define FPGA_CRC_LEN 2 ///< FPGA CRC byte length. +#ifdef _DD_ +#define FPGA_WRITE_CMD_HDR_LEN 5 ///< FPGA write command header byte length. +#define FPGA_READ_CMD_HDR_LEN 5 ///< FPGA read command header byte length. +#else #define FPGA_WRITE_CMD_HDR_LEN 4 ///< FPGA write command header byte length. #define FPGA_READ_CMD_HDR_LEN 4 ///< FPGA read command header byte length. +#endif #define FPGA_WRITE_RSP_HDR_LEN 3 ///< FPGA write command response header byte length. #define FPGA_READ_RSP_HDR_LEN 3 ///< FPGA read command response header byte length. @@ -87,13 +97,6 @@ #define FPGA_ADC1_AUTO_READ_ENABLE 0x01 ///< Auto-read enable bit for ADC1 control register. -#define FPGA_BLOOD_LEAK_STATUS_MASK 0x1000 ///< Bit mask for blood leak detector. -#define FPGA_BLOOD_LEAK_ST_BIT_INDEX 12 ///< Bit index for the blood leak self test status bit. -#define FPGA_BLOOD_LEAK_ZERO_STATE_MASK 0x2000 ///< Bit mask for blood leak detector zero. -#define FPAG_BLOOD_LEAK_ZERO_BIT_INDEX 13 ///< Bit index for the blood leak zero status bit. -#define FPGA_BLOOD_LEAK_ZERO_CMD 0x02 ///< Bit for blood leak detector zero command. -#define FPGA_BLOOD_LEAK_SELF_TEST_CMD 0x01 ///< Bit for blood leak detector self test command. - // ********** private data ********** // FPGA state @@ -385,9 +388,6 @@ #ifdef _DD_ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_STATE, fpgaState ) #endif -#ifdef _RO_ - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_FP_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_STATE, fpgaState ) -#endif break; } @@ -418,10 +418,20 @@ fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_HEADER_START_ADDR ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_HEADER_START_ADDR ); +#ifdef _DD_ + fpgaReadCmdBuffer[ 3 ] = GET_LSB_OF_WORD( fpgaHeaderSize ); + fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( fpgaHeaderSize ); +#else fpgaReadCmdBuffer[ 3 ] = fpgaHeaderSize; +#endif crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); +#ifdef _DD_ + fpgaReadCmdBuffer[ 5 ] = GET_MSB_OF_WORD( crc ); + fpgaReadCmdBuffer[ 6 ] = GET_LSB_OF_WORD( crc ); +#else fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc ); +#endif // Prep DMA for sending the read cmd and receiving the response fpgaReadCommandInProgress = TRUE; setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + fpgaHeaderSize + FPGA_CRC_LEN ); @@ -500,24 +510,35 @@ fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE; fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_WRITE_START_ADDR ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_WRITE_START_ADDR ); +#ifdef _DD_ + fpgaWriteCmdBuffer[ 3 ] = GET_LSB_OF_WORD( fpgaActuatorSetPointsSize ); + fpgaWriteCmdBuffer[ 4 ] = GET_MSB_OF_WORD( fpgaActuatorSetPointsSize ); +#else fpgaWriteCmdBuffer[ 3 ] = fpgaActuatorSetPointsSize; +#endif memcpy( &( fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ] ), fpgaActuatorSetPointsPtr, fpgaActuatorSetPointsSize ); crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + fpgaActuatorSetPointsSize ); fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + fpgaActuatorSetPointsSize ] = GET_MSB_OF_WORD( crc ); fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + fpgaActuatorSetPointsSize + 1 ] = GET_LSB_OF_WORD( crc ); -#ifdef _TD_ - // reset transitory commands once they're copied to buffer for transmit to FPGA - fpgaResetTransitoryCmds(); -#endif // Construct bulk read command to read sensor data registers starting at address 8 fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_READ_START_ADDR ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_READ_START_ADDR ); +#ifdef _DD_ + fpgaReadCmdBuffer[ 3 ] = GET_LSB_OF_WORD( fpgaSensorReadingsSize ); + fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( fpgaSensorReadingsSize ); +#else fpgaReadCmdBuffer[ 3 ] = fpgaSensorReadingsSize; +#endif crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); +#ifdef _DD_ + fpgaReadCmdBuffer[ 5 ] = GET_MSB_OF_WORD( crc ); + fpgaReadCmdBuffer[ 6 ] = GET_LSB_OF_WORD( crc ); +#else fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc ); +#endif // Prep DMA for sending the bulk write cmd and receiving its response setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + fpgaActuatorSetPointsSize + FPGA_CRC_LEN ); @@ -685,9 +706,6 @@ #ifdef _DD_ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_CMD_TOO_MUCH_DATA, bytes2Transmit ); #endif -#ifdef _RO_ - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_FP_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_CMD_TOO_MUCH_DATA, bytes2Transmit ); -#endif } } @@ -731,9 +749,6 @@ #ifdef _DD_ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_RSP_TOO_MUCH_DATA, bytes2Receive ) #endif -#ifdef _RO_ - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_FP_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_RSP_TOO_MUCH_DATA, bytes2Receive ) -#endif } } @@ -777,9 +792,6 @@ #ifdef _DD_ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_CMD_TOO_MUCH_DATA, bytes2Transmit ) #endif -#ifdef _RO_ - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_FP_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_CMD_TOO_MUCH_DATA, bytes2Transmit ) -#endif } } @@ -823,9 +835,6 @@ #ifdef _DD_ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_RSP_TOO_MUCH_DATA, bytes2Receive ) #endif -#ifdef _RO_ - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_FP_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_RSP_TOO_MUCH_DATA, bytes2Receive ) -#endif } }