Index: firmware/source/sys_link.cmd
===================================================================
diff -u -r86d861623e84ebdebae69d710fef89fa86f96712 -rafbb1c610228924c9908d137019055a17f73b1f2
--- firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 86d861623e84ebdebae69d710fef89fa86f96712)
+++ firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision afbb1c610228924c9908d137019055a17f73b1f2)
@@ -47,8 +47,14 @@
 --retain="*(.intvecs)"
 
 /* USER CODE BEGIN (1) */
-/* IGNORE the generated Memory code, overridden below */
 #if 0
+/* NOTE: the default memory mapy is created by HALCoGen and it starts from 0x00000000
+   The memory map cannot be changed in HALCoGen so the memory map that starts from
+   0x00010000 shall be created directly in sys_link.cmd below. So #if 1 and #if 0 were
+   added to disregard the auto generated memroy map. The edited memory map should
+   be in the user defined code to map sure it is not removed every time HALCoGen is
+   created.
+*/
 /* USER CODE END */
 
 /*----------------------------------------------------------------------------*/
@@ -64,7 +70,6 @@
 /* USER CODE BEGIN (2) */
 #endif
 /* Override Memory Segments with CRC here */
-#if 1
 MEMORY
 {
     VECTORS (X)  : origin=0x00010000
@@ -84,34 +89,14 @@
 
     RAM     (RW) : origin=0x08004c00
                    length=0x0002b400
-#endif
-// TODO do we need ECC?
-//#if 1
-//    ECC_VEC  (R) : origin=(0xf0400000 + (start(VECTORS) >> 3))
-//                   length=(size(VECTORS) >> 3)
-//                   ECC={algorithm=algoL2R4F021, input_range=VECTORS}
-//
-//    ECC_CRC  (R) : origin=(0xf0400000 + (start(CRCMEM)  >> 3))
-//                   length=(size(CRCMEM)  >> 3)
-//                   ECC={algorithm=algoL2R4F021, input_range=CRCMEM }
-//
-//    ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0)  >> 3))
-//                   length=(size(FLASH0)  >> 3)
-//                   ECC={algorithm=algoL2R4F021, input_range=FLASH0 }
-//#endif
 /* USER CODE END */
 }
 
 /* USER CODE BEGIN (3) */
-/* IGNORE the generated Sections code, overridden below */
-//ECC
-//{
-//    algoL2R4F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
-//                   hamming_mask = R4         /* Use R4/R5 build in Mask */
-//                   parity_mask  = 0x0c       /* Set which ECC bits are Even and Odd parity */
-//                   mirroring    = F021       /* RM57Lx and TMS570LCx are build in F021 */
-//}
 #if 0
+/* NOTE: the default section has been disabled to run crc check of the image
+   in the user defined section below.
+*/
 /* USER CODE END */
 
 /*----------------------------------------------------------------------------*/
@@ -132,7 +117,6 @@
 /* USER CODE BEGIN (4) */
 #endif
 /* Override Sections with CRCs here */
-#if 1
 SECTIONS
 {
     .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C )
@@ -145,7 +129,6 @@
     .sysmem  : {} > RAM
 
     .TI.crctab : {} > CRCMEM
-#endif
 /* USER CODE END */
 }