Index: firmware/.ccsproject
===================================================================
diff -u
--- firmware/.ccsproject (revision 0)
+++ firmware/.ccsproject (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,16 @@
+
+
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+
Index: firmware/.cproject
===================================================================
diff -u
--- firmware/.cproject (revision 0)
+++ firmware/.cproject (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,176 @@
+
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Index: firmware/.project
===================================================================
diff -u
--- firmware/.project (revision 0)
+++ firmware/.project (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,27 @@
+
+
+ TD
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ com.ti.ccstudio.core.ccsNature
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.core.ccnature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
Index: firmware/.settings/org.eclipse.cdt.codan.core.prefs
===================================================================
diff -u
--- firmware/.settings/org.eclipse.cdt.codan.core.prefs (revision 0)
+++ firmware/.settings/org.eclipse.cdt.codan.core.prefs (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
Index: firmware/.settings/org.eclipse.cdt.debug.core.prefs
===================================================================
diff -u
--- firmware/.settings/org.eclipse.cdt.debug.core.prefs (revision 0)
+++ firmware/.settings/org.eclipse.cdt.debug.core.prefs (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
Index: firmware/.settings/org.eclipse.core.resources.prefs
===================================================================
diff -u
--- firmware/.settings/org.eclipse.core.resources.prefs (revision 0)
+++ firmware/.settings/org.eclipse.core.resources.prefs (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,20 @@
+eclipse.preferences.version=1
+encoding//Debug/App/Controllers/subdir_rules.mk=UTF-8
+encoding//Debug/App/Controllers/subdir_vars.mk=UTF-8
+encoding//Debug/App/Modes/subdir_rules.mk=UTF-8
+encoding//Debug/App/Modes/subdir_vars.mk=UTF-8
+encoding//Debug/App/Monitors/subdir_rules.mk=UTF-8
+encoding//Debug/App/Monitors/subdir_vars.mk=UTF-8
+encoding//Debug/App/Services/subdir_rules.mk=UTF-8
+encoding//Debug/App/Services/subdir_vars.mk=UTF-8
+encoding//Debug/App/Tasks/subdir_rules.mk=UTF-8
+encoding//Debug/App/Tasks/subdir_vars.mk=UTF-8
+encoding//Debug/FWCommon/FlashDrvr/subdir_rules.mk=UTF-8
+encoding//Debug/FWCommon/FlashDrvr/subdir_vars.mk=UTF-8
+encoding//Debug/FWCommon/subdir_rules.mk=UTF-8
+encoding//Debug/FWCommon/subdir_vars.mk=UTF-8
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/source/subdir_rules.mk=UTF-8
+encoding//Debug/source/subdir_vars.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
Index: firmware/App/Controllers/AlarmLamp.c
===================================================================
diff -u
--- firmware/App/Controllers/AlarmLamp.c (revision 0)
+++ firmware/App/Controllers/AlarmLamp.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,370 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file AlarmLamp.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include "AlarmLamp.h"
+//#include "CPLD.h"
+#include "Messaging.h"
+#include "TaskGeneral.h"
+#include "Timers.h"
+
+/**
+ * @addtogroup AlarmLamp
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define NUM_OF_ALARM_LAMP_PATTERN_SEQUENCE_STEPS 2 ///< Number of steps in an alarm lamp pattern sequence.
+
+/// Enumeration of alarm lamp color states.
+typedef enum LampStates
+{
+ LAMP_STATE_OFF = 0, ///< Alarm lamp color (R, G, or B) is off.
+ LAMP_STATE_ON, ///< Alarm lamp color (R, G, or B) is on.
+ NUM_OF_LAMP_STATES ///< Number of alarm lamp color states.
+} LAMP_STATE_T;
+
+/// Alarm lamp pattern record
+struct LampPatterns
+{
+ U32 duration[ NUM_OF_ALARM_LAMP_PATTERN_SEQUENCE_STEPS ]; ///< Duration (in ms) of the 2 step alarm lamp pattern sequence.
+ LAMP_STATE_T green[ NUM_OF_ALARM_LAMP_PATTERN_SEQUENCE_STEPS ]; ///< Lamp color state of the 2 step alarm lamp pattern sequence for green.
+ LAMP_STATE_T blue[ NUM_OF_ALARM_LAMP_PATTERN_SEQUENCE_STEPS ]; ///< Lamp color state of the 2 step alarm lamp pattern sequence for blue.
+ LAMP_STATE_T red[ NUM_OF_ALARM_LAMP_PATTERN_SEQUENCE_STEPS ]; ///< Lamp color state of the 2 step alarm lamp pattern sequence for red.
+};
+
+/// Enumeration of alarm lamp self-test states.
+typedef enum Alarm_Lamp_Self_Test_States
+{
+ ALARM_LAMP_SELF_TEST_STATE_START = 0, ///< Start state of alarm lamp self-test.
+ ALARM_LAMP_SELF_TEST_STATE_RED, ///< Red state of alarm lamp self-test.
+ ALARM_LAMP_SELF_TEST_STATE_YELLOW, ///< Yellow state of alarm lamp self-test.
+ ALARM_LAMP_SELF_TEST_STATE_GREEN, ///< Green state of alarm lamp self-test.
+ ALARM_LAMP_SELF_TEST_STATE_COMPLETE, ///< Completed state of alarm lamp self-test.
+ NUM_OF_ALARM_LAMP_SELF_TEST_STATES ///< Number of states in alarm lamp self-test.
+} ALARM_LAMP_SELF_TEST_STATE_T;
+
+#define POST_LAMP_STEP_TIME_MS 1000 ///< Duration (in ms) for each alarm lamp self-test step.
+
+// ********** private data **********
+
+/// Current alarm lamp pattern (overrideable).
+static OVERRIDE_U32_T currentLampPattern = { LAMP_PATTERN_MANUAL, LAMP_PATTERN_FAULT, LAMP_PATTERN_FAULT, 0 };
+static LAMP_PATTERN_T pendingLampPattern = LAMP_PATTERN_MANUAL; ///< Pending alarm lamp pattern.
+static U32 currentLampPatternStep = 0; ///< Current alarm lamp pattern step.
+static U32 lampPatternStepTimer = 0; ///< Timer counter for current alarm lamp pattern step.
+static BOOL alarmLampOn = FALSE; ///< Flag indicates whether an any lamp is currently on.
+
+/// Two step alarm lamp patterns (repeating).
+const struct LampPatterns LAMP_PATTERNS[ NUM_OF_LAMP_PATTERNS ] = {
+ { { 500, 500 }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_OFF, LAMP_STATE_OFF } }, // LAMP_PATTERN_OFF
+ { { 500, 500 }, { LAMP_STATE_ON, LAMP_STATE_ON }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_OFF, LAMP_STATE_OFF } }, // LAMP_PATTERN_OK
+ { { 250, 250 }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_ON, LAMP_STATE_OFF } }, // LAMP_PATTERN_FAULT
+ { { 250, 250 }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_ON, LAMP_STATE_OFF } }, // LAMP_PATTERN_HIGH_ALARM
+ { { 1000, 1000 }, { LAMP_STATE_ON, LAMP_STATE_OFF }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_ON, LAMP_STATE_OFF } }, // LAMP_PATTERN_MED_ALARM
+ { { 500, 500 }, { LAMP_STATE_ON, LAMP_STATE_ON }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_ON, LAMP_STATE_ON } }, // LAMP_PATTERN_LOW_ALARM
+ { { 0, 0 }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_OFF, LAMP_STATE_OFF }, { LAMP_STATE_OFF, LAMP_STATE_OFF } } // LAMP_PATTERN_MANUAL
+};
+
+static ALARM_LAMP_SELF_TEST_STATE_T alarmLampSelfTestState = ALARM_LAMP_SELF_TEST_STATE_START; ///< Current alarm lamp self-test state.
+static U32 alarmLampSelfTestStepTimerCount = 0; ///< Timer counter for current alarm lamp self-test state.
+
+// ********** private function prototypes **********
+
+static void setAlarmLampToPatternStep( void );
+
+/*********************************************************************//**
+ * @brief
+ * The initAlarmLamp function initializes the AlarmLamp module.
+ * @details Inputs: none
+ * @details Outputs: AlarmLamp module initialized.
+ * @return none
+ *************************************************************************/
+void initAlarmLamp( void )
+{
+ pendingLampPattern = LAMP_PATTERN_MANUAL;
+ currentLampPatternStep = 0;
+ lampPatternStepTimer = 0;
+ alarmLampOn = FALSE;
+
+ alarmLampSelfTestState = ALARM_LAMP_SELF_TEST_STATE_START;
+ alarmLampSelfTestStepTimerCount = 0;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execAlarmLamp function executes the alarm lamp service for the
+ * current lamp pattern.
+ * @details Inputs: pendingLampPattern, currentLampPattern, lampPatternStepTimer,
+ * lampPatterns.
+ * @details Outputs: currentLampPattern
+ * @return none
+ *************************************************************************/
+void execAlarmLamp( void )
+{
+ // If starting a new lamp pattern, reset pattern variables
+ if ( pendingLampPattern != currentLampPattern.data )
+ {
+ currentLampPattern.data = pendingLampPattern;
+ currentLampPatternStep = 0;
+
+ setAlarmLampToPatternStep();
+ }
+ // Otherwise, increment pattern timer
+ else
+ {
+ lampPatternStepTimer += ALARM_LAMP_AND_AUDIO_CONTROL_INTERVAL_MS;
+ }
+
+ // Control alarm lamp to currently set pattern (unless we are in manual pattern)
+ if ( getCurrentAlarmLampPattern() != LAMP_PATTERN_MANUAL )
+ {
+ // If pattern step duration has elapsed, move to next step
+ if ( lampPatternStepTimer >= LAMP_PATTERNS[ getCurrentAlarmLampPattern() ].duration[ currentLampPatternStep ] )
+ {
+ // Increment pattern step
+ currentLampPatternStep++;
+ if ( currentLampPatternStep >= NUM_OF_LAMP_STATES )
+ {
+ currentLampPatternStep = 0;
+ }
+ // Set lamps according to pattern step
+ setAlarmLampToPatternStep();
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The requestAlarmLampPattern function sets a request for a new lamp pattern.
+ * @details Inputs: none
+ * @details Outputs: pendingLampPattern
+ * @param lampPattern new lamp pattern
+ * @return none
+ *************************************************************************/
+void requestAlarmLampPattern( LAMP_PATTERN_T lampPattern )
+{
+ if ( lampPattern < NUM_OF_LAMP_PATTERNS )
+ {
+ pendingLampPattern = lampPattern;
+ }
+ else
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_LAMP_INVALID_PATTERN_REQUESTED, lampPattern )
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getCurrentAlarmLampPattern function gets the current alarm lamp
+ * pattern in effect.
+ * @details Inputs: currentLampPattern
+ * @details Outputs: none
+ * @return currentLampPattern
+ *************************************************************************/
+LAMP_PATTERN_T getCurrentAlarmLampPattern( void )
+{
+ LAMP_PATTERN_T result = (LAMP_PATTERN_T)currentLampPattern.data;
+
+ if ( OVERRIDE_KEY == currentLampPattern.override )
+ {
+ result = (LAMP_PATTERN_T)currentLampPattern.ovData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getAlarmLampOn function gets the current alarm lamp on flag.
+ * @details Inputs: alarmLampOn
+ * @details Outputs: none
+ * @return alarmLampOn
+ *************************************************************************/
+BOOL getAlarmLampOn( void )
+{
+ return alarmLampOn;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execAlarmLampTest function executes the alarm lamp test.
+ * This function should be called periodically until a pass or fail
+ * result is returned.
+ * @details Inputs: alarmLampSelfTestState, alarmLampSelfTestStepTimerCount
+ * @details Outputs: alarmLampSelfTestState, alarmLampSelfTestStepTimerCount
+ * @return in progress, passed, or failed
+ *************************************************************************/
+SELF_TEST_STATUS_T execAlarmLampTest( void )
+{
+ SELF_TEST_STATUS_T result = SELF_TEST_STATUS_IN_PROGRESS;
+
+ switch ( alarmLampSelfTestState )
+ {
+ case ALARM_LAMP_SELF_TEST_STATE_START:
+ alarmLampSelfTestState = ALARM_LAMP_SELF_TEST_STATE_RED;
+ alarmLampSelfTestStepTimerCount = getMSTimerCount();
+// setCPLDLampRed( PIN_SIGNAL_HIGH );
+ break;
+
+ case ALARM_LAMP_SELF_TEST_STATE_RED:
+ if ( TRUE == didTimeout( alarmLampSelfTestStepTimerCount, POST_LAMP_STEP_TIME_MS ) )
+ {
+ alarmLampSelfTestState = ALARM_LAMP_SELF_TEST_STATE_YELLOW;
+ alarmLampSelfTestStepTimerCount = getMSTimerCount();
+// setCPLDLampGreen( PIN_SIGNAL_HIGH ); // Green + red = yellow
+ }
+ break;
+
+ case ALARM_LAMP_SELF_TEST_STATE_YELLOW:
+ if ( TRUE == didTimeout( alarmLampSelfTestStepTimerCount, POST_LAMP_STEP_TIME_MS ) )
+ {
+ alarmLampSelfTestState = ALARM_LAMP_SELF_TEST_STATE_GREEN;
+ alarmLampSelfTestStepTimerCount = getMSTimerCount();
+// setCPLDLampRed( PIN_SIGNAL_LOW );
+ }
+ break;
+
+ case ALARM_LAMP_SELF_TEST_STATE_GREEN:
+ if ( TRUE == didTimeout( alarmLampSelfTestStepTimerCount, POST_LAMP_STEP_TIME_MS ) )
+ {
+ alarmLampSelfTestState = ALARM_LAMP_SELF_TEST_STATE_COMPLETE;
+// setCPLDLampGreen( PIN_SIGNAL_LOW );
+ requestAlarmLampPattern( LAMP_PATTERN_OK );
+ result = SELF_TEST_STATUS_PASSED;
+ }
+ break;
+
+ case ALARM_LAMP_SELF_TEST_STATE_COMPLETE:
+ // If we get called in this state, assume we are doing self-test again
+ alarmLampSelfTestState = ALARM_LAMP_SELF_TEST_STATE_START;
+ break;
+
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_LAMP_INVALID_SELF_TEST_STATE, alarmLampSelfTestState )
+ result = SELF_TEST_STATUS_FAILED;
+ break;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The resetAlarmLampPOSTState function resets the alarm lamp post state.
+ * @details Inputs: none
+ * @details Outputs: alarmLampSelfTestState
+ * @return none
+ *************************************************************************/
+void resetAlarmLampPOSTState( void )
+{
+ alarmLampSelfTestState = ALARM_LAMP_SELF_TEST_STATE_START;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setAlarmLampToPatternStep function sets the lamps according to the
+ * current lamp pattern and lamp pattern step.
+ * @details Inputs: lampPatterns[], currentLampPatternStep
+ * @details Outputs: lampPatternStepTimer reset. Lamps set per current pattern.
+ * @return none
+ *************************************************************************/
+static void setAlarmLampToPatternStep( void )
+{
+ PIN_SIGNAL_STATE_T green = PIN_SIGNAL_LOW;
+ PIN_SIGNAL_STATE_T blue = PIN_SIGNAL_LOW;
+ PIN_SIGNAL_STATE_T red = PIN_SIGNAL_LOW;
+
+ alarmLampOn = FALSE;
+ lampPatternStepTimer = 0;
+ if ( LAMP_PATTERNS[ getCurrentAlarmLampPattern() ].green[ currentLampPatternStep ] == LAMP_STATE_ON )
+ {
+ green = PIN_SIGNAL_HIGH;
+ alarmLampOn = TRUE;
+ }
+#if 0 // This is dead code until blue color is used somewhere
+ if ( LAMP_PATTERNS[ getCurrentAlarmLampPattern() ].blue[ currentLampPatternStep ] == LAMP_STATE_ON )
+ {
+ blue = PIN_SIGNAL_HIGH;
+ alarmLampOn = TRUE;
+ }
+#endif
+ if ( LAMP_PATTERNS[ getCurrentAlarmLampPattern() ].red[ currentLampPatternStep ] == LAMP_STATE_ON )
+ {
+ red = PIN_SIGNAL_HIGH;
+ alarmLampOn = TRUE;
+ }
+
+#ifndef TASK_TIMING_OUTPUT_ENABLED
+// setCPLDLampGreen( green );
+// setCPLDLampBlue( blue );
+// setCPLDLampRed( red );
+#endif
+}
+
+
+/*************************************************************************
+ * TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/*********************************************************************//**
+ * @brief
+ * The testSetCurrentLampPatternOverride function overrides the state of the
+ * current alarm lamp pattern with a given pattern.
+ * @details Inputs: none
+ * @details Outputs: currentLampPattern
+ * @param value override state for the alarm lamp pattern
+ * @return TRUE if override successful, FALSE if not
+ *************************************************************************/
+BOOL testSetCurrentLampPatternOverride( U32 value )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ currentLampPattern.ovData = value;
+ currentLampPattern.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetCurrentLampPatternOverride function resets the override of the
+ * state of the alarm lamp pattern.
+ * @details Inputs: none
+ * @details Outputs: currentLampPattern
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetCurrentLampPatternOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ currentLampPattern.override = OVERRIDE_RESET;
+ currentLampPattern.ovData = currentLampPattern.ovInitData;
+ }
+
+ return result;
+}
+
+/**@}*/
Index: firmware/App/Controllers/AlarmLamp.h
===================================================================
diff -u
--- firmware/App/Controllers/AlarmLamp.h (revision 0)
+++ firmware/App/Controllers/AlarmLamp.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,62 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file AlarmLamp.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __ALARM_LAMP_H__
+#define __ALARM_LAMP_H__
+
+#include "TDCommon.h"
+
+/**
+ * @defgroup AlarmLamp AlarmLamp
+ * @brief The Alarm Lamp module manages the state of the alarm lamp.
+ *
+ * @addtogroup AlarmLamp
+ * @{
+ */
+
+// ********** public definitions **********
+
+/// Enumeration of alarm lamp patterns.
+typedef enum LampPatternEnum
+{
+ LAMP_PATTERN_OFF = 0, ///< Alarm lamp pattern where lamp is off
+ LAMP_PATTERN_OK, ///< Alarm lamp pattern for ok state
+ LAMP_PATTERN_FAULT, ///< Alarm lamp pattern for fault state
+ LAMP_PATTERN_HIGH_ALARM, ///< Alarm lamp pattern for high priority alarm state
+ LAMP_PATTERN_MED_ALARM, ///< Alarm lamp pattern for medium priority alarm state
+ LAMP_PATTERN_LOW_ALARM, ///< Alarm lamp pattern for low priority alarm state
+ LAMP_PATTERN_MANUAL, ///< Alarm lamp pattern is managed manually in the state
+ NUM_OF_LAMP_PATTERNS ///< Number of alarm lamp patterns
+} LAMP_PATTERN_T;
+
+// ********** public function prototypes **********
+
+void initAlarmLamp( void );
+void execAlarmLamp( void );
+void requestAlarmLampPattern( LAMP_PATTERN_T lampPattern );
+SELF_TEST_STATUS_T execAlarmLampTest( void );
+void resetAlarmLampPOSTState( void );
+
+LAMP_PATTERN_T getCurrentAlarmLampPattern( void );
+BOOL getAlarmLampOn( void );
+
+BOOL testSetCurrentLampPatternOverride( U32 value );
+BOOL testResetCurrentLampPatternOverride( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Modes/ModeFault.c
===================================================================
diff -u
--- firmware/App/Modes/ModeFault.c (revision 0)
+++ firmware/App/Modes/ModeFault.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,219 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file ModeFault.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include "Messaging.h"
+#include "ModeFault.h"
+#include "OperationModes.h"
+#include "Utilities.h"
+
+/**
+ * @addtogroup TDFaultMode
+ * @{
+ */
+
+// ********** private data **********
+
+static HD_FAULT_STATE_T faultState; ///< Currently active fault state.
+static SELF_TEST_STATUS_T faultPOSTSelfTestResult; ///< Fault POST self test result.
+
+// ********** private function prototypes **********
+
+static HD_FAULT_STATE_T handleFaultStartState( void );
+static HD_FAULT_STATE_T handleFaultRunNVPOSTsState( void );
+
+/*********************************************************************//**
+ * @brief
+ * The initFaultMode function initializes the Fault Mode module.
+ * @details Inputs: none
+ * @details Outputs: Fault Mode module initialized.
+ * @return none
+ *************************************************************************/
+void initFaultMode( void )
+{
+ faultState = HD_FAULT_STATE_START;
+ faultPOSTSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The transitionToFaultMode function prepares for transition to fault mode.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return initial state of the fault mode state machine
+ *************************************************************************/
+U32 transitionToFaultMode( void )
+{
+ TD_OP_MODE_T previousOpMode = getPreviousOperationMode();
+// DD_OP_MODE_T dgOperationMode = getDGOpMode();
+
+ initFaultMode();
+// requestAlarmLampPattern( LAMP_PATTERN_FAULT ); // in case we get here before LED POST can take alarm lamp out of manual control.
+// doorClosedRequired( FALSE, FALSE );
+// syringeDetectionRequired( FALSE );
+// setVenousBubbleDetectionEnabled( FALSE );
+ setCurrentSubState( NO_SUB_STATE );
+
+ // Set user alarm recovery actions allowed in this mode
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_RESUME, FALSE );
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_RINSEBACK, FALSE );
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_END_TREATMENT, FALSE );
+ // Stop trimmer heater
+// cmdStopDGTrimmerHeater();
+// // Stop syringe pump
+// stopSyringePump();
+
+ // Publish POST failure status to UI if fault triggered in Init/POST mode
+ if ( MODE_INIT == previousOpMode )
+ {
+// sendPOSTFinalResult( FALSE );
+ }
+
+ if ( ( MODE_PRET == previousOpMode ) || ( MODE_TREA == previousOpMode ) )
+ {
+// collectTreatmentLogData();
+// sendTreatmentLogDataToUI();
+ }
+
+ // Release RTC in case the RTC semaphore was not released prior to transitioning to fault mode.
+ // In fault mode, the non-volatile data mgmt POST might be run again so the RTC has to be available. Also,
+ // the RTC time is read every second which requires the semaphore.
+ releaseSemaphore( SEMAPHORE_RTC );
+
+ return faultState;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execFaultMode function executes the Fault Mode state machine.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return current state of the fault mode
+ *************************************************************************/
+U32 execFaultMode( void )
+{
+// BOOL stop = isStopButtonPressed();
+// DG_OP_MODE_T dgOperationMode = getDGOpMode();
+
+ // Ensure all pumps are stopped
+// signalBloodPumpHardStop();
+// setAirPumpState( AIR_PUMP_STATE_OFF );
+
+ // Ensure all valves are in safe position
+// setValveAirTrap( STATE_CLOSED );
+// setValvePosition( VBA, VALVE_POSITION_C_CLOSE );
+// setValvePosition( VBV, VALVE_POSITION_C_CLOSE );
+
+ // If DG not stopped, stop it
+// if ( DG_MODE_GENE == dgOperationMode )
+// {
+// cmdStopDG();
+// }
+
+ switch( faultState )
+ {
+ case HD_FAULT_STATE_START:
+ faultState = handleFaultStartState();
+ break;
+
+ case HD_FAULT_STATE_RUN_NV_POSTS:
+ faultState = handleFaultRunNVPOSTsState();
+ break;
+
+ case HD_FAULT_STATE_COMPLETE:
+ // Do nothing unless the test configuration to recover treatment is enabled
+// if ( ( TRUE == getTestConfigStatus( TEST_CONFIG_RECOVER_TREATMENT ) ) && ( TRUE == hasRecoverFromFaultModeBeenSet() ) )
+// {
+// TD_OP_MODE_T prevMode = getPreviousOperationMode();
+//
+// requestNewOperationMode( prevMode );
+// }
+ break;
+
+ default:
+ faultState = HD_FAULT_STATE_COMPLETE;
+ break;
+ }
+
+ return faultState;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalAlarmActionToFaultMode function executes the given alarm action
+ * as appropriate while in Fault Mode.
+ * @details Inputs: none
+ * @details Outputs: given alarm action executed
+ * @param action ID of alarm action to execute
+ * @return none
+ *************************************************************************/
+void signalAlarmActionToFaultMode( ALARM_ACTION_T action )
+{
+ // Fault mode is terminal and already in safe state - no alarm actions handled in this mode.
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handleFaultStartState function handles the start state of the fault mode.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return next state
+ *************************************************************************/
+static HD_FAULT_STATE_T handleFaultStartState( void )
+{
+ HD_FAULT_STATE_T state = HD_FAULT_STATE_COMPLETE;
+// NVDATAMGMT_RECORDS_READ_STATUS_T status = getNVRecordsReadStatus();
+//
+// switch ( status )
+// {
+// // If the records are queued or already read, go directly to NV POST to process
+// // their CRCs.
+// case NVDATAMGMT_RECORDS_QUEUED:
+// case NVDATAMGMT_RECORDS_READ:
+// state = HD_FAULT_STATE_RUN_NV_POSTS;
+// break;
+//
+// // If the NV post was completed prior to transitioning to fault mode, do nothing
+// case NVDATAMGMT_RECORDS_CRC_CHECKED:
+// state = HD_FAULT_STATE_COMPLETE;
+// break;
+// }
+
+ return state;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handleFaultRunNVPOSTsState function handles running non-volatile POSTs.
+ * @details Inputs: faultPOSTSelfTestResult
+ * @details Outputs: faultPOSTSelfTestResult
+ * @return next state
+ *************************************************************************/
+static HD_FAULT_STATE_T handleFaultRunNVPOSTsState( void )
+{
+ HD_FAULT_STATE_T state = HD_FAULT_STATE_RUN_NV_POSTS;
+// faultPOSTSelfTestResult = execNVDataMgmtSelfTest();
+//
+// // Regardless of the status of the NV POST transition to the complete state.
+// if ( ( SELF_TEST_STATUS_PASSED == faultPOSTSelfTestResult ) || ( SELF_TEST_STATUS_FAILED == faultPOSTSelfTestResult ) )
+// {
+// state = HD_FAULT_STATE_COMPLETE;
+// }
+
+ return state;
+}
+
+/**@}*/
Index: firmware/App/Modes/ModeFault.h
===================================================================
diff -u
--- firmware/App/Modes/ModeFault.h (revision 0)
+++ firmware/App/Modes/ModeFault.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,41 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file ModeFault.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __MODE_FAULT_H__
+#define __MODE_FAULT_H__
+
+#include "../TDCommon.h"
+#include "TDDefs.h"
+
+/**
+ * @defgroup TDFaultMode TDFaultMode
+ * @brief FaultMode module.
+ *
+ * @addtogroup TDFaultMode
+ * @{
+ */
+
+// ********** public function prototypes **********
+
+void initFaultMode( void ); // Initialize this module
+U32 transitionToFaultMode( void ); // Prepares for transition to fault mode
+U32 execFaultMode( void ); // Execute the fault mode state machine (call from OperationModes)
+void signalAlarmActionToFaultMode( ALARM_ACTION_T action ); // Execute alarm action as appropriate for fault mode
+
+/**@}*/
+
+#endif
Index: firmware/App/Modes/ModeInitPOST.c
===================================================================
diff -u
--- firmware/App/Modes/ModeInitPOST.c (revision 0)
+++ firmware/App/Modes/ModeInitPOST.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,566 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file ModeInitPOST.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include "reg_crc.h" // Used to hold reset reason code at startup before bits get cleared
+#include "reg_system.h" // Used to access exception status registers for reset reason code at startup
+#include "system.h"
+
+//#include "AlarmLamp.h"
+//#include "BloodFlow.h"
+//#include "Buttons.h"
+//#include "Compatible.h"
+//#include "CPLD.h"
+//#include "Fans.h"
+//#include "FPGA.h"
+//#include "Integrity.h"
+#include "Messaging.h"
+#include "ModeInitPOST.h"
+//#include "NVDataMgmt.h"
+#include "OperationModes.h"
+//#include "PresOccl.h"
+//#include "SyringePump.h"
+#include "SystemCommTD.h"
+#include "TaskGeneral.h"
+//#include "Temperatures.h"
+//#include "Valves.h"
+#include "WatchdogMgmt.h"
+
+ /**
+ * @addtogroup TDInitAndPOSTMode
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define START_POST_DELAY_COUNT ( ( 1 * MS_PER_SECOND ) / TASK_GENERAL_INTERVAL ) ///< Start POST delay in count.
+
+/// Delay (in task intervals) after POST completes.
+#define POST_COMPLETED_DELAY ( 2 * MS_PER_SECOND / TASK_GENERAL_INTERVAL )
+
+/// Maximum wait time for UI to send its final POST result.
+#define POST_UI_MAX_WAIT_TIME ( 2 * MS_PER_SECOND / TASK_GENERAL_INTERVAL )
+
+// ********** private data **********
+
+static HD_POST_STATE_T postState; ///< Current state of initialize and POST mode.
+static BOOL postCompleted; ///< Flag indicates whether POST is completed.
+static BOOL postPassed; ///< Flag indicates all POST tests passed.
+static BOOL tempPOSTPassed; ///< Flag indicates all POST tests have passed so far.
+
+static BOOL uiPOSTPassed; ///< Final result for UI POST tests (TRUE = passed, FALSE = failed).
+static BOOL dgPOSTPassed; ///< Final result for DG POST tests (TRUE = passed, FALSE = failed).
+static BOOL uiPOSTResultReceived; ///< Have we received a final POST result from the UI?
+static BOOL dgPOSTResultReceived; ///< Have we received a final POST result from the DG?
+static U32 waitForUIPostTimerCtr; ///< Timer counter to limit wait for UI final POST result.
+static U32 postCompleteDelayTimerCtr; ///< Timer counter for 2 second delay after POST completes and before transitioning to Standbymode.
+
+static UI_VERSIONS_T uiVersion = { 0, 0, 0, 0, 0 }; ///< Version and compatibility information reported by UI.
+static DD_VERSIONS_T dgVersion = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }; ///< Version and compatibility information reported by DG.
+static U32 startPOSTDelayCounter = 0; ///< Start POST delay counter.
+
+extern U32 savedResetReasonCode; ///< Saved reset reason code from sys_startup.c.
+
+// ********** private function prototypes **********
+
+static HD_POST_STATE_T handlePOSTStatus( SELF_TEST_STATUS_T testStatus );
+static HD_POST_STATE_T handlePOSTStateStart( void );
+static SELF_TEST_STATUS_T execFWCompatibilityTest( void );
+static SELF_TEST_STATUS_T execUITest( void );
+
+/*********************************************************************//**
+ * @brief
+ * The initInitAndPOSTMode function initializes the Initialize & POST Mode module.
+ * @details Inputs: none
+ * @details Outputs: Initialize & POST Mode module initialized.
+ * @return none
+ *************************************************************************/
+void initInitAndPOSTMode( void )
+{
+ postState = POST_STATE_START;
+ postCompleted = FALSE;
+ postPassed = FALSE;
+ tempPOSTPassed = TRUE;
+ uiPOSTPassed = FALSE;
+ dgPOSTPassed = FALSE;
+ uiPOSTResultReceived = FALSE;
+ dgPOSTResultReceived = FALSE;
+ waitForUIPostTimerCtr = 0;
+ postCompleteDelayTimerCtr = 0;
+ startPOSTDelayCounter = 0;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The transitionToInitAndPOSTMode function prepares for transition to
+ * initialize & POST mode.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return initial state
+ *************************************************************************/
+U32 transitionToInitAndPOSTMode( void )
+{
+ initInitAndPOSTMode();
+
+ // Set user alarm recovery actions allowed in this mode
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_RESUME, FALSE );
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_RINSEBACK, FALSE );
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_END_TREATMENT, FALSE );
+
+// resetNVDataMgmtPOSTState();
+// resetWatchdogPOSTState();
+// resetSafetyShutdownPOSTState();
+// resetValvesPOSTState();
+// resetAlarmAudioPOSTState();
+// resetAlarmLampPOSTState();
+// resetStuckButtonPOSTState();
+
+ return postState;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execInitAndPOSTMode function executes the Initialize & POST Mode
+ * state machine.
+ * @details Inputs: postState
+ * @details Outputs: postState, postPassed, postCompleted
+ * @return current state (sub-mode)
+ *************************************************************************/
+U32 execInitAndPOSTMode( void )
+{
+ SELF_TEST_STATUS_T testStatus = SELF_TEST_STATUS_IN_PROGRESS;
+// BOOL stop = isStopButtonPressed();
+//
+// if ( TRUE == stop )
+// {
+// // Ignore stop button in this mode.
+// }
+
+ // Execute current POST state *Note - these switch cases must be in same order as enum HD_POST_States
+ switch ( postState )
+ {
+ case POST_STATE_START:
+ postState = handlePOSTStateStart();
+ break;
+
+ case POST_STATE_FW_INTEGRITY:
+// testStatus = execIntegrityTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ // NOTE: all the actuators and sensors must execute their POST after NVDataMgmt
+ // NVDataMgmt must load all the calibration data into RAM so the actuators
+ // can query their corresponding calibration values successfully
+ case POST_STATE_NVDATAMGMT:
+// testStatus = execNVDataMgmtSelfTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_WATCHDOG:
+// testStatus = execWatchdogTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_SAFETY_SHUTDOWN:
+// testStatus = execSafetyShutdownTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_BLOOD_FLOW:
+// testStatus = execBloodFlowTest();
+ postState = handlePOSTStatus( testStatus );
+// sendUIRequestPOSTFinalResult(); // request UI POST final result here so we have it before UI test below
+ break;
+
+ case POST_STATE_VALVES:
+// testStatus = execValvesSelfTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_SYRINGE_PUMP:
+// testStatus = execSyringePumpSelfTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_PRES_OCCL:
+// testStatus = execPresOcclSelfTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_ALARM_AUDIO:
+#ifndef _RELEASE_
+// if ( getSoftwareConfigStatus( SW_CONFIG_DISABLE_ALARM_AUDIO ) != SW_CONFIG_ENABLE_VALUE )
+#endif
+// {
+// testStatus = execAlarmAudioSelfTest();
+// }
+#ifndef _RELEASE_
+// else
+ {
+ testStatus = SELF_TEST_STATUS_PASSED;
+ }
+#endif
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_ALARM_LAMP:
+// testStatus = execAlarmLampTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_TEMPERATURES:
+// testStatus = execTemperaturesSelfTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ // NOTE: fans self test must be called after temperatures since the
+ // temperatures must get their calibration first before the fans start monitoring
+ // for RPM out of range
+ case POST_STATE_FANS:
+// testStatus = execFansSelfTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_STUCK_BUTTON:
+// testStatus = execStuckButtonTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_UI_POST:
+// testStatus = execUITest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ case POST_STATE_FW_COMPATIBILITY:
+// testStatus = execFWCompatibilityTest();
+ postState = handlePOSTStatus( testStatus );
+ break;
+
+ // Should be last POST (and last POST test must be a test that completes in a single call)
+ case POST_STATE_FPGA:
+// testStatus = execFPGATest();
+ handlePOSTStatus( testStatus ); // Ignoring return value because last test
+ if ( TRUE == tempPOSTPassed )
+ {
+ postState = POST_STATE_COMPLETED;
+ }
+ else
+ {
+ postState = POST_STATE_FAILED;
+ }
+ break;
+
+ case POST_STATE_COMPLETED:
+
+ // Set overall HD POST completed status to TRUE
+ postCompleted = TRUE;
+ // Broadcast final POST passed once. We stay in this state for POST_COMPLETED_DELAY.
+ if ( FALSE == postPassed )
+ {
+// sendPOSTFinalResult( TRUE );
+ }
+ // Set overall HD POST status to "passed"
+ postPassed = TRUE;
+ // Delay before going to standby mode
+ if ( ++postCompleteDelayTimerCtr > POST_COMPLETED_DELAY )
+ {
+ requestNewOperationMode( MODE_STAN );
+ }
+ break;
+
+ case POST_STATE_FAILED:
+ // Should not get here - any failed post test should have already triggered a fault and taken us to fault mode
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_MODE_INIT_POST_INVALID_POST_STATE, postState )
+ break;
+ }
+
+ return postState;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalAlarmActionToInitAndPOSTMode function executes the given alarm action
+ * as appropriate while in InitAndPOST Mode.
+ * @details Inputs: none
+ * @details Outputs: given alarm action executed
+ * @param action ID of alarm action to execute
+ * @return none
+ *************************************************************************/
+void signalAlarmActionToInitAndPOSTMode( ALARM_ACTION_T action )
+{
+ // TODO - anything required here?
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalUIPOSTFinalResult function records the final POST result for
+ * the UI.
+ * @details Inputs: none
+ * @details Outputs: uiPOSTPassed
+ * @param passed TRUE if UI POST tests all passed, FALSE if any UI POST test failed
+ * @return none
+ *************************************************************************/
+void signalUIPOSTFinalResult( BOOL passed )
+{
+ uiPOSTPassed = passed;
+ uiPOSTResultReceived = TRUE;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalDDPOSTFinalResult function records the final POST result for
+ * the DD.
+ * @details Inputs: none
+ * @details Outputs: dgPOSTPassed, dgPOSTResultReceived
+ * @param passed TRUE if DD POST tests all passed, FALSE if any DD POST test failed
+ * @return none
+ *************************************************************************/
+void signalDDPOSTFinalResult( BOOL passed )
+{
+ dgPOSTPassed = passed;
+ dgPOSTResultReceived = TRUE;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDDPOSTPassed function gets the POST passed status of the DD sub-system.
+ * @details Inputs: dgPOSTPassed, dgPOSTResultReceived
+ * @details Outputs: none
+ * @return TRUE if DD POST result received and passed, FALSE if not
+ *************************************************************************/
+BOOL getDDPOSTPassed( void )
+{
+ BOOL result = ( TRUE == dgPOSTResultReceived && TRUE == dgPOSTPassed ? TRUE : FALSE );
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalUIVersion function records the reported UI version information.
+ * @details Inputs: none
+ * @details Outputs: uiVersion
+ * @param version Version information reported by UI
+ * @return none
+ *************************************************************************/
+void signalUIVersion( UI_VERSIONS_T version )
+{
+ uiVersion = version;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalDDVersion function records the reported DD version information.
+ * @details Inputs: none
+ * @details Outputs: dgVersion
+ * @param version Version information reported by DD
+ * @return none
+ *************************************************************************/
+void signalDDVersion( DD_VERSIONS_T version )
+{
+ dgVersion = version;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDDVersion function returns the DD version information.
+ * @details Inputs: dgVersion
+ * @details Outputs: none
+ * @return dgVersion
+ *************************************************************************/
+DD_VERSIONS_T getDDVersion( void )
+{
+ return dgVersion;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isPOSTCompleted function determines whether all HD POST have
+ * been run and completed. If true, call the isPOSTPassed() to see final
+ * result (pass/fail).
+ * @details Inputs: postCompleted
+ * @details Outputs: none
+ * @return true if all HD POST tests have completed, false if not
+ *************************************************************************/
+BOOL isPOSTCompleted( void )
+{
+ return postCompleted;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isPOSTPassed function determines whether all HD POST have passed.
+ * Call this function after POST is complete (call isPOSTCompleted function).
+ * @details Inputs: postPassed
+ * @details Outputs: none
+ * @return true if all HD POST tests have passed, false if not
+ *************************************************************************/
+BOOL isPOSTPassed( void )
+{
+ return postPassed;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isDGPOSTPassed function determines whether all DG POST have passed.
+ * @details Inputs: dgPOSTPassed
+ * @details Outputs: none
+ * @return true if all DG POST tests have passed, false if not
+ *************************************************************************/
+BOOL isDGPOSTPassed( void )
+{
+ return dgPOSTPassed;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handlePOSTStatus function handles a status result returned by a
+ * POST function.
+ * @details Inputs: testStatus
+ * @details Outputs: tempPOSTPassed
+ * @param testStatus status reported by last test
+ * @return recommended next POST state
+ *************************************************************************/
+static HD_POST_STATE_T handlePOSTStatus( SELF_TEST_STATUS_T testStatus )
+{
+ HD_POST_STATE_T result = postState;
+
+#ifdef BOARD_WITH_NO_HARDWARE
+ testStatus = SELF_TEST_STATUS_PASSED;
+#endif
+
+ if ( testStatus == SELF_TEST_STATUS_PASSED )
+ {
+ // Broadcast passed POST result
+// sendPOSTTestResult( (HD_POST_STATE_T)((int)postState), TRUE );
+ // Move on to next POST test
+ result = (HD_POST_STATE_T)((int)postState + 1);
+ }
+ else if ( testStatus == SELF_TEST_STATUS_FAILED )
+ {
+ // At least one POST has failed
+ tempPOSTPassed = FALSE;
+ // Broadcast failed POST results
+// sendPOSTTestResult( (HD_POST_STATE_T)((int)postState), FALSE );
+// sendPOSTFinalResult( FALSE );
+ // Test that failed should have triggered a fault which will request fault mode, so should POST state machine should never see FAILED state and will fault if it does
+ result = POST_STATE_FAILED;
+ }
+ else
+ {
+ // Test still in progress - do nothing
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handlePOSTStateStart function handles the POST start state.
+ * @details Inputs: startPOSTDelayCounter
+ * @details Outputs: startPOSTDelayCounter
+ * @return next POST state
+ *************************************************************************/
+static HD_POST_STATE_T handlePOSTStateStart( void )
+{
+ HD_POST_STATE_T state = POST_STATE_START;
+
+ // There is a delay before starting POST to make sure the CAN bus is up and listening so
+ // when the event data can be sent
+ if ( ++startPOSTDelayCounter > START_POST_DELAY_COUNT )
+ {
+ U32 resetReason = systemREG1->SYSESR | crcREG->PSA_SIGREGL1; // power-on reset bit preserved in an unused CRC register
+
+ systemREG1->SYSESR = systemREG1->SYSESR; // clear reset bit(s) after logging event so subsequent resets can be properly identified as not being power-on resets.
+ crcREG->PSA_SIGREGL1 = 0; // clear preserved power-on reset bit.
+
+// sendUIVersionRequest(); // request UI to send us its version - needed for compatibility check
+
+// if ( TRUE == isDGCommunicating() )
+// {
+// sendRequestForDGResendAlarms(); // request DG to re-send any active alarms that may have been triggered before we came up
+// }
+
+ // Send the startup event
+// SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_STARTUP, systemREG1->DEV, 0x12345678 ) // log startup event w/ device ID bits
+// SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_STARTUP, resetReason, systemREG1->GBLSTAT ) // log startup event w/ reset reason(s) bits
+
+ // Send the first submode change event. It is the mode Init and it does not start from a previous
+ // mode previous and current are both published as Init
+// SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_OP_MODE_CHANGE, MODE_INIT, MODE_INIT )
+ state = POST_STATE_COMPLETED; //POST_STATE_FW_INTEGRITY;
+ startPOSTDelayCounter = 0;
+ }
+
+ return state;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execFWCompatibilityTest function executes the firmware compatibility test.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return in progress, passed, or failed
+ *************************************************************************/
+static SELF_TEST_STATUS_T execFWCompatibilityTest( void )
+{
+ SELF_TEST_STATUS_T result = SELF_TEST_STATUS_PASSED;
+
+// if ( uiVersion.compatibility != SW_COMPATIBILITY_REV )
+// {
+// result = SELF_TEST_STATUS_FAILED;
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_UI_COMPATIBILITY_ERROR, uiVersion.compatibility, SW_COMPATIBILITY_REV )
+// }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execUITest function executes the UI POST passed test.
+ * @details Inputs: uiPOSTResultReceived, uiPOSTPassed, waitForUIPostTimerCtr
+ * @details Outputs: waitForUIPostTimerCtr
+ * @return in progress, passed, or failed
+ *************************************************************************/
+static SELF_TEST_STATUS_T execUITest( void )
+{
+ SELF_TEST_STATUS_T result = SELF_TEST_STATUS_IN_PROGRESS;
+
+ // UI should have sent POST results before we start this test
+// if ( TRUE == uiPOSTResultReceived )
+// {
+// if ( TRUE == uiPOSTPassed )
+ {
+ result = SELF_TEST_STATUS_PASSED;
+ }
+// else
+// {
+// SET_ALARM_WITH_1_U32_DATA( ALARM_ID_HD_UI_POST_TIMEOUT, 0 )
+// result = SELF_TEST_STATUS_FAILED;
+// }
+// }
+// // If UI had not already sent POST results before we started, allow finite period for UI to send.
+// else if ( ++waitForUIPostTimerCtr > POST_UI_MAX_WAIT_TIME )
+// {
+// SET_ALARM_WITH_1_U32_DATA( ALARM_ID_HD_UI_POST_TIMEOUT, 1 )
+// result = SELF_TEST_STATUS_FAILED;
+// }
+
+ return result;
+}
+
+/**@}*/
Index: firmware/App/Modes/ModeInitPOST.h
===================================================================
diff -u
--- firmware/App/Modes/ModeInitPOST.h (revision 0)
+++ firmware/App/Modes/ModeInitPOST.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,51 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file ModeInitPOST.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __MODE_INIT_POST_H__
+#define __MODE_INIT_POST_H__
+
+#include "TDCommon.h"
+#include "TDDefs.h"
+
+/**
+ * @defgroup TDInitAndPOSTMode TDInitAndPOSTMode
+ * @brief Initialization and POST mode module. Manages initialization and POST
+ * mode functions via a state machine.
+ *
+ * @addtogroup TDInitAndPOSTMode
+ * @{
+ */
+
+// ********** public function prototypes **********
+
+void initInitAndPOSTMode( void ); // Initialize this module
+U32 transitionToInitAndPOSTMode( void ); // Prepares for transition to init. & POST mode
+U32 execInitAndPOSTMode( void ); // Execute the init. & POST mode state machine (call from OperationModes)
+BOOL isPOSTCompleted( void ); // Determine whether POST has completed yet
+BOOL isPOSTPassed( void ); // Determine whether POST has passed
+BOOL isDGPOSTPassed( void ); // Determine whether DG POST has passed
+void signalAlarmActionToInitAndPOSTMode( ALARM_ACTION_T action ); // Execute alarm action as appropriate for fault mode
+void signalUIPOSTFinalResult( BOOL passed ); // Record UI POST result
+void signalDDPOSTFinalResult( BOOL passed ); // Record DD POST result
+void signalUIVersion( UI_VERSIONS_T version ); // Record UI version info
+void signalDDVersion( DD_VERSIONS_T version ); // Record DD version info
+DD_VERSIONS_T getDDVersion( void ); // Get DD version info
+BOOL getDDPOSTPassed( void ); // Get DD POST pass/fail status
+
+/**@}*/
+
+#endif
Index: firmware/App/Modes/ModeService.c
===================================================================
diff -u
--- firmware/App/Modes/ModeService.c (revision 0)
+++ firmware/App/Modes/ModeService.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,115 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file ModeService.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include "TDCommon.h"
+//#include "AirPump.h"
+//#include "BloodFlow.h"
+//#include "Buttons.h"
+//#include "DDInterface.h"
+#include "ModeService.h"
+//#include "NVDataMgmt.h"
+#include "OperationModes.h"
+//#include "Switches.h"
+//#include "SyringePump.h"
+//#include "Valves.h"
+
+/**
+ * @addtogroup TDServiceMode
+ * @{
+ */
+
+// ********** private data **********
+
+// ********** private function prototypes **********
+
+/*********************************************************************//**
+ * @brief
+ * The initServiceMode function initializes the Service Mode module.
+ * @details Inputs: none
+ * @details Outputs: Service Mode module initialized.
+ * @return none
+ *************************************************************************/
+void initServiceMode( void )
+{
+}
+
+/*********************************************************************//**
+ * @brief
+ * The transitionToServiceMode function prepares for transition to service mode.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return initial state
+ *************************************************************************/
+U32 transitionToServiceMode( void )
+{
+ initServiceMode();
+
+// doorClosedRequired( FALSE, FALSE );
+// syringeDetectionRequired( FALSE );
+ setCurrentSubState( NO_SUB_STATE );
+
+ // Set user alarm recovery actions allowed in this mode
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_RESUME, FALSE );
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_RINSEBACK, FALSE );
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_END_TREATMENT, FALSE );
+
+ // Start out with all actuators off in service mode (exception for valves which will be in insert position to allow cartridge insert)
+// stopSyringePump();
+// signalBloodPumpHardStop();
+// setAirPumpState( AIR_PUMP_STATE_OFF );
+
+// setValveAirTrap( STATE_CLOSED );
+// setValvePosition( VBA, VALVE_POSITION_A_INSERT_EJECT );
+// setValvePosition( VBV, VALVE_POSITION_A_INSERT_EJECT );
+
+ return 0;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execServiceMode function executes the Service Mode state machine.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return current state (sub-mode)
+ *************************************************************************/
+U32 execServiceMode( void )
+{
+// BOOL stop = isStopButtonPressed();
+//
+// if ( TRUE == stop )
+// {
+// // Ignore stop button in this mode.
+// }
+
+ return 0; // TODO - return current state
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalAlarmActionToServiceMode function executes the given alarm action
+ * as appropriate while in Service Mode.
+ * @details Inputs: none
+ * @details Outputs: given alarm action executed
+ * @param action ID of alarm action to execute
+ * @return none
+ *************************************************************************/
+void signalAlarmActionToServiceMode( ALARM_ACTION_T action )
+{
+ // TODO - implement
+}
+
+/**@}*/
Index: firmware/App/Modes/ModeService.h
===================================================================
diff -u
--- firmware/App/Modes/ModeService.h (revision 0)
+++ firmware/App/Modes/ModeService.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,41 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file ModeService.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __MODE_SERVICE_H__
+#define __MODE_SERVICE_H__
+
+#include "../TDCommon.h"
+#include "TDDefs.h"
+
+/**
+ * @defgroup TDServiceMode TDServiceMode
+ * @brief Service mode module.
+ *
+ * @addtogroup TDServiceMode
+ * @{
+ */
+
+// ********** public function prototypes **********
+
+void initServiceMode( void ); // Initialize this module
+U32 transitionToServiceMode( void ); // Prepares for transition to service mode
+U32 execServiceMode( void ); // Execute the service mode state machine (call from OperationModes)
+void signalAlarmActionToServiceMode( ALARM_ACTION_T action ); // Execute alarm action as appropriate for Service mode
+
+/**@}*/
+
+#endif
Index: firmware/App/Modes/ModeStandby.c
===================================================================
diff -u
--- firmware/App/Modes/ModeStandby.c (revision 0)
+++ firmware/App/Modes/ModeStandby.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,299 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file ModeStandby.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+
+#include "DDInterface.h"
+#include "Messaging.h"
+#include "ModeStandby.h"
+#include "OperationModes.h"
+
+/**
+ * @addtogroup TDStandbyMode
+ * @{
+ */
+
+// ********** private definitions **********
+
+// ********** private data **********
+
+static HD_STANDBY_STATE_T currentStandbyState; ///< Current state (sub-mode) of standby mode.
+static BOOL treatStartReqReceived; ///< Flag indicates user has requested initiation of a treatment.
+
+// ********** private function prototypes **********
+
+static HD_STANDBY_STATE_T handleStandbyModeStartState( void );
+static HD_STANDBY_STATE_T handleStandbyModeWaitForTreatmentState( void );
+
+/*********************************************************************//**
+ * @brief
+ * The initStandbyMode function initializes the Standby Mode module.
+ * @details Inputs: none
+ * @details Outputs: currentStandbyState, treatStartReqReceived,
+ * disinfectCancelReqID, homingInitiated
+ * @return none
+ *************************************************************************/
+void initStandbyMode( void )
+{
+ currentStandbyState = STANDBY_START_STATE;
+ treatStartReqReceived = FALSE;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The transitionToStandbyMode function prepares for transition to standby mode.
+ * @details Inputs: none
+ * @details Outputs: Standby Mode module re-initialized, DG interface initialized,
+ * blood & dialysate pumps shut off.
+ * @return initial state
+ *************************************************************************/
+U32 transitionToStandbyMode( void )
+{
+ TD_OP_MODE_T previousOpMode = getPreviousOperationMode();
+
+ // Re-initialize when transitioning to standby mode
+ initStandbyMode();
+ initDDInterface();
+ setCurrentSubState( NO_SUB_STATE );
+
+ // Set user alarm recovery actions allowed in this mode
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_RESUME, FALSE );
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_RINSEBACK, FALSE );
+ setAlarmUserActionEnabled( ALARM_USER_ACTION_END_TREATMENT, FALSE );
+
+ // Pumps should be off
+// signalBloodPumpHardStop();
+// stopSyringePump();
+
+ // Set valves to default positions
+// setValveAirTrap( STATE_CLOSED );
+// setValvePosition( VBA, VALVE_POSITION_A_INSERT_EJECT );
+// setValvePosition( VBV, VALVE_POSITION_A_INSERT_EJECT );
+
+// doorClosedRequired( FALSE, FALSE ); // door no longer required to be closed in standby mode
+// syringeDetectionRequired( FALSE );
+
+ // Request DD service record and usage information from DD
+// sendDGServiceRequestToDG();
+// sendDGUsageInfoRequestToDG();
+
+ return currentStandbyState;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execStandbyMode function executes the Standby Mode state machine.
+ * @details Inputs: currentStandbyState
+ * @details Outputs: currentStandbyState
+ * @return current state (sub-mode)
+ *************************************************************************/
+U32 execStandbyMode( void )
+{
+// BOOL stop = isStopButtonPressed();
+
+ // State machine to get DG to prep a reservoir so we can start a treatment
+ switch ( currentStandbyState )
+ {
+ case STANDBY_START_STATE:
+ currentStandbyState = handleStandbyModeStartState();
+ break;
+
+ case STANDBY_WAIT_FOR_TREATMENT_STATE:
+ currentStandbyState = handleStandbyModeWaitForTreatmentState();
+ break;
+
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_MODE_STANDBY_INVALID_STATE, currentStandbyState );
+ currentStandbyState = STANDBY_START_STATE;
+ break;
+ }
+
+ return currentStandbyState;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handleStandbyModeStartState function handles the standby start state.
+ * This state waits for the door to be closed and then initiates homing of
+ * pumps and valves and transitions to the wait for treatment state.
+ * @details Inputs:
+ * @details Outputs:
+ * @return next state of the standby mode state machine
+ *************************************************************************/
+static HD_STANDBY_STATE_T handleStandbyModeStartState( void )
+{
+ HD_STANDBY_STATE_T state = STANDBY_WAIT_FOR_TREATMENT_STATE;
+
+ // Wait for door to be closed so we can home actuators
+// if ( STATE_CLOSED == getSwitchStatus( FRONT_DOOR ) )
+// {
+// // If we haven't already initiated homing of actuators, initiate now
+// if ( homingInitiated != TRUE )
+// {
+// VALVE_T valve;
+//
+// // Home pumps and valves
+// for ( valve = VDI; valve < NUM_OF_VALVES; ++valve )
+// {
+// homeValve( valve, VALVE_NO_FORCE_HOME, VALVE_CARTRIDGE_MAY_BE_PRESENT );
+// }
+// homeBloodPump();
+// homeDialInPump();
+// homeDialOutPump();
+// retractSyringePump();
+//
+// homingInitiated = TRUE;
+// }
+// else
+// {
+// // If homing has been initiated, wait for syringe pump to home and the verify force sensor calibration
+//#ifndef _RELEASE_
+// if ( SW_CONFIG_ENABLE_VALUE == getSoftwareConfigStatus( SW_CONFIG_DISABLE_SYRINGE_PUMP ) )
+// {
+// state = STANDBY_WAIT_FOR_TREATMENT_STATE; // Go to wait for treatment state after above check
+// }
+// else
+//#endif
+// {
+// if ( ( TRUE == isSyringePumpHome() ) && ( TRUE == isSyringePumpStopped() ) )
+// {
+// syringePumpVerifyForceSensorDACCalibration();
+// homingInitiated = FALSE; // reset for next time
+// doorClosedRequired( FALSE, FALSE ); // door no longer required to be closed in standby mode
+// state = STANDBY_WAIT_FOR_TREATMENT_STATE; // Go to wait for treatment state after above check
+// }
+// }
+// }
+// }
+
+ return state;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handleStandbyModeWaitForTreatmentState function handles wait for
+ * treatment state.
+ * @details Inputs: treatStartReqReceived
+ * @details Outputs: treatStartReqReceived
+ * @return next state of the standby mode state machine
+ *************************************************************************/
+static HD_STANDBY_STATE_T handleStandbyModeWaitForTreatmentState( void )
+{
+ HD_STANDBY_STATE_T state = STANDBY_WAIT_FOR_TREATMENT_STATE;
+// DG_OP_MODE_T dgOperationMode = getDDOpMode();
+
+// switch ( dgOperationMode )
+// {
+// case DG_MODE_GENE:
+// // If DG is in idle generation state while we are in standby mode, transition DG to standby too
+// cmdStopDG();
+// break;
+//
+// // If DG is any of the cleaning modes, set the HD standby to be in the corresponding cleaning mode
+// case DG_MODE_FLUS:
+// case DG_MODE_HEAT:
+// case DG_MODE_CHEM:
+// case DG_MODE_CHFL:
+// case DG_MODE_HCOL:
+// case DG_MODE_ROPS:
+// setRequestedCleaningMode( dgOperationMode );
+// state = STANDBY_WAIT_FOR_DG_CLEANING_MODE_TO_START_STATE;
+// break;
+//
+// default:
+// // Do nothing. There are other DG modes that HD standby does not need to act upon them.
+// break;
+// }
+
+ // If DD is communicating and we don't yet have DD version info, request it
+// if ( TRUE == isDDCommunicating() )
+// {
+// DG_VERSIONS_T ddVersion = getDDVersion();
+//
+// if ( 0 == dgVersion.compatibilityRev )
+// {
+// sendFWVersionRequest();
+// }
+// }
+
+ // If treatment start is requested by user, initiate treatment workflow (transition to treatment params mode).
+ if ( TRUE == treatStartReqReceived )
+ {
+// PRESSURE_LIMIT_CHANGE_RESPONSE_T respRecord = { TRUE, REQUEST_REJECT_REASON_NONE, 0, 0, 0 };
+
+ // Initialize treatment modes before starting a new treatment
+// initTreatParamsMode();
+// initPreTreatmentMode();
+// initTreatmentMode();
+// initPostTreatmentMode();
+ // Send UI default pressure settings since user is not asked to set them.
+// respRecord.artPresLimitWindowmmHg = getTreatmentParameterS32DefaultValue( TREATMENT_PARAM_ART_PRES_LIMIT_WINDOW );
+// respRecord.venPresLimitWindowmmHg = getTreatmentParameterS32DefaultValue( TREATMENT_PARAM_VEN_PRES_LIMIT_WINDOW );
+// respRecord.venPresLimitAsymmetricmmHg = getTreatmentParameterS32DefaultValue( TREATMENT_PARAM_VEN_PRES_LIMIT_ASYMMETRIC );
+// sendPressureLimitsChangeResponse( &respRecord );
+ // Start treatment workflow with treatment parameters mode
+// requestNewOperationMode( MODE_TPAR );
+// treatStartReqReceived = FALSE;
+ }
+
+ return state;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalAlarmActionToStandbyMode function executes the given alarm action
+ * as appropriate while in Standby Mode.
+ * @details Inputs: none
+ * @details Outputs: given alarm action executed
+ * @param action ID of alarm action to execute
+ * @return none
+ *************************************************************************/
+void signalAlarmActionToStandbyMode( ALARM_ACTION_T action )
+{
+ switch ( action )
+ {
+ case ALARM_ACTION_STOP:
+ if ( isAlarmActive( ALARM_ID_HD_VENOUS_BUBBLE_DETECTED ) != TRUE )
+ {
+ // no stop action in standby mode
+ }
+ // if Dialin enabled bubble detection, stop on venous bubble detection alarm
+ else
+ {
+// // Pumps should be off
+// signalBloodPumpHardStop();
+// stopSyringePump();
+//
+// // Set valves to safe positions
+// setValveAirTrap( STATE_CLOSED );
+// setValvePosition( VBA, VALVE_POSITION_C_CLOSE );
+// setValvePosition( VBV, VALVE_POSITION_C_CLOSE );
+ }
+ break;
+
+ default:
+ // do not handle other actions in standby mode
+ break;
+ }
+}
+
+
+/*************************************************************************
+ * TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/**@}*/
Index: firmware/App/Modes/ModeStandby.h
===================================================================
diff -u
--- firmware/App/Modes/ModeStandby.h (revision 0)
+++ firmware/App/Modes/ModeStandby.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,44 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file ModeStandby.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __MODE_STANDBY_H__
+#define __MODE_STANDBY_H__
+
+#include "TDCommon.h"
+#include "TDDefs.h"
+
+/**
+ * @defgroup TDStandbyMode TDStandbyMode
+ * @brief StandbyMode module.
+ *
+ * @addtogroup TDStandbyMode
+ * @{
+ */
+
+// ********** public definitions **********
+
+// ********** public function prototypes **********
+
+void initStandbyMode( void ); // Initialize this module
+U32 transitionToStandbyMode( void ); // Prepares for transition to standby mode
+U32 execStandbyMode( void ); // Execute the standby mode state machine (call from OperationModes)
+
+void signalAlarmActionToStandbyMode( ALARM_ACTION_T action ); // Execute alarm action as appropriate for Standby mode
+
+/**@}*/
+
+#endif
Index: firmware/App/Modes/OperationModes.c
===================================================================
diff -u
--- firmware/App/Modes/OperationModes.c (revision 0)
+++ firmware/App/Modes/OperationModes.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,711 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file OperationModes.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include
+#include
+#include "gio.h"
+
+#include "ModeInitPOST.h"
+#include "ModeService.h"
+#include "ModeFault.h"
+#include "ModeStandby.h"
+//#include "ModeTreatmentParams.h"
+//#include "ModePreTreat.h"
+//#include "ModeTreatment.h"
+//#include "ModePostTreat.h"
+//#include "NVDataMgmt.h"
+#include "OperationModes.h"
+#include "TaskGeneral.h"
+#include "Timers.h"
+
+/**
+ * @addtogroup TDOperationModes
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define BROADCAST_TD_OP_MODE_INTERVAL ( 250 / TASK_GENERAL_INTERVAL ) ///< TD operation mode broadcast interval (in task interval/sec).
+#define DATA_PUBLISH_COUNTER_START_COUNT 11 ///< Data publish counter start count.
+#define MAX_PENDING_CONFIRM_REQUESTS 4 ///< Maximum number of confirmation requests allowed at any given time.
+
+/// Structure for confirmation request.
+typedef struct
+{
+ GENERIC_CONFIRM_ID_T requestID; ///< Request ID
+ GENERIC_CONFIRM_COMMAND_T requestType; ///< Request Type
+ U32 timeStamp; ///< Timestamp for request
+ CONFIRMATION_REQUEST_STATUS_T status; ///< Request status (pending, accepted, rejected)
+} CONFIRMATION_REQUEST_T;
+
+// ********** private data **********
+
+static volatile BOOL modeRequest[ NUM_OF_MODES - 1 ]; ///< Pending operation mode change requests.
+static TD_OP_MODE_T lastMode; ///< Last operation mode prior to current mode.
+static TD_OP_MODE_T currentMode; ///< Current operation mode.
+static U32 currentSubMode; ///< The currently active state of the active mode.
+static U32 broadcastModeIntervalCtr; ///< Interval counter used to determine when to broadcast operation mode. Initialize to 11 to stagger broadcast.
+static U32 currentSubState; ///< current sub state.
+static U32 current4thLevelState; ///< current 4th level state.
+
+/// Interval (in task intervals) at which to publish operation mode data to CAN bus.
+static OVERRIDE_U32_T opModePublishInterval = { BROADCAST_TD_OP_MODE_INTERVAL, BROADCAST_TD_OP_MODE_INTERVAL, BROADCAST_TD_OP_MODE_INTERVAL, 0 };
+/// Local structure init for saving confirmation requests
+static CONFIRMATION_REQUEST_T confirmRequests[ MAX_PENDING_CONFIRM_REQUESTS ] =
+ { GENERIC_CONFIRM_ID_NONE, GENERIC_CONFIRM_CMD_REQUEST_OPEN, 0, CONFIRMATION_REQUEST_STATUS_UNUSED,
+ GENERIC_CONFIRM_ID_NONE, GENERIC_CONFIRM_CMD_REQUEST_OPEN, 0, CONFIRMATION_REQUEST_STATUS_UNUSED,
+ GENERIC_CONFIRM_ID_NONE, GENERIC_CONFIRM_CMD_REQUEST_OPEN, 0, CONFIRMATION_REQUEST_STATUS_UNUSED,
+ GENERIC_CONFIRM_ID_NONE, GENERIC_CONFIRM_CMD_REQUEST_OPEN, 0, CONFIRMATION_REQUEST_STATUS_UNUSED, };
+
+/// This matrix determines legal transitions from one mode to another
+static const TD_OP_MODE_T MODE_TRANSITION_TABLE[ NUM_OF_MODES - 1 ][ NUM_OF_MODES - 1 ] = {
+// From to-> FAULT SERVICE INIT STANBY TRT.PARAMS PRE-TREAT TREATMENT POST_TREA
+/* FAUL */{ MODE_FAUL, MODE_SERV, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, },
+/* SERV */{ MODE_NLEG, MODE_SERV, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, },
+/* INIT */{ MODE_FAUL, MODE_NLEG, MODE_INIT, MODE_STAN, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, },
+/* STAN */{ MODE_FAUL, MODE_SERV, MODE_INIT, MODE_STAN, MODE_TPAR, MODE_NLEG, MODE_NLEG, MODE_NLEG, },
+/* TPAR */{ MODE_FAUL, MODE_NLEG, MODE_NLEG, MODE_STAN, MODE_TPAR, MODE_PRET, MODE_NLEG, MODE_NLEG, },
+/* PRET */{ MODE_FAUL, MODE_NLEG, MODE_NLEG, MODE_STAN, MODE_NLEG, MODE_PRET, MODE_TREA, MODE_POST, },
+/* TREA */{ MODE_FAUL, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_TREA, MODE_POST, },
+/* POST */{ MODE_FAUL, MODE_NLEG, MODE_NLEG, MODE_STAN, MODE_NLEG, MODE_NLEG, MODE_NLEG, MODE_POST, }, };
+
+// ********** private function prototypes **********
+
+static TD_OP_MODE_T arbitrateModeRequest( void );
+static void transitionToNewOperationMode( TD_OP_MODE_T newMode );
+static void broadcastOperationMode( void );
+
+/*********************************************************************//**
+ * @brief
+ * The initOperationModes function initializes the Operation Modes module.
+ * @details Inputs: none
+ * @details Outputs: Operation Modes module initialized.
+ * @return none
+ *************************************************************************/
+void initOperationModes( void )
+{
+ U32 i;
+
+ // Initialize mode requests to none pending
+ for ( i = 0; i < ( NUM_OF_MODES - 1 ); i++ )
+ {
+ modeRequest[ i ] = FALSE;
+ }
+
+ // Start in init mode
+ lastMode = MODE_INIT;
+ currentMode = MODE_INIT;
+ currentSubMode = 0;
+ currentSubState = NO_SUB_STATE;
+ current4thLevelState = NO_SUB_STATE;
+ broadcastModeIntervalCtr = DATA_PUBLISH_COUNTER_START_COUNT;
+
+ transitionToNewOperationMode( MODE_INIT );
+
+ // Call initializers for the individual modes
+ initFaultMode();
+ initServiceMode();
+ initInitAndPOSTMode();
+ initStandbyMode();
+// initTreatParamsMode();
+// initPreTreatmentMode();
+// initTreatmentMode();
+// initPostTreatmentMode();
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execOperationModes function executes the Operation Modes state machine.
+ * @details Inputs: none
+ * @details Outputs: currentMode is set by state machine.
+ * @return none
+ *************************************************************************/
+void execOperationModes( void )
+{
+ TD_OP_MODE_T newMode;
+ U32 priorSubMode = currentSubMode;
+ U32 priorSubState = currentSubState;
+ U32 prior4thLevelState = current4thLevelState;
+
+ // Any new mode requests?
+ newMode = arbitrateModeRequest(); // Will return current mode if no pending requests
+
+ if ( getTestConfigStatus( TEST_CONFIG_RECOVER_TREATMENT ) != TRUE )
+ {
+ newMode = MODE_TRANSITION_TABLE[ currentMode ][ newMode ];
+ }
+
+ // Is requested new mode valid and legal at this time?
+ if ( newMode >= MODE_NLEG )
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_OP_MODES_ILLEGAL_MODE_TRANSITION_REQUESTED, newMode )
+ newMode = currentMode;
+ }
+
+ // Has mode changed?
+ if ( currentMode != newMode )
+ {
+ lastMode = currentMode;
+ // Handle transition to new mode
+ transitionToNewOperationMode( newMode );
+ currentMode = newMode;
+
+ if ( MODE_TREA == lastMode )
+ {
+ // If the last mode is treatment but the new mode is not treatment
+ // it means the treatment is done. Get the elapsed time since the beginning of the treatment and convert it to hours to be written
+// U32 txElapsedTimeMS = calcTimeSince( getTreatmentStartTimeStamp() );
+// F32 txElapsedTimeHrs = (F32)txElapsedTimeMS / ( (F32)( MIN_PER_HOUR * SEC_PER_MIN * MS_PER_SECOND ) );
+ // Write the treatment hours and set the service to be false so the treatment hours is not reset
+// setTxTimeHours( txElapsedTimeHrs );
+ }
+ sendOperationStatusEvent();
+ }
+
+ // Mode specific processing to be done continuously
+ switch ( currentMode )
+ {
+ case MODE_FAUL:
+ currentSubMode = execFaultMode();
+ break;
+
+ case MODE_SERV:
+ currentSubMode = execServiceMode();
+ break;
+
+ case MODE_INIT:
+ currentSubMode = execInitAndPOSTMode();
+ break;
+
+ case MODE_STAN:
+ currentSubMode = execStandbyMode();
+ break;
+
+// case MODE_TPAR:
+// currentSubMode = execTreatParamsMode();
+// break;
+//
+// case MODE_PRET:
+// currentSubMode = execPreTreatmentMode();
+// break;
+//
+// case MODE_TREA:
+// currentSubMode = execTreatmentMode();
+// break;
+//
+// case MODE_POST:
+// currentSubMode = execPostTreatmentMode();
+// break;
+
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_OP_MODES_INVALID_MODE_STATE, currentMode )
+ currentMode = MODE_FAUL;
+ currentSubMode = 0;
+ break;
+ } // End switch
+
+#ifndef _VECTORCAST_
+ // Send operation status event when appropriate
+ if ( ( priorSubMode != currentSubMode ) || ( priorSubState != currentSubState ) || ( prior4thLevelState != current4thLevelState ) )
+#endif
+ {
+ sendOperationStatusEvent();
+ SEND_EVENT_WITH_2_U32_DATA( TD_EVENT_SUB_MODE_CHANGE, priorSubMode, currentSubMode )
+ }
+
+ // Broadcast current operation mode on interval
+ broadcastOperationMode();
+}
+
+/*********************************************************************//**
+ * @brief
+ * The requestNewOperationMode function requests transition to a new
+ * operation mode. The request will be arbitrated when the state machine
+ * is next executed.
+ * @details Inputs: none
+ * @details Outputs: modeRequest[]
+ * @return none
+ *************************************************************************/
+void requestNewOperationMode( TD_OP_MODE_T newMode )
+{
+ // Validate requested mode
+ if ( newMode < MODE_NLEG )
+ {
+ // Make request
+ modeRequest[ newMode ] = TRUE;
+ }
+ else
+ { // Invalid mode requested
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_OP_MODES_INVALID_MODE_REQUESTED, newMode )
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getCurrentOperationMode function gets the current operation mode.
+ * @details Inputs: currentMode
+ * @details Outputs: none
+ * @return the current operation mode
+ *************************************************************************/
+TD_OP_MODE_T getCurrentOperationMode( void )
+{
+ return currentMode;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getPreviousOperationMode function gets the previous operation mode.
+ * @details Inputs: lastMode
+ * @details Outputs: none
+ * @return the previous operation mode
+ *************************************************************************/
+TD_OP_MODE_T getPreviousOperationMode( void )
+{
+ return lastMode;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getCurrentSubMode function gets the current operation sub-mode.
+ * @details Inputs: currentSubMode
+ * @details Outputs: none
+ * @return the current operation sub-mode
+ *************************************************************************/
+U32 getCurrentSubMode( void )
+{
+ return currentSubMode;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The initiateAlarmAction function initiate an alarm or alarm recovery
+ * action according to the current operation mode.
+ * @details Inputs: currentMode
+ * @details Outputs: given action forwarded to current operation mode for execution
+ * @param action ID of action to be initiated
+ * @return none
+ *************************************************************************/
+void initiateAlarmAction( ALARM_ACTION_T action )
+{
+ // Forward request to the current operation mode
+ switch ( currentMode )
+ {
+ case MODE_FAUL:
+ signalAlarmActionToFaultMode( action );
+ break;
+ case MODE_SERV:
+ signalAlarmActionToServiceMode( action );
+ break;
+ case MODE_INIT:
+ signalAlarmActionToInitAndPOSTMode( action );
+ break;
+ case MODE_STAN:
+ signalAlarmActionToStandbyMode( action );
+ break;
+// case MODE_TPAR:
+// signalAlarmActionToTreatParamsMode( action );
+// break;
+// case MODE_PRET:
+// signalAlarmActionToPreTreatmentMode( action );
+// break;
+// case MODE_TREA:
+// signalAlarmActionToTreatmentMode( action );
+// break;
+// case MODE_POST:
+// signalAlarmActionToPostTreatmentMode( action );
+// break;
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_OP_MODES_INVALID_MODE_TO_SIGNAL_ACTION, currentMode )
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The arbitrateModeRequest function arbitrates any pending mode transition
+ * requests.
+ * @details Inputs: modeRequest[]
+ * @details Outputs: modeRequest[] is reset
+ * @return the next operation mode (current mode if no requests pending)
+ *************************************************************************/
+static TD_OP_MODE_T arbitrateModeRequest( void )
+{
+ TD_OP_MODE_T reqMode = currentMode;
+ U32 i;
+
+ // Block additional requests until after mode arbitration
+ _disable_IRQ();
+
+ // Select highest priority mode request -or- current mode if no requests pending
+ for ( i = 0; i < MODE_NLEG; i++ )
+ {
+ if ( modeRequest[ i ] != FALSE )
+ {
+ reqMode = (TD_OP_MODE_T)i;
+ break;
+ }
+ }
+
+ // Clear all requests now that an arbitration winner is selected
+ for ( i = 0; i < MODE_NLEG; i++ )
+ {
+ modeRequest[ i ] = FALSE;
+ }
+
+ // Un-block requests
+ _enable_IRQ();
+
+ return reqMode;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The transitionToNewOperationMode function calls the transition to function
+ * for a new operation mode that we are transitioning to.
+ * @details Inputs: none
+ * @details Outputs: transition function called for new mode
+ * @return none
+ *************************************************************************/
+static void transitionToNewOperationMode( TD_OP_MODE_T newMode )
+{
+ // Setup for new operating mode
+ switch ( newMode )
+ {
+ case MODE_FAUL:
+ currentSubMode = transitionToFaultMode();
+ break;
+ case MODE_SERV:
+ currentSubMode = transitionToServiceMode();
+ break;
+ case MODE_INIT:
+ currentSubMode = transitionToInitAndPOSTMode();
+ break;
+ case MODE_STAN:
+ currentSubMode = transitionToStandbyMode();
+ break;
+// case MODE_TPAR:
+// currentSubMode = transitionToTreatParamsMode();
+// break;
+// case MODE_PRET:
+// currentSubMode = transitionToPreTreatmentMode();
+// break;
+// case MODE_TREA:
+// currentSubMode = transitionToTreatmentMode();
+// break;
+// case MODE_POST:
+// currentSubMode = transitionToPostTreatmentMode();
+// break;
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_OP_MODES_INVALID_MODE_TO_TRANSITION_TO, newMode )
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The broadcastOperationMode function sends the current operation mode at
+ * the prescribed interval.
+ * @details Inputs: broadcastModeIntervalCtr
+ * @details Outputs: HD operation mode broadcast message sent.
+ * @return none
+ *************************************************************************/
+static void broadcastOperationMode( void )
+{
+ if ( ++broadcastModeIntervalCtr >= getU32OverrideValue( &opModePublishInterval ) )
+ {
+ OP_MODE_PAYLOAD_T data;
+
+ broadcastModeIntervalCtr = 0;
+ data.opMode = (U32)currentMode;
+ data.subMode = currentSubMode;
+ broadcastData( MSG_ID_HD_OP_MODE_DATA, COMM_BUFFER_OUT_CAN_TD_BROADCAST, (U08*)&data, sizeof( OP_MODE_PAYLOAD_T ) );
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getConfirmationRequestStatus function returns the status of a confirmation request
+ * @details Inputs: confirmRequests[]
+ * @details Outputs: confirmRequests[] consumed/cleared if completed.
+ * @param requestID ID of confirmation being requested
+ * @return Status of given confirmation
+ *************************************************************************/
+CONFIRMATION_REQUEST_STATUS_T getConfirmationRequestStatus( GENERIC_CONFIRM_ID_T requestID )
+{
+// BOOL pending = FALSE;
+// U32 pendingIndex = 0;
+ CONFIRMATION_REQUEST_STATUS_T status = CONFIRMATION_REQUEST_STATUS_PENDING;
+// U32 i;
+
+// for ( i = 0; i < MAX_PENDING_CONFIRM_REQUESTS; i++ )
+// {
+// if ( confirmRequests[ i ].requestID == requestID )
+// {
+// status = confirmRequests[ i ].status;
+// if ( status != CONFIRMATION_REQUEST_STATUS_PENDING )
+// {
+// // Send UI clear
+// if ( CONFIRMATION_REQUEST_STATUS_TIMEOUT == status )
+// {
+// sendConfirmationRequest( confirmRequests[ i ].requestID, GENERIC_CONFIRM_CMD_TIMEOUT_CLOSE, 0 );
+// }
+// else
+// {
+// sendConfirmationRequest( confirmRequests[ i ].requestID, GENERIC_CONFIRM_CMD_ACCEPT_CLOSE, 0 );
+// }
+//
+// // Clear the confirmation request, it is done and consumed
+// confirmRequests[ i ].requestID = GENERIC_CONFIRM_ID_NONE;
+// confirmRequests[ i ].requestType = GENERIC_CONFIRM_CMD_REQUEST_OPEN;
+// confirmRequests[ i ].timeStamp = 0;
+// confirmRequests[ i ].status = CONFIRMATION_REQUEST_STATUS_UNUSED;
+// }
+// }
+// else if ( CONFIRMATION_REQUEST_STATUS_PENDING == confirmRequests[ i ].status )
+// {
+// if ( TRUE == pending )
+// {
+// // Is this newer than other pending request?
+// if ( confirmRequests[ i ].timeStamp > confirmRequests[ pendingIndex ].timeStamp )
+// {
+// pendingIndex = i;
+// }
+// }
+// else
+// {
+// pendingIndex = i;
+// pending = TRUE;
+// }
+// }
+// }
+//
+// if ( ( CONFIRMATION_REQUEST_STATUS_PENDING != status ) && ( TRUE == pending ) )
+// {
+// // Last confirmation cleared, pending request must be resent to UI
+// sendConfirmationRequest( confirmRequests[ pendingIndex ].requestID, confirmRequests[ pendingIndex ].requestType, 0 );
+// }
+
+ return status;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setConfirmationRequestStatus function sets the status of a confirmation request
+ * @details Inputs: confirmRequests[]
+ * @details Outputs: confirmRequests[].
+ * @param requestID ID of confirmation being requested
+ * @param status Status to set for given confirmation (open, close, reject)
+ * @return none
+ *************************************************************************/
+void setConfirmationRequestStatus( GENERIC_CONFIRM_ID_T requestID, CONFIRMATION_REQUEST_STATUS_T status )
+{
+ U32 i;
+
+ for ( i = 0; i < MAX_PENDING_CONFIRM_REQUESTS; i++ )
+ {
+ if ( confirmRequests[ i ].requestID == requestID )
+ {
+ confirmRequests[ i ].status = status;
+ break;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The addConfirmationRequest function sends a confirmation request to UI
+ * @details Inputs: confirmRequests[]
+ * @details Outputs: confirmRequests[] new added.
+ * @param requestID ID of confirmation being requested
+ * @param requestType Type of confirmation being requested (open, close, reject)
+ * @param rejectReason Reason for reject if type is reject
+ * @return request ID - will be non-zero if added
+ *************************************************************************/
+GENERIC_CONFIRM_ID_T addConfirmationRequest( GENERIC_CONFIRM_ID_T requestID, GENERIC_CONFIRM_COMMAND_T requestType, U32 rejectReason )
+{
+// U32 i;
+// BOOL confirmAlreadyPending = FALSE;
+ GENERIC_CONFIRM_ID_T newID = GENERIC_CONFIRM_ID_NONE;
+
+// // Check to make sure specified confirmation is not already pending
+// for ( i = 0; i < MAX_PENDING_CONFIRM_REQUESTS; i++ )
+// {
+// if ( ( confirmRequests[ i ].requestID == requestID ) &&
+// ( confirmRequests[ i ].status != CONFIRMATION_REQUEST_STATUS_UNUSED ) )
+// {
+// confirmAlreadyPending = TRUE;
+// break;
+// }
+// }
+//
+// // If not already pending, add confirmation to list of pending confirmations and send to UI to be displayed
+// if ( confirmAlreadyPending != TRUE )
+// {
+// for ( i = 0; i < MAX_PENDING_CONFIRM_REQUESTS; i++ )
+// {
+// if ( CONFIRMATION_REQUEST_STATUS_UNUSED == confirmRequests[ i ].status )
+// {
+// // Save the confirmation request info
+// confirmRequests[ i ].requestID = requestID;
+// confirmRequests[ i ].requestType = requestType;
+// confirmRequests[ i ].timeStamp = getMSTimerCount();
+// confirmRequests[ i ].status = CONFIRMATION_REQUEST_STATUS_PENDING;
+// newID = requestID;
+// sendConfirmationRequest( requestID, requestType, rejectReason );
+// break;
+// }
+// }
+// }
+
+ return newID;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setCurrentSubState function sets the current subState.
+ * @details Inputs: subState
+ * @details Outputs: currentSubState
+ * @param subState the enumerated sub state.
+ * @return none
+ *************************************************************************/
+void setCurrentSubState( U32 subState )
+{
+ currentSubState = subState;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setCurrent4thLevelState function sets the current 4th level state.
+ * @details Inputs: state
+ * @details Outputs: current4thLevelState
+ * @param subState the enumerated sub state.
+ * @return none
+ *************************************************************************/
+void setCurrent4thLevelState( U32 state )
+{
+ current4thLevelState = state;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The sendOperationStatusEvent function constructs and sends an HD operation
+ * status event.
+ * @details Inputs: currentMode, currentSubMode, currentSubState, current4thLevelState
+ * @details Outputs: dat1, dat2.
+ * @param none
+ * @return none
+ *************************************************************************/
+void sendOperationStatusEvent( void )
+{
+ EVENT_DATA_T dat1;
+ EVENT_DATA_T dat2;
+ U32 opData = ( (U08)currentMode +
+ ( (U08)currentSubMode << SHIFT_8_BITS_FOR_BYTE_SHIFT ) +
+ ( (U08)currentSubState << SHIFT_16_BITS_FOR_WORD_SHIFT ) +
+ ( (U08)current4thLevelState << SHIFT_24_BITS ) );
+
+ dat2.dataType = EVENT_DATA_TYPE_U32;
+ dat2.data.uInt.data = 0;
+
+ dat1.dataType = EVENT_DATA_TYPE_U32;
+ dat1.data.uInt.data = opData;
+
+ sendEvent( TD_EVENT_OPERATION_STATUS, dat1, dat2 );
+}
+
+
+/*************************************************************************
+ * TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/*********************************************************************//**
+ * @brief
+ * The testSetOperationMode function will transition to a given operation
+ * mode if the transition is legal.
+ * @details Inputs: none
+ * @details Outputs: modeRequest[]
+ * @param newMode ID of requested mode to transition to
+ * @return TRUE if request successful, FALSE if not
+ *************************************************************************/
+BOOL testSetOperationMode( TD_OP_MODE_T newMode )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ TD_OP_MODE_T check = MODE_TRANSITION_TABLE[ currentMode ][ newMode ];
+
+ // Is mode transition legal?
+ if ( check == newMode )
+ {
+ requestNewOperationMode( newMode );
+ result = TRUE;
+ }
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testSetOpModePublishIntervalOverride function sets the override of the
+ * operation mode publication interval.
+ * @details Inputs: none
+ * @details Outputs: opModePublishInterval
+ * @param ms milliseconds between operation mode broadcasts
+ * @return TRUE if override set successful, FALSE if not
+ *************************************************************************/
+BOOL testSetOpModePublishIntervalOverride( U32 ms )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ U32 intvl = ms / TASK_GENERAL_INTERVAL;
+
+ result = TRUE;
+ opModePublishInterval.ovData = intvl;
+ opModePublishInterval.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetOpModePublishIntervalOverride function resets the override of the
+ * operation mode data publication interval.
+ * @details Inputs: none
+ * @details Outputs: opModePublishInterval
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetOpModePublishIntervalOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ opModePublishInterval.override = OVERRIDE_RESET;
+ opModePublishInterval.ovData = opModePublishInterval.ovInitData;
+ }
+
+ return result;
+}
+
+/**@}*/
Index: firmware/App/Modes/OperationModes.h
===================================================================
diff -u
--- firmware/App/Modes/OperationModes.h (revision 0)
+++ firmware/App/Modes/OperationModes.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,65 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file OperationModes.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __OP_MODES_H__
+#define __OP_MODES_H__
+
+#include "TDCommon.h"
+#include "TDDefs.h"
+
+/**
+ * @defgroup TDOperationModes TDOperationModes
+ * @brief Operation Modes module.
+ *
+ * @addtogroup TDOperationModes
+ * @{
+ */
+
+// ********** public definitions **********
+
+#define NO_SUB_STATE 0xFF ///< value for when submode does not have specific substates and is not applicable.
+
+/// Payload record structure for op mode broadcast message
+typedef struct
+{
+ U32 opMode; ///< Current operating mode
+ U32 subMode; ///< Current sub-mode of current operating mode
+} OP_MODE_PAYLOAD_T;
+
+// ********** public function prototypes **********
+
+void initOperationModes( void ); // Initialize this module
+void execOperationModes( void ); // Execute the operation modes state machine (scheduled periodic call)
+void requestNewOperationMode( TD_OP_MODE_T newMode ); // Request a transition to a new operation mode
+TD_OP_MODE_T getCurrentOperationMode( void ); // Get the current operation mode
+TD_OP_MODE_T getPreviousOperationMode( void ); // Get the previous operation mode
+U32 getCurrentSubMode( void ); // Get the current sub-mode
+void initiateAlarmAction( ALARM_ACTION_T action ); // Initiate an alarm or alarm recovery action according to current op mode
+CONFIRMATION_REQUEST_STATUS_T getConfirmationRequestStatus( GENERIC_CONFIRM_ID_T requestID ); // Get the current confirmation request status
+void setConfirmationRequestStatus( GENERIC_CONFIRM_ID_T requestID, CONFIRMATION_REQUEST_STATUS_T status ); // Set the confirmation request status
+GENERIC_CONFIRM_ID_T addConfirmationRequest( GENERIC_CONFIRM_ID_T requestID, GENERIC_CONFIRM_COMMAND_T requestType, U32 rejectReason ); // Add a new confirmation request
+void setCurrentSubState( U32 subState ); // Set the current substate.
+void setCurrent4thLevelState( U32 state ); // Set the current 4th level state.
+void sendOperationStatusEvent( void ); // Constructs and sends operation status event
+
+BOOL testSetOperationMode( TD_OP_MODE_T newMode ); // Force transition to a given mode (if allowed)
+BOOL testSetOpModePublishIntervalOverride( U32 ms );
+BOOL testResetOpModePublishIntervalOverride( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Monitors/FluidLeak.c
===================================================================
diff -u
--- firmware/App/Monitors/FluidLeak.c (revision 0)
+++ firmware/App/Monitors/FluidLeak.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,257 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file FluidLeak.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include "TDCommon.h"
+#include "FluidLeak.h"
+//#include "FPGA.h"
+#include "Messaging.h"
+#include "OperationModes.h"
+#include "PersistentAlarm.h"
+#include "TaskPriority.h"
+#include "Timers.h"
+
+/**
+ * @addtogroup FluidLeak
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define FLUID_LEAK_PUB_INTERVAL ( MS_PER_SECOND / TASK_PRIORITY_INTERVAL ) ///< Interval (ms/task time) at which the fluid leak data is published on the CAN bus.
+#define DATA_PUBLISH_COUNTER_START_COUNT 50 ///< Data publish counter start count.
+
+/// Persist time (in ms) for fluid leak error condition.
+static const U32 FLUID_LEAK_ERROR_PERSIST_MS = 250;
+
+// ********** private data **********
+
+static U32 fluidLeakStatePublicationTimerCounter; ///< Timer counter used to schedule fluid leak publication to CAN bus.
+
+/// Interval (in ms) at which to publish fluid leak data to CAN bus.
+static OVERRIDE_U32_T fluidLeakStatePublishInterval = { FLUID_LEAK_PUB_INTERVAL, FLUID_LEAK_PUB_INTERVAL, 0, 0 };
+static OVERRIDE_U32_T fluidLeakState; ///< Detected fluid leak state for fluid leak detector.
+
+// ********** private function prototypes **********
+
+static void publishFluidLeakState( void );
+
+/*********************************************************************//**
+ * @brief
+ * The initFluidLeak function initializes the Fluid Leak module.
+ * @details Inputs: none
+ * @details Outputs: Fluid Leak module initialized.
+ * @return none
+ *************************************************************************/
+void initFluidLeak( void )
+{
+ fluidLeakState.data = FLUID_LEAK_STATE_DRY;
+ fluidLeakState.ovInitData = FLUID_LEAK_STATE_DRY;
+ fluidLeakState.ovData = FLUID_LEAK_STATE_DRY;
+ fluidLeakState.override = OVERRIDE_RESET;
+ fluidLeakStatePublicationTimerCounter = DATA_PUBLISH_COUNTER_START_COUNT;
+
+ initPersistentAlarm( ALARM_ID_HD_FLUID_LEAK_DETECTED, 0, FLUID_LEAK_ERROR_PERSIST_MS );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execFluidLeak function executes the fluid leak monitor.
+ * @details Inputs: FPGA fluid leak state GPIO pin state
+ * @details Outputs: fluidLeakState
+ * @return none
+ *************************************************************************/
+void execFluidLeak( void )
+{
+ BOOL noFluidLeakDetected = TRUE;// = noFPGAFluidLeakDetected();
+
+ if ( getCurrentOperationMode() != MODE_INIT )
+ {
+ // Get latest state reading
+ if ( TRUE == noFluidLeakDetected )
+ {
+ fluidLeakState.data = FLUID_LEAK_STATE_DRY;
+ }
+ else
+ {
+ fluidLeakState.data = FLUID_LEAK_STATE_WET;
+ }
+
+ // Check state reading and act upon
+ if ( FLUID_LEAK_STATE_WET == getFluidLeakState() )
+ {
+ if ( TRUE == isPersistentAlarmTriggered( ALARM_ID_HD_FLUID_LEAK_DETECTED, TRUE ) )
+ {
+ activateAlarmNoData( ALARM_ID_HD_FLUID_LEAK_DETECTED );
+ }
+ }
+ else // FLUID_LEAK_STATE_DRY == getFluidLeakState()
+ {
+ isPersistentAlarmTriggered( ALARM_ID_HD_FLUID_LEAK_DETECTED, FALSE );
+ clearAlarmCondition( ALARM_ID_HD_FLUID_LEAK_DETECTED );
+ }
+ }
+
+ // Publish fluid leak state if due
+ publishFluidLeakState();
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFluidLeakState function gets the current reading for the fluid
+ * leak detector.
+ * @details Inputs: fluidLeakState
+ * @details Outputs: none
+ * @param none
+ * @return the current fluid leak state.
+ *************************************************************************/
+FLUID_LEAK_STATES_T getFluidLeakState( void )
+{
+ FLUID_LEAK_STATES_T result = (FLUID_LEAK_STATES_T)fluidLeakState.data;
+
+ if ( OVERRIDE_KEY == fluidLeakState.override )
+ {
+ result = (FLUID_LEAK_STATES_T)fluidLeakState.ovData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The publishFluidLeakState function publishes fluid leak state at the set interval.
+ * @details Inputs: fluidLeakState
+ * @details Outputs: if broadcast is due, send fluid leak state
+ * @return none
+ *************************************************************************/
+static void publishFluidLeakState( void )
+{
+ // Publish fluid leak state on interval
+ if ( ++fluidLeakStatePublicationTimerCounter >= getU32OverrideValue( &fluidLeakStatePublishInterval ) )
+ {
+ FLUID_LEAK_DATA_T data;
+
+ data.fluidLeakState = (U32)getFluidLeakState();
+
+ broadcastData( MSG_ID_HD_FLUID_LEAK_STATE_DATA, COMM_BUFFER_OUT_CAN_TD_BROADCAST, (U08*)&data, sizeof( FLUID_LEAK_DATA_T ) );
+ fluidLeakStatePublicationTimerCounter = 0;
+ }
+}
+
+
+/*************************************************************************
+ * TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/*********************************************************************//**
+ * @brief
+ * The testSetFluidLeakStatePublishIntervalOverride function overrides the
+ * fluid leak state publish interval.
+ * @details Inputs: none
+ * @details Outputs: fluidLeakStatePublishInterval
+ * @param value override fluid leak state publish interval with (in ms)
+ * @return TRUE if override successful, FALSE if not
+ *************************************************************************/
+BOOL testSetFluidLeakStatePublishIntervalOverride( U32 value )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ U32 intvl = value / TASK_PRIORITY_INTERVAL;
+
+ result = TRUE;
+ fluidLeakStatePublishInterval.ovData = intvl;
+ fluidLeakStatePublishInterval.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetFluidLeakStatePublishIntervalOverride function resets the override
+ * of the fluid leak state publish interval.
+ * @details Inputs: none
+ * @details Outputs: fluidLeakStatePublishInterval
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetFluidLeakStatePublishIntervalOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ fluidLeakStatePublishInterval.override = OVERRIDE_RESET;
+ fluidLeakStatePublishInterval.ovData = fluidLeakStatePublishInterval.ovInitData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testSetFluidLeakStateOverride function overrides the state
+ * of the fluid leak detector.
+ * @details Inputs: none
+ * @details Outputs: fluidLeakState
+ * @param none
+ * @param state override fluid leak detector with this
+ * @return TRUE if override successful, FALSE if not
+ *************************************************************************/
+BOOL testSetFluidLeakStateOverride( FLUID_LEAK_STATES_T state )
+{
+ BOOL result = FALSE;
+
+ if ( ( state < NUM_OF_FLUID_LEAK_STATES ) )
+ {
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ fluidLeakState.ovData = (U32)state;
+ fluidLeakState.override = OVERRIDE_KEY;
+ }
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetFluidLeakStateOverride function resets the override of the
+ * fluid leak detector.
+ * @details Inputs: none
+ * @details Outputs: fluidLeakState
+ * @param none
+ * @return TRUE if reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetFluidLeakStateOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ fluidLeakState.override = OVERRIDE_RESET;
+ fluidLeakState.ovData = fluidLeakState.ovInitData;
+ }
+
+ return result;
+}
+
+/**@}*/
Index: firmware/App/Monitors/FluidLeak.h
===================================================================
diff -u
--- firmware/App/Monitors/FluidLeak.h (revision 0)
+++ firmware/App/Monitors/FluidLeak.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,64 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file FluidLeak.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __FLUID_LEAK_H__
+#define __FLUID_LEAK_H__
+
+#include "TDCommon.h"
+
+/**
+ * @defgroup FluidLeak FluidLeak
+ * @brief Fluid Leak detector monitor module. Monitors the
+ * fluid leak detector.
+ *
+ * SMD Fluid Controls - OS3 Industrial Optical Float Switch Part No. OS3-C2 10D3 003
+ *
+ * @addtogroup FluidLeak
+ * @{
+ */
+
+// ********** public definitions **********
+
+/// Enumeration of fluid leak detector states.
+typedef enum FluidLeakDetectorStates
+{
+ FLUID_LEAK_STATE_WET = 0, ///< Fluid leak detector senses fluid
+ FLUID_LEAK_STATE_DRY, ///< Fluid leak detector does not sense any fluid
+ NUM_OF_FLUID_LEAK_STATES ///< Number of fluid leak detector states
+} FLUID_LEAK_STATES_T;
+
+/// Fluid leak publish data structure
+typedef struct
+{
+ U32 fluidLeakState; ///< Fluid leak state.
+} FLUID_LEAK_DATA_T;
+
+// ********** public function prototypes **********
+
+void initFluidLeak( void );
+void execFluidLeak( void );
+
+FLUID_LEAK_STATES_T getFluidLeakState( void );
+
+BOOL testSetFluidLeakStatePublishIntervalOverride( U32 value );
+BOOL testResetFluidLeakStatePublishIntervalOverride( void );
+BOOL testSetFluidLeakStateOverride( FLUID_LEAK_STATES_T state );
+BOOL testResetFluidLeakStateOverride( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/AlarmMgmtSWFaults.h
===================================================================
diff -u
--- firmware/App/Services/AlarmMgmtSWFaults.h (revision 0)
+++ firmware/App/Services/AlarmMgmtSWFaults.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,37 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file AlarmMgmtSWFaults.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __ALARM_MGMT_SW_FAULTS_H__
+#define __ALARM_MGMT_SW_FAULTS_H__
+
+/**
+ * @addtogroup AlarmManagement
+ * @{
+ */
+
+// ********** public definitions **********
+
+/// Listing of specific software faults for logging purposes.
+typedef enum
+{
+ SW_FAULT_ID_NONE = 0,
+ NUM_OF_SW_FAULT_IDS
+} SW_FAULT_ID_T;
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/AlarmMgmtTD.c
===================================================================
diff -u
--- firmware/App/Services/AlarmMgmtTD.c (revision 0)
+++ firmware/App/Services/AlarmMgmtTD.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1936 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file AlarmMgmtTD.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include "mibspi.h"
+
+#include "AlarmLamp.h"
+//#include "CPLD.h"
+//#include "FPGA.h"
+//#include "InternalADC.h"
+#include "Messaging.h"
+#include "OperationModes.h"
+#include "TaskGeneral.h"
+#include "Timers.h"
+
+/**
+ * @addtogroup AlarmManagementTD
+ * @{
+ */
+
+// ********** private definitions **********
+
+/// Interval to control lamp and audio and to publish alarm status data.
+#define ALARM_STATUS_PUBLISH_INTERVAL ( ALARM_LAMP_AND_AUDIO_CONTROL_INTERVAL_MS / TASK_GENERAL_INTERVAL )
+
+/// Interval (ms/task time) at which the alarm information is published on the CAN bus.
+#define ALARM_INFO_PUB_INTERVAL ( MS_PER_SECOND / TASK_GENERAL_INTERVAL )
+
+#define SUPERVISOR_ALARM_KEY 0xD2C3B4A5 ///< 32-bit key required for clear all alarms request.
+
+/// Interval (ms/task time) Alarms are blocked after the return of AC power.
+#define ALARM_BLOCKED_COUNT_AFTER_AC_RETURN ( 10*MS_PER_SECOND / TASK_GENERAL_INTERVAL )
+
+#define ALARM_SILENCE_EXPIRES_IN_SECS (60) ///< Alarm silence expiration time in seconds.
+
+#define LOWEST_ALARM_SUB_RANK 999 ///< Lowest alarm sub-rank that can be set.
+#define ALARM_NOT_BLOCKED 0 ///< Alarm blocked timer value that indicates no alarm block
+
+#define MIN_TIME_BETWEEN_ALARM_ACTIONS_MS MS_PER_SECOND ///< Minimum time between user alarm actions (in ms).
+
+/// A blank alarm data record for alarms that do not include alarm data when triggered.
+const ALARM_DATA_T BLANK_ALARM_DATA = { ALARM_DATA_TYPE_NONE, 0 };
+
+/// Pin SPI3-CS0 - re-purposed as output GPIO for backup alarm audio enable.
+#define BACKUP_AUDIO_ENABLE_SPI3_PORT_MASK 0x00000001
+// Backup alarm audio enable/disable macros
+#define SET_BACKUP_AUDIO_ENABLE() {mibspiREG3->PC3 |= BACKUP_AUDIO_ENABLE_SPI3_PORT_MASK;} ///< Macro to enable backup alarm audio.
+#define CLR_BACKUP_AUDIO_ENABLE() {mibspiREG3->PC3 &= ~BACKUP_AUDIO_ENABLE_SPI3_PORT_MASK;} ///< Macro to disable backup alarm audio.
+
+#define ALARM_AUDIO_TEST_TONE 4 ///< Alarm audio state for continuous test tone.
+#define ALARM_AUDIO_CURRENT_LG_MIN_MA 50.0F ///< Minimum audio current (low gain) during test tone self-test (in mA).
+#define ALARM_AUDIO_CURRENT_LG_MAX_MA 20.0F ///< Maximum audio current (low gain) during no tone self-test (in mA).
+#define ALARM_AUDIO_MAX_TEST_TIME_MS 1000 ///< Maximum time for audio current to reach threshold in test.
+#define MAX_ALARM_AUDIO_VOLUME_INDEX 0 ///< Index for maximum alarm audio volume.
+#define MIN_ALARM_AUDIO_VOLUME_INDEX (MAX_ALARM_VOLUME_LEVEL - 1 ) ///< Index for minimum alarm audio volume.
+
+/// Alarm priority ranking record.
+typedef struct
+{
+ ALARM_ID_T alarmID; ///< ID of highest priority alarm in this priority category
+ U32 subRank; ///< Sub-rank of this alarm
+ S32 timeSinceTriggeredMS; ///< Time (in ms) since this alarm was triggered
+} ALARM_PRIORITY_RANKS_T;
+
+/// Enumeration of alarm audio self-test states.
+typedef enum Alarm_Audio_Self_Test_States
+{
+ ALARM_AUDIO_SELF_TEST_STATE_START = 0, ///< Start state of alarm audio self-test.
+ ALARM_AUDIO_SELF_TEST_STATE_PRIMARY, ///< Test tone state of alarm audio self-test.
+ ALARM_AUDIO_SELF_TEST_STATE_NO_TONE, ///< No tone state of alarm audio self-test.
+ ALARM_AUDIO_SELF_TEST_STATE_COMPLETE, ///< Completed state of alarm audio self-test.
+ NUM_OF_ALARM_AUDIO_SELF_TEST_STATES ///< Number of states in alarm audio self-test.
+} ALARM_AUDIO_SELF_TEST_STATE_T;
+
+/// Enumeration of alarm audio volume factors.
+typedef enum Alarm_Audio_Volume_Factors
+{
+ ALARM_AUDIO_VOLUME_GAIN = 0, ///< Gain setting for alarm audio volume.
+ ALARM_AUDIO_VOLUME_DIVIDER, ///< Divider setting for alarm audio volume.
+ NUM_OF_ALARM_AUDIO_VOLUME_FACTORS ///< Number of alarm audio volume factors.
+} ALARM_AUDIO_VOLUME_FACTOR_T;
+
+/// Lookup table to determine appropriate divider for a given alarm audio volume level.
+const U08 ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[MAX_ALARM_VOLUME_LEVEL][NUM_OF_ALARM_AUDIO_VOLUME_FACTORS] = {
+ { 1, 0 },
+ { 1, 1 },
+ { 3, 1 },
+ { 3, 2 },
+ { 4, 2 }
+};
+
+// ********** private data **********
+
+static OVERRIDE_U32_T alarmStartedAt[ NUM_OF_ALARM_IDS ]; ///< Table - when alarm became active for each alarm (if active) or zero (if inactive)
+static U32 alarmStatusPublicationTimerCounter = 0; ///< Used to schedule alarm status publication to CAN bus.
+static U32 alarmInfoPublicationTimerCounter = 0; ///< Used to schedule alarm information publication to CAN bus.
+static U32 audioTestStartTime; ///< Start time of audio alarm current self-test.
+static U32 alarmsBlockedTimer = 0; ///< Countdown timer used to temporarily block new alarms from being initiated
+static U32 lastUserAlarmActionReceivedTime = 0; ///< Time of last alarm action by user received from the UI (ms timestamp).
+
+/// Interval (in task intervals) at which to publish alarm status to CAN bus.
+static OVERRIDE_U32_T alarmStatusPublishInterval = { ALARM_STATUS_PUBLISH_INTERVAL, ALARM_STATUS_PUBLISH_INTERVAL, ALARM_STATUS_PUBLISH_INTERVAL, 0 };
+
+/// Interval (in task intervals) at which to publish alarm information to CAN bus.
+static OVERRIDE_U32_T alarmInfoPublishInterval = { ALARM_INFO_PUB_INTERVAL, ALARM_INFO_PUB_INTERVAL, ALARM_INFO_PUB_INTERVAL, 0 };
+
+/// Alarm audio attenuation level (0..4 where 0 = max volume and 4 = min volume).
+static OVERRIDE_U32_T alarmAudioVolumeLevel = { MAX_ALARM_VOLUME_ATTENUATION, MAX_ALARM_VOLUME_ATTENUATION, MAX_ALARM_VOLUME_ATTENUATION, 0 };
+
+static OVERRIDE_F32_T alarmPrimaryAudioCurrentHG = { 0.0, 0.0, 0.0, 0 }; ///< Alarm audio current (high gain) measured at ADC.
+
+static OVERRIDE_F32_T alarmPrimaryAudioCurrentLG = { 0.0, 0.0, 0.0, 0 }; ///< Alarm audio current (low gain) measured at ADC.
+
+static OVERRIDE_F32_T alarmBackupAudioCurrent = { 0.0, 0.0, 0.0, 0 }; ///< Alarm backup audio current measured at ADC.
+
+static COMP_ALARM_STATUS_T alarmStatus; ///< Record for the current composite alarm status.
+static ALARM_PRIORITY_RANKS_T alarmPriorityFIFO[ NUM_OF_ALARM_PRIORITIES ]; ///< FIFO - first activated or highest sub-rank alarm in each alarm priority category.
+
+static BOOL alarmUserRecoveryActionEnabled[ NUMBER_OF_ALARM_USER_ACTIONS ]; ///< Alarm user recovery actions enabled flags.
+
+static BOOL alarmButtonBlockers[ NUM_OF_ALARM_BUTTON_BLOCKERS ]; ///< Flags indicating whether alarm table or state properties are blocking alarm buttons for UI.
+
+static ALARM_AUDIO_SELF_TEST_STATE_T alarmAudioSelfTestState; ///< Current state of the alarm audio self tests.
+
+static BOOL alarmAudioTestToneRequested; ///< Flag indicates whether alarm audio test tone should be output.
+static BOOL resumeBlockedByAlarmProperty; ///< Flag indicates whether treatment resumption is currently blocked by alarm property.
+
+// ********** private function prototypes **********
+
+static void activateAlarmTD( ALARM_ID_T alarm );
+
+static void monitorAlarms( void );
+static void updateAlarmsState( void );
+static void setAlarmLamp( void );
+static void setAlarmAudio( void );
+static void updateAlarmsSilenceStatus( void );
+static void updateAlarmsFlags( void );
+
+static BOOL clearAllRecoverableAlarms( ALARM_USER_ACTION_T action );
+static void resetAlarmPriorityFIFO( ALARM_PRIORITY_T priority );
+
+static U32 getAlarmStartTime( ALARM_ID_T alarmID );
+
+static void publishAlarmInfo( void );
+
+/*********************************************************************//**
+ * @brief
+ * The initAlarmMgmtTD function initializes the AlarmMgmt module.
+ * @details Inputs: none
+ * @details Outputs: AlarmMgmtTD module initialized.
+ * @return none
+ *************************************************************************/
+void initAlarmMgmtTD( void )
+{
+ ALARM_PRIORITY_T p;
+ ALARM_ID_T a;
+ ALARM_BUTTON_BLOCKER_T b;
+
+ // Disable backup audio
+ CLR_BACKUP_AUDIO_ENABLE();
+
+ // Initialize alarm states and start time stamps
+ for ( a = ALARM_ID_NO_ALARM; a < NUM_OF_ALARM_IDS; a++ )
+ {
+ setAlarmActive( a, FALSE );
+ setAlarmConditionDetected( a, FALSE );
+ alarmStartedAt[ a ].data = 0;
+ alarmStartedAt[ a ].ovData = 0;
+ alarmStartedAt[ a ].ovInitData = 0;
+ alarmStartedAt[ a ].override = OVERRIDE_RESET;
+ }
+ // Initialize alarm FIFOs
+ for ( p = ALARM_PRIORITY_NONE; p < NUM_OF_ALARM_PRIORITIES; p++ )
+ {
+ alarmPriorityFIFO[ p ].alarmID = ALARM_ID_NO_ALARM;
+ alarmPriorityFIFO[ p ].subRank = LOWEST_ALARM_SUB_RANK;
+ alarmPriorityFIFO[ p ].timeSinceTriggeredMS = 0;
+ }
+ // Initialize alarm button blocker flags
+ for ( b = (ALARM_BUTTON_BLOCKER_T)0; b < NUM_OF_ALARM_BUTTON_BLOCKERS; b++ )
+ {
+ alarmButtonBlockers[ b ] = FALSE;
+ }
+ // Initialize composite alarm state
+ alarmStatus.alarmsState = ALARM_PRIORITY_NONE;
+ alarmStatus.alarmsSilenced = FALSE;
+ alarmStatus.alarmsSilenceStart = 0;
+ alarmStatus.alarmsSilenceExpiresIn = 0;
+ alarmStatus.alarmsEscalatesIn = 0;
+ alarmStatus.alarmsToEscalate = FALSE;
+ alarmStatus.alarmTop = ALARM_ID_NO_ALARM;
+ alarmStatus.topAlarmConditionDetected = FALSE;
+ alarmStatus.systemFault = FALSE;
+ alarmStatus.stop = FALSE;
+ alarmStatus.lampOn = FALSE;
+ alarmStatus.noClear = FALSE;
+ alarmStatus.noResume = FALSE;
+ alarmStatus.noRinseback = FALSE;
+ alarmStatus.noEndTreatment = FALSE;
+ alarmStatus.noBloodRecirc = FALSE;
+ alarmStatus.noDialRecirc = FALSE;
+ alarmStatus.ok = FALSE;
+
+ alarmsBlockedTimer = 0;
+ lastUserAlarmActionReceivedTime = 0;
+ alarmAudioTestToneRequested = FALSE;
+ resumeBlockedByAlarmProperty = FALSE;
+ alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_START;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execAlarmMgmt function executes the alarm management functions to be
+ * done periodically. The composite alarm state is updated, alarm lamp and
+ * audio patterns are updated, and status is sent out to the rest of the system.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void execAlarmMgmt( void )
+{
+ monitorAlarms();
+ updateAlarmsState();
+ updateAlarmsFlags();
+ updateAlarmsSilenceStatus();
+ // Publish alarm status and information at interval
+ publishAlarmInfo();
+
+ // Block new machine alarms during power fail recovery
+ if ( alarmsBlockedTimer > 0 )
+ {
+ alarmsBlockedTimer--;
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The activateAlarmTD function activates a given TD alarm.
+ * @details Inputs: none
+ * @details Outputs: alarmIsActive[], alarmStartedAt[], alarmStatus is updated
+ * @param alarm ID of alarm to activate
+ * @return none
+ *************************************************************************/
+static void activateAlarmTD( ALARM_ID_T alarm )
+{
+ // Verify valid alarm index
+ if ( ( alarm > ALARM_ID_NO_ALARM ) && ( alarm < NUM_OF_ALARM_IDS ) )
+ {
+ ALARM_T props = getAlarmProperties( alarm );
+ ALARM_T props_top = getAlarmProperties( alarmStatus.alarmTop );
+
+ // No need to do anything if alarm is already active, but if condition was cleared then re-trigger alarm
+ if ( ( FALSE == isAlarmActive( alarm ) ) ||
+ ( ( FALSE == isAlarmConditionDetected( alarm ) ) && ( FALSE == props.alarmConditionClearImmed ) ) )
+ {
+ activateAlarm( alarm );
+ alarmStartedAt[ alarm ].data = getMSTimerCount();
+ // If alarms are silenced and this new alarm is of higher or same priority, end silence due to new alarm
+ if ( ( props.alarmPriority > props_top.alarmPriority ) ||
+ ( ( props.alarmPriority == props_top.alarmPriority ) &&
+ ( props.alarmSubRank < props_top.alarmSubRank ) ) )
+ {
+ alarmStatus.alarmsSilenced = FALSE;
+ }
+ // If alarm status was that no alarms currently active, set this alarm as top alarm until status formally updated later
+ if ( ALARM_ID_NO_ALARM == alarmStatus.alarmTop )
+ {
+ alarmStatus.alarmTop = alarm;
+ }
+ // If alarm stops, set that status immediately (don't wait for status update function)
+ if ( TRUE == props.alarmStops )
+ {
+ alarmStatus.stop = TRUE;
+ }
+ // If alarm is a fault (and not in service mode), request transition to fault mode
+ if ( ( TRUE == props.alarmIsFault ) && ( getCurrentOperationMode() != MODE_SERV ) )
+ {
+ requestNewOperationMode( MODE_FAUL );
+ }
+
+ // If alarm has stop property, signal stop now
+ if ( TRUE == props.alarmStops )
+ {
+ initiateAlarmAction( ALARM_ACTION_STOP );
+ }
+ }
+ }
+ else
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_INVALID_ALARM_TO_ACTIVATE, alarm )
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The clearAlarmTD function clears a given TDalarm if it is recoverable.
+ * Also an alarm message is broadcast to the rest of the system.
+ * @details Inputs: none
+ * @details Outputs: AlarmStatusTable[], alarmIsActive[], alarmStartedAt[],
+ * alarmIsDetected[]
+ * @param alarm ID of alarm to clear
+ * @return none
+ *************************************************************************/
+void clearAlarmTD( ALARM_ID_T alarm )
+{
+ // Verify given alarm
+ if ( ( alarm > ALARM_ID_NO_ALARM ) && ( alarm < NUM_OF_ALARM_IDS ) )
+ {
+ ALARM_T props = getAlarmProperties( alarm );
+
+ // Verify alarm can be cleared
+ if ( FALSE == props.alarmNoClear )
+ {
+ // Clear alarm and broadcast alarm clear if not already cleared
+ if ( TRUE == isAlarmActive( alarm ) )
+ {
+ clearAlarm( alarm );
+ alarmStartedAt[ alarm ].data = 0;
+ }
+ }
+ }
+ else
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_INVALID_ALARM_TO_CLEAR, alarm )
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The activateAlarmNoData function activates a given alarm. Also, an alarm
+ * message is broadcast to the rest of the system. This function will
+ * include given data in the broadcast message for logging.
+ * @details Inputs: none
+ * @details Outputs: alarm triggered message sent, alarm activated
+ * @param alarm ID of alarm to activate
+ * @return none
+ *************************************************************************/
+void activateAlarmNoData( ALARM_ID_T alarm )
+{
+ activateAlarm2Data( alarm, BLANK_ALARM_DATA, BLANK_ALARM_DATA, FALSE );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The activateAlarm1Data function activates a given alarm. Also, an alarm
+ * message is broadcast to the rest of the system. This function will
+ * include given data in the broadcast message for logging.
+ * @details Inputs: none
+ * @details Outputs: alarm triggered message sent, alarm activated
+ * @param alarm ID of alarm to activate
+ * @param alarmData supporting data to include in alarm msg
+ * @return none
+ *************************************************************************/
+void activateAlarm1Data( ALARM_ID_T alarm, ALARM_DATA_T alarmData )
+{
+ activateAlarm2Data( alarm, alarmData, BLANK_ALARM_DATA, FALSE );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The activateAlarm2Data function activates a given alarm. Also, an alarm
+ * message is broadcast to the rest of the system. This function will
+ * include two given data in the broadcast message for logging.
+ * @details Inputs: alarmsBlockedTimer, determines blocked alarm conditions
+ * @details Outputs: alarm triggered message sent, alarm activated
+ * @param alarm ID of alarm to activate
+ * @param alarmData1 supporting data to include in alarm msg
+ * @param alarmData2 supporting data to include in alarm msg
+ * @param outside flag indicates whether alarm is originating from outside HD f/w
+ * @return none
+ *************************************************************************/
+void activateAlarm2Data( ALARM_ID_T alarm, ALARM_DATA_T alarmData1, ALARM_DATA_T alarmData2, BOOL outside )
+{
+ // Block if new alarms are occur during loss of AC power
+// if ( ( TRUE == getCPLDACPowerLossDetected() ) )
+// {
+// alarmsBlockedTimer = ALARM_BLOCKED_COUNT_AFTER_AC_RETURN;
+// }
+ // Sanity check, verify valid alarm index
+ if ( ( alarm > ALARM_ID_NO_ALARM ) && ( alarm < NUM_OF_ALARM_IDS ) )
+ {
+ // if the block timer is 0 OR we have an unblockable alarm
+ if ( ( ALARM_NOT_BLOCKED == alarmsBlockedTimer )
+ || ( ALARM_ID_HD_AC_POWER_LOST == alarm )
+ || ( ALARM_ID_HD_AC_POWER_LOST_IN_TREATMENT == alarm )
+ || ( ALARM_ID_HD_DG_RESTARTED_FAULT == alarm ) )
+ {
+ TD_OP_MODE_T opMode = getCurrentOperationMode();
+// TREATMENT_STATE_T ts = getTreatmentState();
+
+ ALARM_T props = getAlarmProperties( alarm );
+
+ // do not trigger alarm if blocked by current mode/state
+// if ( ( ( props.alarmBlockRinseback != TRUE ) || ( opMode != MODE_TREA ) || ( ts != TREATMENT_RINSEBACK_STATE ) || ( TRUE == outside ) ) &&
+// ( ( props.alarmBlockEndTx != TRUE ) || ( opMode != MODE_POST ) || ( TRUE == outside )) )
+ {
+ // Broadcast alarm and data if alarm not already active
+ if ( FALSE == isAlarmActive( alarm ) )
+ {
+ ALARM_TRIGGERED_PAYLOAD_T data;
+
+ data.alarm = (U32)alarm;
+ data.almDataType1 = (U32)alarmData1.dataType;
+ data.almData1 = alarmData1.data.uInt.data;
+ data.almDataType2 = (U32)alarmData2.dataType;
+ data.almData2 = alarmData2.data.uInt.data;
+ data.almPriority = props.alarmPriority;
+ data.almRank = props.alarmSubRank;
+ data.almClrTopOnly = props.alarmClearOnly;
+
+ broadcastData( MSG_ID_ALARM_TRIGGERED, COMM_BUFFER_OUT_CAN_TD_ALARM, (U08*)&data, sizeof( ALARM_TRIGGERED_PAYLOAD_T ) );
+ // Send information for UI to log to treatment log
+ if ( ( TRUE == props.alarmTreatmentLog ) && ( MODE_TREA == getCurrentOperationMode() ) )
+ {
+ F32 data1;
+ F32 data2;
+
+ memcpy( &data1, &alarmData1.data, sizeof( F32 ) );
+ memcpy( &data2, &alarmData2.data, sizeof( F32 ) );
+// sendTreatmentLogAlarmEventData( alarm, data1, data2 );
+ }
+ }
+ activateAlarmTD( alarm );
+ }
+ }
+ }
+ else
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_INVALID_ALARM_TO_ACTIVATE, alarm )
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setAlarmUserActionEnabled function enables/disables specific alarm
+ * recovery user actions while in specific modes. Ack option is always
+ * potentially enabled - automatically enabled as appropriate by updateAlarmsFlags().
+ * @details Inputs: none
+ * @details Outputs:
+ * @param action ID of user alarm recovery action to enable/disable
+ * @param enabled set to TRUE to enable action, FALSE to disable
+ * @return none
+ *************************************************************************/
+void setAlarmUserActionEnabled( ALARM_USER_ACTION_T action, BOOL enabled )
+{
+ if ( action < NUMBER_OF_ALARM_USER_ACTIONS )
+ {
+ alarmUserRecoveryActionEnabled[ action ] = enabled;
+ }
+ else
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_INVALID_USER_ACTION, (U32)action )
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalAlarmSilence function handles an alarm silence request from
+ * the user.
+ * @details Inputs: none
+ * @details Outputs: alarm silence status updated
+ * @param cmd ID of user command (1=silence, 0=cancel silence)
+ * @return none
+ *************************************************************************/
+void signalAlarmSilence( ALARM_SILENCE_CMD_T cmd )
+{
+ if ( ALARM_SILENCE_CMD_START == cmd )
+ {
+ if ( FALSE == alarmStatus.alarmsSilenced )
+ {
+ alarmStatus.alarmsSilenced = TRUE;
+ alarmStatus.alarmsSilenceStart = getMSTimerCount();
+ alarmStatus.alarmsSilenceExpiresIn = ALARM_SILENCE_EXPIRES_IN_SECS;
+ }
+ }
+ else
+ {
+ if ( TRUE == alarmStatus.alarmsSilenced )
+ {
+ alarmStatus.alarmsSilenced = FALSE;
+ alarmStatus.alarmsSilenceStart = 0;
+ alarmStatus.alarmsSilenceExpiresIn = 0;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The signalAlarmUserActionInitiated function clears all non-recoverable alarms
+ * and initiates selected user action. User actions are debounced (must come
+ * at least 1 second after last). And user actions must be appropriate for current
+ * alarm state.
+ * @details Inputs: ALARM_TABLE[], alarmStatus, lastUserAlarmActionReceivedTime
+ * @details Outputs: alarmIsActive[], lastUserAlarmActionReceivedTime
+ * @param action ID of user's selected action to initiate
+ * @return none
+ *************************************************************************/
+void signalAlarmUserActionInitiated( ALARM_USER_ACTION_T action )
+{
+ BOOL alarmActionIsValid = FALSE;
+
+ // Validate user selected action is appropriate per current alarm system status
+ switch ( action )
+ {
+ case ALARM_USER_ACTION_RESUME:
+ if ( alarmStatus.noResume != TRUE )
+ {
+ alarmActionIsValid = TRUE;
+ }
+ break;
+
+ case ALARM_USER_ACTION_RINSEBACK:
+ if ( alarmStatus.noRinseback != TRUE )
+ {
+ alarmActionIsValid = TRUE;
+ }
+ break;
+
+ case ALARM_USER_ACTION_END_TREATMENT:
+ if ( alarmStatus.noEndTreatment != TRUE )
+ {
+ alarmActionIsValid = TRUE;
+ }
+ break;
+
+ case ALARM_USER_ACTION_ACK:
+ if ( TRUE == alarmStatus.ok )
+ {
+ alarmActionIsValid = TRUE;
+ }
+ break;
+
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_INVALID_ALARM_USER_ACTION, action );
+ break;
+ }
+
+ // Ignore alarm action if invalid or too soon after last one (essentially a debounce in case user double tapped a button)
+ if ( ( TRUE == alarmActionIsValid ) && ( calcTimeSince( lastUserAlarmActionReceivedTime ) >= MIN_TIME_BETWEEN_ALARM_ACTIONS_MS ) )
+ {
+ BOOL allRecAlarmsCleared = TRUE;
+
+ // Clear recoverable alarms on user action
+ if ( action != ALARM_USER_ACTION_END_TREATMENT ) // end tx action must be confirmed first
+ {
+ ALARM_ID_T a = alarmStatus.alarmTop;
+ ALARM_T props = getAlarmProperties( a );
+
+ if ( ALARM_USER_ACTION_ACK == action )
+ {
+ // If user acknowledged alarm w/ clear only property, just clear that alarm
+ if ( TRUE == props.alarmClearOnly )
+ {
+ clearAlarmTD( a );
+ }
+ // Otherwise we must be in mode/state where ack was only option - so clear all like other options
+ else
+ {
+ allRecAlarmsCleared = clearAllRecoverableAlarms( action );
+ }
+ }
+ else
+ {
+ allRecAlarmsCleared = clearAllRecoverableAlarms( action );
+ }
+ }
+
+ // Initiate user selected action
+ switch ( action )
+ {
+ case ALARM_USER_ACTION_RESUME:
+ if ( TRUE == allRecAlarmsCleared )
+ { // only resume if we've cleared all recoverable alarms
+ initiateAlarmAction( ALARM_ACTION_RESUME );
+ }
+ break;
+
+ case ALARM_USER_ACTION_RINSEBACK:
+ initiateAlarmAction( ALARM_ACTION_RINSEBACK );
+ break;
+
+ case ALARM_USER_ACTION_END_TREATMENT:
+ // Send message to UI to get user confirmation to end treatment - action initiated only upon receipt of user confirmation from UI
+ addConfirmationRequest( GENERIC_CONFIRM_ID_TREATMENT_END, GENERIC_CONFIRM_CMD_REQUEST_OPEN, 0 );
+ break;
+
+ case ALARM_USER_ACTION_ACK:
+ initiateAlarmAction( ALARM_ACTION_ACK );
+ break;
+
+// This default cannot be reached in VectorCAST due to check above for alarmActionIsValid
+#ifndef _VECTORCAST_
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_INVALID_ALARM_USER_ACTION, action );
+ break;
+#endif
+ }
+ }
+
+ // Remember last time user selected an alarm action
+ lastUserAlarmActionReceivedTime = getMSTimerCount();
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isAnyAlarmActive function determines whether any alarm is currently
+ * active.
+ * @details Inputs: alarmStatus
+ * @details Outputs: none
+ * @return TRUE if any alarm is active, FALSE if not
+ *************************************************************************/
+BOOL isAnyAlarmActive( void )
+{
+ BOOL result = ( alarmStatus.alarmTop != ALARM_ID_NO_ALARM ? TRUE : FALSE );
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isBloodRecircBlocked function determines whether any currently
+ * active alarm is blocking blood re-circulation.
+ * @details Inputs: alarmStatus
+ * @details Outputs: none
+ * @return TRUE if any active alarm prevents blood re-circulation, FALSE if not
+ *************************************************************************/
+BOOL isBloodRecircBlocked( void )
+{
+ return alarmStatus.noBloodRecirc;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isDialysateRecircBlocked function determines whether any currently
+ * active alarm is blocking dialysate re-circulation.
+ * @details Inputs: alarmStatus
+ * @details Outputs: none
+ * @return TRUE if any active alarm prevents dialysate re-circulation, FALSE if not
+ *************************************************************************/
+BOOL isDialysateRecircBlocked( void )
+{
+ return alarmStatus.noDialRecirc;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The doesAlarmStatusIndicateEndTxOnly function determines whether any currently
+ * active alarm has ( stop && noRes && /noET ) property, that is end treatment is
+ * the only choice from full stop.
+ * @details Inputs: alarmStatus
+ * @details Outputs: none
+ * @return TRUE if any active alarm has stop property, FALSE if not
+ *************************************************************************/
+BOOL doesAlarmStatusIndicateEndTxOnly( void )
+{
+ return ( ( ( TRUE == alarmStatus.noResume ) &&
+ ( TRUE == alarmStatus.noRinseback ) &&
+ ( TRUE == alarmStatus.stop ) &&
+ ( TRUE == alarmStatus.noBloodRecirc ) &&
+ ( FALSE == alarmStatus.noEndTreatment )
+ ) ? TRUE : FALSE
+ );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The doesAlarmStatusIndicateStop function determines whether any currently
+ * active alarm has stop property.
+ * @details Inputs: alarmStatus
+ * @details Outputs: none
+ * @return TRUE if any active alarm has stop property, FALSE if not
+ *************************************************************************/
+BOOL doesAlarmStatusIndicateStop( void )
+{
+ return alarmStatus.stop;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The doesAlarmIndicateNoResume function determines whether any currently
+ * active alarm has treatment resume blocked property.
+ * @details Inputs: resumeBlockedByAlarmProperty
+ * @details Outputs: none
+ * @return TRUE if any active alarm has no resume property, FALSE if not
+ *************************************************************************/
+BOOL doesAlarmIndicateNoResume( void )
+{
+ return resumeBlockedByAlarmProperty;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getCurrentAlarmStatePriority function determines the current alarm
+ * state priority (NONE, LOW, MEDIUM, or HIGH).
+ * @details Inputs: alarmStatus
+ * @details Outputs: none
+ * @return current alarm state priority
+ *************************************************************************/
+ALARM_PRIORITY_T getCurrentAlarmStatePriority( void )
+{
+ return alarmStatus.alarmsState;
+}
+
+/*********************************************************************//**
+ * @brief
+* The setAlarmAudioVolume function sets the current alarm audio volume level.
+* @details Inputs: none
+* @details Outputs: alarmAudioVolumeLevel
+* @param volumeLevel level of volume requested (1..5)
+* @return none
+*************************************************************************/
+void setAlarmAudioVolume( U32 volumeLevel )
+{
+ BOOL accepted = FALSE;
+ U32 rejReason = REQUEST_REJECT_REASON_NONE;
+
+ if ( ( volumeLevel > 0 ) && ( volumeLevel <= MAX_ALARM_VOLUME_LEVEL ) )
+ {
+ // Convert volume level to attenuation level
+ alarmAudioVolumeLevel.data = MAX_ALARM_VOLUME_LEVEL - volumeLevel;
+ accepted = TRUE;
+ }
+ else
+ {
+ rejReason = REQUEST_REJECT_REASON_PARAM_OUT_OF_RANGE;
+ }
+
+ // Send response to UI
+// sendAlarmAudioVolumeSetResponse( accepted, rejReason );
+}
+
+/*********************************************************************//**
+ * @brief
+* The handleActiveAlarmListRequest function processes the active alarms list
+* request from UI.
+* @details Inputs: alarmIsActive[]
+* @details Outputs: sent active alarms list to UI
+* @return none
+*************************************************************************/
+void handleActiveAlarmListRequest( void )
+{
+ ACTIVE_ALARM_LIST_RESPONSE_PAYLOAD_T activeAlarmPayload;
+ U32 index;
+ U32 activeAlarmListIndex = 0;
+
+ activeAlarmPayload.accepted = TRUE;
+ activeAlarmPayload.rejectionReason = (U32)REQUEST_REJECT_REASON_NONE;
+
+ // Blank alarm list initially
+ for ( index = 0; index < MAX_ALARM_LIST_SIZE; index++ )
+ {
+ activeAlarmPayload.activeAlarmList[ index ] = ALARM_ID_NO_ALARM;
+ }
+
+ // Fill alarm list from (up to) 10 highest priority active alarms
+ if ( TRUE == isAnyAlarmActive() )
+ {
+ for ( index = 0; index < NUM_OF_ALARM_IDS; index++ )
+ {
+ ALARM_RANK_T ranks = getAlarmRank( index );
+
+ if ( ( TRUE == isAlarmActive( ranks.alarmID ) ) && ( activeAlarmListIndex < MAX_ALARM_LIST_SIZE ) )
+ {
+ activeAlarmPayload.activeAlarmList[ activeAlarmListIndex ] = ranks.alarmID;
+ activeAlarmListIndex++;
+ }
+ }
+ }
+
+// sendActiveAlarmsList( activeAlarmPayload );
+}
+
+/*********************************************************************//**
+ * @brief
+* The handleResendActiveAlarmsRequest function processes the request to re-send
+* all active alarms.
+* @details Inputs: alarmIsActive[]
+* @details Outputs: none
+* @return none
+*************************************************************************/
+void handleResendActiveAlarmsRequest( void )
+{
+ U32 index;
+
+ if ( TRUE == isAnyAlarmActive() )
+ {
+ for ( index = 0; index < NUM_OF_ALARM_IDS; index++ )
+ {
+ if ( TRUE == isAlarmActive( (ALARM_ID_T)index ) )
+ {
+ ALARM_TRIGGERED_PAYLOAD_T data;
+ ALARM_T props = getAlarmProperties( index );
+
+ data.alarm = index;
+ data.almDataType1 = BLANK_ALARM_DATA.dataType;
+ data.almData1 = BLANK_ALARM_DATA.data.uInt.data;
+ data.almDataType2 = BLANK_ALARM_DATA.dataType;
+ data.almData2 = BLANK_ALARM_DATA.data.uInt.data;
+ data.almPriority = props.alarmPriority;
+ data.almRank = props.alarmSubRank;
+ data.almClrTopOnly = props.alarmClearOnly;
+
+ broadcastData( MSG_ID_ALARM_TRIGGERED, COMM_BUFFER_OUT_CAN_TD_ALARM, (U08*)&data, sizeof( ALARM_TRIGGERED_PAYLOAD_T ) );
+ }
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getAlarmStartTime function gets the active state of a given alarm.
+ * @details Inputs: alarmStartedAt[]
+ * @details Outputs: none
+ * @param alarmID ID of alarm to check
+ * @return The start time stamp of given alarm ID
+ *************************************************************************/
+static U32 getAlarmStartTime( ALARM_ID_T alarmID )
+{
+ U32 result = 0;
+
+ if ( alarmID < NUM_OF_ALARM_IDS )
+ {
+ if ( OVERRIDE_KEY == alarmStartedAt[ alarmID ].override )
+ {
+ result = alarmStartedAt[ alarmID ].ovData;
+ }
+ else
+ {
+ result = alarmStartedAt[ alarmID ].data;
+ }
+ }
+ else
+ {
+ activateAlarmNoData( ALARM_ID_TD_SOFTWARE_FAULT );
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The monitorAlarms function monitors alarm audio current.
+ * @details Inputs: none
+ * @details Outputs: alarmPrimaryAudioCurrentHG
+ * @return none
+ *************************************************************************/
+static void monitorAlarms( void )
+{
+ U32 volume = getAlarmAudioVolume();
+
+// alarmPrimaryAudioCurrentHG.data = getIntADCVoltageConverted( INT_ADC_PRIMARY_ALARM_CURRENT_HG );
+// alarmPrimaryAudioCurrentLG.data = getIntADCVoltageConverted( INT_ADC_PRIMARY_ALARM_CURRENT_LG );
+// alarmBackupAudioCurrent.data = getFPGABackupAlarmAudioCurrent();
+
+ // Check for user confirmation of end treatment alarm response
+ if ( CONFIRMATION_REQUEST_STATUS_ACCEPTED == getConfirmationRequestStatus( GENERIC_CONFIRM_ID_TREATMENT_END ) )
+ {
+ // To avoid raising repeated alarm before reaching end treatment
+// setVenousBubbleDetectionEnabled( FALSE );
+ clearAllRecoverableAlarms( ALARM_USER_ACTION_END_TREATMENT );
+ initiateAlarmAction( ALARM_ACTION_END_TREATMENT );
+ }
+
+ // TODO - Check current vs. expected audio output
+}
+
+/*********************************************************************//**
+ * @brief
+ * The updateAlarmsState function updates the alarms state and alarm to
+ * display.
+ * @details Inputs: alarmStatusTable[]
+ * @details Outputs: alarmPriorityFIFO[], alarmStatus
+ * @return none
+ *************************************************************************/
+static void updateAlarmsState( void )
+{
+ ALARM_PRIORITY_T highestPriority = ALARM_PRIORITY_NONE, p;
+ ALARM_ID_T a;
+ BOOL faultsActive = FALSE;
+ BOOL dialysateRecircBlocked = FALSE;
+ BOOL bloodRecircBlocked = FALSE;
+
+ // Reset priority FIFOs so we can re-determine them below
+ for ( p = ALARM_PRIORITY_NONE; p < NUM_OF_ALARM_PRIORITIES; p++ )
+ {
+ resetAlarmPriorityFIFO( p );
+ }
+
+ // Update FIFOs and sub-ranks per active alarms table - for alarm ranking purposes to determine "top" alarm
+ for ( a = ALARM_ID_NO_ALARM; a < NUM_OF_ALARM_IDS; a++ )
+ {
+ if ( TRUE == isAlarmActive( a ) )
+ {
+ ALARM_T props = getAlarmProperties( a );
+ ALARM_PRIORITY_T almPriority = props.alarmPriority;
+ U32 subRank = props.alarmSubRank;
+ U32 msSinceTriggered = calcTimeSince( getAlarmStartTime( a ) );
+
+ // See if this alarm is higher rank than highest active alarm in this priority category so far (lower rank # = higher rank)
+ if ( subRank <= alarmPriorityFIFO[ almPriority ].subRank )
+ {
+ // If sub-rank is a tie, see which alarm was triggered first
+ if ( subRank == alarmPriorityFIFO[ almPriority ].subRank )
+ {
+ if ( (S32)msSinceTriggered > alarmPriorityFIFO[ almPriority ].timeSinceTriggeredMS )
+ {
+ alarmPriorityFIFO[ almPriority ].alarmID = a;
+ alarmPriorityFIFO[ almPriority ].subRank = subRank;
+ alarmPriorityFIFO[ almPriority ].timeSinceTriggeredMS = (S32)msSinceTriggered;
+ }
+ }
+ // Otherwise, this alarm simply outranks current candidate and wins outright
+ else
+ {
+ alarmPriorityFIFO[ almPriority ].alarmID = a;
+ alarmPriorityFIFO[ almPriority ].subRank = subRank;
+ alarmPriorityFIFO[ almPriority ].timeSinceTriggeredMS = (S32)msSinceTriggered;
+ }
+ }
+ // Track highest priority alarm found so far of all priority categories
+ highestPriority = MAX( almPriority, highestPriority );
+ // Track whether any active faults have been found so far
+ if ( TRUE == props.alarmIsFault )
+ {
+ faultsActive = TRUE;
+ }
+ // Track whether any active alarms prevent dialysate re-circulation so far
+ if ( TRUE == props.alarmNoDialysateRecirc )
+ {
+ dialysateRecircBlocked = TRUE;
+ }
+ // Track whether any active alarms prevent blood re-circulation so far
+ if ( TRUE == props.alarmNoBloodRecirc )
+ {
+ bloodRecircBlocked = TRUE;
+ }
+ }
+ }
+
+ // Update alarm to display per highest priority FIFO
+ alarmStatus.alarmsState = highestPriority;
+ alarmStatus.alarmTop = alarmPriorityFIFO[ highestPriority ].alarmID;
+ alarmStatus.topAlarmConditionDetected = isAlarmConditionDetected( alarmStatus.alarmTop );
+ alarmStatus.systemFault = faultsActive;
+ alarmStatus.noBloodRecirc = bloodRecircBlocked;
+ alarmStatus.noDialRecirc = dialysateRecircBlocked;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setAlarmLamp function sets the alarm lamp pattern according to the
+ * current state of alarms.
+ * @details Inputs: none
+ * @details Outputs: Alarm lamp patter set according to current alarms status.
+ * @return none
+ *************************************************************************/
+static void setAlarmLamp( void )
+{
+ // Set alarm lamp pattern to appropriate pattern for current alarm state
+ if ( getCurrentAlarmLampPattern() != LAMP_PATTERN_MANUAL )
+ {
+ switch ( alarmStatus.alarmsState )
+ {
+ case ALARM_PRIORITY_NONE:
+ requestAlarmLampPattern( LAMP_PATTERN_OK );
+ break;
+
+ case ALARM_PRIORITY_LOW:
+ requestAlarmLampPattern( LAMP_PATTERN_LOW_ALARM );
+ break;
+
+ case ALARM_PRIORITY_MEDIUM:
+ requestAlarmLampPattern( LAMP_PATTERN_MED_ALARM );
+ break;
+
+ case ALARM_PRIORITY_HIGH:
+ {
+ ALARM_T propsTop = getAlarmProperties( alarmStatus.alarmTop );
+
+ if ( TRUE == propsTop.alarmIsFault )
+ {
+ requestAlarmLampPattern( LAMP_PATTERN_FAULT );
+ }
+ else
+ {
+ requestAlarmLampPattern( LAMP_PATTERN_HIGH_ALARM );
+ }
+ }
+ break;
+
+ default:
+ requestAlarmLampPattern( LAMP_PATTERN_FAULT );
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_LAMP_INVALID_ALARM_STATE, alarmStatus.alarmsState )
+ break;
+ }
+ }
+
+ // Execute alarm lamp controller
+ execAlarmLamp();
+
+ // Set lamp on flag to match current state of alarm lamp
+ if ( getCurrentAlarmLampPattern() != LAMP_PATTERN_MANUAL )
+ {
+ alarmStatus.lampOn = getAlarmLampOn();
+ }
+ else
+ {
+ alarmStatus.lampOn = FALSE;
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setAlarmAudio function sets the alarm audio pattern according to
+ * the current state of alarms.
+ * @details Inputs: alarmAudioTestToneRequested
+ * @details Outputs: alarmAudioTestToneRequested
+ * @return none
+ *************************************************************************/
+static void setAlarmAudio( void )
+{
+ U32 volume = getAlarmAudioVolume();
+
+ // If audio test in progress, play test tone.
+ if ( TRUE == alarmAudioTestToneRequested )
+ { // Play test tone at min volume
+// setAlarmAudioState( ALARM_AUDIO_TEST_TONE,
+// ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[MAX_ALARM_AUDIO_VOLUME_INDEX][ALARM_AUDIO_VOLUME_GAIN],
+// ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[MAX_ALARM_AUDIO_VOLUME_INDEX][ALARM_AUDIO_VOLUME_DIVIDER] );
+ // If we're in Fault mode, ensure audio test tone request is cancelled.
+ if ( MODE_FAUL == getCurrentOperationMode() )
+ {
+ alarmAudioTestToneRequested = FALSE;
+ }
+
+ }
+ // If alarm silenced, play no alarm audio.
+ else if ( ( ALARM_PRIORITY_NONE == alarmStatus.alarmsState ) || ( TRUE == alarmStatus.alarmsSilenced ) )
+ {
+// setAlarmAudioState( ALARM_PRIORITY_NONE,
+// ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[volume][ALARM_AUDIO_VOLUME_GAIN],
+// ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[volume][ALARM_AUDIO_VOLUME_DIVIDER] );
+ }
+ // Otherwise, play alarm audio as appropriate based on current alarm status
+ else
+ {
+ if ( alarmStatus.alarmsState < NUM_OF_ALARM_PRIORITIES )
+ {
+#ifndef _RELEASE_
+// if ( getSoftwareConfigStatus( SW_CONFIG_DISABLE_ALARM_AUDIO ) != SW_CONFIG_ENABLE_VALUE )
+#endif
+ {
+// setAlarmAudioState( alarmStatus.alarmsState,
+// ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[volume][ALARM_AUDIO_VOLUME_GAIN],
+// ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[volume][ALARM_AUDIO_VOLUME_DIVIDER] );
+ }
+ }
+// else
+// {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_AUDIO_INVALID_ALARM_STATE, alarmStatus.alarmsState )
+// setAlarmAudioState( ALARM_PRIORITY_HIGH,
+// ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[volume][ALARM_AUDIO_VOLUME_GAIN],
+// ALARM_AUDIO_DIVIDER_LOOKUP_TABLE[volume][ALARM_AUDIO_VOLUME_DIVIDER] );
+// }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The updateAlarmsSilenceStatus function updates the alarms silence state.
+ * @details Inputs: alarmStatus
+ * @details Outputs: alarmStatus
+ * @return none
+ *************************************************************************/
+static void updateAlarmsSilenceStatus( void )
+{
+ // If alarms not silenced, reset alarms silence related properties
+ if ( TRUE != alarmStatus.alarmsSilenced )
+ {
+ alarmStatus.alarmsSilenceExpiresIn = 0;
+ alarmStatus.alarmsSilenceStart = 0;
+ }
+ else
+ {
+ U32 timeSinceAlarmSilenceStart = calcTimeSince( alarmStatus.alarmsSilenceStart ) / MS_PER_SECOND;
+
+ if ( timeSinceAlarmSilenceStart >= ALARM_SILENCE_EXPIRES_IN_SECS )
+ {
+ alarmStatus.alarmsSilenceExpiresIn = 0;
+ }
+ else
+ {
+ alarmStatus.alarmsSilenceExpiresIn = ALARM_SILENCE_EXPIRES_IN_SECS - timeSinceAlarmSilenceStart;
+ }
+ // If alarms silence expires, end it
+ if ( 0 == alarmStatus.alarmsSilenceExpiresIn )
+ {
+ alarmStatus.alarmsSilenced = FALSE;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The updateAlarmsFlags function updates the alarms flags of the alarms
+ * status record.
+ * @details Inputs: alarmStatus, alarmIsActive, ALARM_TABLE, alarmButtonBlockers
+ * @details Outputs: alarmStatus, alarmUserRecoveryActionEnabled,
+ * @return none
+ *************************************************************************/
+static void updateAlarmsFlags( void )
+{
+ BOOL systemFault = FALSE;
+ BOOL stop = FALSE;
+ BOOL noClear = FALSE;
+ BOOL noResume = FALSE;
+ BOOL noResumePerAlarmPropertyOnly = FALSE;
+ BOOL noRinseback = FALSE;
+ BOOL noEndTreatment = FALSE;
+ BOOL endTxOnlyAlarmActive = FALSE;
+ BOOL usrAckReq = FALSE;
+ BOOL noMinimize = TRUE;
+ TD_OP_MODE_T currentMode = getCurrentOperationMode();
+ ALARM_T propsTop = getAlarmProperties( alarmStatus.alarmTop );
+ ALARM_ID_T a;
+
+ // Set user alarm recovery actions allowed by state flags
+ alarmButtonBlockers[ ALARM_BUTTON_STATE_BLOCK_RESUME ] = ( TRUE == alarmUserRecoveryActionEnabled[ ALARM_USER_ACTION_RESUME ] ? FALSE : TRUE );
+ alarmButtonBlockers[ ALARM_BUTTON_STATE_BLOCK_RINSEBACK ] = ( TRUE == alarmUserRecoveryActionEnabled[ ALARM_USER_ACTION_RINSEBACK ] ? FALSE : TRUE );
+ alarmButtonBlockers[ ALARM_BUTTON_STATE_BLOCK_END_TREATMENT ] = ( TRUE == alarmUserRecoveryActionEnabled[ ALARM_USER_ACTION_END_TREATMENT ] ? FALSE : TRUE );
+ // Reset user alarm recovery actions allowed by active alarms flags
+ alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_RESUME ] = FALSE;
+ alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_RINSEBACK ] = FALSE;
+ alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_END_TREATMENT ] = FALSE;
+
+ // Determine alarm flags
+ for ( a = ALARM_ID_NO_ALARM; a < NUM_OF_ALARM_IDS; a++ )
+ {
+ if ( TRUE == isAlarmActive( a ) )
+ {
+ ALARM_T props = getAlarmProperties( a );
+
+ systemFault = ( TRUE == props.alarmIsFault ? TRUE : systemFault );
+ stop = ( TRUE == props.alarmStops ? TRUE : stop );
+ noClear = ( TRUE == props.alarmNoClear ? TRUE : noClear );
+ noResumePerAlarmPropertyOnly = ( props.alarmNoResume ? TRUE : noResumePerAlarmPropertyOnly );
+ // Set user alarm recovery actions allowed flags
+ alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_RESUME ] |= props.alarmNoResume;
+ alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_RINSEBACK ] |= props.alarmNoRinseback;
+ alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_END_TREATMENT ] |= props.alarmNoEndTreatment;
+ if ( TRUE == alarmUserRecoveryActionEnabled[ ALARM_USER_ACTION_RESUME ] )
+ {
+ noResume = ( TRUE == props.alarmNoResume ? TRUE : noResume );
+ }
+ else
+ {
+ noResume = TRUE;
+ }
+ if ( TRUE == alarmUserRecoveryActionEnabled[ ALARM_USER_ACTION_RINSEBACK ] )
+ {
+ noRinseback = ( TRUE == props.alarmNoRinseback ? TRUE : noRinseback );
+ }
+ else
+ {
+ noRinseback = TRUE;
+ }
+ if ( TRUE == alarmUserRecoveryActionEnabled[ ALARM_USER_ACTION_END_TREATMENT ] )
+ {
+ noEndTreatment = ( TRUE == props.alarmNoEndTreatment ? TRUE : noEndTreatment );
+ }
+ else
+ {
+ noEndTreatment = TRUE;
+ }
+ // if there are any active alarms that only allow end treatment, set flag so we can ensure we do not allow OK option.
+ if ( ( TRUE == props.alarmNoResume ) &&
+ ( TRUE == props.alarmNoRinseback ) &&
+ ( FALSE == props.alarmNoEndTreatment ) )
+ {
+ endTxOnlyAlarmActive = TRUE;
+ }
+ } // If alarm active
+ } // Alarm table loop
+
+ // If top alarm condition not cleared, block resume
+ if ( TRUE == alarmStatus.topAlarmConditionDetected )
+ {
+ noResume = TRUE;
+ }
+
+ // If top alarm has clear only property or no other user options enabled for recoverable alarm and condition cleared, set user ack flag and block other flags
+ if ( ( TRUE == propsTop.alarmClearOnly ) ||
+ ( ( FALSE == alarmStatus.noClear ) && ( TRUE == noResume ) && ( TRUE == noRinseback ) && ( TRUE == noEndTreatment ) &&
+ ( FALSE == alarmStatus.topAlarmConditionDetected ) ) )
+ {
+ usrAckReq = TRUE;
+ noResume = TRUE;
+ noRinseback = TRUE;
+ noEndTreatment = TRUE;
+ }
+
+ // if OK option enabled and there are any active alarms that only allow end treatment, block OK option and allow end treatment option (DEN-16594).
+ if ( ( TRUE == usrAckReq ) && ( TRUE == endTxOnlyAlarmActive ) )
+ {
+ usrAckReq = FALSE;
+ noEndTreatment = FALSE;
+ }
+
+ // If AC power is out, block all user options
+// if ( TRUE == getCPLDACPowerLossDetected() )
+// {
+// usrAckReq = FALSE;
+// noResume = TRUE;
+// noRinseback = TRUE;
+// noEndTreatment = TRUE;
+// }
+
+ // If in Treatment-Stop state or Fault/Service/Standby Mode, allow user to minimize the alarm window
+// if ( ( MODE_FAUL == currentMode ) || ( MODE_SERV == currentMode ) || ( MODE_STAN == currentMode ) ||
+// ( ( MODE_TREA == currentMode ) && ( TREATMENT_STOP_STATE == getTreatmentState() ) ) )
+ {
+ noMinimize = FALSE;
+ }
+
+ // Set updated alarm flags
+ alarmStatus.systemFault = systemFault;
+ alarmStatus.stop = stop;
+ alarmStatus.noClear = noClear;
+ alarmStatus.noResume = noResume;
+ alarmStatus.noRinseback = noRinseback;
+ alarmStatus.noEndTreatment = noEndTreatment;
+ alarmStatus.ok = usrAckReq;
+ alarmStatus.noMinimize = noMinimize;
+ resumeBlockedByAlarmProperty = noResumePerAlarmPropertyOnly;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The clearAllRecoverableAlarms function clears all currently active
+ * recoverable alarms.
+ * @details Inputs: ALARM_TABLE[]
+ * @details Outputs: alarmIsActive[]
+ * @param action user action that prompted clearing of recoverable alarms
+ * @return TRUE if all recoverable alarms cleared, FALSE if any left active
+ *************************************************************************/
+static BOOL clearAllRecoverableAlarms( ALARM_USER_ACTION_T action )
+{
+ BOOL result = TRUE;
+ ALARM_ID_T a;
+
+ // assigning to 1 in order to prevent ALARM_ID_NO_ALARM being cleared
+ // which will cause a fault
+ for ( a = ( ( ALARM_ID_T ) 1 ); a < NUM_OF_ALARM_IDS; a++ )
+ {
+ ALARM_T props = getAlarmProperties( a );
+
+ // Clear alarm if alarm allowed to be cleared and not clear only (those are cleared individually)
+ if ( ( FALSE == props.alarmNoClear ) && ( FALSE == props.alarmClearOnly ) )
+ {
+ // Clear alarm if active and condition not active
+ if ( ( TRUE == isAlarmActive( a ) ) &&
+ ( ( TRUE == props.alarmConditionClearImmed ) || ( isAlarmConditionDetected( a ) != TRUE ) || ( action != ALARM_USER_ACTION_RESUME ) ) )
+ {
+ TD_OP_MODE_T mode = getCurrentOperationMode();
+ U32 sub = getCurrentSubMode();
+
+ // check special cases where we do not want to clear this alarm - otherwise, clear it
+ if ( ( ALARM_ID_DG_CREATING_DIALYSATE_PLEASE_WAIT == a ) && ( TRUE == isAlarmConditionDetected( a ) ) && ( mode != MODE_POST ) &&
+ ( action != ALARM_USER_ACTION_RINSEBACK ) && ( action != ALARM_USER_ACTION_END_TREATMENT ) )
+ {
+ // do not clear this alarm if condition not cleared first (unless treatment is over)
+ result = FALSE;
+ }
+ else
+ {
+ // clear this alarm
+ clearAlarmTD( a );
+ }
+ }
+ else if ( TRUE == isAlarmActive( a ) )
+ {
+ result = FALSE; // we didn't clear this alarm because condition still active
+ }
+ }
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The resetAlarmPriorityFIFO function resets a FIFO for a given alarm
+ * priority.
+ * @details Inputs: none
+ * @details Outputs: alarmPriorityFIFO[]
+ * @param priority priority of FIFO to reset
+ * @return none
+ *************************************************************************/
+static void resetAlarmPriorityFIFO( ALARM_PRIORITY_T priority )
+{
+ // Verify priority
+ if ( priority < NUM_OF_ALARM_PRIORITIES )
+ {
+ alarmPriorityFIFO[ priority ].alarmID = ALARM_ID_NO_ALARM;
+ alarmPriorityFIFO[ priority ].subRank = LOWEST_ALARM_SUB_RANK;
+ alarmPriorityFIFO[ priority ].timeSinceTriggeredMS = -1;
+ }
+ else
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_INVALID_FIFO_TO_RESET, priority )
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The publishAlarmInfo function publishes alarm information and status
+ * at the set intervals.
+ * @details Inputs: alarmInfoPublicationTimerCounter, alarmButtonBlockers
+ * @details Outputs: alarmStatusPublicationTimerCounter
+ * @return none
+ *************************************************************************/
+static void publishAlarmInfo( void )
+{
+ // Publish alarm status at interval
+ if ( ++alarmStatusPublicationTimerCounter >= getU32OverrideValue( &alarmStatusPublishInterval ) )
+ {
+ // Lamp and audio timing sync'd with broadcast so UI can stay in sync with lamp rhythm
+ setAlarmLamp();
+ setAlarmAudio();
+// broadcastAlarmStatus( alarmStatus );
+ alarmStatusPublicationTimerCounter = 0;
+ }
+
+ // Publish voltages monitor data on interval
+ if ( ++alarmInfoPublicationTimerCounter >= getU32OverrideValue( &alarmInfoPublishInterval ) )
+ {
+ ALARM_INFO_PAYLOAD_T data;
+
+ data.audioVolume = MAX_ALARM_VOLUME_LEVEL - getAlarmAudioVolume(); // convert back to 1..5 volume level for publication
+ data.audioCurrHG = getAlarmAudioPrimaryHighGainCurrent();
+ data.audioCurrLG = getAlarmAudioPrimaryLowGainCurrent();
+ data.backupAudioCurr = getAlarmAudioBackupCurrent();
+// data.safetyShutdown = isSafetyShutdownActivated();
+// data.acPowerLost = getCPLDACPowerLossDetected();
+ data.uiAlarmButtonBlocks[ ALARM_BUTTON_TABLE_BLOCK_RESUME ] = (U08)alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_RESUME ];
+ data.uiAlarmButtonBlocks[ ALARM_BUTTON_TABLE_BLOCK_RINSEBACK ] = (U08)alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_RINSEBACK ];
+ data.uiAlarmButtonBlocks[ ALARM_BUTTON_TABLE_BLOCK_END_TREATMENT ] = (U08)alarmButtonBlockers[ ALARM_BUTTON_TABLE_BLOCK_END_TREATMENT ];
+ data.uiAlarmButtonBlocks[ ALARM_BUTTON_STATE_BLOCK_RESUME ] = (U08)alarmButtonBlockers[ ALARM_BUTTON_STATE_BLOCK_RESUME ];
+ data.uiAlarmButtonBlocks[ ALARM_BUTTON_STATE_BLOCK_RINSEBACK ] = (U08)alarmButtonBlockers[ ALARM_BUTTON_STATE_BLOCK_RINSEBACK ];
+ data.uiAlarmButtonBlocks[ ALARM_BUTTON_STATE_BLOCK_END_TREATMENT ] = (U08)alarmButtonBlockers[ ALARM_BUTTON_STATE_BLOCK_END_TREATMENT ];
+
+// broadcastData( MSG_ID_HD_ALARM_INFORMATION_DATA, COMM_BUFFER_OUT_CAN_TD_BROADCAST, (U08*)&data, sizeof( ALARM_INFO_PAYLOAD_T ) );
+ alarmInfoPublicationTimerCounter = 0;
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getAlarmAudioVolume function gets the current alarm audio volume level.
+ * @details Inputs: alarmAudioVolumeLevel
+ * @details Outputs: none
+ * @return the current alarm audio volume level.
+ *************************************************************************/
+U32 getAlarmAudioVolume( void )
+{
+ U32 result = alarmAudioVolumeLevel.data;
+
+#ifndef _RELEASE_
+ // Check the software configurations
+// if ( SW_CONFIG_ENABLE_VALUE == getSoftwareConfigStatus( SW_CONFIG_ENABLE_ALARM_VOLUME_DEFAULT_LOW ) )
+// {
+// result = MIN_ALARM_VOLUME_ATTENUATION;
+// }
+#endif
+
+ if ( OVERRIDE_KEY == alarmAudioVolumeLevel.override )
+ {
+ result = alarmAudioVolumeLevel.ovData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getAlarmAudioPrimaryHighGainCurrent function gets the current alarm
+ * audio high gain current.
+ * @details Inputs: alarmPrimaryAudioCurrentHG
+ * @details Outputs: none
+ * @return the current alarm audio high gain current (in mA).
+ *************************************************************************/
+F32 getAlarmAudioPrimaryHighGainCurrent( void )
+{
+ F32 result = alarmPrimaryAudioCurrentHG.data;
+
+ if ( OVERRIDE_KEY == alarmPrimaryAudioCurrentHG.override )
+ {
+ result = alarmPrimaryAudioCurrentHG.ovData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getAlarmAudioPrimaryLowGainCurrent function gets the current alarm
+ * audio low gain current.
+ * @details Inputs: alarmPrimaryAudioCurrentLG
+ * @details Outputs: none
+ * @return the current alarm audio low gain current (in mA).
+ *************************************************************************/
+F32 getAlarmAudioPrimaryLowGainCurrent( void )
+{
+ F32 result = alarmPrimaryAudioCurrentLG.data;
+
+ if ( OVERRIDE_KEY == alarmPrimaryAudioCurrentLG.override )
+ {
+ result = alarmPrimaryAudioCurrentLG.ovData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getAlarmAudioBackupCurrent function gets the current backup alarm
+ * audio current.
+ * @details Inputs: alarmBackupAudioCurrent
+ * @details Outputs: none
+ * @return the current backup alarm audio current (in mA).
+ *************************************************************************/
+F32 getAlarmAudioBackupCurrent( void )
+{
+ F32 result = alarmBackupAudioCurrent.data;
+
+ if ( OVERRIDE_KEY == alarmBackupAudioCurrent.override )
+ {
+ result = alarmBackupAudioCurrent.ovData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execAlarmAudioSelfTest function outputs a test audio tone and
+ * measures the audio current level.
+ * @details Inputs: alarmAudioSelfTestState, audioTestStartTime
+ * @details Outputs: audioTestStartTime, alarmAudioTestToneRequested
+ * @return the current backup alarm audio current (in mA).
+ *************************************************************************/
+SELF_TEST_STATUS_T execAlarmAudioSelfTest( void )
+{
+ SELF_TEST_STATUS_T result = SELF_TEST_STATUS_IN_PROGRESS;
+// F32 almLGCurrent = getIntADCVoltageConverted( INT_ADC_PRIMARY_ALARM_CURRENT_LG );
+//
+// switch ( alarmAudioSelfTestState )
+// {
+// case ALARM_AUDIO_SELF_TEST_STATE_START:
+// if ( almLGCurrent < ALARM_AUDIO_CURRENT_LG_MAX_MA )
+// {
+// audioTestStartTime = getMSTimerCount();
+// // Start test tone
+// alarmAudioTestToneRequested = TRUE;
+// setAlarmAudio();
+// alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_PRIMARY;
+// }
+// else
+// {
+// result = SELF_TEST_STATUS_FAILED;
+// SET_ALARM_WITH_2_F32_DATA( ALARM_ID_HD_ALARM_AUDIO_SELF_TEST_FAILURE, almLGCurrent, ALARM_AUDIO_CURRENT_LG_MAX_MA );
+// alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_COMPLETE;
+// }
+// break;
+//
+// case ALARM_AUDIO_SELF_TEST_STATE_PRIMARY:
+// // Check if alarm audio current is sufficiently high indicating alarm tone is being output
+// if ( almLGCurrent > ALARM_AUDIO_CURRENT_LG_MIN_MA )
+// {
+// alarmAudioTestToneRequested = FALSE;
+// audioTestStartTime = getMSTimerCount();
+// alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_NO_TONE;
+// }
+// else if ( TRUE == didTimeout( audioTestStartTime, ALARM_AUDIO_MAX_TEST_TIME_MS ) )
+// {
+// alarmAudioTestToneRequested = FALSE;
+// result = SELF_TEST_STATUS_FAILED;
+// SET_ALARM_WITH_2_F32_DATA( ALARM_ID_HD_ALARM_AUDIO_SELF_TEST_FAILURE, almLGCurrent, ALARM_AUDIO_CURRENT_LG_MIN_MA );
+// alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_COMPLETE;
+// }
+// break;
+//
+// case ALARM_AUDIO_SELF_TEST_STATE_NO_TONE:
+// if ( almLGCurrent < ALARM_AUDIO_CURRENT_LG_MAX_MA )
+// {
+// result = SELF_TEST_STATUS_PASSED;
+// alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_COMPLETE;
+// }
+// else if ( TRUE == didTimeout( audioTestStartTime, ALARM_AUDIO_MAX_TEST_TIME_MS ) )
+// {
+// result = SELF_TEST_STATUS_FAILED;
+// SET_ALARM_WITH_2_F32_DATA( ALARM_ID_HD_ALARM_AUDIO_SELF_TEST_FAILURE, almLGCurrent, ALARM_AUDIO_CURRENT_LG_MAX_MA );
+// alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_COMPLETE;
+// }
+// break;
+//
+// case ALARM_AUDIO_SELF_TEST_STATE_COMPLETE:
+// alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_START; // Should only get here if re-starting self-tests.
+// break;
+//
+// default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_HD_INVALID_ALARM_AUDIO_STATE, (U32)alarmAudioSelfTestState )
+// break;
+// }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The resetAlarmAudioPOSTState function resets the alarm audio POST state.
+ * @details Inputs: none
+ * @details Outputs: alarmAudioSelfTestState
+ * @return none
+ *************************************************************************/
+void resetAlarmAudioPOSTState( void )
+{
+ alarmAudioSelfTestState = ALARM_AUDIO_SELF_TEST_STATE_START;
+}
+
+
+/*************************************************************************
+ * TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/*********************************************************************//**
+ * @brief
+ * The testSetAlarmStartOverride function overrides the start time
+ * for a given alarm with the alarm management with a given start time.
+ * @details Inputs: none
+ * @details Outputs: alarmStartedAt[]
+ * @param alarmID ID of alarm to override start time for
+ * @param value override time since start (in ms) for the given alarm ID
+ * @return TRUE if override successful, FALSE if not
+ *************************************************************************/
+BOOL testSetAlarmStartOverride( U32 alarmID, U32 value )
+{
+ BOOL result = FALSE;
+
+ if ( alarmID < NUM_OF_ALARM_IDS )
+ {
+ // Verify tester has logged in with HD
+ if ( TRUE == isTestingActivated() )
+ {
+ U32 tim = getMSTimerCount();
+
+ if ( tim > value )
+ {
+ result = TRUE;
+ alarmStartedAt[ alarmID ].ovData = ( tim - value );
+ alarmStartedAt[ alarmID ].override = OVERRIDE_KEY;
+ }
+ }
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetAlarmStartOverride function resets the override of the
+ * start time for a given alarm with the alarm management.
+ * @details Inputs: none
+ * @details Outputs: alarmStartedAt[]
+ * @param alarmID ID of alarm to reset override of start time for
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetAlarmStartOverride( U32 alarmID )
+{
+ BOOL result = FALSE;
+
+ if ( alarmID < NUM_OF_ALARM_IDS )
+ {
+ // Verify tester has logged in with HD
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmStartedAt[ alarmID ].override = OVERRIDE_RESET;
+ alarmStartedAt[ alarmID ].ovData = alarmStartedAt[ alarmID ].ovInitData;
+ }
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testClearAllAlarms function clears all active alarms, even if they
+ * are non-recoverable or faults. The caller of this function must provide
+ * the correct 32-bit key. A Dialin user must also be logged into HD.
+ * @details Inputs: none
+ * @details Outputs: alarmIsActive[], alarmStartedAt[]
+ * @param key 32-bit supervisor alarm key required to perform this function
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testClearAllAlarms( U32 key )
+{
+ BOOL result = FALSE;
+
+ // Verify key
+ if ( SUPERVISOR_ALARM_KEY == key )
+ {
+ // Verify tester has logged in with HD
+ if ( TRUE == isTestingActivated() )
+ {
+ ALARM_ID_T a;
+
+ // clear the flags when Dialin clears alarms
+ resumeBlockedByAlarmProperty = FALSE;
+
+ // Clear all active alarms
+ for ( a = ALARM_ID_NO_ALARM; a < NUM_OF_ALARM_IDS; a++ )
+ {
+ if ( TRUE == isAlarmActive( a ) )
+ {
+ ALARM_T props = getAlarmProperties( a );
+ ALARM_ID_DATA_PUBLISH_T data;
+
+ data.alarmID = (U32)a;
+
+ broadcastData( MSG_ID_ALARM_CLEARED, COMM_BUFFER_OUT_CAN_TD_ALARM, (U08*)&data, sizeof( ALARM_ID_DATA_PUBLISH_T ) );
+ setAlarmActive( a , FALSE );
+ alarmStartedAt[ a ].data = 0;
+ // Clear FIFO if this alarm was in it
+ if ( alarmPriorityFIFO[ props.alarmPriority ].alarmID == a )
+ {
+ resetAlarmPriorityFIFO( props.alarmPriority );
+ }
+ }
+ }
+ result = TRUE;
+ }
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testSetAlarmStatusPublishIntervalOverride function sets the override of the
+ * alarm status publication interval.
+ * @details Inputs: none
+ * @details Outputs: alarmStatusPublishInterval
+ * @param ms milliseconds between alarm status broadcasts
+ * @return TRUE if override set successful, FALSE if not
+ *************************************************************************/
+BOOL testSetAlarmStatusPublishIntervalOverride( U32 ms )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ U32 intvl = ms / TASK_GENERAL_INTERVAL;
+
+ result = TRUE;
+ alarmStatusPublishInterval.ovData = intvl;
+ alarmStatusPublishInterval.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetAlarmStatusPublishIntervalOverride function resets the override of the
+ * alarm status publication interval.
+ * @details Inputs: none
+ * @details Outputs: alarmStatusPublishInterval
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetAlarmStatusPublishIntervalOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmStatusPublishInterval.override = OVERRIDE_RESET;
+ alarmStatusPublishInterval.ovData = alarmStatusPublishInterval.ovInitData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testSetAlarmInfoPublishIntervalOverride function sets the override of the
+ * alarm information publication interval.
+ * @details Inputs: none
+ * @details Outputs: alarmInfoPublishInterval
+ * @param ms milliseconds between alarm info broadcasts
+ * @return TRUE if override set successful, FALSE if not
+ *************************************************************************/
+BOOL testSetAlarmInfoPublishIntervalOverride( U32 ms )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ U32 intvl = ms / TASK_GENERAL_INTERVAL;
+
+ result = TRUE;
+ alarmInfoPublishInterval.ovData = intvl;
+ alarmInfoPublishInterval.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetAlarmInfoPublishIntervalOverride function resets the override of the
+ * alarm information publication interval.
+ * @details Inputs: none
+ * @details Outputs: alarmInfoPublishInterval
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetAlarmInfoPublishIntervalOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmInfoPublishInterval.override = OVERRIDE_RESET;
+ alarmInfoPublishInterval.ovData = alarmInfoPublishInterval.ovInitData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testSetAlarmAudioVolumeLevelOverride function sets the override of the
+ * alarm audio volume.
+ * @details Inputs: none
+ * @details Outputs: alarmAudioVolumeLevel
+ * @param volume volume level (1..5) of alarm audio
+ * @return TRUE if override set successful, FALSE if not
+ *************************************************************************/
+BOOL testSetAlarmAudioVolumeLevelOverride( U32 volume )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmAudioVolumeLevel.ovData = MAX_ALARM_VOLUME_LEVEL - volume;
+ alarmAudioVolumeLevel.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetAlarmAudioVolumeLevelOverride function resets the override of the
+ * alarm audio volume.
+ * @details Inputs: none
+ * @details Outputs: alarmAudioVolumeLevel
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetAlarmAudioVolumeLevelOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmAudioVolumeLevel.override = OVERRIDE_RESET;
+ alarmAudioVolumeLevel.ovData = alarmAudioVolumeLevel.ovInitData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testSetPrimaryAlarmAudioCurrentHGOverride function sets the override of the
+ * alarm audio current (high gain) in mA.
+ * @details Inputs: none
+ * @details Outputs: alarmPrimaryAudioCurrentHG
+ * @param mA milliamps measured from high gain channel of primary alarm audio
+ * @return TRUE if override set successful, FALSE if not
+ *************************************************************************/
+BOOL testSetPrimaryAlarmAudioCurrentHGOverride( F32 mA )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmPrimaryAudioCurrentHG.ovData = mA;
+ alarmPrimaryAudioCurrentHG.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetPrimaryAlarmAudioCurrentHGOverride function resets the override of the
+ * alarm audio current (high gain).
+ * @details Inputs: none
+ * @details Outputs: alarmPrimaryAudioCurrentHG
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetPrimaryAlarmAudioCurrentHGOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmPrimaryAudioCurrentHG.override = OVERRIDE_RESET;
+ alarmPrimaryAudioCurrentHG.ovData = alarmPrimaryAudioCurrentHG.ovInitData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testSetPrimaryAlarmAudioCurrentLGOverride function sets the override of the
+ * alarm audio current (low gain) in mA.
+ * @details Inputs: none
+ * @details Outputs: alarmPrimaryAudioCurrentLG
+ * @param mA milliamps measured from low gain channel of primary alarm audio
+ * @return TRUE if override set successful, FALSE if not
+ *************************************************************************/
+BOOL testSetPrimaryAlarmAudioCurrentLGOverride( F32 mA )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmPrimaryAudioCurrentLG.ovData = mA;
+ alarmPrimaryAudioCurrentLG.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetPrimaryAlarmAudioCurrentLGOverride function resets the override of the
+ * alarm audio current (low gain).
+ * @details Inputs: none
+ * @details Outputs: alarmPrimaryAudioCurrentLG
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetPrimaryAlarmAudioCurrentLGOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmPrimaryAudioCurrentLG.override = OVERRIDE_RESET;
+ alarmPrimaryAudioCurrentLG.ovData = alarmPrimaryAudioCurrentLG.ovInitData;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testSetBackupAlarmAudioCurrentOverride function sets the override of the
+ * alarm audio current (backup) in mA.
+ * @details Inputs: none
+ * @details Outputs: alarmBackupAudioCurrent
+ * @param mA milliamps measured from backup channel of primary alarm audio
+ * @return TRUE if override set successful, FALSE if not
+ *************************************************************************/
+BOOL testSetBackupAlarmAudioCurrentOverride( F32 mA )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmBackupAudioCurrent.ovData = mA;
+ alarmBackupAudioCurrent.override = OVERRIDE_KEY;
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetBackupAlarmAudioCurrentOverride function resets the override of the
+ * alarm audio current (backup).
+ * @details Inputs: none
+ * @details Outputs: alarmBackupAudioCurrent
+ * @return TRUE if override reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetBackupAlarmAudioCurrentOverride( void )
+{
+ BOOL result = FALSE;
+
+ if ( TRUE == isTestingActivated() )
+ {
+ result = TRUE;
+ alarmBackupAudioCurrent.override = OVERRIDE_RESET;
+ alarmBackupAudioCurrent.ovData = alarmBackupAudioCurrent.ovInitData;
+ }
+
+ return result;
+}
+
+/**@}*/
Index: firmware/App/Services/AlarmMgmtTD.h
===================================================================
diff -u
--- firmware/App/Services/AlarmMgmtTD.h (revision 0)
+++ firmware/App/Services/AlarmMgmtTD.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,181 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file AlarmMgmtTD.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __ALARM_MGMT_TD_H__
+#define __ALARM_MGMT_TD_H__
+
+#include "TDCommon.h"
+#include "AlarmDefs.h"
+#include "AlarmMgmtSWFaults.h"
+
+/**
+ * @defgroup AlarmManagementTD AlarmManagementTD
+ * @brief Alarm Management service module for TD firmware. Provides general
+ * alarm managementfunctionality including support functions for triggering
+ * and clearingspecific alarms.
+ *
+ * @addtogroup AlarmManagementTD
+ * @{
+ */
+
+/// Interval (in ms) at which alarm lamp and audio control will be executed.
+#define ALARM_LAMP_AND_AUDIO_CONTROL_INTERVAL_MS 250
+
+#define MAX_ALARM_VOLUME_LEVEL 5 ///< Maximum alarm audio level.
+#define MAX_ALARM_VOLUME_ATTENUATION 4 ///< Maximum alarm audio attenuation.
+#define MIN_ALARM_VOLUME_ATTENUATION 0 ///< Minimum alarm audio attenuation.
+#define MAX_ALARM_LIST_SIZE 10 ///< Maximum number of active alarms inside alarm list.
+
+/// Enumeration of alarm actions.
+typedef enum Alarm_Actions
+{
+ ALARM_ACTION_STOP = 0, ///< Alarm state requests HD in safe state (pumps stopped, heater off, valves in safe state)
+ ALARM_ACTION_RESUME, ///< User selected resume from alarm recovery options
+ ALARM_ACTION_RINSEBACK, ///< User selected rinseback from alarm recovery options
+ ALARM_ACTION_END_TREATMENT, ///< User selected end treatment from alarm recovery options
+ ALARM_ACTION_ACK, ///< User selected Ack from alarm recovery options
+ NUMBER_OF_ALARM_ACTIONS ///< Number of alarm actions
+} ALARM_ACTION_T;
+
+#pragma pack(push, 4)
+/// Record structure for detailing the properties of the current composite alarm status.
+typedef struct
+{
+ ALARM_PRIORITY_T alarmsState; ///< Current alarm priority level
+ BOOL alarmsSilenced; ///< Alarms are currently silenced?
+ U32 alarmsSilenceStart; ///< Time stamp for when alarms were silenced (ms)
+ U32 alarmsSilenceExpiresIn; ///< Time until alarm silence expires (seconds)
+ BOOL alarmsToEscalate; ///< Are any active alarms due to escalate (should UI show count down timer?)
+ U32 alarmsEscalatesIn; ///< Time until alarm will escalate (seconds)
+ ALARM_ID_T alarmTop; ///< ID of current top alarm that will drive lamp/audio and UI should be displaying right now
+ BOOL topAlarmConditionDetected; ///< Condition for top alarm is still being detected
+ BOOL systemFault; ///< A system fault is active?
+ BOOL stop; ///< We should be in controlled stop right now
+ BOOL noClear; ///< No recovery will be possible
+ BOOL noResume; ///< Treatment may not be resumed at this time
+ BOOL noRinseback; ///< Rinseback may not be initiated at this time
+ BOOL noEndTreatment; ///< Ending the treatment is not an option at this time
+ BOOL noBloodRecirc; ///< No blood re-circulation allowed at this time
+ BOOL noDialRecirc; ///< No dialysate re-circulation allowed at this time
+ BOOL ok; ///< Display OK button instead of other options
+ BOOL noMinimize; ///< Prevent user from minimizing the alarm window
+ BOOL lampOn; ///< The alarm lamp is on
+ BOOL unused; ///< Flag not used - available
+} COMP_ALARM_STATUS_T;
+
+#pragma pack(pop)
+
+/// Enumeration of alarm button blockers.
+typedef enum Alarm_Button_Blockers
+{
+ ALARM_BUTTON_TABLE_BLOCK_RESUME = 0, ///< Alarm table properties are blocking alarm resume button
+ ALARM_BUTTON_TABLE_BLOCK_RINSEBACK, ///< Alarm table properties are blocking alarm rinseback button
+ ALARM_BUTTON_TABLE_BLOCK_END_TREATMENT, ///< Alarm table properties are blocking alarm end treatment button
+ ALARM_BUTTON_STATE_BLOCK_RESUME, ///< State properties are blocking alarm resume button
+ ALARM_BUTTON_STATE_BLOCK_RINSEBACK, ///< State properties are blocking alarm rinseback button
+ ALARM_BUTTON_STATE_BLOCK_END_TREATMENT, ///< State properties are blocking alarm end treatment button
+ NUM_OF_ALARM_BUTTON_BLOCKERS ///< Number of alarm actions
+} ALARM_BUTTON_BLOCKER_T;
+
+#pragma pack(push, 1)
+
+/// Payload record structure for the alarm info message.
+typedef struct
+{
+ U32 audioVolume; ///< Audio volume level (1..5)
+ F32 audioCurrHG; ///< Primary alarm audio current - high gain (mA)
+ F32 audioCurrLG; ///< Primary alarm audio current - low gain (mA)
+ F32 backupAudioCurr; ///< Backup alarm audio current (mA)
+ BOOL safetyShutdown; ///< Safety shutdown activated? (T/F)
+ BOOL acPowerLost; ///< Has A/C power been lost? (T/F)
+ U08 uiAlarmButtonBlocks[ NUM_OF_ALARM_BUTTON_BLOCKERS ]; ///< Flags indicating UI alarm buttons blocked by alarm table or state
+} ALARM_INFO_PAYLOAD_T;
+
+#pragma pack(pop)
+
+#pragma pack(push, 2)
+
+/// Payload record structure for an alarm status message.
+typedef struct
+{
+ U32 alarmState; ///< Alarm state: 0 = no alarms, 1 = low priority, 2 = medium priority, 3 = high priority
+ U32 alarmTop; ///< ID of top active alarm
+ U32 escalatesIn; ///< Top active alarm escalates in this many seconds
+ U32 silenceExpiresIn; ///< Silencing of alarms expires in this many seconds
+ U16 alarmsFlags; ///< Bit flags: 1 = true, 0 = false for each bit flag
+} ALARM_COMP_STATUS_PAYLOAD_T;
+
+#pragma pack(pop)
+
+/// Alarm list request response payload record structure.
+typedef struct
+{
+ BOOL accepted; ///< Accepted/Rejected.
+ U32 rejectionReason; ///< Rejection reason if not accepted.
+ U32 activeAlarmList[ MAX_ALARM_LIST_SIZE ]; ///< Active Alarm List array.
+} ACTIVE_ALARM_LIST_RESPONSE_PAYLOAD_T;
+
+// ********** public function prototypes **********
+
+void initAlarmMgmtTD( void );
+void execAlarmMgmt( void );
+
+void clearAlarmTD( ALARM_ID_T alarm );
+void activateAlarmNoData( ALARM_ID_T alarm );
+void activateAlarm1Data( ALARM_ID_T alarm, ALARM_DATA_T alarmData );
+void activateAlarm2Data( ALARM_ID_T alarm, ALARM_DATA_T alarmData1, ALARM_DATA_T alarmData2, BOOL outside );
+void setAlarmUserActionEnabled( ALARM_USER_ACTION_T action, BOOL enabled );
+void signalAlarmSilence( ALARM_SILENCE_CMD_T cmd );
+void signalAlarmUserActionInitiated( ALARM_USER_ACTION_T action );
+BOOL isAnyAlarmActive( void );
+BOOL isBloodRecircBlocked( void );
+BOOL isDialysateRecircBlocked( void );
+BOOL doesAlarmStatusIndicateStop( void );
+BOOL doesAlarmIndicateNoResume( void );
+BOOL doesAlarmStatusIndicateEndTxOnly( void );
+ALARM_PRIORITY_T getCurrentAlarmStatePriority( void );
+void setAlarmAudioVolume( U32 volumeLevel );
+
+void handleActiveAlarmListRequest( void );
+void handleResendActiveAlarmsRequest( void );
+
+U32 getAlarmAudioVolume( void );
+F32 getAlarmAudioPrimaryHighGainCurrent( void );
+F32 getAlarmAudioPrimaryLowGainCurrent( void );
+F32 getAlarmAudioBackupCurrent( void );
+SELF_TEST_STATUS_T execAlarmAudioSelfTest( void );
+void resetAlarmAudioPOSTState( void );
+
+BOOL testSetAlarmStartOverride( U32 alarmID, U32 value );
+BOOL testResetAlarmStartOverride( U32 alarmID );
+BOOL testClearAllAlarms( U32 key );
+BOOL testSetAlarmStatusPublishIntervalOverride( U32 ms );
+BOOL testResetAlarmStatusPublishIntervalOverride( void );
+BOOL testSetAlarmInfoPublishIntervalOverride( U32 ms );
+BOOL testResetAlarmInfoPublishIntervalOverride( void );
+BOOL testSetAlarmAudioVolumeLevelOverride( U32 volume );
+BOOL testResetAlarmAudioVolumeLevelOverride( void );
+BOOL testSetPrimaryAlarmAudioCurrentHGOverride( F32 mA );
+BOOL testResetPrimaryAlarmAudioCurrentHGOverride( void );
+BOOL testSetPrimaryAlarmAudioCurrentLGOverride( F32 mA );
+BOOL testResetPrimaryAlarmAudioCurrentLGOverride( void );
+BOOL testSetBackupAlarmAudioCurrentOverride( F32 mA );
+BOOL testResetBackupAlarmAudioCurrentOverride( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/CommBuffers.c
===================================================================
diff -u
--- firmware/App/Services/CommBuffers.c (revision 0)
+++ firmware/App/Services/CommBuffers.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,396 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file CommBuffers.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include
+#include
+#include // For memcpy()
+
+#include "CommBuffers.h"
+#include "SystemCommTD.h"
+#include "Timers.h"
+
+/**
+ * @addtogroup CommBuffers
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define COMM_BUFFER_LENGTH 768 ///< Max bytes in each comm buffer (each side of double buffer is this size)
+#define DOUBLE_BUFFERS 2 ///< Need 2 buffers for double buffering
+#define BUFFER_OVERFLOW_PERSISTENCE_MS 5000 ///< How many ms buffer overflows must persist before fault
+
+// ********** private data **********
+
+static volatile U32 commBufferByteCount[ NUM_OF_COMM_BUFFERS ][ DOUBLE_BUFFERS ]; ///< For each buffer, how many bytes does it contain? (also index to next available)
+static volatile U32 activeDoubleBuffer[ NUM_OF_COMM_BUFFERS ]; ///< For each buffer, which double buffer is being fed right now?
+static U08 commBuffers[ NUM_OF_COMM_BUFFERS ][ DOUBLE_BUFFERS ][ COMM_BUFFER_LENGTH ]; ///< Each is double buffered to avoid thread contention
+static U32 firstBufferOverflowTimeStamp = 0; ///< Time stamp of a prior overflow event - allows for an overflow persistence check
+
+// ********** private function prototypes **********
+
+static U32 switchDoubleBuffer( COMM_BUFFER_T buffer );
+static void getDataFromInactiveBuffer( COMM_BUFFER_T buffer, U08 *data, U32 len );
+
+/*********************************************************************//**
+ * @brief
+ * The initCommBuffers function initializes the CommBuffers module.
+ * @details Inputs: none
+ * @details Outputs: CommBuffers module initialized.
+ * @return none
+ *************************************************************************/
+void initCommBuffers( void )
+{
+ S32 b;
+
+ // Reset and zero out all buffers
+ for ( b = 0; b < NUM_OF_COMM_BUFFERS; b++ )
+ {
+ clearBuffer( (COMM_BUFFER_T)b );
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The clearBuffer function clears (empties) a given buffer.
+ * Caller should ensure buffer won't be used while this function is clearing
+ * the buffer.
+ * @details Inputs: none
+ * @details Outputs: given buffer is cleared.
+ * @param buffer the buffer to clear
+ * @return none
+ *************************************************************************/
+void clearBuffer( COMM_BUFFER_T buffer )
+{
+ if ( buffer < NUM_OF_COMM_BUFFERS )
+ {
+ S32 d;
+
+ // Thread protection for queue operations
+ _disable_IRQ();
+
+ activeDoubleBuffer[ buffer ] = 0;
+ for ( d = 0; d < DOUBLE_BUFFERS; d++ )
+ {
+ commBufferByteCount[ buffer ][ d ] = 0;
+ memset( &commBuffers[ buffer ][ d ][ 0 ], 0, COMM_BUFFER_LENGTH );
+ }
+
+ // Release thread protection
+ _enable_IRQ();
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The addToCommBuffer function adds data of specified length to a specified
+ * communication buffer. S/W fault if buffer too full to add data.
+ * This function will always add to the active double buffer.
+ * This function should only be called from the background, general, or
+ * priority tasks (BG or IRQ) for thread safety.
+ * @details Inputs: commBufferByteCount[], activeDoubleBuffer[]
+ * @details Outputs: commBuffers[], commBufferByteCount[]
+ * @param buffer which comm buffer to add data to
+ * @param data pointer to byte array containing data to add
+ * @param len length of data (in bytes)
+ * @return TRUE if data added to buffer successfully, FALSE if not
+ *************************************************************************/
+BOOL addToCommBuffer( COMM_BUFFER_T buffer, U08* data, U32 len )
+{
+ BOOL result = FALSE;
+
+ // Verify given buffer
+ if ( buffer < NUM_OF_COMM_BUFFERS )
+ {
+ BOOL bufferFull = FALSE;
+ U32 activeBuffer;
+ U32 currentActiveBufCount; // Where to start adding new data to buffer (after existing data)
+
+ if ( ( FALSE == isOnlyCANNode() ) || ( FALSE == isCANBoxForXmit( (CAN_MESSAGE_BOX_T)buffer ) ) )
+ {
+ // Thread protection for queue operations
+ _disable_IRQ();
+
+ activeBuffer = activeDoubleBuffer[ buffer ];
+ currentActiveBufCount = commBufferByteCount[ buffer ][ activeBuffer ];
+
+ // Check to make sure buffer is not too full to service this add
+ if ( len <= ( COMM_BUFFER_LENGTH - currentActiveBufCount ) )
+ {
+ U08 *buffPtr; // Buffer destination for added data
+
+ // Set destination pointer to end of active buffer data
+ buffPtr = &commBuffers[ buffer ][ activeBuffer ][ currentActiveBufCount ];
+ // Copy source data to destination buffer
+ memcpy( buffPtr, data, len );
+ // Adjust buffer count per this data add (also reserves space to add data before releasing thread protection)
+ commBufferByteCount[ buffer ][ activeBuffer ] += len;
+ // Data successfully added to buffer
+ result = TRUE;
+ }
+ else // Buffer too full to add this much data
+ {
+ bufferFull = TRUE;
+ }
+ // Release thread protection
+ _enable_IRQ();
+ }
+
+ // If buffer was full, check persistence - trigger s/w fault if persists
+ if ( TRUE == bufferFull )
+ {
+ clearBuffer( buffer );
+ // Not first overflow?
+ if ( firstBufferOverflowTimeStamp != 0 )
+ {
+ // If buffer overflows persists, fault
+ if ( calcTimeSince( firstBufferOverflowTimeStamp ) > BUFFER_OVERFLOW_PERSISTENCE_MS )
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_ADD_TOO_MUCH_DATA, (U32)buffer )
+ }
+ }
+ else // First overflow - set time stamp for persistence check
+ {
+ firstBufferOverflowTimeStamp = getMSTimerCount();
+ }
+ }
+ else
+ { // If good for persistence time period, reset persistence check
+ if ( ( firstBufferOverflowTimeStamp != 0 ) && ( calcTimeSince( firstBufferOverflowTimeStamp ) > BUFFER_OVERFLOW_PERSISTENCE_MS ) )
+ {
+ firstBufferOverflowTimeStamp = 0;
+ }
+ }
+ }
+ else // Invalid buffer given
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_ADD_INVALID_BUFFER, buffer )
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFromCommBuffer function fills a given byte array with a given
+ * number of bytes from a given buffer and returns the number of bytes
+ * retrieved from the buffer. This function will draw from the inactive
+ * double buffer first and, if needed, switch double buffers to draw the
+ * rest of the requested data.
+ * Only one function in one thread should be calling this function for a given
+ * buffer.
+ * @details Inputs: commBuffers[], commBufferByteCount[], activeDoubleBuffer[]
+ * @details Outputs: commBuffers[], commBufferByteCount[], activeDoubleBuffer[],
+ * and the given data array is populated with data from the buffer.
+ * @param buffer which comm buffer to retrieve data from
+ * @param data pointer to byte array to stuff data into
+ * @param len number of bytes to retrieve into given data array.
+ * @return the number of bytes retrieved.
+ *************************************************************************/
+U32 getFromCommBuffer( COMM_BUFFER_T buffer, U08* data, U32 len )
+{
+ U32 result = 0;
+
+ // Verify given buffer
+ if ( buffer < NUM_OF_COMM_BUFFERS )
+ {
+ // Thread protection for queue operations
+ _disable_IRQ();
+ // Verify requested # of bytes to get are in the buffer
+ if ( ( len <= ( COMM_BUFFER_LENGTH * DOUBLE_BUFFERS ) ) && ( len <= numberOfBytesInCommBuffer( buffer ) ) )
+ {
+ U32 activeBuffer = activeDoubleBuffer[ buffer ];
+ U32 inactiveBuffer = GET_TOGGLE( activeBuffer, 0, 1 );
+ U32 bytesInInactiveBuffer = commBufferByteCount[ buffer ][ inactiveBuffer ];
+ U32 sizeOfFirstConsumption = MIN( len, bytesInInactiveBuffer );
+
+ // See what we can get from inactive buffer
+ getDataFromInactiveBuffer( buffer, data, sizeOfFirstConsumption ); // Will switch double buffers if we empty inactive buffer
+ // Will return # of bytes consumed
+ result = sizeOfFirstConsumption;
+ // Do we need more from active buffer?
+ if ( len > sizeOfFirstConsumption )
+ {
+ U32 remNumOfBytes = len - sizeOfFirstConsumption;
+ U08 *remPtr = data + sizeOfFirstConsumption;
+
+ getDataFromInactiveBuffer( buffer, remPtr, remNumOfBytes );
+ // Will return # of bytes consumed
+ result += remNumOfBytes;
+ }
+ }
+ // Release thread protection
+ _enable_IRQ();
+ }
+ else // Invalid buffer given
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_GET_INVALID_BUFFER, buffer )
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The peekFromCommBuffer function fills a given byte array with a given
+ * number of bytes from a given buffer. This function does NOT consume
+ * the bytes - it only peeks at them. A call to numberOfBytesInCommBuffer()
+ * should be made before calling this function to determine how many bytes
+ * are currently in the buffer. Do not call this function with a "len"
+ * longer than what is currently in the buffer.
+ * @details Inputs: commBuffers[], commBufferByteCount[], activeDoubleBuffer[]
+ * @details Outputs: given array populated with requested number of bytes from the buffer.
+ * @param buffer which comm buffer to retrieve data from
+ * @param data pointer to byte array to stuff data into
+ * @param len number of bytes to retrieve into given data array.
+ * @return the number of bytes retrieved.
+ *************************************************************************/
+U32 peekFromCommBuffer( COMM_BUFFER_T buffer, U08 *data, U32 len )
+{
+ U32 numOfBytesPeeked = 0;
+
+ // Verify given buffer
+ if ( buffer < NUM_OF_COMM_BUFFERS )
+ {
+ // Thread protection for queue operations
+ _disable_IRQ();
+ // Verify requested # of bytes to peek are in the buffer
+ if ( ( len <= ( COMM_BUFFER_LENGTH * DOUBLE_BUFFERS ) ) && ( len <= numberOfBytesInCommBuffer( buffer ) ) )
+ {
+ U32 activeBuffer = activeDoubleBuffer[ buffer ];
+ U32 inactiveBuffer = GET_TOGGLE( activeBuffer, 0, 1 );
+ U32 bytesInInactiveBuffer = commBufferByteCount[ buffer ][ inactiveBuffer ];
+
+ if ( len <= bytesInInactiveBuffer )
+ {
+ memcpy( data, &commBuffers[ buffer ][ inactiveBuffer ][ 0 ], len );
+ numOfBytesPeeked = len;
+ }
+ else // Will need to get the rest from active buffer
+ {
+ U32 remNumOfBytes = len - bytesInInactiveBuffer;
+ U08 *remPtr = data + bytesInInactiveBuffer;
+
+ memcpy( data, &commBuffers[ buffer ][ inactiveBuffer ][ 0 ], bytesInInactiveBuffer );
+ memcpy( remPtr, &commBuffers[ buffer ][ activeBuffer ][ 0 ], remNumOfBytes );
+ numOfBytesPeeked = bytesInInactiveBuffer + remNumOfBytes;
+ }
+ }
+ // Release thread protection
+ _enable_IRQ();
+ }
+ else // Invalid buffer given
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_PEEK_INVALID_BUFFER, buffer )
+ }
+
+ return numOfBytesPeeked;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The numberOfBytesInCommBuffer function determines how many bytes
+ * are currently contained in a given comm buffer. Both double buffers
+ * are considered for this.
+ * @details Inputs: activeDoubleBuffer[], commBufferByteCount[]
+ * @details Outputs: none
+ * @param buffer which comm buffer to get byte count for
+ * @return the number of bytes in the given comm buffer.
+ *************************************************************************/
+U32 numberOfBytesInCommBuffer( COMM_BUFFER_T buffer )
+{
+ U32 result = 0;
+
+ // Verify given buffer
+ if ( buffer < NUM_OF_COMM_BUFFERS )
+ {
+ U32 activeBuffer = activeDoubleBuffer[ buffer ];
+ U32 inactiveBuffer = GET_TOGGLE( activeBuffer, 0, 1 );
+
+ result = commBufferByteCount[ buffer ][ inactiveBuffer ] + commBufferByteCount[ buffer ][ activeBuffer ];
+ }
+ else // Invalid buffer
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_COUNT_INVALID_BUFFER, buffer )
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The switchDoubleBuffer function switches the active and inactive buffers
+ * for the given buffer.
+ * This function should only be called when the current inactive buffer has
+ * been emptied. Any unconsumed data in inactive buffer will be lost.
+ * @details Inputs: activeDoubleBuffer[]
+ * @details Outputs: activeDoubleBuffer[], commBufferByteCount[]
+ * @param buffer which comm buffer to switch double buffers on
+ * @return the new active buffer for the given buffer.
+ *************************************************************************/
+static U32 switchDoubleBuffer( COMM_BUFFER_T buffer )
+{
+ U32 activeBuffer = activeDoubleBuffer[ buffer ];
+ U32 inactiveBuffer = GET_TOGGLE( activeBuffer, 0, 1 );
+
+ // Ensure inactive buffer is reset before making active
+ commBufferByteCount[ buffer ][ inactiveBuffer ] = 0;
+ // Switch buffers
+ activeDoubleBuffer[ buffer ] = inactiveBuffer;
+
+ // Return the new active buffer (was just inactive)
+ return inactiveBuffer;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDataFromInactiveBuffer function retrieves a given number of bytes
+ * from the inactive buffer of a given buffer. This function should only be
+ * called by getFromCommBuffer(). Params will be pre-validated there.
+ * @details Inputs: commBuffers[], activeDoubleBuffer[], commBufferByteCount[]
+ * @details Outputs: commBuffers[], activeDoubleBuffer[], commBufferByteCount[]
+ * @param buffer which comm buffer get data from
+ * @param data pointer to byte array to populate with data
+ * @param len number of bytes to get from comm buffer
+ * @return none
+ *************************************************************************/
+static void getDataFromInactiveBuffer( COMM_BUFFER_T buffer, U08 *data, U32 len )
+{
+ U32 activeBuffer = activeDoubleBuffer[ buffer ];
+ U32 inactiveBuffer = GET_TOGGLE( activeBuffer, 0, 1 );
+ U32 bytesInInactiveBuffer = commBufferByteCount[ buffer ][ inactiveBuffer ];
+
+ // Get the requested data from inactive buffer
+ memcpy( data, &commBuffers[ buffer ][ inactiveBuffer ][ 0 ], len );
+
+ if ( len < bytesInInactiveBuffer )
+ {
+ U08 *endPtr = (&commBuffers[ buffer ][ inactiveBuffer ][ 0 ] + len);
+
+ // Move un-consumed data in inactive buffer to start of inactive buffer
+ memcpy( &commBuffers[ buffer ][ inactiveBuffer ][ 0 ], endPtr, ( bytesInInactiveBuffer - len ) );
+ // Reduce byte count for inactive buffer by # of bytes consumed
+ commBufferByteCount[ buffer ][ inactiveBuffer ] -= len;
+ }
+ else
+ {
+ // Inactive buffer has been emptied so switch double buffers
+ switchDoubleBuffer( buffer ); // Switch will zero count off inactive buffer
+ }
+}
+
+/**@}*/
Index: firmware/App/Services/CommBuffers.h
===================================================================
diff -u
--- firmware/App/Services/CommBuffers.h (revision 0)
+++ firmware/App/Services/CommBuffers.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,67 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file CommBuffers.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __COMM_BUFFERS_H__
+#define __COMM_BUFFERS_H__
+
+#include "../TDCommon.h"
+
+/**
+ * @defgroup CommBuffers CommBuffers
+ * @brief The communication buffers module provides buffering services for
+ * incoming and outgoing CAN data. A separate buffer is provided for each
+ * CAN ID (channel) so that frame order is maintained for a given channel.
+ *
+ * @addtogroup CommBuffers
+ * @{
+ */
+
+// ********** public definitions **********
+
+/// Enumeration of CAN communication buffers. Buffers are ordered by priority.
+typedef enum Comm_Buffers
+{
+ COMM_BUFFER_NOT_USED = 0, ///< CAN message boxes start at 1 so we will not use this buffer
+ COMM_BUFFER_OUT_CAN_TD_ALARM, ///< Buffer for outgoing HD alarm messages
+ COMM_BUFFER_IN_CAN_DD_ALARM, ///< Buffer for incoming DD alarm messages
+ COMM_BUFFER_IN_CAN_RO_ALARM, ///< Buffer for incoming RO alarm messages
+ COMM_BUFFER_IN_CAN_UI_ALARM, ///< Buffer for incoming UI alarm messages
+ COMM_BUFFER_OUT_CAN_TD_2_DD, ///< Buffer for outgoing HD to DD messages
+ COMM_BUFFER_IN_CAN_DD_2_TD, ///< Buffer for incoming DD to HD messages
+ COMM_BUFFER_OUT_CAN_TD_2_UI, ///< Buffer for outgoing HD to UI messages
+ COMM_BUFFER_IN_CAN_UI_2_TD, ///< Buffer for incoming UI to HD messages
+ COMM_BUFFER_OUT_CAN_TD_BROADCAST, ///< Buffer for outgoing HD broadcast messages
+ COMM_BUFFER_IN_CAN_DD_BROADCAST, ///< Buffer for incoming DD broadcast messages
+ COMM_BUFFER_IN_CAN_RO_BROADCAST, ///< Buffer for incoming RO broadcast messages
+ COMM_BUFFER_IN_CAN_UI_BROADCAST, ///< Buffer for incoming UI broadcast messages
+ COMM_BUFFER_IN_CAN_PC, ///< Buffer for incoming PC to HD messages
+ COMM_BUFFER_OUT_CAN_PC, ///< Buffer for outgoing HD to PC messages
+ NUM_OF_COMM_BUFFERS ///< Number of CAN communication buffers
+} COMM_BUFFER_T;
+
+// ********** public function prototypes **********
+
+void initCommBuffers( void );
+void clearBuffer( COMM_BUFFER_T buffer );
+BOOL addToCommBuffer( COMM_BUFFER_T buffer, U08 *data, U32 len );
+U32 getFromCommBuffer( COMM_BUFFER_T buffer, U08 *data, U32 len );
+U32 peekFromCommBuffer( COMM_BUFFER_T buffer, U08 *data, U32 len );
+U32 numberOfBytesInCommBuffer( COMM_BUFFER_T buffer );
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/DDInterface.c
===================================================================
diff -u
--- firmware/App/Services/DDInterface.c (revision 0)
+++ firmware/App/Services/DDInterface.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1065 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file DDInterface.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include // To check for NaN
+
+#include "DDDefs.h"
+#include "DDInterface.h"
+#include "Messaging.h"
+#include "ModeInitPOST.h"
+#include "OperationModes.h"
+#include "PersistentAlarm.h"
+#include "SystemCommTD.h"
+#include "TaskGeneral.h"
+#include "Timers.h"
+
+/**
+ * @addtogroup DDInterface
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define START_DG_CMD TRUE ///< Parameter for DG start/stop command function. True = start.
+#define STOP_DG_CMD FALSE ///< Parameter for DG start/stop command function. False = stop.
+
+#define SIZE_OF_LARGE_LOAD_CELL_AVG 32 ///< Large load cell moving average has 32 samples.
+
+#define DIALYSATE_TEMP_OUT_OF_TARGET_CLEAR_TOL_C 2.0F ///< Dialysate temperature clear alarm tolerance C
+#define DIALYSATE_TEMP_OUT_OF_TARGET_TOL_C 4.0F ///< Dialysate temperature out of target tolerance C.
+#define DIALYSATE_TEMP_OUT_OF_TARGET_TIMEOUT_MS ( 90 * MS_PER_SECOND ) ///< Dialysate temperature out of target timeout in milliseconds.
+#define DIALYSATE_TEMP_UPPER_MAX_SAFETY_LIMIT_C 46.0F ///< Dialysate upper bound maximum temperature limit in C.
+#define DIALYSATE_TEMP_UPPER_MAX_SAFETY_TIMEOUT_MS ( 1 * MS_PER_SECOND ) ///< Dialysate temperature upper bound maximum safety timeout in milliseconds.
+#define DIALYSATE_TEMP_UPPER_SAFETY_LIMIT_C 42.0F ///< Dialysate upper bound safety temperature limit in C.
+#define DIALYSATE_TEMP_UPPER_SAFETY_TIMEOUT_MS ( 300 * MS_PER_SECOND ) ///< Dialysate temperature upper bound timeout in milliseconds.
+#define DIALYSATE_TEMP_LOWER_SAFETY_LIMIT_C 33.0F ///< Dialysate lower bound safety temperature limit in C.
+#define DIALYSATE_TEMP_LOWER_SAFETY_TIMEOUT_MS ( 300 * MS_PER_SECOND ) ///< Dialysate temperature lower bound timeout in milliseconds.
+#define DIALYSATE_TEMP_CLEAR_TIMEOUT_MS ( 10 * MS_PER_SECOND ) ///< Dialysate temperature clear persistence timeout.
+#define DG_DATA_FRESHNESS_TIMEOUT_MS ( 3 * MS_PER_SECOND ) ///< DG data freshness timeout (in ms).
+#define DG_TRIMMER_HTR_CHECK_INTERVAL ( MS_PER_SECOND / TASK_GENERAL_INTERVAL + 2 ) ///< DG trimmer heater check interval in general task execution time counts.
+
+// ********** private data **********
+
+// DG status
+static DG_OP_MODE_T dgCurrentOpMode; ///< Current DG operation mode.
+static U32 dgSubMode; ///< Current state (sub-mode) of current DG operation mode.
+static BOOL dgStartCommandSent; ///< Flag indicates command to start DG has been sent.
+static BOOL dgStarted; ///< Flag indicates whether we have commanded the DG to start or stop.
+static BOOL dgTrimmerHeaterOn; ///< Flag indicates whether we have commanded the DG to start or stop the trimmer heater.
+
+// DG sensor data
+static F32 dgDialysateTemp; ///< Dialysate temperature reported by the DG.
+static F32 dgRedundantDialysateTemp; ///< Redundant dialysate temperature reported by the DG.
+static F32 dgHeatDisinfectTemp; ///< Heat disinfect temperature reported by the DG.
+static F32 dgTrimmerTempSet; ///< Trimmer heater target temperature commanded.
+
+static U32 dgTrimmerTempCheckTimerCtr; ///< Trimmer heater temp check interval timer counter.
+
+// DG Dialysate flow rate
+static F32 dgDialysateFlowRateLMin; ///< Latest dialysate flow rate (in L/min) reported by the DG.
+static F32 dgDialysateFlowRateRawLMin; ///< Latest raw dialysate flow rate (in L/min) reported by the DG.
+static BOOL dgDialysateFlowDataFreshFlag = FALSE; ///< Flag to signal the execDialInFlowMonitor() to process fresh flow rate data
+static BOOL dgDialysateTemperatureDataFreshFlag = FALSE; ///< Flag to signal the handleTemperatureReadingsFromDG() to process fresh temperature data
+static BOOL dgReservoirsDataFreshFlag = FALSE; ///< Flag to signal the handleDGReservoirData() to process fresh reservoirs data
+static BOOL dgOpModeDataFreshFlag = FALSE; ///< Flag to signal the handleDGOpMode() to process fresh dg op mode data
+
+static DG_DISINFECT_UI_STATES_T disinfectsStatus; ///< DG disinfects status.
+static DG_MIXING_RATIOS_T dgMixingRatios; ///< DG mixing ratios.
+static HEATERS_DATA_T dgHeatersData; ///< DG heaters data.
+static DG_SERVICE_AND_USAGE_DATA_T dgServiceAndUsageData; ///< DG service and usage data.
+
+// DG command response
+static DG_CMD_RESPONSE_T dgCmdResp[ NUM_OF_DG_COMMANDS ]; ///< Keep the latest DG command response for each command.
+
+// ********** private function prototypes **********
+
+static void checkDGRestart( void );
+static void checkDGTrimmerHeaterStatus( void );
+static void checkDGDataFreshness( ALARM_ID_T alarmID, BOOL *dgFreshDataFlag );
+
+/*********************************************************************//**
+ * @brief
+ * The initDDInterface function initializes the DDInterface module.
+ * @details Inputs: none
+ * @details Outputs: DDInterface module initialized.
+ * @return none
+ *************************************************************************/
+void initDDInterface( void )
+{
+ U32 i;
+
+ // NOTE: the active reservoir is set to reservoir 1 since DG will send active reservoir 1 as active on power up
+ dgStarted = FALSE;
+ dgTrimmerHeaterOn = FALSE;
+ dgTrimmerTempSet = 0.0F;
+ dgTrimmerTempCheckTimerCtr = 0;
+ dgDialysateTemp = 0.0F;
+ dgCurrentOpMode = DG_MODE_INIT;
+ dgSubMode = 0;
+ dgStartCommandSent = FALSE;
+ dgDialysateFlowRateLMin = 0.0F;
+ dgDialysateFlowRateRawLMin = 0.0F;
+ dgDialysateFlowDataFreshFlag = FALSE;
+ dgHeatDisinfectTemp = 0.0F;
+
+ // initialize DG command response
+ for ( i = 0; i < NUM_OF_DG_COMMANDS; i++ )
+ {
+ dgCmdResp[ i ].commandID = DG_CMD_NONE;
+ dgCmdResp[ i ].rejected = TRUE;
+ dgCmdResp[ i ].rejectCode = DG_CMD_REQUEST_REJECT_REASON_NONE;
+ }
+
+ initPersistentAlarm( ALARM_ID_HD_DIALYSATE_TEMP_ABOVE_TARGET_TEMP, DIALYSATE_TEMP_CLEAR_TIMEOUT_MS, DIALYSATE_TEMP_OUT_OF_TARGET_TIMEOUT_MS );
+ initPersistentAlarm( ALARM_ID_HD_DIALYSATE_TEMP_BELOW_TARGET_TEMP, DIALYSATE_TEMP_CLEAR_TIMEOUT_MS, DIALYSATE_TEMP_OUT_OF_TARGET_TIMEOUT_MS );
+ initPersistentAlarm( ALARM_ID_HD_DIALYSATE_TEMP_ABOVE_SAFETY_TEMP, DIALYSATE_TEMP_CLEAR_TIMEOUT_MS, DIALYSATE_TEMP_UPPER_MAX_SAFETY_TIMEOUT_MS );
+
+ initPersistentAlarm( ALARM_ID_HD_NEW_LOAD_CELL_DATA_MESSAGE_NOT_RECEIVE, DG_DATA_FRESHNESS_TIMEOUT_MS, DG_DATA_FRESHNESS_TIMEOUT_MS );
+ initPersistentAlarm( ALARM_ID_HD_NEW_DIALYSATE_TEMP_DATA_MESSAGE_NOT_RECEIVE, DG_DATA_FRESHNESS_TIMEOUT_MS, DG_DATA_FRESHNESS_TIMEOUT_MS );
+ initPersistentAlarm( ALARM_ID_HD_NEW_RESERVOIRS_DATA_MESSAGE_NOT_RECEIVE, DG_DATA_FRESHNESS_TIMEOUT_MS, DG_DATA_FRESHNESS_TIMEOUT_MS );
+ initPersistentAlarm( ALARM_ID_HD_DG_NEW_OPERATION_MODE_MESSAGE_NOT_RECEIVE, DG_DATA_FRESHNESS_TIMEOUT_MS, DG_DATA_FRESHNESS_TIMEOUT_MS );
+}
+
+/**********************************************************************//**
+ * @brief
+ * The checkDGDataFreshness function checks the condition
+ * for triggering an alarm if the DG fresh data is not received for 2 seconds.
+ * @details Inputs: none
+ * @details Outputs: an alarm is triggered or an alarm condition is cleared
+ * @param alarm ID of alarm to check
+ * @param flag to signal the fresh data processing
+ * @return None
+ *************************************************************************/
+static void checkDGDataFreshness( ALARM_ID_T alarmID, BOOL *dgFreshDataFlag )
+{
+ if ( TRUE == *dgFreshDataFlag )
+ {
+ *dgFreshDataFlag = FALSE;
+ checkPersistentAlarm( alarmID, FALSE, 0.0, 0.0 );
+ }
+ else
+ { // Alarm if not receiving DG fresh data message in timely manner
+ if ( TRUE == isDDCommunicating() )
+ {
+ checkPersistentAlarm( alarmID, TRUE, 0.0, 0.0 );
+ }
+ else
+ {
+ checkPersistentAlarm( alarmID, FALSE, 0.0, 0.0 );
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execDGInterfaceMonitor function executes the DG Interface monitoring
+ * function. Ensures DG is sending fresh data in a timely manner.
+ * @details Inputs: dgLoadCellDataFreshFlag, dgDialysateTemperatureDataFreshFlag,
+ * dgReservoirsDataFreshFlag, dgOpModeDataFreshFlag
+ * @details Outputs: dgLoadCellDataFreshFlag, dgDialysateTemperatureDataFreshFlag,
+ * dgReservoirsDataFreshFlag, dgOpModeDataFreshFlag
+ * @return none
+ *************************************************************************/
+void execDGInterfaceMonitor( void )
+{
+// if ( getCPLDACPowerLossDetected() != TRUE )
+ {
+ // Trigger alarm if not receiving new dialysate temperature data message in timely manner
+ checkDGDataFreshness( ALARM_ID_HD_NEW_DIALYSATE_TEMP_DATA_MESSAGE_NOT_RECEIVE, &dgDialysateTemperatureDataFreshFlag );
+
+ // Trigger alarm if not receiving new reservoirs data message in timely manner
+ checkDGDataFreshness( ALARM_ID_HD_NEW_RESERVOIRS_DATA_MESSAGE_NOT_RECEIVE, &dgReservoirsDataFreshFlag );
+
+ // Trigger alarm if not receiving new DG op mode message in timely manner
+ checkDGDataFreshness( ALARM_ID_HD_DG_NEW_OPERATION_MODE_MESSAGE_NOT_RECEIVE, &dgOpModeDataFreshFlag );
+ if ( TRUE == isAlarmActive( ALARM_ID_HD_DG_NEW_OPERATION_MODE_MESSAGE_NOT_RECEIVE ) )
+ {
+ // we don't want to keep thinking DG is in a useful mode - set it to fault mode until DG is able to report its' true mode status
+ setDGOpMode( DG_MODE_FAUL, 0 );
+ }
+
+ // Check to see if DG has restarted
+ checkDGRestart();
+
+ // Check the status of the trimmer heater
+ if ( ++dgTrimmerTempCheckTimerCtr >= DG_TRIMMER_HTR_CHECK_INTERVAL )
+ {
+ dgTrimmerTempCheckTimerCtr = 0;
+ checkDGTrimmerHeaterStatus();
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDGOpMode function gets the current DG operating mode.
+ * @details Inputs: dgCurrentOpMode
+ * @details Outputs: none
+ * @return Current DG operating mode.
+ *************************************************************************/
+DG_OP_MODE_T getDGOpMode( void )
+{
+ return dgCurrentOpMode;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDGSubMode function gets the current DG operating sub-mode.
+ * @details Inputs: dgSubMode
+ * @details Outputs: none
+ * @return Current DG operating sub-mode.
+ *************************************************************************/
+U32 getDGSubMode( void )
+{
+ return dgSubMode;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDGDialysateFlowRateLMin function gets the latest dialysate flow
+ * rate reported by the DG.
+ * @details Inputs: dgDialysateFlowRateLMin
+ * @details Outputs: none
+ * @return Latest dialysate flow rate (in L/min) reported by DG.
+ *************************************************************************/
+F32 getDGDialysateFlowRateLMin( void )
+{
+ F32 result = dgDialysateFlowRateLMin;
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDGRawDialysateFlowRateLMin function gets the latest raw dialysate flow
+ * rate reported by the DG.
+ * @details Inputs: dgDialysateFlowRateRawLMin
+ * @details Outputs: none
+ * @return Latest dialysate flow rate (in L/min) reported by DG.
+ *************************************************************************/
+F32 getDGRawDialysateFlowRateLMin( void )
+{
+ F32 result = dgDialysateFlowRateRawLMin;
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDialysateFlowDataFreshFlag function returns a flag to indicate
+ * if the dialysate flow rate data reported by the DG is fresh or stale data.
+ * @details Inputs: dgDialysateFlowDataFreshFlag
+ * @details Outputs: dgDialysateFlowDataFreshFlag
+ * @return T/F flag to indicate fresh/stale status of dialysate flow data.
+ *************************************************************************/
+BOOL getDialysateFlowDataFreshFlag( void )
+{
+ BOOL result = dgDialysateFlowDataFreshFlag;
+
+ dgDialysateFlowDataFreshFlag = FALSE;
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDialysateTemperature function gets the latest dialysate temperature.
+ * @details Inputs: dgDialysateTemp
+ * @details Outputs: none
+ * @return the latest dialysate temperature
+ *************************************************************************/
+F32 getDialysateTemperature( void )
+{
+ return dgDialysateTemp;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getRedundantDialysateTemperature function gets the latest redundant
+ * dialysate temperature.
+ * @details Inputs: dgRedundantDialysateTemp
+ * @details Outputs: none
+ * @return the latest redundant dialysate temperature
+ *************************************************************************/
+F32 getRedundantDialysateTemperature( void )
+{
+ return dgRedundantDialysateTemp;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getHeatDisinfectTemperatureSensorValue function gets the latest
+ * heat disinfect temperature sensor value.
+ * @details Inputs: dgDialysateTemp
+ * @details Outputs: none
+ * @return the current heat disinfect temperature sensor value
+ *************************************************************************/
+F32 getHeatDisinfectTemperatureSensorValue( void )
+{
+ return dgHeatDisinfectTemp;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getTrimmerHeaterCommandedOn function gets the latest on/off commanded
+ * status of the trimmer heater.
+ * @details Inputs: dgTrimmerHeaterOn
+ * @details Outputs: none
+ * @return dgTrimmerHeaterOn
+ *************************************************************************/
+BOOL getTrimmerHeaterCommandedOn( void )
+{
+ return dgTrimmerHeaterOn;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDGDisinfectsStates function returns the DG disinfects readings.
+ * @details Inputs: disinfectsStatus
+ * @details Outputs: none
+ * @return the current DG disinfects readings
+ *************************************************************************/
+DG_DISINFECT_UI_STATES_T getDGDisinfectsStates( void )
+{
+ return disinfectsStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDGMixingRatios function returns the DG mixing ratios and the fill
+ * prep time.
+ * @details Inputs: dgMixingRatios
+ * @details Outputs: none
+ * @return getDGMixingRatios which is the DG mixing ratios
+ *************************************************************************/
+DG_MIXING_RATIOS_T getDGMixingRatios( void )
+{
+ return dgMixingRatios;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getHDVersionDGServiceAndUsageData function copies the HD version of
+ * the DG service and usage data into the provided buffer.
+ * @details Inputs: dgServiceAndUsageData
+ * @details Outputs: none
+ * @param data which is a pointer of type DG_SERVICE_AND_USAGE_DATA_T that
+ * is the provided buffer
+ * @return none
+ *************************************************************************/
+void getHDVersionDGServiceAndUsageData( DG_SERVICE_AND_USAGE_DATA_T* data )
+{
+ memcpy( data, &dgServiceAndUsageData, sizeof( DG_SERVICE_AND_USAGE_DATA_T ) );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setDGOpMode function sets the latest DG operating mode reported by
+ * the DG.
+ * @details Inputs: none
+ * @details Outputs: dgCurrentOpMode, dgSubMode, dgOpModeDataFreshFlag
+ * @param opMode operating mode reported by DG
+ * @param subMode sub-mode (current state) of operating mode reported by DG
+ * @return none
+ *************************************************************************/
+void setDGOpMode( U32 opMode, U32 subMode )
+{
+ if ( opMode < NUM_OF_DG_MODES )
+ {
+ // reset POST passed flag if DG restarted or faulted or went to service mode
+ if ( ( opMode < DG_MODE_STAN ) && ( dgCurrentOpMode >= DG_MODE_STAN ) )
+ {
+ signalDDPOSTFinalResult( FALSE );
+ }
+ // update DG op mode and sub-mode
+ dgCurrentOpMode = (DG_OP_MODE_T)opMode;
+ dgSubMode = subMode;
+ }
+ else
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_INVALID_DG_OPERATING_MODE, opMode );
+ }
+
+ dgOpModeDataFreshFlag = TRUE;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setDialysateTemperatureReadings function sets the latest dialysate
+ * temperatures reported by the DG.
+ * @details Inputs: none
+ * @details Outputs: dgDialysateTemp, dgRedundantDialysateTemp,
+ * dgDialysateTemperatureDataFreshFlag
+ * @param tdi dialysate temperature reported by DG
+ * @param tro redundant dialysate temperature reported by DG
+ * @param thd heat disinfect temperature sensor reported by DG
+ * @return none
+ *************************************************************************/
+void setDialysateTemperatureReadings( F32 tdi, F32 tro, F32 thd )
+{
+ dgDialysateTemp = tdi;
+ dgRedundantDialysateTemp = tro;
+ dgHeatDisinfectTemp = thd;
+ dgDialysateTemperatureDataFreshFlag = TRUE;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setDialysateFlowData function sets the latest dialysate flow rate
+ * and its freshness status. The dialysate flow data is reported by the DG.
+ * @details Inputs: none
+ * @details Outputs: dgDialysateFlowRateLMin, dgDialysateFlowRateRawLMin,
+ * dgDialysateFlowDataFreshFlag
+ * @param flowRates latest DG flow rates (mL/min) reported by DG
+ * @return none
+ *************************************************************************/
+void setDialysateFlowData( FLOW_SENSORS_DATA_T flowRates )
+{
+ // Check if the sent value by DG is a NaN
+ if ( isnan( flowRates.dialysateFlowRateLPM ) )
+ {
+ flowRates.dialysateFlowRateLPM = 0.0F;
+ }
+ if ( isnan( flowRates.dialysateRawFlowRateLPM ) )
+ {
+ flowRates.dialysateRawFlowRateLPM = 0.0F;
+ }
+
+ dgDialysateFlowRateLMin = flowRates.dialysateFlowRateLPM;
+ dgDialysateFlowRateRawLMin = flowRates.dialysateRawFlowRateLPM;
+ dgDialysateFlowDataFreshFlag = TRUE;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setDGDisinfectsStates function sets the latest disinfects states
+ * from DG.
+ * @details Inputs: none
+ * @details Outputs: disinfectsStatus
+ * @param states latest DG disinfects state readings
+ * @return none
+ *************************************************************************/
+void setDGDisinfectsStates( DG_DISINFECT_UI_STATES_T states )
+{
+ memcpy( &disinfectsStatus, &states, sizeof(DG_DISINFECT_UI_STATES_T) );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setDGMixingRatios function sets the mixing ratios as well as the fill
+ * prep time upon a request from DG.
+ * @details Inputs: none
+ * @details Outputs: dgMixingRatios
+ * @param ratios the mixing ratios from DG
+ * @return none
+ *************************************************************************/
+void setDGMixingRatios( DG_MIXING_RATIOS_T ratios )
+{
+ memcpy( &dgMixingRatios, &ratios, sizeof( DG_MIXING_RATIOS_T ) );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setDGHeatersData function sets heaters data that has been read from DG.
+ * @details Inputs: none
+ * @details Outputs: dgHeatersData
+ * @param data which is a pointer to the received heaters data
+ * @return none
+ *************************************************************************/
+void setDGHeatersData( HEATERS_DATA_T *data )
+{
+ memcpy( &dgHeatersData, data, sizeof( HEATERS_DATA_T ) );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setHDVersionDGServiceRecord function sets the HD version of the DG
+ * service record.
+ * @details Inputs: none
+ * @details Outputs: dgServiceAndUsageData
+ * @param data which is a pointer to the received HD version of the DG service
+ * record
+ * @return none
+ *************************************************************************/
+void setHDVersionDGServiceRecord( DG_SERVICE_RECORD_T* data )
+{
+ dgServiceAndUsageData.isDGServiceRecordAvailable = TRUE;
+ memcpy( &dgServiceAndUsageData.dgServiceRecord, data, sizeof( DG_SERVICE_RECORD_T ) );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setHDVersionDGUsageInfo function sets the HD version of the DG
+ * usage information.
+ * @details Inputs: none
+ * @details Outputs: dgServiceAndUsageData
+ * @param data which is a pointer to the received HD version of the DG usage
+ * info
+ * @return none
+ *************************************************************************/
+void setHDVersionDGUsageInfo( DG_USAGE_INFO_RECORD_T* data )
+{
+ dgServiceAndUsageData.isDGUsageInfoAvailable = TRUE;
+ memcpy( &dgServiceAndUsageData.dgUsageInfo, data, sizeof( DG_USAGE_INFO_RECORD_T ) );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdSetDGDialysateHeatingParams function sends the dialysate heating
+ * parameters to DG.
+ * @details Inputs: none
+ * @details Outputs: dgTrimmerTempSet
+ * @param heatingParams Dialysate heating parameters to be sent to DG
+ * @return none
+ *************************************************************************/
+void cmdSetDGDialysateHeatingParams( DG_CMD_DIALYSATE_HEATING_PARAMS_T heatingParams )
+{
+ dgTrimmerTempSet = heatingParams.trimmerTargetTemperature;
+ // TODO what should we do with the BOOL return of this function?
+// sendDialysateHeatingParamsToDG( &heatingParams );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDG function sends a start command to the DG. DG will transition
+ * from standby to recirculate mode and start producing warm, pure water.
+ * @details Inputs: none
+ * @details Outputs: start DG command sent
+ * @return none
+ *************************************************************************/
+void cmdStartDG( void )
+{
+ dgStartCommandSent = TRUE;
+
+// sendDGStartStopCommand( (BOOL)START_DG_CMD );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDG function sends a stop command to the DG. DG will transition
+ * from recirculate mode to standby mode. Pumps and heater go off.
+ * @details Inputs: none
+ * @details Outputs: stop DG command sent
+ * @return none
+ *************************************************************************/
+void cmdStopDG( void )
+{
+ dgStarted = FALSE;
+
+// sendDGStartStopCommand( (BOOL)STOP_DG_CMD );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDGTrimmerHeater function sends a start trimmer heater command
+ * to the DG.
+ * @details Inputs: none
+ * @details Outputs: start DG trimmer heater command sent
+ * @return none
+ *************************************************************************/
+void cmdStartDGTrimmerHeater( void )
+{
+ dgTrimmerHeaterOn = TRUE;
+ dgCmdResp[ DG_CMD_START_TRIMMER_HEATER ].commandID = DG_CMD_NONE;
+
+// sendDGStartStopTrimmerHeaterCommand( START_DG_CMD );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDGTrimmerHeater function sends a stop trimmer heater command
+ * to the DG.
+ * @details Inputs: none
+ * @details Outputs: stop DG trimmer heater command sent
+ * @return none
+ *************************************************************************/
+void cmdStopDGTrimmerHeater( void )
+{
+ dgTrimmerHeaterOn = FALSE;
+ dgCmdResp[ DG_CMD_STOP_TRIMMER_HEATER ].commandID = DG_CMD_NONE;
+
+// sendDGStartStopTrimmerHeaterCommand( STOP_DG_CMD );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDGFill function sends a fill command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: fill command sent to DG.
+ * @param fillToVolMl volume (in mL) to fill inactive reservoir to
+ * @param targetFlowLPM target flow rate in L/min
+ * @return none
+ *************************************************************************/
+void cmdStartDGFill( U32 fillToVolMl, F32 targetFlowLPM )
+{
+ dgCmdResp[ DG_CMD_START_FILL ].commandID = DG_CMD_NONE;
+
+ if ( ( FALSE == isAlarmActive( ALARM_ID_DG_ACID_BOTTLE_LOW_VOLUME ) ) && ( FALSE == isAlarmActive( ALARM_ID_DG_BICARB_BOTTLE_LOW_VOLUME ) ) )
+ {
+ // The empty bottle alarms should not be active. If they are, the user shall insert the new bottle first and then hit Ok/Resume and
+ // then the fill can go. This is to make sure the next fill is done the full bottles
+// sendDGFillCommand( DG_CMD_START, fillToVolMl, targetFlowLPM );
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDGFill function sends a fill command with stop parameter message to the DG.
+ * @details Inputs: none
+ * @details Outputs: fill command with stop parameter sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStopDGFill( void )
+{
+ dgCmdResp[ DG_CMD_STOP_FILL ].commandID = DG_CMD_NONE;
+
+// sendDGFillCommand( DG_CMD_STOP, 0, 0 );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDGDrain function sends a drain command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: drain command sent to DG.
+ * @param drainToVolMl volume (in mL) to drain inactive reservoir to
+ * @param tareLoadCell flag to tell DG tare load cell or not
+ * @param start flag to tell DG to start or stop the drain mode
+ * @return none
+ *************************************************************************/
+void cmdStartDGDrain( U32 drainToVolMl, BOOL tareLoadCell, BOOL rinse, BOOL start )
+{
+ DRAIN_RESERVOIR_CMD_PAYLOAD_T payload;
+
+ dgCmdResp[ DG_CMD_START_DRAIN ].commandID = DG_CMD_NONE;
+ payload.drainToVolumeML = drainToVolMl;
+ payload.tareLoadCells = tareLoadCell;
+ payload.rinseConcentrateLines = rinse;
+ payload.cmd = start;
+
+// sendDGDrainCommand( &payload );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdDGSampleWater function sends a sample water command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: sample water command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdDGSampleWater( SAMPLE_WATER_CMD_T cmd )
+{
+// sendDGSampleWaterCommand( cmd );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdDGParkConcentratePumps function sends a park concentrate pumps command
+ * message to the DG.
+ * @details Inputs: none
+ * @details Outputs: park concentrate pumps command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdDGParkConcentratePumps( void )
+{
+ dgCmdResp[ DG_CMD_PARK_CONCENTRATE_PUMPS ].commandID = DG_CMD_NONE;
+
+// sendDGParkConcentratePumpsCommand( );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDGFlush function sends a start flush command message to
+ * the DG.
+ * @details Inputs: none
+ * @details Outputs: start flush mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStartDGFlush( void )
+{
+ BOOL start = TRUE;
+
+ dgCmdResp[ DG_CMD_START_FLUSH ].commandID = DG_CMD_NONE;
+
+// sendDGStartFlushModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDGFlush function sends a stop flush command message to
+ * the DG.
+ * @details Inputs: none
+ * @details Outputs: stop flush mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStopDGFlush( void )
+{
+ BOOL start = FALSE;
+
+ dgCmdResp[ DG_CMD_STOP_FLUSH ].commandID = DG_CMD_NONE;
+
+// sendDGStartFlushModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDGHeatDisinfect function sends a start heat disinfect
+ * command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: start heat disinfect mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStartDGHeatDisinfect( void )
+{
+ BOOL start = TRUE;
+
+ dgCmdResp[ DG_CMD_START_HEAT_DISINFECT ].commandID = DG_CMD_NONE;
+
+// sendDGStartHeatDisinfectModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDGHeatDisinfect function sends a stop heat disinfect
+ * command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: stop heat disinfect mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStopDGHeatDisinfect( void )
+{
+ BOOL start = FALSE;
+
+ dgCmdResp[ DG_CMD_STOP_HEAT_DISINFECT ].commandID = DG_CMD_NONE;
+
+// sendDGStartHeatDisinfectModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDGChemicalDisinfect function sends a start chemical disinfect
+ * command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: start chemical disinfect mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStartDGChemicalDisinfect( void )
+{
+ BOOL start = TRUE;
+
+ dgCmdResp[ DG_CMD_START_CHEM_DISINFECT ].commandID = DG_CMD_NONE;
+// sendDGStartChemicalDisinfectModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDGChemicalDisinfect function sends a stop chemical disinfect
+ * command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: stop chemical disinfect mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStopDGChemicalDisinfect( void )
+{
+ BOOL start = FALSE;
+
+ dgCmdResp[ DG_CMD_STOP_CHEM_DISINFECT ].commandID = DG_CMD_NONE;
+// sendDGStartChemicalDisinfectModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDGChemicalFlushDisinfect function sends a start chemical disinfect
+ * flush command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: start chemical disinfect flush mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStartDGChemicalFlushDisinfect( void )
+{
+ BOOL start = TRUE;
+
+ dgCmdResp[ DG_CMD_START_CHEM_DISINFECT_FLUSH ].commandID = DG_CMD_NONE;
+// sendDGStartStopChemicalDisinfectFlushModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDGChemFlushDisinfect function sends a stop chemical disinfect
+ * flush command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: stop chemical disinfect flush mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStopDGChemFlushDisinfect( void )
+{
+ BOOL start = FALSE;
+
+ dgCmdResp[ DG_CMD_STOP_CHEM_DISINFECT_FLUSH ].commandID = DG_CMD_NONE;
+// sendDGStartStopChemicalDisinfectFlushModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDGActiveCool function sends a stop active cool command
+ * message to the DG.
+ * @details Inputs: none
+ * @details Outputs: stop active cool mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStopDGActiveCool( void )
+{
+ dgCmdResp[ DG_CMD_STOP_ACTIVE_COOL ].commandID = DG_CMD_NONE;
+// sendDGStopActiveCoolModeCommand();
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStartDGROPermeateSampleMode function sends an RO permeate sample
+ * start command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: start RO permeate sample mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStartDGROPermeateSampleMode( void )
+{
+ BOOL start = TRUE;
+
+ dgCmdResp[ DG_CMD_START_RO_PERMEATE_SAMPLE ].commandID = DG_CMD_NONE;
+// sendDGStartStopDGROPermeateSampleModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdStopDGROPermeateSampleMode function sends an RO permeate sample
+ * stop command message to the DG.
+ * @details Inputs: none
+ * @details Outputs: stop RO permeate sample mode command sent to DG.
+ * @return none
+ *************************************************************************/
+void cmdStopDGROPermeateSampleMode( void )
+{
+ BOOL start = FALSE;
+
+ dgCmdResp[ DG_CMD_STOP_RO_PERMEATE_SAMPLE ].commandID = DG_CMD_NONE;
+// sendDGStartStopDGROPermeateSampleModeCommand( start );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdRequestDGConcentrateRatios function sends a request to DG to receive
+ * the concentrate ratios.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void cmdRequestDGMixingRatios( void )
+{
+ dgCmdResp[ DG_CMD_REQUEST_CONC_MIXING_RATIOS ].commandID = DG_CMD_NONE;
+// sendDGConcentrateMixingRatiosRequest();
+}
+
+/*********************************************************************//**
+ * @brief
+ * The cmdSetDGToServiceMode function sends a request to DG to transition
+ * to service mode.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void cmdSetDGToServiceMode( void )
+{
+// sendDGServiceModeRequest();
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handleDGCommandResponse function processes the latest DG command response.
+ * @details Inputs: none
+ * @details Outputs: process command response from DG
+ * @param dgCmdRespPtr pointer to DG command response data record
+ * @return none
+ *************************************************************************/
+void handleDGCommandResponse( DG_CMD_RESPONSE_T *dgCmdRespPtr )
+{
+ if ( dgCmdRespPtr->commandID < NUM_OF_DG_COMMANDS )
+ {
+ if ( DG_CMD_NONE != dgCmdRespPtr->commandID )
+ {
+ memcpy( &dgCmdResp[ dgCmdRespPtr->commandID ], dgCmdRespPtr, sizeof( DG_CMD_RESPONSE_T ) );
+ }
+ }
+ else
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_HD_INVALID_COMMAND_RESPONSE_ID, dgCmdRespPtr->commandID );
+ }
+
+ if ( TRUE == dgCmdRespPtr->rejected )
+ {
+ switch ( dgCmdRespPtr->rejectCode )
+ {
+ case DG_CMD_REQUEST_REJECT_REASON_INVALID_PARAMETER:
+ SET_ALARM_WITH_1_U32_DATA( ALARM_ID_HD_DG_COMMAND_INVALID_PARAMETER_FAULT, dgCmdRespPtr->commandID );
+ break;
+
+ case DG_CMD_REQUEST_REJECT_REASON_NONE:
+ case DG_CMD_REQUEST_REJECT_REASON_INVALID_MODE:
+ default:
+ // Our state machines will detect and handle DG mode out of sync
+ // TODO Consider a generic handler for all state machine
+ break;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getDGCommandResponse function gets the latest command response from DG.
+ * @details Inputs: dgCmdResp
+ * @details Outputs: none
+ * @param commandID id of specific interested command response
+ * @param cmdRespPtr pointer to data record to copy DG command response to
+ * @return TRUE if a specific command response has been received, otherwise FALSE
+ *************************************************************************/
+BOOL getDGCommandResponse( U32 commandID, DG_CMD_RESPONSE_T *cmdRespPtr )
+{
+ BOOL hasCommandResp = FALSE;
+
+ if ( commandID == dgCmdResp[ commandID ].commandID )
+ {
+ hasCommandResp = TRUE;
+ memcpy( cmdRespPtr, &dgCmdResp[ commandID ], sizeof( DG_CMD_RESPONSE_T ) );
+ }
+
+ return hasCommandResp;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The checkDialysateTemperature function checks the dialysate temperature
+ * reported by DG and alarm if temperature is out of range.
+ * @details Inputs: dgTrimmerTempSet, dgDialysateTemp
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void checkDialysateTemperature( void )
+{
+ BOOL isTDiTempAboveHighSafety = ( dgDialysateTemp >= DIALYSATE_TEMP_UPPER_MAX_SAFETY_LIMIT_C ? TRUE : FALSE );
+ BOOL isTDiTempAboveLowSafety = ( dgDialysateTemp > DIALYSATE_TEMP_UPPER_SAFETY_LIMIT_C ? TRUE : FALSE );
+ BOOL isTDITempBelowLowSafety = ( dgDialysateTemp < DIALYSATE_TEMP_LOWER_SAFETY_LIMIT_C ? TRUE : FALSE );
+ F32 TDiHigh = dgTrimmerTempSet + DIALYSATE_TEMP_OUT_OF_TARGET_TOL_C;
+ BOOL isTDiTempAboveDialysateTarget = ( dgDialysateTemp >= TDiHigh ? TRUE : FALSE );
+ F32 TDiLow = dgTrimmerTempSet - DIALYSATE_TEMP_OUT_OF_TARGET_TOL_C;
+ BOOL isTDiTempBelowDialysateTarget = ( dgDialysateTemp <= TDiLow ? TRUE : FALSE );
+ BOOL isTempBelowTrigger = (BOOL)( isTDITempBelowLowSafety || isTDiTempBelowDialysateTarget );
+ BOOL isTempAboveTrigger = (BOOL)( isTDiTempAboveLowSafety || isTDiTempAboveDialysateTarget );
+
+// if ( getTargetDialInFlowRate() > 0 )
+ {
+ // check clear condition first
+ if ( TRUE == isAlarmActive( ALARM_ID_HD_DIALYSATE_TEMP_ABOVE_SAFETY_TEMP ) )
+ {
+ isTDiTempAboveHighSafety = ( dgDialysateTemp <= ( dgTrimmerTempSet + DIALYSATE_TEMP_OUT_OF_TARGET_CLEAR_TOL_C ) ? FALSE : TRUE );
+ }
+ checkPersistentAlarm(ALARM_ID_HD_DIALYSATE_TEMP_ABOVE_SAFETY_TEMP, isTDiTempAboveHighSafety, dgDialysateTemp, dgTrimmerTempSet );
+
+ if ( TRUE == isAlarmActive( ALARM_ID_HD_DIALYSATE_TEMP_ABOVE_TARGET_TEMP ) )
+ {
+ isTempAboveTrigger = ( dgDialysateTemp <= ( dgTrimmerTempSet + DIALYSATE_TEMP_OUT_OF_TARGET_CLEAR_TOL_C ) ? FALSE : TRUE );
+ }
+ checkPersistentAlarm(ALARM_ID_HD_DIALYSATE_TEMP_ABOVE_TARGET_TEMP, isTempAboveTrigger, dgDialysateTemp, dgTrimmerTempSet );
+
+ if ( TRUE == isAlarmActive( ALARM_ID_HD_DIALYSATE_TEMP_BELOW_TARGET_TEMP ) )
+ {
+ isTempBelowTrigger = ( dgDialysateTemp >= ( dgTrimmerTempSet - DIALYSATE_TEMP_OUT_OF_TARGET_CLEAR_TOL_C ) ? FALSE : TRUE );
+ }
+ checkPersistentAlarm(ALARM_ID_HD_DIALYSATE_TEMP_BELOW_TARGET_TEMP, isTempBelowTrigger, dgDialysateTemp, dgTrimmerTempSet );
+ }
+// else
+// {
+// checkPersistentAlarm(ALARM_ID_HD_DIALYSATE_TEMP_ABOVE_SAFETY_TEMP, FALSE, dgDialysateTemp, dgTrimmerTempSet );
+// checkPersistentAlarm(ALARM_ID_HD_DIALYSATE_TEMP_ABOVE_TARGET_TEMP, FALSE, dgDialysateTemp, dgTrimmerTempSet );
+// checkPersistentAlarm(ALARM_ID_HD_DIALYSATE_TEMP_BELOW_TARGET_TEMP, FALSE, dgDialysateTemp, dgTrimmerTempSet );
+// }
+}
+
+// ********** private functions **********
+
+/*********************************************************************//**
+ * @brief
+ * The checkDGRestart function checks to see if DG has restarted after started
+ * by HD and triggers appropriate alarm.
+ * @details Inputs: dgStartCommandSent, dgStarted, dgCurrentOpMode
+ * @details Outputs: dgStartCommandSent, dgStarted, triggers a fault alarm if DG restarted
+ * @return none
+ *************************************************************************/
+static void checkDGRestart( void )
+{
+ if ( ( dgStartCommandSent == TRUE ) && ( DG_MODE_GENE == dgCurrentOpMode ) )
+ {
+ dgStartCommandSent = FALSE;
+ dgStarted = TRUE;
+ }
+
+ if ( TRUE == dgStarted )
+ {
+ if ( ( DG_MODE_FAUL != dgCurrentOpMode ) && ( DG_MODE_GENE != dgCurrentOpMode ) &&
+ ( DG_MODE_FILL != dgCurrentOpMode ) && ( DG_MODE_DRAI != dgCurrentOpMode ) )
+ {
+ activateAlarmNoData( ALARM_ID_HD_DG_RESTARTED_FAULT );
+ dgStarted = FALSE; // do not want to re-trigger alarm after alarm is cleared
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The checkDGTrimmerHeaterStatus function checks to see the status of the
+ * trimmer heater and set them according to the status of the trimmer heater flag.
+ * @details Inputs: dgTrimmerHeaterOn, dgHeatersData
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+static void checkDGTrimmerHeaterStatus( void )
+{
+ U32 trimmerState = dgHeatersData.trimmerHeaterState;
+ DG_OP_MODE_T dgOp = getDGOpMode();
+
+// if ( getCPLDACPowerLossDetected() != TRUE )
+ {
+ if ( ( DG_MODE_GENE == dgOp ) || ( DG_MODE_FILL == dgOp ) || ( DG_MODE_DRAI == dgOp ) )
+ {
+ // In heat disinfect and chemical disinfect, the trimmer heater is controlled by the DG itself so no commands from HD should be sent
+ // regarding the trimmer heater.
+ if ( ( TRUE == dgTrimmerHeaterOn ) && ( HEATER_EXEC_STATE_OFF == trimmerState ) )
+ {
+ cmdStartDGTrimmerHeater();
+ }
+ else if ( ( FALSE == dgTrimmerHeaterOn ) && ( trimmerState != HEATER_EXEC_STATE_OFF ) )
+ {
+ cmdStopDGTrimmerHeater();
+ }
+ }
+ }
+}
+
+
+/*************************************************************************
+ * TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/**@}*/
Index: firmware/App/Services/DDInterface.h
===================================================================
diff -u
--- firmware/App/Services/DDInterface.h (revision 0)
+++ firmware/App/Services/DDInterface.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,157 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file DDInterface.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __DD_INTERFACE_H__
+#define __DD_INTERFACE_H__
+
+#include "TDCommon.h"
+#include "DDDefs.h"
+
+/**
+ * @defgroup DDInterface DDInterface
+ * @brief DDG interface/monitor module. Interfaces with and monitors the
+ * DD (dialysate delivery) sub-system.
+ *
+ * @addtogroup DDInterface
+ * @{
+ */
+
+// ********** public definitions **********
+
+#define DEFAULT_TARGET_FILL_FLOW_RATE_LPM 0.8F ///< Default target fill flow rate in L/min.
+#define DRAIN_RESERVOIR_TO_VOLUME_ML 0 ///< Drain reservoir to this volume (in mL) during treatment.
+#define LOAD_CELL_ILLEGAL_WEIGHT_VALUE -10000.0F ///< Initial value for Load Cells, known bad value
+
+/// DG Concentrate ratios data structure.
+typedef struct
+{
+ F32 acidMixingRatio; ///< Acid mixing ratio
+ F32 bicarbMixingRatio; ///< Bicarb mixing ratio
+ U32 timeFillPrepMS; ///< Fill prepare time in milliseconds
+} DG_MIXING_RATIOS_T;
+
+/// Payload record structure for a reservoirs data message.
+typedef struct
+{
+ U32 resID; ///< Active reservoir ID
+ U32 setFillToVolumeMl; ///< Reservoir set fill to target volume in ml
+ U32 setDrainToVolumeMl; ///< Reservoir set drain to target volume in ml
+ U32 timeReservoirCycleMS; ///< Reservoir time cycle in milliseconds
+ U32 timeReservoirFill2SwitchMS; ///< Reservoir time fill to switch in milliseconds
+ F32 timeUFDecayMS; ///< Ultrafilter decay time in milliseconds
+ F32 tempUFFill; ///< Ultrafilter fill temperature in C
+ F32 tempReservoirUseActual; ///< Reservoir actual use temperature in C
+ F32 tempReservoirEndFill; ///< Reservoir end of the fill temperature in C
+ F32 tempAvgFill; ///< Average fill temperature in C
+ F32 tempLastFill; ///< Last fill temperature in C
+ F32 timereservoirFillMS; ///< Reservoir fill time in milliseconds
+} DG_RESERVOIRS_DATA_PAYLOAD_T;
+
+/// Payload record structure for a drain reservoir command message.
+typedef struct
+{
+ U32 drainToVolumeML; ///< Drain to target volume in ml
+ BOOL tareLoadCells; ///< Flag indicates to tare load cells or not
+ BOOL rinseConcentrateLines; ///< Flag indicates to rinse concentrate lines or not
+ BOOL cmd; ///< Flag indicates to start or stop the drain mode
+} DRAIN_RESERVOIR_CMD_PAYLOAD_T;
+
+/// DG command response data record structure.
+typedef struct
+{
+ U32 commandID; ///< The command DG is responding to
+ BOOL rejected; ///< Flag indicates if the command has been rejected
+ U32 rejectCode; ///< Reason code for rejecting the command
+} DG_CMD_RESPONSE_T;
+
+/// DG heat/chemical disinfects and flush state for UI structure.
+typedef struct DG_Disinfects
+{
+ U32 chemDisinfectUIState; ///< DG chemical disinfect UI state
+ U32 heatDisinfectUIState; ///< DG heat disinfect UI state
+ U32 flushUIState; ///< DG flush UI state
+} DG_DISINFECT_UI_STATES_T;
+
+/// HD version of the DG service record
+typedef struct
+{
+ DG_SERVICE_RECORD_T dgServiceRecord; ///< HD version of the DG service record.
+ DG_USAGE_INFO_RECORD_T dgUsageInfo; ///< HD version of the DG usage info.
+ BOOL isDGServiceRecordAvailable; ///< Flag to indicate DG service record is available.
+ BOOL isDGUsageInfoAvailable; ///< Flag to indicate DG usage info is available.
+} DG_SERVICE_AND_USAGE_DATA_T;
+
+// ********** public function prototypes **********
+
+void initDDInterface( void );
+
+void execDGInterfaceMonitor( void );
+
+DG_OP_MODE_T getDGOpMode( void );
+U32 getDGSubMode( void );
+BOOL getDialysateFlowDataFreshFlag( void );
+F32 getDGDialysateFlowRateLMin( void );
+F32 getDGRawDialysateFlowRateLMin( void );
+F32 getDialysateTemperature( void );
+F32 getRedundantDialysateTemperature( void );
+F32 getHeatDisinfectTemperatureSensorValue( void );
+BOOL getTrimmerHeaterCommandedOn( void );
+DG_DISINFECT_UI_STATES_T getDGDisinfectsStates( void );
+DG_MIXING_RATIOS_T getDGMixingRatios( void );
+void getHDVersionDGServiceAndUsageData( DG_SERVICE_AND_USAGE_DATA_T* data );
+
+void setDGOpMode( U32 opMode, U32 subMode );
+void setDialysateTemperatureReadings( F32 tdi, F32 tro, F32 thd );
+void setDialysateFlowData( FLOW_SENSORS_DATA_T flowRates );
+void setDGDisinfectsStates( DG_DISINFECT_UI_STATES_T states );
+void setDGMixingRatios( DG_MIXING_RATIOS_T ratios );
+void setDGHeatersData( HEATERS_DATA_T *data );
+void setHDVersionDGServiceRecord( DG_SERVICE_RECORD_T* data );
+void setHDVersionDGUsageInfo( DG_USAGE_INFO_RECORD_T* data );
+
+void cmdSetDGDialysateHeatingParams( DG_CMD_DIALYSATE_HEATING_PARAMS_T heatingParams );
+void cmdStartDG( void );
+void cmdStopDG( void );
+void cmdStartDGFill( U32 fillToVolMl, F32 targetFlowLPM );
+void cmdStopDGFill( void );
+void cmdStartDGDrain( U32 drainToVolMl, BOOL tareLoadCell, BOOL rinse, BOOL start );
+void cmdStartDGTrimmerHeater( void );
+void cmdStopDGTrimmerHeater( void );
+void cmdDGSampleWater( SAMPLE_WATER_CMD_T cmd );
+void cmdStartDGFlush( void );
+void cmdDGParkConcentratePumps( void );
+void cmdStopDGFlush( void );
+void cmdStartDGHeatDisinfect( void );
+void cmdStopDGHeatDisinfect( void );
+void cmdStartDGChemicalDisinfect( void );
+void cmdStopDGChemicalDisinfect( void );
+void cmdStartDGChemicalFlushDisinfect( void );
+void cmdStopDGChemFlushDisinfect( void );
+void cmdStopDGActiveCool( void );
+void cmdStartDGROPermeateSampleMode( void );
+void cmdStopDGROPermeateSampleMode( void );
+void cmdRequestDGMixingRatios( void );
+void cmdSetDGToServiceMode( void );
+
+void handleDGCommandResponse( DG_CMD_RESPONSE_T *dgCmdRespPtr );
+BOOL getDGCommandResponse( U32 commandID, DG_CMD_RESPONSE_T *cmdRespPtr );
+
+void checkDialysateTemperature( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/FpgaTD.c
===================================================================
diff -u
--- firmware/App/Services/FpgaTD.c (revision 0)
+++ firmware/App/Services/FpgaTD.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1620 @@
+/**************************************************************************
+*
+* Copyright (c) 2019-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file FPGA.c
+*
+* @author (last) Sean Nash
+* @date (last) 10-Sep-2023
+*
+* @author (original) Dara Navaei
+* @date (original) 05-Nov-2019
+*
+***************************************************************************/
+
+#include // For memset(), memcpy()
+
+#include "sci.h"
+#include "sys_dma.h"
+
+#include "Comm.h"
+#include "Compatible.h"
+#include "FPGA.h"
+#include "FpgaTD.h"
+#include "Messaging.h"
+#include "OperationModes.h"
+#include "PersistentAlarm.h"
+#include "Timers.h"
+#include "Utilities.h"
+
+/**
+ * @addtogroup FpgaTD
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define FPGA_EXPECTED_ID 0x5A ///< Expected ID for HD FPGA.
+
+#define PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE 1 ///< Tolerance for processor clock speed check against FPGA clock.
+
+#define MAX_FPGA_COMM_FAILURES_WINDOW_MS ( 1 * SEC_PER_MIN * MS_PER_SECOND ) ///< FPGA comm failures window
+#define MAX_FPGA_COMM_FAILURES 3 ///< FPGA maximum comm failures per MAX_FPGA_COMM_FAILURES_WINDOW_MS
+#define MIN_POWER_ON_TIME_FOR_COMM_FAILS ( 1 * MS_PER_SECOND ) ///< Allow FPGA comm errors for first second after power-up
+
+// FPGA Sensors Record
+#pragma pack(push,1)
+/// Record structure for FPGA header read.
+typedef struct
+{
+ U08 fpgaId; ///< Reg 0. FPGA ID code. Checked against expected value at power up to verify basic FPGA communication and operation.
+ U08 fpgaRev; ///< Reg 1. FPGA revision (minor) being reported.
+ U08 fpgaRevMajor; ///< Reg 2. FPGA revision (major) being reported.
+ U08 fpgaRevLab; ///< Reg 3. FPGA revision (lab) being reported.
+ U16 fpgaStatus; ///< Reg 4. FPGA status register.
+} FPGA_HEADER_T; // Read only on FPGA
+
+/// Record structure for FPGA continuous priority reads.
+typedef struct
+{
+ U08 errorCountProcessor; ///< Reg 256. Error count for processor communications
+ U08 errorCountPC; ///< Reg 257. TBD.
+ U08 fpgaHWConfigReg; ///< Reg 258. Hardware configuration register (i.e. BETA or DVT)
+ U08 sPumpDACRdStatus; ///< Reg 259. Syringe pump DAC read status.
+ U16 sPumpDACSet; ///< Reg 260. Syringe pump DAC setting.
+ U16 sPumpDACEEProm; ///< Reg 262. Syringe pump DAC EEProm data.
+ U08 reserved4; ///< Reg 264. Reserved.
+ U08 reserved5; ///< Reg 265. Reserved.
+ U08 reserved6; ///< Reg 266. Reserved.
+ U08 reserved7; ///< Reg 267. Reserved.
+ F32 reserved8; ///< Reg 268. Reserved.
+ U08 reserved9; ///< Reg 272. Reserved.
+ U08 reserved10; ///< Reg 273. Reserved.
+ U08 reserved11; ///< Reg 274. Reserved.
+ U08 reserved12; ///< Reg 275. Reserved.
+ U16 bloodOcclusionData; ///< Reg 276. Blood pump occlusion sensor data.
+ U08 bloodOcclusionReadCount; ///< Reg 278. Blood pump occlusion sensor read count.
+ U08 bloodOcclusionErrorCount; ///< Reg 279. Blood pump occlusion sensor error count.
+ U16 obsolete1; ///< Reg 280. Unused.
+ U08 obsolete2; ///< Reg 282. Unused.
+ U08 obsolete3; ///< Reg 283. Unused.
+ U16 obsolete4; ///< Reg 284. Unused.
+ U08 obsolete5; ///< Reg 286. Unused.
+ U08 obsolete6; ///< Reg 287. Unused.
+ U16 bloodPumpHallSensorCount; ///< Reg 288. Blood pump hall sensor count.
+ U08 bloodPumpHallSensorStatus; ///< Reg 290. Blood pump hall sensor status.
+ U08 dialInPumpHallSensorStatus; ///< Reg 291. Dialysate inlet pump hall sensor status.
+ U32 adc1Channel0; ///< Reg 292. ADC1 channel 0 data.
+ U32 adc1Channel1; ///< Reg 296. ADC1 channel 1 data.
+ U32 reserved13; ///< Reg 300. Reserved.
+ U32 reserved14; ///< Reg 304. Reserved.
+ F32 reserved15; ///< Reg 308. Reserved.
+ U08 adc1SequenceCount; ///< Reg 312. ADC1 round robin channel sequence count.
+ U08 adc1ErrorCount; ///< Reg 313. ADC1 error count.
+ U16 accelX; ///< Reg 314. Accelerometer X axis data.
+ U16 accelY; ///< Reg 316. Accelerometer Y axis data.
+ U16 accelZ; ///< Reg 318. Accelerometer Z axis data.
+ U16 accelXMax; ///< Reg 320. Accelerometer X axis max data (since last read).
+ U16 accelYMax; ///< Reg 322. Accelerometer Y axis max data (since last read).
+ U16 accelZMax; ///< Reg 324. Accelerometer Z axis max data (since last read).
+ U16 accelFaultRegister; ///< Reg 326. Accelerometer fault register.
+ U16 accelSampleCounter; ///< Reg 328. Accelerometer sample count.
+ U16 venousPressure; ///< Reg 330. Venous pressure sensor data.
+ U16 venousTemperature; ///< Reg 332. Venous pressure sensor temperature.
+ U08 venousReadCounter; ///< Reg 334. Venous pressure sensor read count.
+ U08 dialOutPumpSensorStatus; ///< Reg 335. Dialysate outlet pump hall sensor status.
+ U16 dialInPumpHallSensorCount; ///< Reg 336. Dialysate inlet pump hall sensor count.
+ U16 dialOutPumpHallSensorCount; ///< Reg 338. Dialysate outlet pump hall sensor count.
+ U32 reserved16; ///< Reg 340. Reserved.
+ U32 reserved17; ///< Reg 344. Reserved.
+ F32 reserved18; ///< Reg 348. Reserved.
+ U16 fan1PulseTime; ///< Reg 352. Fan 1 pulse time in 2.5 uSec resolution. 0xFFFF if fan RPM < 500 RPM.
+ U16 fan2PUlseTime; ///< Reg 354. Fan 2 pulse time in 2.5 uSec resolution. 0xFFFF if fan RPM < 500 RPM.
+ U16 fpgaGPIO; ///< Reg 356. FPGA GPIO register.
+ S16 VBAPosition; ///< Reg 358. Encoder position from VBA pinch valve. 0 until PID interface is enabled.
+ S16 VBVPosition; ///< Reg 360. Encoder position from VBV pinch valve. 0 until PID interface is enabled.
+ S16 VDiPosition; ///< Reg 362. Encoder position from VDi pinch valve. 0 until PID interface is enabled.
+ S16 VDoPosition; ///< Reg 364. Encoder position from VDo pinch valve. 0 until PID interface is enabled.
+ S16 fpgaIntVoltage; ///< Reg 366. Internal FPGA Vcc voltage. 3V range over 12 bits (0..4095).
+ U16 valveStatus; ///< Reg 368. Valve status register.
+ U16 VBAPWMTarget; ///< Reg 370. PWM target duty cycle for VBA pinch valve.
+ U16 VBVPWMTarget; ///< Reg 372. PWM target duty cycle for VBV pinch valve.
+ U16 VDiPWMTarget; ///< Reg 374. PWM target duty cycle for VDi pinch valve.
+ U16 VDoPWMTarget; ///< Reg 376. PWM target duty cycle for VDo pinch valve.
+ U16 fpgaAuxVoltage; ///< Reg 378. Internal FPGA Vcc Aux voltage. 3V range over 12 bits (0..4095).
+ U08 syringePumpStatus; ///< Reg 380. Syringe pump status register.
+ U08 syringePumpADCReadCounter; ///< Reg 381. Syringe pump ADC read counter.
+ U08 syringePumpADCandDACStatus; ///< Reg 382. Syringe pump ADC and DAC status register.
+ U08 syringePumpEncoderStatus; ///< Reg 383. Syringe pump encoder status register.
+ U32 syringePumpEncPosition; ///< Reg 384. Syringe pump encoder position
+ U16 syringePumpAdcDataReadCh0; ///< Reg 388. Syringe pump ADC channel 0 register (10 bit).
+ U16 syringePumpAdcDataReadCh1; ///< Reg 390. Syringe pump ADC channel 1 register (10 bit).
+ U16 syringePumpAdcDataReadCh2; ///< Reg 392. Syringe pump ADC channel 2 register (10 bit).
+ U16 syringePumpAdcDataReadCh3; ///< Reg 394. Syringe pump ADC channel 3 register (10 bit).
+ U16 VBASpeed; ///< Reg 396. VBA pinch valve speed (Register VAUX0)
+ U16 VBVSpeed; ///< Reg 398. VBV pinch valve speed (Register VAUX1)
+ U16 VBVCurrent; ///< Reg 400. VBV pinch valve current (Register VAUX2)
+ U16 VDoCurrent; ///< Reg 402. VDo pinch valve current (Register VAUX3)
+ U16 VBACurrent; ///< Reg 404. VBA pinch valve current (Register VAUX8)
+ U16 VDiSpeed; ///< Reg 406. VDi pinch valve current (Register VAUX5)
+ U16 VDoSpeed; ///< Reg 408. VDo pinch valve speed (Register VAUX10)
+ U16 VDiCurrent; ///< Reg 410. VDi pinch valve current (Register VAUX13)
+ U16 fpgaTemperature; ///< Reg 412. FPGA die temperature (deg C = counts x (503.975/4096) - 273.15).
+ U16 fpgaVpvn; ///< Reg 414. FPGA pvn voltage. 1V range over 12 bits (0..4095).
+ U16 fpgaTimerCount_ms; ///< Reg 416. Free running 1ms timer counter. Rolls over at 65535.Internal FPGA timer count in ms.
+ U16 backupAlarmAudioPeakCurrent; ///< Reg 418. Piezo alarm peak ADC current in previous 10ms. 12 bit unsigned.
+ U08 V1EncError; ///< Reg 420. Pinch valve V1 encoder error counter.
+ U08 V2EncError; ///< Reg 421. Pinch valve V2 encoder error counter.
+ U08 V3EncError; ///< Reg 422. Pinch valve V3 encoder error counter.
+ U08 V4EncError; ///< Reg 423. Pinch valve V4 encoder error counter.
+ U08 ADACounter; ///< Reg 424. ADA bubble counter.
+ U08 ADVCounter; ///< Reg 425. ADV bubble counter.
+ U08 reserved19; ///< Reg 426. Reserved.
+ U08 reserved20; ///< Reg 427. Reserved.
+ U08 VenousErrorCounter; ///< Reg 428. Venous error counter.
+ U08 reserved21; ///< Reg 429. Reserved.
+ U16 reserved22; ///< Reg 430. Reserved.
+ U16 reserved23; ///< Reg 432. Reserved.
+ U16 reserved24; ///< Reg 434. Reserved.
+ U16 reserved25; ///< Reg 436. Reserved.
+ U16 reserved26; ///< Reg 438. Reserved.
+ U16 arterialPressure; ///< Reg 440. Arterial pressure sensor.
+ U16 arterialPressureTemperature; ///< Reg 442. Arterial pressure sensor temperature.
+ U08 arterialPressureReadCount; ///< Reg 444. Arterial pressure sensor read count.
+ U08 arterialPressureErrorCount; ///< Reg 445. Arterial pressure sensor error count.
+ U08 bloodLeakTxFIFOCount; ///< Reg 446. Blood leak transmit FIFO count.
+ U08 bloodLeakRxErrorCount; ///< Reg 447. Blood leak receive error count.
+ U16 bloodLeakRxFIFOCount; ///< Reg 448. Blood leak receive FIFO count.
+ U08 bloodLeakRxFIFODataOut; ///< Reg 450. Blood leak receive FIFO data out.
+ U08 dummyByte; ///< Reg 451. Dummy byte to meet the even of the data.
+ U16 fpgaCompatibilityRev; ///< Reg 452. Compatibility revisions
+} FPGA_SENSORS_T;
+
+/// Record structure for FPGA continuous priority writes.
+typedef struct
+{
+ U08 fpgaSensorTest; ///< Reg 11. Blood leak and bubble detector sensor test register.
+ U16 fpgaPIDControl; ///< Reg 12. Valve PID enables.
+ S16 VBASetPoint; ///< Reg 14. VBA pinch valve is commanded to this set point position.
+ S16 VBVSetPoint; ///< Reg 16. VBV pinch valve is commanded to this set point position.
+ S16 VDiSetPoint; ///< Reg 18. VDi pinch valve is commanded to this set point position.
+ S16 VDoSetPoint; ///< Reg 20. VDo pinch valve is commanded to this set point position.
+ S16 VSpareSetPoint; ///< Reg 22. VSpare pinch valve is commanded to this set point position.
+ U16 VBAPWMFixed; ///< Reg 24. VBA PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction.
+ U16 VBVPWMFixed; ///< Reg 26. VBV PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction.
+ U16 VDiPWMFixed; ///< Reg 28. VDi PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction.
+ U16 VDoPWMFixed; ///< Reg 30. VDo PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction.
+ U16 VSparePWMFixed; ///< Reg 32. Vspare PWM set to fixed current by setting fixed PWM duty cycle. Range 750 to 4250. < 2500 is reverse direction.
+ U08 alarmControl; ///< Reg 34. Alarm (audio) control register.
+ U08 syringePumpControl; ///< Reg 35. Syringe pump control register.
+ U32 syringePumpStepToggleTime; ///< Reg 36. Syringe pump step time toggle register. Sets time between step toggle which dictates stepper motor speed.
+ U16 syringePumpDACOut; ///< Reg 40. Syringe pump DAC output level (12-bit).
+ U08 syringePumpADCandDACControl; ///< Reg 42. Syringe pump ADC and DAC control register.
+ U08 bloodLeakUARTControl; ///< Reg 43. Blood leak UART control.
+ U08 bloodLeakFIFOTransmit; ///< Reg 44. Character word store in FIFO to be transmitted into blood leak UART interface.
+} FPGA_ACTUATORS_T;
+#pragma pack(pop)
+
+// ********** private data **********
+
+// FPGA data
+static FPGA_HEADER_T fpgaHeader; ///< Record of last received FPGA header data.
+static FPGA_SENSORS_T fpgaSensorReadings; ///< Record of last received FPGA priority sensor data.
+static FPGA_ACTUATORS_T fpgaActuatorSetPoints; ///< Record of next transmitted FPGA priority actuator data.
+
+// FPGA Clock Speed Test
+static U16 currentFPGATimerCount_ms = 0; ///< Last read ms timer count from FPGA.
+static U32 currentTimerCount_ms = 0; ///< Last read ms timer count from processor.
+
+// ********** private function prototypes **********
+
+/*********************************************************************//**
+ * @brief
+ * The initFpgaTD function initializes the TD FPGA module.
+ * @details Inputs: none
+ * @details Outputs: TD FPGA module initialized.
+ * @return none
+ *************************************************************************/
+void initFpgaTD( void )
+{
+ // Initialize fpga driver
+ initFPGA( (U08*)&fpgaHeader, (U08*)&fpgaSensorReadings, (U08*)&fpgaActuatorSetPoints,
+ sizeof(FPGA_HEADER_T), sizeof(FPGA_SENSORS_T), sizeof(FPGA_ACTUATORS_T) );
+ // Initialize fpga data structures
+ memset( &fpgaHeader, 0, sizeof(FPGA_HEADER_T) );
+ memset( &fpgaSensorReadings, 0, sizeof(FPGA_SENSORS_T) );
+ memset( &fpgaActuatorSetPoints, 0, sizeof(FPGA_ACTUATORS_T) );
+ fpgaActuatorSetPoints.alarmControl = (U08)MIN_ALARM_VOLUME_ATTENUATION << 2; // Start alarm audio volume at maximum
+
+ // Set the HD valves fixed PWM mode to 2500, so if it was commanded to be in PWM mode rather than PID control
+ // the valves will not move to 0 position
+// fpgaActuatorSetPoints.VDiPWMFixed = FPGA_VALVES_MIN_PWM_MODE_COUNT;
+// fpgaActuatorSetPoints.VDoPWMFixed = FPGA_VALVES_MIN_PWM_MODE_COUNT;
+// fpgaActuatorSetPoints.VBAPWMFixed = FPGA_VALVES_MIN_PWM_MODE_COUNT;
+// fpgaActuatorSetPoints.VBVPWMFixed = FPGA_VALVES_MIN_PWM_MODE_COUNT;
+
+ // initialize FPGA comm failures windowed timer count
+ initTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES, MAX_FPGA_COMM_FAILURES, MAX_FPGA_COMM_FAILURES_WINDOW_MS);
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execFPGATest function executes the FPGA self-test.
+ * @details Inputs: fpgaHeader
+ * @details Outputs: none
+ * @return passed, or failed
+ *************************************************************************/
+SELF_TEST_STATUS_T execFPGATest( void )
+{
+ SELF_TEST_STATUS_T result;
+
+ // check FPGA reported correct ID
+ if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId )
+ {
+ // Check FPGA compatibility w/ firmware
+ if ( HD_FPGA_COMPATIBILITY_REV == fpgaSensorReadings.fpgaCompatibilityRev )
+ {
+ result = SELF_TEST_STATUS_PASSED;
+ }
+ else
+ {
+ result = SELF_TEST_STATUS_FAILED;
+ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_POST_TEST_FAILED, (U32)HD_FPGA_COMPATIBILITY_REV, (U32)fpgaSensorReadings.fpgaCompatibilityRev )
+ }
+ }
+ else
+ {
+ result = SELF_TEST_STATUS_FAILED;
+ SET_ALARM_WITH_1_U32_DATA( ALARM_ID_HD_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaId )
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGATimerCount function gets the latest FPGA timer millisecond count.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last FPGA timer count
+ *************************************************************************/
+U16 getFPGATimerCount( void )
+{
+ return fpgaSensorReadings.fpgaTimerCount_ms;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The execFPGAClockSpeedTest function verifies the processor clock speed
+ * against the FPGA clock.
+ * @details Inputs: fpgaHeader
+ * @details Outputs: none
+ * @return passed, or failed
+ *************************************************************************/
+void execFPGAClockSpeedTest( void )
+{
+// DEBUG WARNING
+// It may be necessary to comment out the following
+// code to prevent the alarm from occurring while
+// debugging.
+ U16 newFPGATimerCount_ms = getFPGATimerCount();
+ U32 newTimerCount_ms = getMSTimerCount();
+ U32 diffFPGATimerCount = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms );
+ U32 diffTimerCount = u32DiffWithWrap( currentTimerCount_ms, newTimerCount_ms );
+
+ if ( getCurrentOperationMode() != MODE_INIT )
+ {
+ if ( abs( diffFPGATimerCount - diffTimerCount ) > PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE )
+ {
+ if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR ) )
+ {
+ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_CLOCK_SPEED_CHECK_FAILURE, diffFPGATimerCount, diffTimerCount );
+ }
+ }
+ }
+
+ currentFPGATimerCount_ms = newFPGATimerCount_ms;
+ currentTimerCount_ms = newTimerCount_ms;
+
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAVersions function gets the fpga version numbers.
+ * @details Inputs: fpgaHeader
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void getFPGAVersions( U08 *Id, U08 *Maj, U08 *Min, U08 *Lab )
+{
+ *Id = fpgaHeader.fpgaId;
+ *Min = fpgaHeader.fpgaRev;
+ *Maj = fpgaHeader.fpgaRevMajor;
+ *Lab = fpgaHeader.fpgaRevLab;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGATemperature function gets the fpga internal die temperature.
+ * @details Inputs: fpgaHeader
+ * @details Outputs: none
+ * @return current internal FPGA die temperature (in counts)
+ *************************************************************************/
+U16 getFPGATemperature( void )
+{
+ return fpgaSensorReadings.fpgaTemperature;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAVcc function gets the fpga input voltage.
+ * @details Inputs: fpgaHeader
+ * @details Outputs: none
+ * @return current FPGA input voltage (in volts)
+ *************************************************************************/
+F32 getFPGAVcc( void )
+{
+ F32 result = 0.0;//(F32)fpgaSensorReadings.fpgaIntVoltage * FPGA_INPUT_VOLTAGE_SCALE / (F32)BITS_12_FULL_SCALE;
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAVccAux function gets the fpga aux. voltage.
+ * @details Inputs: fpgaHeader
+ * @details Outputs: none
+ * @return current FPGA aux. voltage (in volts)
+ *************************************************************************/
+F32 getFPGAVccAux( void )
+{
+ F32 result = 0.0;//(F32)fpgaSensorReadings.fpgaAuxVoltage * FPGA_INPUT_VOLTAGE_SCALE / (F32)BITS_12_FULL_SCALE;
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAVpvn function gets the fpga pvn voltage.
+ * @details Inputs: fpgaHeader
+ * @details Outputs: none
+ * @return current FPGA pvn voltage (in volts)
+ *************************************************************************/
+F32 getFPGAVpvn( void )
+{
+ F32 result = 0.0;//(F32)fpgaSensorReadings.fpgaVpvn * FPGA_PVN_VOLTAGE_SCALE / (F32)BITS_12_FULL_SCALE;
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setAlarmAudioState function sets the fpga audio control to the given
+ * state and volume.
+ * @details Inputs: none
+ * @details Outputs: alarm audio state and attenuation set
+ * @param state the state of alarm audio to command (3..5):
+ * 0 - No alarm tone
+ * 1 - Low priority alarm tone (c e)
+ * 2 - Medium priority alarm tone (c f# c)
+ * 3 - High priority alarm tone (c f# c - c f#)
+ * 4 - Continuous test tone (e)
+ * @param volumeLevel the level of attenuation to command (0..2):
+ * 4 - 3 dB gain
+ * 3 - 6 dB gain
+ * 2 - 9 dB gain
+ * 1 - 12 dB gain
+ * 0 - 15 dB gain
+ * @param volumeDivider further attenuation via divider (6..7):
+ * 0 - Divide by 2
+ * 1 - Divide by 4
+ * 2 - Divide by 8
+ * 3 - Divide by 16
+ * @return none
+ *************************************************************************/
+void setAlarmAudioState( U32 state, U32 volumeLevel, U32 volumeDivider )
+{
+// U08 audioCmd = (U08)state;
+//
+// audioCmd |= ( (U08)volumeLevel << FPGA_ALARM_AUDIO_VOLUME_SHIFT );
+// audioCmd |= ( (U08)volumeDivider << FPGA_ALARM_AUDIO_DIVIDE_SHIFT );
+//
+// if ( ( state <= NUM_OF_ALARM_PRIORITIES ) && ( volumeLevel <= MAX_ALARM_VOLUME_ATTENUATION ) )
+// {
+// fpgaActuatorSetPoints.alarmControl = audioCmd;
+// }
+// else
+// {
+// // S/w fault to indicate issue w/ s/w
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_ALARM_AUDIO_PARAM, (U32)audioCmd )
+// // Set alarm audio to high priority, max volume for safety since s/w seems to be having trouble setting audio correctly
+// audioCmd = (U08)ALARM_PRIORITY_HIGH;
+// audioCmd |= ( (U08)MIN_ALARM_VOLUME_ATTENUATION << FPGA_ALARM_AUDIO_VOLUME_SHIFT );
+// fpgaActuatorSetPoints.alarmControl = audioCmd;
+// }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodPumpHallSensorCount function gets the latest blood pump
+ * hall sensor count. Count is a 16 bit free running counter. If counter is
+ * counting up, indicates motor is running in forward direction. If counter is
+ * counting down, indicates motor is running in reverse direction. Counter will
+ * wrap at 0/65535.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last blood pump hall sensor count reading.
+ *************************************************************************/
+U16 getFPGABloodPumpHallSensorCount( void )
+{
+ return fpgaSensorReadings.bloodPumpHallSensorCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodPumpHallSensorStatus function gets the latest blood pump
+ * hall sensor status.
+ * Bit 7 - Derived direction of the blood pump motor (0=Fwd, 1=Rev)
+ * Bit 6 - Unused
+ * Bit 5-0 - Direction error count since power-up (rolls over)
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last blood pump hall sensor status reading.
+ *************************************************************************/
+U08 getFPGABloodPumpHallSensorStatus( void )
+{
+ return fpgaSensorReadings.bloodPumpHallSensorStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGADialInPumpHallSensorCount function gets the latest dialysate inlet pump
+ * hall sensor count. Count is a 16 bit free running counter. If counter is
+ * counting up, indicates motor is running in forward direction. If counter is
+ * counting down, indicates motor is running in reverse direction. Counter will
+ * wrap at 0/65535.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last dialysate inlet pump hall sensor count reading.
+ *************************************************************************/
+U16 getFPGADialInPumpHallSensorCount( void )
+{
+ return fpgaSensorReadings.dialInPumpHallSensorCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGADialInPumpHallSensorStatus function gets the latest dialysate inlet pump
+ * hall sensor status.
+ * Bit 7 - Derived direction of the dialysate inlet pump motor (0=Fwd, 1=Rev)
+ * Bit 6 - Unused
+ * Bit 5-0 - Direction error count since power-up (rolls over)
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last dialysate inlet pump hall sensor status reading.
+ *************************************************************************/
+U08 getFPGADialInPumpHallSensorStatus( void )
+{
+ return fpgaSensorReadings.dialInPumpHallSensorStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGADialOutPumpHallSensorCount function gets the latest dialysate outlet pump
+ * hall sensor count. Count is a 16-bit free running counter. If counter is
+ * counting up, indicates motor is running in forward direction. If counter is
+ * counting down, indicates motor is running in reverse direction. Counter will
+ * wrap at 0/65535.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last dialysate outlet pump hall sensor count reading.
+ *************************************************************************/
+U16 getFPGADialOutPumpHallSensorCount( void )
+{
+ return fpgaSensorReadings.dialOutPumpHallSensorCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGADialOutPumpHallSensorStatus function gets the latest dialysate outlet pump
+ * hall sensor status.
+ * Bit 7 - Derived direction of the dialysate outlet pump motor (0=Fwd, 1=Rev)
+ * Bit 6 - Unused
+ * Bit 5-0 - Direction error count since power-up (rolls over)
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last dialysate outlet pump hall sensor status reading.
+ *************************************************************************/
+U08 getFPGADialOutPumpHallSensorStatus( void )
+{
+ return fpgaSensorReadings.dialOutPumpSensorStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodPumpOcclusion function gets the latest blood occlusion reading.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last blood occlusion reading
+ *************************************************************************/
+U16 getFPGABloodPumpOcclusion( void )
+{
+ return fpgaSensorReadings.bloodOcclusionData;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodPumpOcclusionReadCounter function gets the latest blood
+ * pump occlusion read counter.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last blood pump occlusion read counter
+ *************************************************************************/
+U08 getFPGABloodPumpOcclusionReadCounter( void )
+{
+ return fpgaSensorReadings.bloodOcclusionReadCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodPumpOcclusionErrorCounter function gets the latest blood
+ * pump occlusion error counter.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last blood pump occlusion error counter
+ *************************************************************************/
+U08 getFPGABloodPumpOcclusionErrorCounter( void )
+{
+ return fpgaSensorReadings.bloodOcclusionErrorCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAArterialPressure function gets the latest arterial pressure reading.
+ * High byte indicates alarm status for ADC channel.
+ * Low 24-bits are channel reading. Subtract 2^23 from low 24 bits to get
+ * signed channel reading.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last arterial pressure reading
+ *************************************************************************/
+U32 getFPGAArterialPressure( void )
+{
+ return fpgaSensorReadings.adc1Channel0;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAArterialPressureReadCounter function gets the latest arterial
+ * pressure sensor read counter.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last arterial pressure sensor read counter
+ *************************************************************************/
+U08 getFPGAArterialPressureReadCounter( void )
+{
+ return fpgaSensorReadings.adc1SequenceCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAArterialPressureErrorCounter function gets the latest arterial
+ * pressure sensor error counter.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last arterial pressure sensor error counter
+ *************************************************************************/
+U08 getFPGAArterialPressureErrorCounter( void )
+{
+ return fpgaSensorReadings.adc1ErrorCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGADVTArterialPressure function gets the latest arterial pressure reading.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last arterial pressure reading
+ *************************************************************************/
+U16 getFPGADVTArterialPressure( void )
+{
+ return fpgaSensorReadings.arterialPressure;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGADVTArterialTemperature function gets the latest arterial pressure
+ * sensor temperature reading.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last arterial pressure sensor temperature reading
+ *************************************************************************/
+U16 getFPGADVTArterialTemperature( void )
+{
+ return fpgaSensorReadings.arterialPressureTemperature;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGADVTArterialPressureReadCounter function gets the latest arterial
+ * pressure sensor read counter.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last arterial pressure sensor read counter
+ *************************************************************************/
+U08 getFPGADVTArterialPressureReadCounter( void )
+{
+ return fpgaSensorReadings.arterialPressureReadCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGATDVTArterialPressureErrorCounter function gets the latest arterial
+ * pressure sensor error counter.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last arterial pressure sensor error counter
+ *************************************************************************/
+U08 getFPGATDVTArterialPressureErrorCounter( void )
+{
+ return fpgaSensorReadings.arterialPressureErrorCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAVenousPressure function gets the latest venous pressure reading.
+ * The high 2 bits are status bits: 00=ok, 01=cmd mode, 10=stale data, 11=diag
+ * The low 14 bits are data. Zero is at 1638. Values above are positive,
+ * below are negative.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last venous pressure reading
+ *************************************************************************/
+U16 getFPGAVenousPressure( void )
+{
+ return fpgaSensorReadings.venousPressure;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAVenousPressureTemperature function gets the latest venous pressure
+ * sensor temperature reading.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last venous pressure sensor temperature reading
+ *************************************************************************/
+U16 getFPGAVenousPressureTemperature( void )
+{
+ return fpgaSensorReadings.venousTemperature;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAVenousPressureReadCounter function gets the latest venous pressure
+ * sensor read counter.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last venous pressure sensor read counter
+ *************************************************************************/
+U08 getFPGAVenousPressureReadCounter( void )
+{
+ return fpgaSensorReadings.venousReadCounter;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAVenousPressureErrorCounter function gets the latest venous pressure
+ * sensor error counter.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last venous pressure sensor error counter
+ *************************************************************************/
+U08 getFPGAVenousPressureErrorCounter( void )
+{
+ return fpgaSensorReadings.VenousErrorCounter;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGASyringePumpControlFlags function sets the syringe pump control
+ * register per given bit flags.
+ * @details Inputs: none
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param bitFlags control bit settings for syringe pump
+ * @return none
+ *************************************************************************/
+void setFPGASyringePumpControlFlags( U08 bitFlags )
+{
+ fpgaActuatorSetPoints.syringePumpControl = bitFlags;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGASyringePumpADCandDACControlFlags function sets the syringe pump
+ * ADC/DAC control register per given bit flags.
+ * @details Inputs: none
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param bitFlags ADC/DAC control bit settings for syringe pump
+ * @return none
+ *************************************************************************/
+void setFPGASyringePumpADCandDACControlFlags( U08 bitFlags )
+{
+ fpgaActuatorSetPoints.syringePumpADCandDACControl = bitFlags;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGASyringePumpDACOutputLevel function sets the syringe pump force
+ * sensor DAC output level register to a given value.
+ * @details Inputs: none
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param counts level to set syringe pump force sensor DAC to
+ * @return none
+ *************************************************************************/
+void setFPGASyringePumpDACOutputLevel( U16 counts )
+{
+ fpgaActuatorSetPoints.syringePumpDACOut = counts;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGASyringePumpStepToggleTime function sets the syringe pump stepper
+ * toggle time register to a given period (in uSec).
+ * @details Inputs: none
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param microSeconds toggle the stepper motor at this time interval to set pump speed
+ * @return none
+ *************************************************************************/
+void setFPGASyringePumpStepToggleTime( U32 microSeconds )
+{
+ fpgaActuatorSetPoints.syringePumpStepToggleTime = microSeconds;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpStatus function gets the latest syringe pump status
+ * register reading. Bit 0 indicates a fault.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump status reading
+ *************************************************************************/
+U08 getFPGASyringePumpStatus( void )
+{
+ return fpgaSensorReadings.syringePumpStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpADCReadCounter function gets the latest syringe pump
+ * ADC read counter. Counter is 8-bit and rolls over when exceeding 255.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump ADC read counter
+ *************************************************************************/
+U08 getFPGASyringePumpADCReadCounter( void )
+{
+ return fpgaSensorReadings.syringePumpADCReadCounter;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpADCandDACStatus function gets the latest syringe pump
+ * ADC/DAC status register reading.
+ * Bit 7 = DAC write and read-back done
+ * Bit 6 = I2C error on DAC data transfer
+ * Bit 0..5 = count of I2C errors, rolls over after 63
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump ADC/DAC status reading
+ *************************************************************************/
+U08 getFPGASyringePumpADCandDACStatus( void )
+{
+ return fpgaSensorReadings.syringePumpADCandDACStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpEncoderStatus function gets the latest syringe pump
+ * encoder status register reading.
+ * Bit 7 = direction (0=fwd, 1=rev)
+ * Bit 0..5 = direction error count (# of errors after power up, rolls over after 63)
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump encoder status reading
+ *************************************************************************/
+U08 getFPGASyringePumpEncoderStatus( void )
+{
+ return fpgaSensorReadings.syringePumpEncoderStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpEncoderPosition function gets the latest syringe pump
+ * encoder position reading.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump encoder position reading
+ *************************************************************************/
+U32 getFPGASyringePumpEncoderPosition( void )
+{
+ return fpgaSensorReadings.syringePumpEncPosition;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpADCChannel0 function gets the latest syringe pump ADC
+ * channel 0 register reading (syringe pump force sensor).
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump ADC channel 0 reading
+ *************************************************************************/
+U16 getFPGASyringePumpADCChannel0( void )
+{
+ return fpgaSensorReadings.syringePumpAdcDataReadCh0;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpADCChannel1 function gets the latest syringe pump ADC
+ * channel 1 register reading (syringe detection switch).
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump ADC channel 1 reading
+ *************************************************************************/
+U16 getFPGASyringePumpADCChannel1( void )
+{
+ return fpgaSensorReadings.syringePumpAdcDataReadCh1;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpADCChannel2 function gets the latest syringe pump ADC
+ * channel 2 register reading (syringe pump home position sensor).
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump ADC channel 2 reading
+ *************************************************************************/
+U16 getFPGASyringePumpADCChannel2( void )
+{
+ return fpgaSensorReadings.syringePumpAdcDataReadCh2;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpADCChannel3 function gets the latest syringe pump ADC
+ * channel 3 register reading.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump ADC channel 3 reading
+ *************************************************************************/
+U16 getFPGASyringePumpADCChannel3( void )
+{
+ return fpgaSensorReadings.syringePumpAdcDataReadCh3;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpDACStatus function gets the latest syringe pump
+ * DAC status.
+ * Bit 0: PD0
+ * Bit 1: PD1
+ * Bit 2: POR
+ * Bit 3: Ready (not busy)
+ * Bits 4..7: N/A
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump DAC status reading
+ *************************************************************************/
+U08 getFPGASyringePumpDACStatus( void )
+{
+ return fpgaSensorReadings.sPumpDACRdStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpDACSetting function gets the latest syringe pump
+ * DAC setting.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump DAC setting
+ *************************************************************************/
+U16 getFPGASyringePumpDACSetting( void )
+{
+ return fpgaSensorReadings.sPumpDACSet;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGASyringePumpDACStoredSetting function gets the latest syringe
+ * pump DAC setting stored in sensor's EEPROM.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return last syringe pump DAC setting stored in EEPROM
+ *************************************************************************/
+U16 getFPGASyringePumpDACStoredSetting( void )
+{
+ return fpgaSensorReadings.sPumpDACEEProm;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAAccelAxes function gets the accelerometer axis readings.
+ * Axis readings are in ADC counts. 0.004 g per LSB.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @param x Populate this param with X axis reading
+ * @param y Populate this param with Y axis reading
+ * @param z Populate this param with Z axis reading
+ * @return none
+ *************************************************************************/
+void getFPGAAccelAxes( S16 *x, S16 *y, S16 *z )
+{
+ *x = (S16)fpgaSensorReadings.accelX;
+ *y = (S16)fpgaSensorReadings.accelY;
+ *z = (S16)fpgaSensorReadings.accelZ;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAAccelMaxes function gets the maximum accelerometer axis readings.
+ * from last FPGA read (every 10ms).
+ * Axis readings are in ADC counts. 0.004 g per LSB.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @param x Populate this param with maximum X axis reading
+ * @param y Populate this param with maximum Y axis reading
+ * @param z Populate this param with maximum Z axis reading
+ * @return none
+ *************************************************************************/
+void getFPGAAccelMaxes( S16 *xmax, S16*ymax, S16*zmax )
+{
+ *xmax = (S16)fpgaSensorReadings.accelXMax;
+ *ymax = (S16)fpgaSensorReadings.accelYMax;
+ *zmax = (S16)fpgaSensorReadings.accelZMax;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAAccelStatus function gets the accelerometer reading count
+ * and error register values.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @param cnt Populate this param with latest sample counter value
+ * @param err Populate this param with latest error
+ * @return none
+ *************************************************************************/
+void getFPGAAccelStatus( U16 *cnt, U16 *err )
+{
+ *cnt = fpgaSensorReadings.accelSampleCounter;
+ *err = fpgaSensorReadings.accelFaultRegister;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABackupAlarmAudioCurrent function gets the latest piezo alarm
+ * audio current reading.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return Latest piezo alarm audio current reading
+ *************************************************************************/
+F32 getFPGABackupAlarmAudioCurrent( void )
+{
+// U16 adcCnts = fpgaSensorReadings.backupAlarmAudioPeakCurrent;
+ F32 result = 0.0;//( ( (F32)adcCnts / (F32)BITS_12_FULL_SCALE ) * FPGA_BACKUP_ALARM_AUDIO_CONVERT ) * (F32)MA_PER_AMP;
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAAirTrapLevels function gets the latest air trap level sensor
+ * readings.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void getFPGAAirTrapLevels( BOOL *airAtLower, BOOL *airAtUpper )
+{
+// U16 fpgaGPIO = fpgaSensorReadings.fpgaGPIO;
+ U16 lower = 0;//fpgaGPIO & FPGA_AIRTRAP_LEVEL_LOW_MASK;
+ U16 upper = 0;//fpgaGPIO & FPGA_AIRTRAP_LEVEL_HIGH_MASK;
+
+ *airAtLower = ( 0 == lower ? FALSE : TRUE );
+ *airAtUpper = ( 0 == upper ? FALSE : TRUE );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGAValvesControlMode function sets the valves control mode.
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param bits : The bits to enable the PID controller of a valve
+ * @return none
+ *************************************************************************/
+void setFPGAValvesControlMode( U16 bits )
+{
+ fpgaActuatorSetPoints.fpgaPIDControl = bits;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getValvesStatus function reads the status of the valves
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return The status of the valves
+ *************************************************************************/
+U16 getFPGAValvesStatus( void )
+{
+ return fpgaSensorReadings.valveStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The noFPGAFluidLeakDetected function returns TRUE if no fluid leak has been
+ * detected (dry) and FALSE if a fluid leak has been detected (wet).
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return noFPGAFluidLeakDetected
+ *************************************************************************/
+BOOL noFPGAFluidLeakDetected( void )
+{
+ U16 noFPGAFluidLeakDetected = 0;//fpgaSensorReadings.fpgaGPIO & FPGA_FLUID_LEAK_STATE_MASK;
+
+ return ( 0 == noFPGAFluidLeakDetected ? FALSE : TRUE );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodLeakStatus function returns the blood leak sensor's
+ * blood detection status bit.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return blood leak sensor self test status bit
+ *************************************************************************/
+U08 getFPGABloodLeakStatus( void )
+{
+ U08 selfTestStatus = 0;//(U08)( ( fpgaSensorReadings.fpgaGPIO & FPGA_BLOOD_LEAK_STATUS_MASK ) >> FPGA_BLOOD_LEAK_ST_BIT_INDEX );
+
+ return selfTestStatus;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGABloodLeakUARTControl function sets the blood leak sensor UART
+ * control value.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void setFPGABloodLeakUARTControl( U08 value )
+{
+ fpgaActuatorSetPoints.bloodLeakUARTControl = value;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGABloodLeakUARTTransmit function sets the blood leak sensor UART
+ * transmit value.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void setFPGABloodLeakUARTTransmit( U08 value )
+{
+ fpgaActuatorSetPoints.bloodLeakFIFOTransmit = value;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodLeakTxFIFOCount function returns the blood leak transmit
+ * FIFO count.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return fpgaSensorReadings.bloodLeakTxFIFOCount
+ *************************************************************************/
+U08 getFPGABloodLeakTxFIFOCount( void )
+{
+ return fpgaSensorReadings.bloodLeakTxFIFOCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodLeakRxFIFOCount function returns the blood leak receive
+ * FIFO count.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return fpgaSensorReadings.bloodLeakRxFIFOCount
+ *************************************************************************/
+U16 getFPGABloodLeakRxFIFOCount( void )
+{
+ return fpgaSensorReadings.bloodLeakRxFIFOCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodLeakRxErrorCount function returns the blood leak receive
+ * error count.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return fpgaSensorReadings.bloodLeakRxErrorCount
+ *************************************************************************/
+U08 getFPGABloodLeakRxErrorCount( void )
+{
+ return fpgaSensorReadings.bloodLeakRxErrorCount;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABloodLeakRxFIFODataOut function returns the blood leak receive
+ * FIFO data out.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return fpgaSensorReadings.bloodLeakRxFIFODataOut
+ *************************************************************************/
+U08 getFPGABloodLeakRxFIFODataOut( void )
+{
+ return fpgaSensorReadings.bloodLeakRxFIFODataOut;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The noFPGABubbleDetected function returns TRUE if no air bubble has been
+ * detected and FALSE if an air bubble has been detected.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return noFPGABubbleDetected
+ *************************************************************************/
+BOOL noFPGABubbleDetected( U32 bubble )
+{
+ U16 noFPGABubbleDetected = 0;
+
+// if ( bubble == ADV )
+// {
+// noFPGABubbleDetected = fpgaSensorReadings.fpgaGPIO & FPGA_ADV_BUBBLE_STATUS_MASK;
+// }
+// else
+// {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_SOFTWARE_FAULT, SW_FAULT_ID_HD_INVALID_BUBBLE_ID, bubble )
+// }
+
+ return ( 0 != noFPGABubbleDetected ? TRUE : FALSE );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGABubbleSelfTest function sets the given air bubble detector into
+ * self-test mode via the FPGA.
+ * @details Inputs: none
+ * @details Outputs: fpgaActuatorSetPoints
+ * @return: none
+ *************************************************************************/
+void setFPGABubbleSelfTest( U32 bubble )
+{
+// if ( bubble == ADV )
+// {
+// fpgaActuatorSetPoints.fpgaSensorTest |= FPGA_ADV_BUBBLE_SELF_TEST_CMD;
+// }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The clearFPGABubbleSelfTest function clears the given air bubble detector
+ * from self-test mode via the FPGA.
+ * @details Inputs: none
+ * @details Outputs: fpgaActuatorSetPoints
+ * @return: none
+ *************************************************************************/
+void clearFPGABubbleSelfTest( U32 bubble )
+{
+// if ( bubble == ADV )
+// {
+// fpgaActuatorSetPoints.fpgaSensorTest &= ~FPGA_ADV_BUBBLE_SELF_TEST_CMD;
+// }
+// else
+// {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_SOFTWARE_FAULT, SW_FAULT_ID_HD_INVALID_BUBBLE_ID, bubble )
+// }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setValveDialyzerInletPosition function sets the position of VDi
+ * in counts
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param setPoint : Next position of the valve in counts
+ * @return none
+ *************************************************************************/
+void setFPGAValveDialyzerInletPosition( S16 setPoint )
+{
+ fpgaActuatorSetPoints.VDiSetPoint = setPoint;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getValveDialyzerInletPosition function reads the current position
+ * of VDi in counts
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return The current position of VDi
+ *************************************************************************/
+S16 getFPGAValveDialyzerInletPosition( void )
+{
+ return fpgaSensorReadings.VDiPosition;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveDialyzerInletCurrentCounts function reads the current \n
+ * of VDi in counts
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return The current of VDi
+ *************************************************************************/
+U16 getFPGAValveDialyzerInletCurrentCounts( void )
+{
+ return fpgaSensorReadings.VDiCurrent;
+}
+
+#ifdef DEBUG_ENABLED
+/*********************************************************************//**
+ * @brief
+ * The setFPGAValveDialyzerInletPWM function sets the PWM of VDI in counts.
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param count which is the PWM of VDI in counts
+ * @return none
+ *************************************************************************/
+void setFPGAValveDialyzerInletPWM( U16 count )
+{
+ fpgaActuatorSetPoints.VDiPWMFixed = count;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveDialyzerInletPWM function reads the current PWM target
+ * of VDI.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return current PWM of VDI
+ *************************************************************************/
+U16 getFPGAValveDialyzerInletPWM( void )
+{
+ return fpgaSensorReadings.VDiPWMTarget;
+}
+#endif
+
+/*********************************************************************//**
+ * @brief
+ * The setFPGAValveDialyzerOutletPosition function sets the position of VDo
+ * in counts
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param setPoint : Next position of the valve in counts
+ * @return none
+ *************************************************************************/
+void setFPGAValveDialyzerOutletPosition( S16 setPoint )
+{
+ fpgaActuatorSetPoints.VDoSetPoint = setPoint;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveDialyzerOutletPosition function reads the current position
+ * of VDo in counts
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return The current position of VDo
+ *************************************************************************/
+S16 getFPGAValveDialyzerOutletPosition( void )
+{
+ return fpgaSensorReadings.VDoPosition;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveDialyzerOutletCurrentCounts function reads the current
+ * of VDo in counts
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return The current of VDo
+ *************************************************************************/
+U16 getFPGAValveDialyzerOutletCurrentCounts( void )
+{
+ return fpgaSensorReadings.VDoCurrent;
+}
+
+#ifdef DEBUG_ENABLED
+/*********************************************************************//**
+ * @brief
+ * The setFPGAValveDialyzerOutletPWM function sets the PWM of VDO in counts.
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param count which is the PWM of VDO in counts
+ * @return none
+ *************************************************************************/
+void setFPGAValveDialyzerOutletPWM( U16 count )
+{
+ fpgaActuatorSetPoints.VDoPWMFixed = count;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveDialyzerOutletPWM function reads the current PWM target
+ * of VDO.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return current PWM of VDO
+ *************************************************************************/
+U16 getFPGAValveDialyzerOutletPWM( void )
+{
+ return fpgaSensorReadings.VDoPWMTarget;
+}
+#endif
+
+/*********************************************************************//**
+ * @brief
+ * The setValveBloodVenousPosition function sets the position of VBV
+ * in counts
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param setPoint : Next position of the valve in counts
+ * @return none
+ *************************************************************************/
+void setFPGAValveBloodVenousPosition( S16 setPoint )
+{
+ fpgaActuatorSetPoints.VBVSetPoint = setPoint;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getValveBloodVenousPosition function reads the current position
+ * of VBV in counts
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return The current position of VBV
+ *************************************************************************/
+S16 getFPGAValveBloodVenousPosition( void )
+{
+ return fpgaSensorReadings.VBVPosition;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveBloodVenousCurrentCounts function reads the current
+ * of VBV in counts
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return The current of VBV
+ *************************************************************************/
+U16 getFPGAValveBloodVenousCurrentCounts( void )
+{
+ return fpgaSensorReadings.VBVCurrent;
+}
+
+#ifdef DEBUG_ENABLED
+/*********************************************************************//**
+ * @brief
+ * The setFPGAValveBloodVenousPWM function sets the PWM of VBV in counts.
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param count which is the PWM of VBV in counts
+ * @return none
+ *************************************************************************/
+void setFPGAValveBloodVenousPWM( U16 count )
+{
+ fpgaActuatorSetPoints.VBVPWMFixed = count;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveBloodVenousPWM function returns the PWM of VBV in counts.
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: none
+ * @return returns the PWM of VBV in counts
+ *************************************************************************/
+U16 getFPGAValveBloodVenousPWM( void )
+{
+ return fpgaSensorReadings.VBVPWMTarget;
+}
+#endif
+
+/*********************************************************************//**
+ * @brief
+ * The setValveBloodArterialPosition function sets the position of VBA
+ * in counts
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param setPoint : Next position of the valve in counts
+ * @return none
+ *************************************************************************/
+void setFPGAValveBloodArterialPosition( S16 setPoint )
+{
+ fpgaActuatorSetPoints.VBASetPoint = setPoint;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getValveBloodArterialPosition function reads the current position
+ * of VBA in counts
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return The current position of VBA
+ *************************************************************************/
+S16 getFPGAValveBloodArterialPosition( void )
+{
+ return fpgaSensorReadings.VBAPosition;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveBloodArterialCurrentCounts function reads the current
+ * of VBA in counts
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return The current of VBA
+ *************************************************************************/
+U16 getFPGAValveBloodArterialCurrentCounts( void )
+{
+ return fpgaSensorReadings.VBACurrent;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGABoardTemperature function reads the FPGA board temperature.
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return Current FPGA board temperature
+ *************************************************************************/
+U16 getFPGABoardTemperature( void )
+{
+ return fpgaSensorReadings.fpgaTemperature;
+}
+
+/*********************************************************************//**
+ * The getFPGAFrontDoorStatus function returns the FPGA front door status
+ * bit.
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return front door FPGA status bit
+ *************************************************************************/
+U16 getFPGAFrontDoorStatus( void )
+{
+ return 0;//( fpgaSensorReadings.fpgaGPIO & FRONT_DOOR_SWITCH_MASK );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAPBAADCTemperature function reads the PBA ADC temperature.
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return PBA ADC temperature
+ *************************************************************************/
+U32 getFPGAPBAADCTemperature( void )
+{
+ return fpgaSensorReadings.adc1Channel1;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAInletFan1TogglePeriod function reads the inlet fan 1 pulse time.
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return Inlet fan 1 pulse time
+ *************************************************************************/
+U16 getFPGAInletFan1TogglePeriod( void )
+{
+ return fpgaSensorReadings.fan1PulseTime;
+}
+
+/*********************************************************************//**
+ * The getFPGAPumpTrackSwitchStatus function returns the FPGA pump track
+ * switch status bit.
+ * @details Inputs: none
+ * @details Outputs: fpgaSensorReadings
+ * @return pump track switch FPGA status bit
+ *************************************************************************/
+U16 getFPGAPumpTrackSwitchStatus( void )
+{
+ return 0;//( fpgaSensorReadings.fpgaGPIO & PUMP_TRACK_SWITCH_MASK );
+}
+
+#ifndef _RELEASE_
+/*********************************************************************//**
+ * @brief
+ * The getHardwareConfigStatus function returns the status of the hardware
+ * configuration.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return status of the hardware configuration
+ *************************************************************************/
+HARDWARE_CONFIG_T getHardwareConfigStatus( void )
+{
+ HARDWARE_CONFIG_T configValue = (HARDWARE_CONFIG_T)fpgaSensorReadings.fpgaHWConfigReg;
+
+ return configValue;
+}
+#endif
+
+#ifdef DEBUG_ENABLED
+/*********************************************************************//**
+ * @brief
+ * The setFPGAValveBloodArterialPWM function sets a PWM for VBA in counts.
+ * @details Inputs: fpgaActuatorSetPoints
+ * @details Outputs: fpgaActuatorSetPoints
+ * @param count which is the PWM of VBA in counts
+ * @return none
+ *************************************************************************/
+void setFPGAValveBloodArterialPWM( U16 count )
+{
+ fpgaActuatorSetPoints.VBAPWMFixed = count;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAValveBloodArterialPWM function returns the current PWM of
+ * VBA in counts.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return current PWM of VBA in counts
+ *************************************************************************/
+U16 getFPGAValveBloodArterialPWM( void )
+{
+ return fpgaSensorReadings.VBAPWMTarget;
+}
+#endif
+
+/*********************************************************************//**
+ * @brief
+ * The checkFPGACommFailure function increments the FPGA comm failure
+ * windowed timer and returns whether or not the number of failures in
+ * the window have been reached.
+ * @details Inputs: ms counter
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+void checkFPGACommFailure( void )
+{
+ if ( getMSTimerCount() > MIN_POWER_ON_TIME_FOR_COMM_FAILS )
+ {
+ if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES ) )
+ {
+ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.errorCountProcessor )
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The checkFPGAFEOEFailure function increments the FPGA comm failure
+ * windowed timer if an FE or OE error has occurred and returns whether
+ * or not the number of failures in
+ * the window have been reached.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return TRUE if windowed count exceeded, else false.
+ *************************************************************************/
+BOOL checkFPGAFEOEFailure( void )
+{
+ BOOL status = false;
+ BOOL FPGAFEOEError = getSci2FEOEError();
+
+ if ( TRUE == FPGAFEOEError)
+ {
+ if ( getMSTimerCount() > MIN_POWER_ON_TIME_FOR_COMM_FAILS )
+ {
+ if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES ) )
+ {
+ SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.errorCountProcessor )
+ status = TRUE;
+ }
+ }
+ }
+
+ return status;
+}
+
+/**@}*/
Index: firmware/App/Services/FpgaTD.h
===================================================================
diff -u
--- firmware/App/Services/FpgaTD.h (revision 0)
+++ firmware/App/Services/FpgaTD.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,161 @@
+/**************************************************************************
+*
+* Copyright (c) 2019-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file FPGA.h
+*
+* @author (last) Sean Nash
+* @date (last) 05-Sep-2023
+*
+* @author (original) Dara Navaei
+* @date (original) 05-Nov-2019
+*
+***************************************************************************/
+
+#ifndef __FPGA_TD_H__
+#define __FPGA_TD_H__
+
+#include "TDCommon.h"
+#include "Interrupts.h"
+
+
+/**
+ * @defgroup FpgaTD FpgaTD
+ * @brief FPGA service module for TD firmware.
+ * The FPGA module contains get/set functions for the TD FPGA registers.
+ *
+ * @addtogroup FpgaTD
+ * @{
+ */
+
+// ********** public definitions **********
+
+// ********** public function prototypes **********
+
+void initFpgaTD( void );
+SELF_TEST_STATUS_T execFPGATest( void );
+void execFPGAClockSpeedTest( void );
+void checkFPGACommFailure( void );
+BOOL checkFPGAFEOEFailure( void );
+U16 getFPGATimerCount( void );
+
+void getFPGAVersions( U08 *Id, U08 *Maj, U08 *Min, U08 *Lab );
+U16 getFPGATemperature( void );
+F32 getFPGAVcc( void );
+F32 getFPGAVccAux( void );
+F32 getFPGAVpvn( void );
+
+void setAlarmAudioState( U32 state, U32 volumeLevel, U32 volumeDivider );
+
+U16 getFPGABloodPumpHallSensorCount( void );
+U08 getFPGABloodPumpHallSensorStatus( void );
+U16 getFPGADialInPumpHallSensorCount( void );
+U08 getFPGADialInPumpHallSensorStatus( void );
+U16 getFPGADialOutPumpHallSensorCount( void );
+U08 getFPGADialOutPumpHallSensorStatus( void );
+
+U32 getFPGAArterialPressure( void );
+U08 getFPGAArterialPressureReadCounter( void );
+U08 getFPGAArterialPressureErrorCounter( void );
+
+U16 getFPGADVTArterialPressure( void );
+U16 getFPGADVTArterialTemperature( void );
+U08 getFPGADVTArterialPressureReadCounter( void );
+U08 getFPGATDVTArterialPressureErrorCounter( void );
+
+U16 getFPGAVenousPressure( void );
+U16 getFPGAVenousPressureTemperature( void );
+U08 getFPGAVenousPressureReadCounter( void );
+U08 getFPGAVenousPressureErrorCounter( void );
+U16 getFPGABloodPumpOcclusion( void );
+U08 getFPGABloodPumpOcclusionReadCounter( void );
+U08 getFPGABloodPumpOcclusionErrorCounter( void );
+
+void setFPGASyringePumpControlFlags( U08 bitFlags );
+void setFPGASyringePumpADCandDACControlFlags( U08 bitFlags );
+void setFPGASyringePumpDACOutputLevel( U16 counts );
+void setFPGASyringePumpStepToggleTime( U32 microSeconds );
+U08 getFPGASyringePumpStatus( void );
+U08 getFPGASyringePumpADCReadCounter( void );
+U08 getFPGASyringePumpADCandDACStatus( void );
+U08 getFPGASyringePumpEncoderStatus( void );
+U32 getFPGASyringePumpEncoderPosition( void );
+U16 getFPGASyringePumpADCChannel0( void );
+U16 getFPGASyringePumpADCChannel1( void );
+U16 getFPGASyringePumpADCChannel2( void );
+U16 getFPGASyringePumpADCChannel3( void );
+U08 getFPGASyringePumpDACStatus( void );
+U16 getFPGASyringePumpDACSetting( void );
+U16 getFPGASyringePumpDACStoredSetting( void );
+
+void getFPGAAccelAxes( S16 *x, S16 *y, S16 *z );
+void getFPGAAccelMaxes( S16 *xm, S16*ym, S16*zm );
+void getFPGAAccelStatus( U16 *cnt, U16 *accelFPGAFaultReg );
+
+F32 getFPGABackupAlarmAudioCurrent( void );
+
+void getFPGAAirTrapLevels( BOOL *airAtLower, BOOL *airAtUpper );
+
+void setFPGAValvesControlMode( U16 bits );
+U16 getFPGAValvesStatus( void );
+
+BOOL noFPGAFluidLeakDetected( void );
+
+U08 getFPGABloodLeakStatus( void );
+
+void setFPGABloodLeakUARTControl( U08 value );
+void setFPGABloodLeakUARTTransmit( U08 value );
+
+U08 getFPGABloodLeakTxFIFOCount( void );
+U16 getFPGABloodLeakRxFIFOCount( void );
+U08 getFPGABloodLeakRxErrorCount( void );
+U08 getFPGABloodLeakRxFIFODataOut( void );
+
+BOOL noFPGABubbleDetected( U32 bubble );
+void setFPGABubbleSelfTest( U32 bubble );
+void clearFPGABubbleSelfTest( U32 bubble );
+
+void setFPGAValveDialyzerInletPosition( S16 setPoint );
+S16 getFPGAValveDialyzerInletPosition( void );
+U16 getFPGAValveDialyzerInletCurrentCounts( void );
+
+void setFPGAValveDialyzerOutletPosition( S16 setPoint );
+S16 getFPGAValveDialyzerOutletPosition( void );
+U16 getFPGAValveDialyzerOutletCurrentCounts( void );
+
+void setFPGAValveBloodVenousPosition( S16 setPoint );
+S16 getFPGAValveBloodVenousPosition( void );
+U16 getFPGAValveBloodVenousCurrentCounts( void );
+
+void setFPGAValveBloodArterialPosition( S16 setPoint );
+S16 getFPGAValveBloodArterialPosition( void );
+U16 getFPGAValveBloodArterialCurrentCounts( void );
+U16 getFPGABoardTemperature( void );
+U32 getFPGAPBAADCTemperature( void );
+U16 getFPGAInletFan1TogglePeriod( void );
+
+U16 getFPGAFrontDoorStatus( void );
+U16 getFPGAPumpTrackSwitchStatus( void );
+
+#ifndef _RELEASE_
+HARDWARE_CONFIG_T getHardwareConfigStatus( void );
+#endif
+
+// The PWM functions are only used during debugging
+#ifdef DEBUG_ENABLED
+ void setFPGAValveDialyzerInletPWM( U16 count );
+ U16 getFPGAValveDialyzerInletPWM( void );
+ void setFPGAValveDialyzerOutletPWM( U16 count );
+ U16 getFPGAValveDialyzerOutletPWM( void );
+ void setFPGAValveBloodVenousPWM( U16 count );
+ U16 getFPGAValveBloodVenousPWM( void );
+ void setFPGAValveBloodArterialPWM( U16 count );
+ U16 getFPGAValveBloodArterialPWM( void );
+#endif
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/Interrupts.c
===================================================================
diff -u
--- firmware/App/Services/Interrupts.c (revision 0)
+++ firmware/App/Services/Interrupts.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,292 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file Interrupts.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include
+#include "can.h"
+#include "het.h"
+#include "rti.h"
+#include "sci.h"
+#include "sys_dma.h"
+
+#include "TDCommon.h"
+//#include "BloodFlow.h"
+#include "Comm.h"
+#include "Interrupts.h"
+//#include "FPGA.h"
+#include "SystemComm.h"
+#include "TaskGeneral.h"
+#include "TaskPriority.h"
+#include "TaskTimer.h"
+#include "Utilities.h"
+
+/**
+ * @addtogroup Interrupts
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define MAX_COMM_ERRORS 5 ///< Maximum number of a given comm error for a given time window.
+#define COMM_ERROR_TIME_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< Time window for comm error counts.
+
+#define HET1_EDGE_BP_ROTOR_HALL_SENSOR 0 ///< HET1 edge detector associated with blood pump rotor hall sensor.
+#define HET1_EDGE_DPO_ROTOR_HALL_SENSOR 1 ///< HET1 edge detector associated with dialysate outlet pump rotor hall sensor.
+#define HET1_EDGE_DPI_ROTOR_HALL_SENSOR 2 ///< HET1 edge detector associated with dialysate inlet pump rotor hall sensor.
+
+// ********** private data **********
+
+static BOOL sci2FEOEError = FALSE; ///< FPGA serial frame or overrun flag;
+
+static U32 can1WarningCnt = 0; ///< CAN warning mode counter.
+static U32 can1BusOffCnt = 0; ///< CAN buss off mode counter.
+static U32 can1ParityCnt = 0; ///< CAN parity error counter.
+
+// ********** private function prototypes **********
+
+/*********************************************************************//**
+ * @brief
+ * The initInterrupts function initializes the Interrupts module.
+ * @details Inputs: none
+ * @details Outputs: Interrupts module initialized.
+ * @return none
+ *************************************************************************/
+void initInterrupts( void )
+{
+ // Initialize various time windowed counts for monitoring CAN & UART errors and warnings
+ initTimeWindowedCount( TIME_WINDOWED_COUNT_CAN_OFF, MAX_COMM_ERRORS, COMM_ERROR_TIME_WINDOW_MS );
+ initTimeWindowedCount( TIME_WINDOWED_COUNT_CAN_PARITY, MAX_COMM_ERRORS, COMM_ERROR_TIME_WINDOW_MS );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The phantomInterrupt function handles phantom interrupts.
+ * @details Inputs: none
+ * @details Outputs: phantom interrupt handled.
+ * @return none
+ *************************************************************************/
+void phantomInterrupt(void)
+{
+// SET_ALARM_WITH_1_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_PHANTOM_INTERRUPT )
+}
+
+/*********************************************************************//**
+ * @brief
+ * The rtiNotification function handles real-time interrupt notifications.
+ * @details Inputs: none
+ * @details Outputs: RTI notification handled.
+ * @param notification Which RTI timer caused this interrupt
+ * @return none
+ *************************************************************************/
+void rtiNotification(uint32 notification)
+{
+ switch ( notification )
+ {
+ case rtiNOTIFICATION_COMPARE0:
+ taskTimer();
+ break;
+
+ case rtiNOTIFICATION_COMPARE1:
+ taskPriority();
+ break;
+
+ case rtiNOTIFICATION_COMPARE2:
+ // Do nothing - unused at this time
+ break;
+
+ case rtiNOTIFICATION_COMPARE3:
+ taskGeneral();
+ break;
+
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_INVALID_RTI_NOTIFICATION, notification )
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The canMessageNotification function handles CAN message notifications.
+ * @details Inputs: none
+ * @details Outputs: CAN message notification handled.
+ * @param node which CAN controller
+ * @param messageBox which message box triggered the message notification
+ * @return none
+ *************************************************************************/
+void canMessageNotification(canBASE_t *node, uint32 messageBox)
+{
+ if ( node == canREG1 )
+ {
+ handleCANMsgInterrupt( (CAN_MESSAGE_BOX_T)messageBox );
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The canErrorNotification function handles CAN error notifications.
+ * @details Inputs: none
+ * @details Outputs: CAN error notification handled.
+ * @param node which CAN controller
+ * @param notification canLEVEL_PASSIVE (0x20) : When RX- or TX error counter are between 32 and 63
+ * canLEVEL_WARNING (0x40) : When RX- or TX error counter are between 64 and 127
+ * canLEVEL_BUS_OFF (0x80) : When RX- or TX error counter are between 128 and 255
+ * canLEVEL_PARITY_ERR (0x100): When parity error detected on CAN RAM read access
+ * @return none
+ *************************************************************************/
+void canErrorNotification(canBASE_t *node, uint32 notification)
+{
+ if ( node == canREG1 )
+ {
+ // Parity error - message RAM is corrupted
+ if ( notification & canLEVEL_PARITY_ERR )
+ {
+ can1ParityCnt++;
+ if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_CAN_PARITY ) )
+ {
+// SET_ALARM_WITH_1_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_CAN_PARITY_ERROR )
+ }
+ }
+ // Bus off - our transmitter has counted 255+ errors
+ else if ( notification & canLEVEL_BUS_OFF )
+ {
+ can1BusOffCnt++;
+ if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_CAN_OFF ) )
+ {
+// SET_ALARM_WITH_1_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_CAN_OFF_ERROR )
+ }
+ }
+ // Warning - our transmitter has counted 96+ errors
+ else if ( notification & canLEVEL_WARNING )
+ {
+ can1WarningCnt++;
+ }
+ else
+ {
+ // Ignore other notifications - unhandled
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The sciNotification function handles UART communication error interrupts.
+ * Frame and Over-run errors are handled.
+ * @details Inputs: none
+ * @details Outputs: UART error interrupts handled.
+ * @param sci Pointer to the SCI peripheral that detected the error
+ * @param flags error flag(s)
+ * @return none
+ *************************************************************************/
+void sciNotification(sciBASE_t *sci, uint32 flags)
+{
+#ifndef _VECTORCAST_
+ // Cannot set the pointers to be equal in VectorCAST. Can define pointers but the user does not have any control on the address of it
+ if ( sci == scilinREG )
+#endif
+ {
+ if ( ( flags & SCI_FE_INT ) != 0 )
+ {
+ sci2FEOEError = TRUE;
+ scilinREG->FLR |= SCI_FE_INT;
+ }
+
+ if ( ( flags & SCI_OE_INT ) != 0 )
+ {
+ sci2FEOEError = TRUE;
+ scilinREG->FLR |= SCI_OE_INT;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The dmaGroupANotification function handles communication DMA interrupts.
+ * @details Inputs: none
+ * @details Outputs: DMA interrupt is handled.
+ * @param inttype type of DMA interrupt
+ * @param channel DMA channel that caused the interrupt
+ * @return none
+ *************************************************************************/
+void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
+{
+ if ( inttype == BTC ) // Block transfer completed interrupt
+ {
+ switch ( channel )
+ {
+ case DMA_CH0: // FPGA receive channel
+ clearSCI2DMAReceiveInterrupt();
+// signalFPGAReceiptCompleted();
+ break;
+
+ case DMA_CH2: // FPGA transmit channel
+ clearSCI2DMATransmitInterrupt();
+// signalFPGATransmitCompleted();
+ break;
+
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_UNEXPECTED_DMA_INTERRUPT, channel )
+ break;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The edgeNotification function handles rotor hall sensor interrupts.
+ * @details Inputs: none
+ * @details Outputs: Rotor hall sensor interrupt is handled according to pin associated with given edge.
+ * @param hetREG HET controller associated with the edge
+ * @param edge Which edge was detected
+ * @return none
+ *************************************************************************/
+void edgeNotification(hetBASE_t * hetREG, uint32 edge)
+{
+ if ( hetREG == hetREG1 )
+ {
+ switch ( edge )
+ {
+ case HET1_EDGE_BP_ROTOR_HALL_SENSOR:
+// signalBloodPumpRotorHallSensor();
+ break;
+
+ default:
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_INTERRUPTS_INVALID_EDGE_DETECTED, edge )
+ break;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getSci2FEOEError function returns the sci2FEOEError (OE - Overrun,
+ * FE - Framing Error) status and resets the status if TRUE
+ * @details Inputs: sci2FEOEError
+ * @details Outputs: none
+ * @return sci2 FE / OE error
+ *************************************************************************/
+BOOL getSci2FEOEError( void )
+{
+ BOOL returnValue = sci2FEOEError;
+
+ if ( TRUE == returnValue )
+ {
+ sci2FEOEError = FALSE;
+ }
+
+ return returnValue;
+}
+
+/**@}*/
Index: firmware/App/Services/Interrupts.h
===================================================================
diff -u
--- firmware/App/Services/Interrupts.h (revision 0)
+++ firmware/App/Services/Interrupts.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,41 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file Interrupts.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __INTERRUPTS_H__
+#define __INTERRUPTS_H__
+
+#include "../TDCommon.h"
+
+/**
+ * @defgroup Interrupts Interrupts
+ * @brief Interrupts module handles various peripheral interrupts.
+ *
+ * @addtogroup Interrupts
+ * @{
+ */
+
+// ********** public definitions **********
+
+// ********** public function prototypes **********
+
+void initInterrupts( void );
+
+BOOL getSci2FEOEError( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/Messaging.c
===================================================================
diff -u
--- firmware/App/Services/Messaging.c (revision 0)
+++ firmware/App/Services/Messaging.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,444 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file Messaging.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include
+#include // For memcpy()
+
+#include "reg_system.h" // Used to access system register to reset processor on request
+
+#include "Compatible.h"
+#include "Messaging.h"
+#include "OperationModes.h"
+#include "Utilities.h"
+
+/**
+ * @addtogroup Messaging
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define MAX_MSGS_BLOCKED_FOR_XMIT 8 ///< Maximum number of messages to block transmission for.
+
+#pragma pack(push,1)
+/// Payload record structure for block message transmission request.
+typedef struct
+{
+ U16 blockedMessages[ MAX_MSGS_BLOCKED_FOR_XMIT ]; ///< Blocked messages.
+} BLOCKED_MSGS_DATA_T;
+#pragma pack(pop)
+
+// ********** private data **********
+
+static BOOL testerLoggedIn = FALSE; ///< Flag indicates whether an external tester (connected PC) has sent a valid login message.
+static volatile U16 nextSeqNo = 1; ///< Value of sequence number to use for next transmitted message.
+
+/// List of message IDs that are requested not to be transmitted.
+static BLOCKED_MSGS_DATA_T blockedMessagesForXmit = { 0, 0, 0, 0, 0, 0, 0, 0 };
+
+// ********** private function prototypes **********
+
+static BOOL sendTestAckResponseMsg( MSG_ID_T msgID, BOOL ack );
+static BOOL sendAckResponseMsg( MSG_ID_T msgID, COMM_BUFFER_T buffer, BOOL ack );
+static BOOL sendUIResponseMsg( MSG_ID_T msgID, BOOL accepted, U32 reason );
+static void sendInstitutionalRecordToUI( HD_INSTITUTIONAL_LOCAL_RECORD_T* instit );
+
+/*********************************************************************//**
+ * @brief
+ * The serializeMessage function serializes a given message into a given
+ * array of bytes. A sequence # is added to the message here and the ACK
+ * bit of the sequence # is set if ACK is required per parameter. A sync byte
+ * is inserted at the beginning of the message and an 8-bit CRC is appended to
+ * the end of the message. The message is queued for transmission in the given buffer.
+ * @details Inputs: blockedMessagesForXmit
+ * @details Outputs: given data array populated with serialized message data and queued for transmit.
+ * @param msg message to serialize
+ * @param buffer outgoing buffer that message should be queued in
+ * @param ackReq is an acknowledgement from receiver required?
+ * @return size (in bytes) of serialized message populated in given data array.
+ *************************************************************************/
+U32 serializeMessage( MESSAGE_T msg, COMM_BUFFER_T buffer, BOOL ackReq )
+{
+ BOOL result = 0;
+ BOOL blocked = FALSE;
+ U32 msgSize = 0;
+ U32 sizeMod, sizePad;
+ U32 i;
+ U08 crc;
+ U08 data[ MAX_ACK_MSG_SIZE ]; // Byte array to populate with message data
+
+ // Check to see if tester has requested this message not be transmited
+ if ( TRUE == isTestingActivated() )
+ {
+ U32 i;
+
+ for ( i = 0; i < MAX_MSGS_BLOCKED_FOR_XMIT; i++ )
+ {
+ if ( msg.hdr.msgID == blockedMessagesForXmit.blockedMessages[ i ] )
+ {
+ blocked = TRUE;
+ break;
+ }
+ }
+ }
+ // Serialize and queue message for transmission unless this message is blocked
+ if ( blocked != TRUE )
+ {
+ // Prefix data with message sync byte
+ data[ msgSize++ ] = MESSAGE_SYNC_BYTE;
+
+ // Set sequence # and ACK bit (unless this is an ACK to a received message)
+ if ( msg.hdr.msgID != MSG_ID_ACK_MESSAGE_THAT_REQUIRES_ACK )
+ {
+ // Thread protect next sequence # access & increment
+ _disable_IRQ();
+ msg.hdr.seqNo = nextSeqNo;
+ nextSeqNo = INC_WRAP( nextSeqNo, MIN_MSG_SEQ_NO, MAX_MSG_SEQ_NO );
+ _enable_IRQ();
+ if ( TRUE == ackReq )
+ {
+ msg.hdr.seqNo *= -1;
+ }
+ }
+
+ // Calculate message CRC
+ crc = crc8( (U08*)(&msg), sizeof( MESSAGE_HEADER_T ) + msg.hdr.payloadLen );
+
+ // Serialize message header data
+ memcpy( &data[ msgSize ], &( msg.hdr ), sizeof( MESSAGE_HEADER_T ) );
+ msgSize += sizeof( MESSAGE_HEADER_T );
+
+ // Serialize message payload (only used bytes per payloadLen field)
+ memcpy( &data[ msgSize ], &( msg.payload ), msg.hdr.payloadLen );
+ msgSize += msg.hdr.payloadLen;
+
+ // Add 8-bit CRC
+ data[ msgSize++ ] = crc;
+
+ // Pad with zero bytes to get length a multiple of CAN_MESSAGE_PAYLOAD_SIZE (8)
+ sizeMod = msgSize % CAN_MESSAGE_PAYLOAD_SIZE;
+ sizePad = ( sizeMod == 0 ? 0 : CAN_MESSAGE_PAYLOAD_SIZE - sizeMod );
+ for ( i = 0; i < sizePad; i++ )
+ {
+ data[ msgSize++ ] = 0;
+ }
+
+#ifndef _RELEASE_
+// if ( getSoftwareConfigStatus( SW_CONFIG_DISABLE_ACK_ERRORS ) != SW_CONFIG_ENABLE_VALUE )
+#endif
+ {
+ // If ACK required, add to pending ACK list
+ if ( TRUE == ackReq )
+ {
+ if ( FALSE == addMsgToPendingACKList( &msg, buffer, data, msgSize ) )
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_MSG_PENDING_ACK_LIST_FULL, (U32)(msg.hdr.msgID) )
+ }
+ }
+ }
+
+ // Add serialized message data to appropriate out-going comm buffer
+ result = addToCommBuffer( buffer, data, msgSize );
+ }
+ else
+ {
+ result = TRUE; // If message blocked, return successful transmission
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The sendACKMsg function constructs and queues for transmit an ACK message
+ * for a given received message.
+ * @details Inputs: none
+ * @details Outputs: ACK message queued for transmit on broadcast CAN channel.
+ * @param message message to send an ACK for
+ * @return TRUE if ACK message queued successfully, FALSE if not
+ *************************************************************************/
+BOOL sendACKMsg( MESSAGE_T *message )
+{
+ BOOL result;
+ MESSAGE_T msg;
+
+ // Create a message record
+ blankMessage( &msg );
+ // Send ACK back with same seq. #, but w/o ACK bit
+ msg.hdr.seqNo = message->hdr.seqNo * -1;
+ // ACK messages always have this ID
+ msg.hdr.msgID = MSG_ID_ACK_MESSAGE_THAT_REQUIRES_ACK;
+ // ACK messages always have no payload
+ msg.hdr.payloadLen = 0;
+
+ // Serialize and queue the message for transmit on broadcast channel
+ result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_TD_BROADCAST, ACK_NOT_REQUIRED );
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The sendAckResponseMsg function constructs a simple response
+ * message for a handled message and queues it for transmit on the
+ * appropriate CAN channel.
+ * @details Inputs: none
+ * @details Outputs: response message constructed and queued for transmit.
+ * @param msgID ID of handled message that we are responding to
+ * @param buffer outgoing buffer that message should be queued in
+ * @param ack TRUE if test message was handled successfully, FALSE if not
+ * @return TRUE if response message successfully queued for transmit, FALSE if not
+ *************************************************************************/
+static BOOL sendAckResponseMsg( MSG_ID_T msgID, COMM_BUFFER_T buffer, BOOL ack )
+{
+ BOOL result;
+ MESSAGE_T msg;
+ ACK_RESPONSE_PAYLOAD_T cmd;
+
+ cmd.acknowledgement = ack;
+
+ // Create a message record
+ blankMessage( &msg );
+ msg.hdr.msgID = msgID;
+ msg.hdr.payloadLen = sizeof( ACK_RESPONSE_PAYLOAD_T );
+ memcpy( &msg.payload, &cmd, sizeof( ACK_RESPONSE_PAYLOAD_T ) );
+
+ // Serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+ result = serializeMessage( msg, buffer, ACK_NOT_REQUIRED );
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The sendUIResponseMsg function constructs an UI response message for a
+ * handled UI message and queues it for transmit on the appropriate CAN channel.
+ * @details Inputs: none
+ * @details Outputs: response message constructed and queued for transmit.
+ * @param msgID ID of handled message that we are responding to
+ * @param accepted T/F - request accepted?
+ * @param reason reason code if rejected
+ * @return TRUE if response message successfully queued for transmit, FALSE if not
+ *************************************************************************/
+static BOOL sendUIResponseMsg( MSG_ID_T msgID, BOOL accepted, U32 reason )
+{
+ BOOL result;
+ MESSAGE_T msg;
+ UI_RESPONSE_PAYLOAD_T cmd;
+
+ cmd.accepted = accepted;
+ cmd.rejectionReason = reason;
+
+ // Create a message record
+ blankMessage( &msg );
+ msg.hdr.msgID = msgID;
+ msg.hdr.payloadLen = sizeof( UI_RESPONSE_PAYLOAD_T );
+ memcpy( &msg.payload, &cmd, sizeof( UI_RESPONSE_PAYLOAD_T ) );
+
+ // Serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+ result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_TD_2_UI, ACK_REQUIRED );
+
+ return result;
+}
+
+
+// ***********************************************************************
+// ***************** Message Sending Helper Functions ********************
+// ***********************************************************************
+
+
+/*********************************************************************//**
+ * @brief
+ * The sendInstitutionalRecordToUI function sends the institutional record to UI
+ * @details Inputs: none
+ * @details Outputs: none
+ * @param instit a pointer to the local institutional recored in the system
+ * messages that is without calibration time and crc
+ * @return none
+ *************************************************************************/
+static void sendInstitutionalRecordToUI( HD_INSTITUTIONAL_LOCAL_RECORD_T* instit )
+{
+ MESSAGE_T msg;
+
+ U08 *payloadPtr = msg.payload;
+ U32 accept = 1;
+ U32 reason = 0;
+
+ // Create a message record
+ blankMessage( &msg );
+ msg.hdr.msgID = MSG_ID_HD_INSTITUTIONAL_RECORD_RESPONSE;
+ msg.hdr.payloadLen = sizeof( U32 ) + sizeof( U32 ) + sizeof( HD_INSTITUTIONAL_LOCAL_RECORD_T );
+
+ memcpy( payloadPtr, &accept, sizeof( U32 ) );
+ payloadPtr += sizeof( U32 );
+ memcpy( payloadPtr, &reason, sizeof( U32 ) );
+ payloadPtr += sizeof( U32 );
+ memcpy( payloadPtr, instit, sizeof( HD_INSTITUTIONAL_LOCAL_RECORD_T ) );
+
+ // Serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+ serializeMessage( msg, COMM_BUFFER_OUT_CAN_TD_2_UI, ACK_NOT_REQUIRED );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handleUITDResetInServiceModeRequest function handles the UI request
+ * to reset HD in service mode
+ * @details Inputs: none
+ * @details Outputs: none
+ * @param message a pointer to the message to handle
+ * @return none
+ *************************************************************************/
+void handleUITDResetInServiceModeRequest( MESSAGE_T* message )
+{
+ // Verify payload length
+ if ( ( 0 == message->hdr.payloadLen ) && ( MODE_SERV == getCurrentOperationMode() ) )
+ {
+#ifndef _VECTORCAST_
+ systemREG1->SYSECR = (0x2) << 14; // Reset processor
+#endif
+ }
+
+ // Respond to request
+ sendAckResponseMsg( (MSG_ID_T)message->hdr.msgID, COMM_BUFFER_OUT_CAN_TD_2_UI, FALSE );
+}
+
+
+/*************************************************************************
+ * TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/*********************************************************************//**
+ * @brief
+ * The isTestingActivated function determines whether a tester has successfully
+ * logged in to activate testing functionality.
+ * @details Inputs: testerLoggedIn
+ * @details Outputs: none
+ * @return TRUE if a tester has logged in to activate testing, FALSE if not
+ *************************************************************************/
+BOOL isTestingActivated( void )
+{
+ return testerLoggedIn;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setTesterStatusToLoggedOut function sets the status of the tester to
+ * logged out.
+ * @details Inputs: none
+ * @details Outputs: testerLoggedIn
+ * @return none
+ *************************************************************************/
+void setTesterStatusToLoggedOut( void )
+{
+ testerLoggedIn = FALSE;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The sendTestAckResponseMsg function constructs a simple response
+ * message for a handled test message and queues it for transmit on the
+ * appropriate UART channel.
+ * @details Inputs: none
+ * @details Outputs: response message constructed and queued for transmit.
+ * @param msgID ID of handled message that we are responding to
+ * @param ack TRUE if test message was handled successfully, FALSE if not
+ * @return TRUE if response message successfully queued for transmit, FALSE if not
+ *************************************************************************/
+static BOOL sendTestAckResponseMsg( MSG_ID_T msgID, BOOL ack )
+{
+ BOOL result;
+ MESSAGE_T msg;
+
+ // Create a message record
+ blankMessage( &msg );
+ msg.hdr.msgID = msgID;
+ msg.hdr.payloadLen = sizeof( U08 );
+ msg.payload[ 0 ] = (U08)ack;
+
+ // Serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+ result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_PC, ACK_NOT_REQUIRED );
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The sendEvent function constructs an TD event message to the UI and
+ * queues the msg for transmit on the appropriate CAN channel.
+ * @details Inputs: none
+ * @details Outputs: TD event msg constructed and queued.
+ * @param event Enumeration of event type that occurred
+ * @param dat1 First data associated with event
+ * @param dat2 Second data associated with event
+ * @return TRUE if msg successfully queued for transmit, FALSE if not
+ *************************************************************************/
+BOOL sendEvent( TD_EVENT_ID_T event, EVENT_DATA_T dat1, EVENT_DATA_T dat2 )
+{
+ BOOL result;
+ MESSAGE_T msg;
+ EVENT_PAYLOAD_T eventStruct;
+
+ eventStruct.event = (U32)event;
+ eventStruct.dataType1 = (U32)dat1.dataType;
+ eventStruct.data1 = dat1.data;
+ eventStruct.dataType2 = (U32)dat2.dataType;
+ eventStruct.data2 = dat2.data;
+
+ // Create a message record
+ blankMessage( &msg );
+ msg.hdr.msgID = MSG_ID_HD_EVENT;
+ // The payload length is the event ID, 2 event datas and the events data types for each of the event data
+ msg.hdr.payloadLen = sizeof( EVENT_PAYLOAD_T );
+
+ memcpy( &msg.payload, &eventStruct, sizeof( EVENT_PAYLOAD_T ) );
+
+ // Serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+ result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_TD_2_UI, ACK_NOT_REQUIRED );
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The handleTesterLogInRequest function handles a request to login as a
+ * tester.
+ * @details Inputs: none
+ * @details Outputs: message handled
+ * @param message a pointer to the message to handle
+ * @return none
+ *************************************************************************/
+void handleTesterLogInRequest( MESSAGE_T *message )
+{
+ // Verify pass code
+ // TODO - placeholder - how do we want to authenticate tester?
+ if ( ( 3 == message->hdr.payloadLen ) && ( 0x31 == message->payload[ 0 ] ) && ( 0x32 == message->payload[ 1 ] ) && ( 0x33 == message->payload[ 2 ] ) )
+ {
+ testerLoggedIn = TRUE;
+ checkInFromUI(); // Allow tasks to begin normal processing when tester has logged in
+ // Set the dialin checkin time stamp until the first checkin message is received from dailin
+ setDialinCheckInTimeStamp();
+ }
+ else
+ {
+ testerLoggedIn = FALSE;
+ }
+ // Respond to would be tester
+ sendTestAckResponseMsg( (MSG_ID_T)message->hdr.msgID, testerLoggedIn );
+}
+
+/**@}*/
Index: firmware/App/Services/Messaging.h
===================================================================
diff -u
--- firmware/App/Services/Messaging.h (revision 0)
+++ firmware/App/Services/Messaging.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,163 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file Messaging.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __MESSAGING_H__
+#define __MESSAGING_H__
+
+#include "TDCommon.h"
+#include "TDDefs.h"
+#include "MessageSupport.h"
+#include "MsgQueues.h"
+
+/**
+ * @defgroup Messaging Messaging
+ * @brief The system communication messages module provides helper functions
+ * for sending outgoing system message and handling incoming system messages.
+ *
+ * @addtogroup Messaging
+ * @{
+ */
+
+// ********** public definitions **********
+
+#define ACK_REQUIRED TRUE ///< Macro for functions that want to know if an outgoing message requires acknowledgement from receiver.
+#define ACK_NOT_REQUIRED FALSE ///< Macro for functions that want to know if an outgoing message requires acknowledgement from receiver.
+
+#pragma pack(push, 1)
+/// Payload record structure for ACK response.
+typedef struct
+{
+ U08 acknowledgement; ///< Acknowledgement Byte
+} ACK_RESPONSE_PAYLOAD_T;
+
+/// Payload record structure for off button response.
+typedef struct
+{
+ U08 userRequest; ///< request to confirm, cancel, or reject off button request
+} UI_OFF_BUTTON_RESPONSE_PAYLOAD_T;
+#pragma pack(pop)
+
+/// Payload record structure for UI response.
+typedef struct
+{
+ BOOL accepted; ///< Accepted/Rejected
+ U32 rejectionReason; ///< Rejection reason if not accepted.
+} UI_RESPONSE_PAYLOAD_T;
+
+/// Payload record structure for UF change response.
+typedef struct
+{
+ BOOL accepted; ///< Accepted/Rejected
+ U32 rejectionReason; ///< Rejection reason if not accepted.
+ F32 ufVolume; ///< UF Volume in mL.
+ U32 durationInMinutes; ///< new Treatment duration in minutes.
+ S32 timeDiff; ///< Treatment duration difference.
+ F32 ufRate; ///< new UF rate in mL/min.
+ F32 rateDiff; ///< difference between new and old UF rates.
+ F32 oldUFRate; ///< Previous UF Rate in mL/min.
+} UF_SETTINGS_CHANGE_RESPONSE_PAYLOAD_T;
+
+/// Payload record structure for UF change confirmation response.
+typedef struct
+{
+ BOOL accepted; ///< Accepted/Rejected
+ U32 rejectionReason; ///< Rejection reason if not accepted.
+ F32 volume; ///< UF Volume in mL.
+ U32 duration; ///< Treatment duration in minutes
+ F32 ufRate; ///< UF rate in mL.
+} UF_SETTINGS_CONFIRMATION_RESPONSE_PAYLOAD_T;
+
+/// Payload record structure for treatment duration change response.
+typedef struct
+{
+ BOOL accepted; ///< Accepted/Rejected
+ U32 rejectionReason; ///< Rejection reason if not accepted.
+ U32 duration; ///< Treatment duration in minutes
+ F32 volume; ///< UF Volume in mL.
+} TREATMENT_TIME_CHANGE_RESPONSE_PAYLOAD_T;
+
+/// Payload record structure for blood / dialysate rate change response.
+typedef struct
+{
+ BOOL accepted; ///< Accepted/Rejected
+ U32 rejectionReason; ///< Rejection reason if not accepted.
+ U32 bloodRate; ///< new blood flow rate
+ U32 dialRate; ///< new dialysate flow rate
+} BLOOD_DIAL_RATE_CHANGE_RESPONSE_PAYLOAD_T;
+
+/// Payload record structure for treatment parameter broadcast messages.
+typedef struct
+{
+ U32 minTreatmentTime; ///< Minimum treatment duration (in minutes)
+ U32 maxTreatmentTime; ///< Maximum treatment duration (in minutes)
+ F32 minUFVolume; ///< Minimum ultrafiltration volume (in mL)
+ F32 maxUFVolume; ///< Maximum ultrafiltration volume (in mL)
+ U32 minDialRate; ///< Minimum dialysate flow rate (in mL/min)
+ U32 maxDialRate; ///< Maximum dialysate flow rate (in mL/min)
+} TREATMENT_PARAM_BROADCAST_PAYLOAD_T;
+
+typedef struct
+{
+ U32 minBloodFlowMLPM; ///< Min blood flow in mL/min.
+ U32 maxBloodFlowMLPM; ///< Max blood flow in mL/min.
+ U32 minDialysateFlowMLPM; ///< Min dialysate flow in mL/min.
+ U32 maxDialysateFlowMLPM; ///< Max dialysate flow in mL/min.
+ U32 minTxDurationMIN; ///< Min treatment duration in minutes.
+ U32 maxTxDurationMIN; ///< Max treatment duration in minutes.
+ U32 minStopHeparinDispBeforeTxEndMIN; ///< Min stop heparin dispense before treatment end in minutes.
+ U32 maxStopHeparinDispBeforeTxEndMIN; ///< Max stop heparin dispense before treatment end in minutes.
+ U32 minSalineBolusVolumeML; ///< Min saline bolus volume in milliliters.
+ U32 maxSalineBolusVolumeML; ///< Max saline bolus volume in milliliters.
+ F32 minDialysateTempC; ///< Min dialysate temperature in C.
+ F32 maxDialysateTempC; ///< Max dialysate temperature in C.
+ S32 minArtPressLimitWindowMMHG; ///< Min arterial pressure limit window in mmHg.
+ S32 maxArtPressLimitWindowMMHG; ///< Max arterial pressure limit window in mmHg.
+ S32 minVenPressLimitWindowMMHG; ///< Min venous pressure limit window in mmHg.
+ S32 maxVenPressLimitWindowMMHG; ///< Max venous pressure limit window in mmHg.
+ S32 minVenAsymPressLimitMMHG; ///< Min venous asymmetric pressure limit in mmHg.
+ S32 maxVenAsymPressLimitMMHG; ///< Max venous asymmetric pressure limit in mmHg.
+ F32 minUFVolumeL; ///< Min ultrafiltration volume in mL.
+ F32 maxUFVolumeL; ///< Max ultrafiltration volume in mL.
+ F32 minHeparinDispRateMLPHR; ///< Min heparin dispense rate in mL/hr.
+ F32 maxHeparinDispRateMLPHR; ///< Max heparin dispense rate in mL/hr.
+ F32 minHeparinBolusVolumeML; ///< Min heparin bolus volume in mL.
+ F32 maxHeparinBolusVolumeML; ///< Max heparin bolus volume in mL.
+ U32 enableChemicalDisinfect; ///< Enable/disable chemical disinfect.
+} HD_INSTITUTIONAL_LOCAL_RECORD_T;
+
+// ********** public function prototypes **********
+
+// Serialize message
+U32 serializeMessage( MESSAGE_T msg, COMM_BUFFER_T buffer, BOOL ackReq );
+
+// ACK MSG
+BOOL sendACKMsg( MESSAGE_T *message );
+
+void handleUITDResetInServiceModeRequest( MESSAGE_T* message );
+
+// Test Support Messaging Functions **************************
+
+BOOL isTestingActivated( void );
+void setTesterStatusToLoggedOut( void );
+
+BOOL sendEvent( TD_EVENT_ID_T event, EVENT_DATA_T dat1, EVENT_DATA_T dat2 );
+
+void handleTesterLogInRequest( MESSAGE_T *message );
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/MsgQueues.c
===================================================================
diff -u
--- firmware/App/Services/MsgQueues.c (revision 0)
+++ firmware/App/Services/MsgQueues.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,244 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file MsgQueues.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include "MsgQueues.h"
+
+/**
+ * @addtogroup MsgQueues
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define MAX_MSG_QUEUE_SIZE 100 ///< Number of messages a queue can hold.
+
+// ********** private data **********
+
+static U32 msgQueueCounts[ NUM_OF_MSG_QUEUES ]; ///< Number of messages in each queue.
+static U32 msgQueueStarts[ NUM_OF_MSG_QUEUES ]; ///< Starting index for each queue.
+static U32 msgQueueNexts[ NUM_OF_MSG_QUEUES ]; ///< Next index for each queue.
+static MESSAGE_WRAPPER_T msgQueues[ NUM_OF_MSG_QUEUES ][ MAX_MSG_QUEUE_SIZE ]; ///< The messages in each queue.
+
+// ********** private function prototypes **********
+
+/*********************************************************************//**
+ * @brief
+ * The initMsgQueues function initializes the MsgQueues module.
+ * @details Inputs: none
+ * @details Outputs: msgQueueCounts[], msgQueueStarts[], msgQueueNexts[], msgQueues[][]
+ * @return none
+ *************************************************************************/
+void initMsgQueues( void )
+{
+ U32 q, m;
+
+ // Reset message queues
+ for ( q = 0; q < NUM_OF_MSG_QUEUES; q++ )
+ {
+ msgQueueCounts[ q ] = 0;
+ msgQueueStarts[ q ] = 0;
+ msgQueueNexts[ q ] = 0;
+ for ( m = 0; m < MAX_MSG_QUEUE_SIZE; m++ )
+ {
+ blankMessageInWrapper( &msgQueues[ q ][ m ] );
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The addToMsgQueue function adds a message to a given message queue.
+ * This function should only be called from the General Task.
+ * @details Inputs: none
+ * @details Outputs: message added to queue
+ * @param queue the message queue to add to
+ * @param msg a pointer to a message structure to add to the queue
+ * @return TRUE if message added to queue, FALSE if could not
+ *************************************************************************/
+BOOL addToMsgQueue( MSG_QUEUE_T queue, MESSAGE_WRAPPER_T *msg )
+{
+ BOOL result = FALSE;
+
+ // Verify given message queue
+ if ( queue < NUM_OF_MSG_QUEUES )
+ {
+ if ( FALSE == isMsgQueueFull( queue ) )
+ {
+ result = TRUE;
+ // Add message to queue
+ msgQueues[ queue ][ msgQueueNexts[ queue ] ] = *msg;
+ // Increment next index to add to
+ msgQueueNexts[ queue ] = INC_WRAP( msgQueueNexts[ queue ], 0, MAX_MSG_QUEUE_SIZE - 1 );
+ // Increment queue count
+ msgQueueCounts[ queue ]++;
+ }
+ else // Msg queue is full
+ {
+// SET_ALARM_WITH_1_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_ADD_QUEUE_FULL )
+ }
+ }
+ else // Invalid message queue
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_ADD_INVALID_QUEUE, queue )
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFromMsgQueue function retrieves the next message from a given
+ * message queue. This function should only be called from the General Task.
+ * @details Inputs: queue
+ * @details Outputs: message retrieved from the queue
+ * @param queue the message queue to retrieve from
+ * @param msg a pointer to a message structure to populate with the retrieved
+ * message.
+ * @return TRUE if a message was found to retrieve, FALSE if not
+ *************************************************************************/
+BOOL getFromMsgQueue( MSG_QUEUE_T queue, MESSAGE_WRAPPER_T *msg )
+{
+ BOOL result = FALSE;
+
+ // Verify given message queue
+ if ( queue < NUM_OF_MSG_QUEUES )
+ {
+ if ( FALSE == isMsgQueueEmpty( queue ) )
+ {
+ result = TRUE;
+ // Get message from queue
+ *msg = msgQueues[ queue ][ msgQueueStarts[ queue ] ];
+ // Increment queue next index to get from
+ msgQueueStarts[ queue ] = INC_WRAP( msgQueueStarts[ queue ], 0, MAX_MSG_QUEUE_SIZE - 1 );
+ // Decrement queue count
+ msgQueueCounts[ queue ]--;
+ }
+ else // Message queue is empty
+ {
+ // Result already set to FALSE
+ }
+ }
+ else // Invalid message queue
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_GET_INVALID_QUEUE, queue )
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isMsgQueueEmpty function determines whether a given message queue is empty.
+ * @details Inputs: msgQueueCounts[]
+ * @details Outputs: none
+ * @param queue the message queue to check
+ * @return TRUE if a given message queue is empty, FALSE if not
+ *************************************************************************/
+BOOL isMsgQueueEmpty( MSG_QUEUE_T queue )
+{
+ BOOL result = FALSE;
+
+ // Verify given message queue
+ if ( queue < NUM_OF_MSG_QUEUES )
+ {
+ if ( msgQueueCounts[ queue ] == 0 )
+ {
+ result = TRUE;
+ }
+ }
+ else // Invalid message queue
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_IS_EMPTY_INVALID_QUEUE, queue )
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isMsgQueueFull function determines whether a given message queue is full.
+ * @details Inputs: msgQueueCounts[]
+ * @details Outputs: none
+ * @param queue the message queue to check
+ * @return TRUE if the given message queue is full, FALSE if not
+ *************************************************************************/
+BOOL isMsgQueueFull( MSG_QUEUE_T queue )
+{
+ BOOL result = TRUE;
+
+ // Verify given message queue
+ if ( queue < NUM_OF_MSG_QUEUES )
+ {
+ if ( msgQueueCounts[ queue ] < MAX_MSG_QUEUE_SIZE )
+ {
+ result = FALSE;
+ }
+ }
+ else // Invalid message queue
+ {
+// SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_IS_FULL_INVALID_QUEUE, queue )
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The blankMessage function blanks a given message.
+ * @details Inputs: none
+ * @details Outputs: given message is blanked
+ * @param message Pointer to the message to blank
+ * @return none
+ *************************************************************************/
+void blankMessage( MESSAGE_T *message )
+{
+ U32 i;
+ U32 msgSize = sizeof(MESSAGE_T);
+ U08 *msgContent = (U08*)message;
+
+ // Zero out the message
+ for ( i = 0; i < msgSize; i++ )
+ {
+ *msgContent++ = 0x0;
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The blankMessageInWrapper function blanks a given message in a wrapper.
+ * @details Inputs: none
+ * @details Outputs: given wrapped message is blanked
+ * @param message Pointer to the message in a wrapper to blank
+ * @return none
+ *************************************************************************/
+void blankMessageInWrapper( MESSAGE_WRAPPER_T *message )
+{
+ U32 i;
+ U32 msgSize = sizeof(MESSAGE_T);
+ U08 *msgContent = (U08*)message;
+
+ // Zero out the message
+ for ( i = 0; i < msgSize; i++ )
+ {
+ *msgContent++ = 0x0;
+ }
+
+ // Set msg ID out of bounds in case blank message goes somewhere
+ message->msg.hdr.msgID = 0xFFFF;
+}
+
+/**@}*/
Index: firmware/App/Services/MsgQueues.h
===================================================================
diff -u
--- firmware/App/Services/MsgQueues.h (revision 0)
+++ firmware/App/Services/MsgQueues.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,82 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file MsgQueues.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __MSG_QUEUES_H__
+#define __MSG_QUEUES_H__
+
+#include "../TDCommon.h"
+
+/**
+ * @defgroup MsgQueues MsgQueues
+ * @brief The message queues module provides queuing services for
+ * incoming CAN messages.
+ *
+ * @addtogroup MsgQueues
+ * @{
+ */
+
+// ********** public definitions **********
+
+#define MAX_MSG_PAYLOAD_SIZE 250 ///< Bytes
+
+/// Enumeration of message queues.
+typedef enum Msg_Queues
+{
+ MSG_Q_IN = 0, ///< Incoming CAN message queue.
+ NUM_OF_MSG_QUEUES ///< Number of message queues.
+} MSG_QUEUE_T;
+
+#pragma pack(push,1)
+
+/// Record structure for message header.
+typedef struct
+{
+ S16 seqNo; ///< Sequence number (and ACK required bit) of message
+ U16 msgID; ///< ID of message
+ U08 payloadLen; ///< Length of payload in bytes
+} MESSAGE_HEADER_T;
+
+/// Record structure for a message (header + payload).
+typedef struct
+{
+ MESSAGE_HEADER_T hdr; ///< Message header
+ U08 payload[ MAX_MSG_PAYLOAD_SIZE ]; ///< Message payload
+} MESSAGE_T;
+
+/// Record structure for a wrapped message (message + CRC).
+typedef struct
+{
+ MESSAGE_T msg; ///< Message
+ U08 crc; ///< Message CRC
+} MESSAGE_WRAPPER_T;
+#pragma pack(pop)
+
+#define MESSAGE_OVERHEAD_SIZE (sizeof(MESSAGE_HEADER_T) + sizeof(U08)) ///< Byte size of a message's overhead (fixed at 6 bytes).
+
+// ********** public function prototypes **********
+
+void initMsgQueues( void );
+BOOL addToMsgQueue( MSG_QUEUE_T queue, MESSAGE_WRAPPER_T *msg );
+BOOL getFromMsgQueue( MSG_QUEUE_T queue, MESSAGE_WRAPPER_T *msg );
+BOOL isMsgQueueEmpty( MSG_QUEUE_T queue );
+BOOL isMsgQueueFull( MSG_QUEUE_T queue );
+void blankMessage( MESSAGE_T *message );
+void blankMessageInWrapper( MESSAGE_WRAPPER_T *message );
+
+/**@}*/
+
+#endif
Index: firmware/App/Services/SystemCommTD.c
===================================================================
diff -u
--- firmware/App/Services/SystemCommTD.c (revision 0)
+++ firmware/App/Services/SystemCommTD.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,459 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file SystemComm.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include
+#include // For memcpy()
+
+#include "can.h"
+#include "sci.h"
+#include "sys_dma.h"
+
+#include "Comm.h"
+#include "Interrupts.h"
+#include "OperationModes.h"
+#include "SystemCommTD.h"
+#include "Timers.h"
+#include "Utilities.h"
+
+/**
+ * @addtogroup SystemCommTD
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define UI_COMM_TIMEOUT_IN_MS 7500 ///< Maximum time (in ms) that UI is allowed to wait before checking in with HD.
+#define UI_COMM_SERVICE_MODE_TIMEOUT_IN_MS (2 * SEC_PER_MIN * MS_PER_SECOND) ///< Maximum time (in ms) that UI is allowed to wait before checking in with HD when in service mode.
+#define DG_COMM_TIMEOUT_IN_MS 1000 ///< DG has not checked in for this much time
+
+#define MAX_COMM_CRC_FAILURES 5 ///< Maximum number of CRC errors within window period before alarm
+#define MAX_COMM_CRC_FAILURE_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< CRC error window
+
+#define MAX_FPGA_CLOCK_SPEED_ERRORS 3 ///< maximum number of FPGA clock speed errors within window period before alarm
+#define MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< FPGA clock speed error window
+
+// ********** private data **********
+
+/// Array of out-going CAN buffers.
+const COMM_BUFFER_T CAN_OUT_BUFFERS[ NUM_OF_CAN_OUT_BUFFERS ] =
+{
+ COMM_BUFFER_OUT_CAN_TD_ALARM,
+ COMM_BUFFER_OUT_CAN_TD_2_DD,
+ COMM_BUFFER_OUT_CAN_TD_2_UI,
+ COMM_BUFFER_OUT_CAN_TD_BROADCAST,
+ COMM_BUFFER_OUT_CAN_PC
+};
+
+/// Array of in-coming CAN buffers.
+const COMM_BUFFER_T CAN_IN_BUFFERS[ NUM_OF_CAN_IN_BUFFERS ] =
+{
+ COMM_BUFFER_IN_CAN_DD_ALARM,
+ COMM_BUFFER_IN_CAN_RO_ALARM,
+ COMM_BUFFER_IN_CAN_UI_ALARM,
+ COMM_BUFFER_IN_CAN_DD_2_TD,
+ COMM_BUFFER_IN_CAN_UI_2_TD,
+ COMM_BUFFER_IN_CAN_DD_BROADCAST,
+ COMM_BUFFER_IN_CAN_RO_BROADCAST,
+ COMM_BUFFER_IN_CAN_UI_BROADCAST,
+ COMM_BUFFER_IN_CAN_PC,
+};
+
+static volatile BOOL tdIsOnlyCANNode = TRUE; ///< Flag indicating whether HD is alone on CAN bus.
+static volatile BOOL ddIsCommunicating = FALSE; ///< Has DD sent a message since last check
+static U32 timeOfLastDGCheckIn = 0; ///< Last time DG checked in
+static volatile BOOL uiIsCommunicating = FALSE; ///< Has UI sent a message since last check
+static U32 timeOfLastUICheckIn = 0; ///< Last time UI checked in
+static volatile BOOL uiDidCommunicate = FALSE; ///< Has UI every sent a message
+
+// ********** private function prototypes **********
+
+
+/*********************************************************************//**
+ * @brief
+ * The initSystemCommTD function initializes the SystemComm module.
+ * @details Inputs: none
+ * @details Outputs: SystemComm module initialized.
+ * @return none
+ *************************************************************************/
+void initSystemCommTD( void )
+{
+ // Initialize bad message CRC time windowed count
+ initTimeWindowedCount( TIME_WINDOWED_COUNT_BAD_MSG_CRC, MAX_COMM_CRC_FAILURES, MAX_COMM_CRC_FAILURE_WINDOW_MS );
+
+ // Initialize FPGA clock speed error time windowed count
+ initTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR, MAX_FPGA_CLOCK_SPEED_ERRORS, MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS);
+}
+
+/*********************************************************************//**
+ * @brief
+ * The checkInFromDG function checks in the DG with the HD - indicating that
+ * the DG is communicating.
+ * @details Inputs: none
+ * @details Outputs: ddIsCommunicating
+ * @return none
+ *************************************************************************/
+void checkInFromDG( void )
+{
+ ddIsCommunicating = TRUE;
+ timeOfLastDGCheckIn = getMSTimerCount();
+
+ if ( TRUE == isAlarmActive( ALARM_ID_HD_DG_COMM_TIMEOUT ) )
+ {
+ clearAlarmCondition( ALARM_ID_HD_DG_COMM_TIMEOUT );
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The checkInFromUI function checks in the UI with the HD - indicating that
+ * the UI is communicating.
+ * @details Inputs: none
+ * @details Outputs: uiIsCommunicating
+ * @return none
+ *************************************************************************/
+void checkInFromUI( void )
+{
+ if ( FALSE == uiDidCommunicate )
+ { // Start DG check-in timer when UI first communicates
+ timeOfLastDGCheckIn = getMSTimerCount();
+ }
+
+ uiIsCommunicating = TRUE;
+ timeOfLastUICheckIn = getMSTimerCount();
+ uiDidCommunicate = TRUE;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isDDCommunicating function determines whether the DD is communicating
+ * with the TD.
+ * @details Inputs: ddIsCommunicating
+ * @details Outputs: none
+ * @return TRUE if DG has checked in since last call, FALSE if not
+ *************************************************************************/
+BOOL isDDCommunicating( void )
+{
+ return ddIsCommunicating;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isUICommunicating function determines whether the UI is communicating
+ * with the HD.
+ * @details Inputs: uiIsCommunicating
+ * @details Outputs: none
+ * @return TRUE if UI has checked in since last call, FALSE if not
+ *************************************************************************/
+BOOL isUICommunicating( void )
+{
+ BOOL result = uiIsCommunicating;
+
+ uiIsCommunicating = FALSE;
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The uiCommunicated function determines whether the UI has communicated.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return TRUE if UI has communicated since power up, FALSE if not
+ *************************************************************************/
+BOOL uiCommunicated( void )
+{
+#ifdef SIMULATE_UI
+ uiDidCommunicate = TRUE;
+#endif
+
+ return uiDidCommunicate;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The isOnlyCANNode function determines whether the HD is the only node
+ * currently on the CAN bus.
+ * @details Inputs: tdIsOnlyCANNode
+ * @details Outputs: none
+ * @return TRUE if HD is only node on CAN bus, FALSE if not
+ *************************************************************************/
+BOOL isOnlyCANNode( void )
+{
+ return tdIsOnlyCANNode;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The setOnlyCANNode function sets whether the HD is the only node
+ * currently on the CAN bus.
+ * @details Inputs: none
+ * @details Outputs: tdIsOnlyCANNode
+ * @return only TRUE if HD is only node on CAN bus, FALSE if not
+ *************************************************************************/
+void setOnlyCANNode( BOOL only )
+{
+ tdIsOnlyCANNode = only;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The clearCANXmitBuffers function clears all CAN transmit buffers.
+ * @details Inputs: CAN_OUT_BUFFERS[]
+ * @details Outputs: CAN transmit buffers cleared.
+ * @return none
+ *************************************************************************/
+void clearCANXmitBuffers( void )
+{
+ U32 i;
+
+ for ( i = 0; i < NUM_OF_CAN_OUT_BUFFERS; i++ )
+ {
+ clearBuffer( getOutBufferID( i ) );
+ }
+}
+
+
+/*************************************************************************
+********************** TRANSMIT SUPPORT FUNCTIONS ************************
+*************************************************************************/
+
+
+
+/*************************************************************************
+********************** RECEIVE SUPPORT FUNCTIONS *************************
+*************************************************************************/
+
+
+/*********************************************************************//**
+ * @brief
+ * The checkForCommTimeouts function checks for sub-system communication
+ * timeout errors.
+ * @details Inputs: timeOfLastDGCheckIn, timeOfLastUICheckIn
+ * @details Outputs: possibly a comm t/o alarm
+ * @return none
+ *************************************************************************/
+void checkForCommTimeouts( void )
+{
+ if ( TRUE == uiDidCommunicate )
+ {
+ TD_OP_MODE_T opMode = getCurrentOperationMode();
+ U32 uiTO_MS = UI_COMM_TIMEOUT_IN_MS;
+
+ // in service mode, allow up to 2 minutes for UI to check-in (for lock-down)
+ if ( MODE_SERV == opMode )
+ {
+ uiTO_MS = UI_COMM_SERVICE_MODE_TIMEOUT_IN_MS;
+ }
+ if ( TRUE == didTimeout( timeOfLastUICheckIn, uiTO_MS ) )
+ {
+#ifndef _RELEASE_
+// if ( getSoftwareConfigStatus( SW_CONFIG_DISABLE_UI_COMM_ALARMS ) != SW_CONFIG_ENABLE_VALUE )
+#endif
+ {
+ activateAlarmNoData( ALARM_ID_HD_UI_COMM_TIMEOUT );
+ }
+ }
+
+ if ( TRUE == didTimeout( timeOfLastDGCheckIn, DG_COMM_TIMEOUT_IN_MS ) )
+ {
+#ifndef RUN_WITHOUT_DG
+ // Only alarm on DG comm loss while in the treatment workflow
+ if ( MODE_PRET == opMode || MODE_TREA == opMode || MODE_POST == opMode )
+ {
+ activateAlarmNoData( ALARM_ID_HD_DG_COMM_TIMEOUT );
+ // we don't want to keep thinking DG is in a useful mode - set it to fault mode until DG is able to report its' true mode status
+// setDGOpMode( DG_MODE_FAUL, 0 );
+ }
+ else // Otherwise clear the alarm
+ {
+ clearAlarmCondition( ALARM_ID_HD_DG_COMM_TIMEOUT );
+ }
+ ddIsCommunicating = FALSE;
+#endif
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getInBufferID function gets the buffer ID for a given buffer index.
+ * @details Inputs: CAN_IN_BUFFERS[]
+ * @details Outputs: none
+ * @param idx incoming buffer index (e.g. 0 indicates first incoming buffer)
+ * @return buffer id associated with given incoming buffer index
+ *************************************************************************/
+COMM_BUFFER_T getInBufferID( U32 idx )
+{
+ COMM_BUFFER_T result = COMM_BUFFER_NOT_USED;
+
+ // validate given index
+ if ( idx < NUM_OF_CAN_IN_BUFFERS )
+ {
+ result = CAN_IN_BUFFERS[ idx ];
+ }
+ else
+ {
+ // TODO - s/w fault
+ }
+
+ return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getOutBufferID function gets the buffer ID for a given buffer index.
+ * @details Inputs: CAN_OUT_BUFFERS[]
+ * @details Outputs: none
+ * @param idx outgoing buffer index (e.g. 0 indicates first outgoing buffer)
+ * @return buffer id associated with given outgoing buffer index
+ *************************************************************************/
+COMM_BUFFER_T getOutBufferID( U32 idx )
+{
+ COMM_BUFFER_T result = COMM_BUFFER_NOT_USED;
+
+ // validate given index
+ if ( idx < NUM_OF_CAN_OUT_BUFFERS )
+ {
+ result = CAN_OUT_BUFFERS[ idx ];
+ }
+ else
+ {
+ // TODO - s/w fault
+ }
+
+ return result;
+
+}
+
+/*********************************************************************//**
+ * @brief
+ * The processReceivedMessage function processes a given message.
+ * @details Inputs: none
+ * @details Outputs: message processed
+ * @param message pointer to message to process
+ * @return none
+ *************************************************************************/
+void processReceivedMessage( MESSAGE_T *message )
+{
+ U16 msgID = message->hdr.msgID;
+
+ // Handle any messages from other sub-systems
+ switch ( msgID )
+ {
+// case MSG_ID_ALARM_TRIGGERED:
+// handleAlarmTriggered( message );
+// break;
+
+// case MSG_ID_ALARM_CONDITION_CLEARED:
+// handleAlarmCleared( message );
+// break;
+
+// case MSG_ID_UI_ALARM_USER_ACTION_REQUEST:
+// handleAlarmUserAction( message );
+// break;
+
+// case MSG_ID_UI_CHECK_IN:
+// handleUICheckIn( message );
+// break;
+
+// case MSG_ID_FW_VERSIONS_REQUEST:
+// handleFWVersionRequest( message );
+// handleHDSerialNumberRequest();
+// break;
+
+// case MSG_ID_DG_VERSION_REPONSE:
+// handleDGVersionResponse( message );
+// break;
+
+// case MSG_ID_USER_ALARM_SILENCE_REQUEST:
+// handleUIAlarmSilenceRequest( message );
+// break;
+
+// case MSG_ID_UI_VERSION_INFO_RESPONSE:
+// handleUIVersionResponse( message );
+// break;
+
+// case MSG_ID_UI_ACTIVE_ALARMS_LIST_REQUEST:
+// handleUIActiveAlarmsListRequest( message );
+// break;
+
+// case MSG_ID_UI_SERVICE_MODE_REQUEST:
+// handleUIServiceModeRequest( message );
+// break;
+
+// case MSG_ID_UI_INSTITUTIONAL_RECORD_REQUEST:
+// handleSendInstitutionalRecordToUI( message );
+// break;
+
+ case MSG_ID_UI_HD_RESET_IN_SERVICE_MODE_REQUEST:
+ handleUITDResetInServiceModeRequest( message );
+ break;
+
+ // NOTE: this always must be the last case
+ case MSG_ID_TESTER_LOGIN_REQUEST:
+ handleTesterLogInRequest( message );
+ break;
+
+ default:
+ // Un-recognized or un-handled message ID received - ignore
+ break;
+ }
+
+ // Handle any test messages if tester has logged in successfully
+ if ( ( msgID > MSG_ID_FIRST_TESTER_MESSAGE ) && ( TRUE == isTestingActivated() ) )
+ {
+ switch ( msgID )
+ {
+// case MSG_ID_HD_GET_TEST_CONFIGURATION:
+// handleTestHDGetTestConfig( message );
+// break;
+//
+// case MSG_ID_HD_RESET_ALL_TEST_CONFIGURATIONS:
+// handleTestHDResetAllTestConfigs( message );
+// break;
+//
+// case MSG_ID_HD_DIALIN_CHECK_IN:
+// handleTestHDDialinCheckIn( message );
+// break;
+//
+// case MSG_ID_HD_SET_TEST_CONFIGURATION:
+// handleTestHDSetTestConfig( message );
+// break;
+//
+// case MSG_ID_HD_GET_INSTITUTIONAL_RECORD:
+// handleGetHDInstitutionalRecord( message );
+// break;
+//
+// case MSG_ID_HD_SET_INSTITUTIONAL_RECORD:
+// handleSetHDInstitutionalRecord( message );
+// break;
+
+ // The default cannot be reached in VectorCAST since the cases are run in a for loop
+ default:
+ // Unrecognized message ID received - ignore
+ break;
+ }
+ }
+}
+
+
+/*************************************************************************
+ * TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/**@}*/
Index: firmware/App/Services/SystemCommTD.h
===================================================================
diff -u
--- firmware/App/Services/SystemCommTD.h (revision 0)
+++ firmware/App/Services/SystemCommTD.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,67 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file SystemCommTD.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __SYSTEM_COMM_TD_H__
+#define __SYSTEM_COMM_TD_H__
+
+#include "../TDCommon.h"
+#include "CommBuffers.h"
+#include "MsgQueues.h"
+#include "SystemComm.h"
+
+/**
+ * @defgroup SystemCommTD SystemCommTD
+ * @brief System communication module. Manages incoming and outgoing CAN frames.
+ *
+ * @addtogroup SystemCommTD
+ * @{
+ */
+
+// ********** public definitions **********
+
+#define MESSAGE_SYNC_BYTE 0xA5 ///< Denali message syncronization byte.
+
+#define CAN_MESSAGE_PAYLOAD_SIZE 8 ///< CAN frame payload size (in bytes).
+
+#define MSG_ACK_BIT 0x8000 ///< ACK bit in sequence number that indicates an ACK is required.
+#define MAX_MSG_SEQ_NO 0x7FFF ///< Maximum sequence number for Denali message (then wraps to 1).
+#define MIN_MSG_SEQ_NO 0x0001 ///< Minimum sequence number for Denali message.
+#define MAX_ACK_MSG_SIZE ( sizeof( MESSAGE_WRAPPER_T ) + 1 + CAN_MESSAGE_PAYLOAD_SIZE ) ///< Maximum size (in bytes) of Denali message including full (wrapped) message + sync + any CAN padding)
+
+#define NUM_OF_CAN_OUT_BUFFERS 5 ///< Number of CAN buffers for transmit
+#define NUM_OF_CAN_IN_BUFFERS 9 ///< Number of CAN buffers for receiving
+
+// ********** public function prototypes **********
+
+void initSystemCommTD( void );
+void processReceivedMessage( MESSAGE_T *message );
+
+COMM_BUFFER_T getInBufferID( U32 idx );
+COMM_BUFFER_T getOutBufferID( U32 idx );
+void checkForCommTimeouts( void );
+void checkInFromDG( void );
+void checkInFromUI( void );
+BOOL isDDCommunicating( void );
+BOOL isUICommunicating( void );
+BOOL uiCommunicated( void );
+BOOL isOnlyCANNode( void );
+void setOnlyCANNode( BOOL only );
+void clearCANXmitBuffers( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/TDCommon.h
===================================================================
diff -u
--- firmware/App/TDCommon.h (revision 0)
+++ firmware/App/TDCommon.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,122 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TDCommon.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __HD_COMMON_H__
+#define __HD_COMMON_H__
+
+#include "hal_stdtypes.h"
+
+// ********** version **********
+
+#define HD_VERSION_MAJOR 0
+#define HD_VERSION_MINOR 0
+#define HD_VERSION_MICRO 0
+#define HD_VERSION_BUILD 0
+
+// ********** development build switches **********
+
+#ifndef _RELEASE_
+#ifndef _VECTORCAST_
+// #define TASK_TIMING_OUTPUT_ENABLED 1 // Re-purposes alarm lamp pins for task timing
+
+ #include
+ #include
+#endif
+#endif
+
+#include "Common.h"
+
+/**
+ * @addtogroup Main
+ * @{
+ */
+
+// **** Common Definitions ****
+
+#pragma pack(push,1)
+
+/// Payload record structure for an HD versions message.
+typedef struct
+{
+ U08 major; ///< HD version major revision.
+ U08 minor; ///< HD version minor revision.
+ U08 micro; ///< HD version micro revision.
+ U16 build; ///< HD build version.
+ U08 fpgaId; ///< HD FPGA ID.
+ U08 fpgaMajor; ///< HD FPGA major revision.
+ U08 fpgaMinor; ///< HD FPGA minor revision.
+ U08 fpgaLab; ///< HD FPGA lab revision.
+ U32 compatibilityRev; ///< HD compatibility revision.
+} HD_VERSIONS_T;
+
+/// DD version struct.
+typedef struct
+{
+ U08 major; ///< DG version major revision.
+ U08 minor; ///< DG version major revision.
+ U08 micro; ///< DG version micro revision.
+ U16 build; ///< DG build version.
+ U08 fpgaId; ///< DG FPGA ID.
+ U08 fpgaMajor; ///< DG FPGA major revision.
+ U08 fpgaMinor; ///< DG FPGA minor revision.
+ U08 fpgaLab; ///< DG FPGA lab revision.
+ U32 compatibilityRev; ///< DG compatibility revision.
+} DD_VERSIONS_T;
+
+/// Record defining the fields in a UI version request message.
+typedef struct
+{
+ U08 major; ///< Major version for UI software.
+ U08 minor; ///< Minor version for UI software.
+ U08 micro; ///< Micro version for UI software.
+ U16 build; ///< Build number for UI software.
+ U32 compatibility; ///< Compatibility revision.
+} UI_VERSIONS_T;
+
+/// Payload record structure for a peristaltic pump data message.
+typedef struct
+{
+ U32 setPoint; ///< Set point.
+ F32 measFlow; ///< Measured flow in mL/min.
+ F32 measRotorSpd; ///< Measured rotor speed in RPM.
+ F32 measPumpSpd; ///< Measured pump speed in RPM.
+ F32 measMCSpd; ///< Measured motor speed in RPM.
+ F32 measMCCurr; ///< Measured motor current in Amps.
+ F32 pwmDC; ///< Duty cycle.
+} PERISTALTIC_PUMP_STATUS_PAYLOAD_T;
+
+/// Payload record structure for a pump set point override message.
+typedef struct
+{
+ BOOL reset; ///< Reset.
+ S32 setPt; ///< Set point.
+ U32 ctrlMode; ///< Control mode.
+} OVERRIDE_PUMP_SET_PT_PAYLOAD_T;
+
+#pragma pack(pop)
+
+// **** Common Macros ****
+
+/**@}*/
+
+// **** VectorCAST Definitions ****
+
+#ifdef _VECTORCAST_
+
+#endif
+
+#endif
Index: firmware/App/Tasks/TaskBG.c
===================================================================
diff -u
--- firmware/App/Tasks/TaskBG.c (revision 0)
+++ firmware/App/Tasks/TaskBG.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,81 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TaskBG.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include
+
+//#include "Battery.h"
+#include "SystemCommTD.h"
+#include "TaskTimer.h"
+#include "Timers.h"
+//#include "Voltages.h"
+#include "WatchdogMgmt.h"
+
+/**
+ * @addtogroup TaskBackground
+ * @{
+ */
+
+// ********** private definitions **********
+
+#define MAX_TIME_FOR_UI_TO_COMMUNICATE_MS ( 2 * SEC_PER_MIN * MS_PER_SECOND ) ///< Maximum time we wait for UI to communicate after power up (2 minutes).
+
+// ********** private data **********
+
+static U32 startUICommTimeout; ///< Timer counter for UI to begin communicating.
+
+// ********** private function prototypes **********
+
+/*********************************************************************//**
+ * @brief
+ * The taskBackground function handles the idle Background Task loop.
+ * Calls the Watchdog Mgmt. and NonVolatile Data services.
+ * @details Inputs: none
+ * @details Outputs: Executive for watchdog mgmt. and non-volatile data services called.
+ * @return none
+ *************************************************************************/
+void taskBackground( void )
+{
+ startUICommTimeout = getMSTimerCount();
+
+#ifndef _VECTORCAST_ // Cannot have infinite loop in unit test tool
+ while ( 1 )
+#endif
+ {
+ // Wait for UI to come up after power up
+ if ( FALSE == uiCommunicated() )
+ {
+#ifndef BOARD_WITH_NO_HARDWARE
+ // Check timeout waiting for UI to check in (via CAN) after startup.
+ if ( TRUE == didTimeout( startUICommTimeout, MAX_TIME_FOR_UI_TO_COMMUNICATE_MS ) )
+ {
+// activateAlarmNoData( ALARM_ID_HD_UI_COMM_POST_FAILED );
+ }
+#endif
+ }
+
+ // Manage the watchdog
+ execWatchdogMgmt();
+//
+// // Manage Non-volatile data manager
+// execNVDataMgmt();
+//
+// // Monitor battery status
+// execBatteryMonitor();
+ }
+}
+
+/**@}*/
Index: firmware/App/Tasks/TaskBG.h
===================================================================
diff -u
--- firmware/App/Tasks/TaskBG.h (revision 0)
+++ firmware/App/Tasks/TaskBG.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,36 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TaskBG.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __TASK_BACKGROUND_H__
+#define __TASK_BACKGROUND_H__
+
+/**
+ * @defgroup TaskBackground TaskBackground
+ * @brief The background task is an infinite loop running in the background
+ * called by main() after initialization.
+ *
+ * @addtogroup TaskBackground
+ * @{
+ */
+
+// Public function prototypes
+
+void taskBackground( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Tasks/TaskGeneral.c
===================================================================
diff -u
--- firmware/App/Tasks/TaskGeneral.c (revision 0)
+++ firmware/App/Tasks/TaskGeneral.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,113 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TaskGeneral.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#include "Messaging.h"
+#include "OperationModes.h"
+#include "SystemComm.h"
+#include "TaskGeneral.h"
+#include "WatchdogMgmt.h"
+
+/**
+ * @addtogroup TaskGeneral
+ * @{
+ */
+
+// ********** private data **********
+
+/*********************************************************************//**
+ * @brief
+ * The taskGeneral function handles the scheduled General Task interrupt.
+ * Calls the executive functions for most monitors and controllers, the
+ * operation modes, the system communications, and alarms.
+ * @details Inputs: none
+ * @details Outputs: Executives running in general task are called.
+ * @return none
+ *************************************************************************/
+void taskGeneral( void )
+{
+#ifdef TASK_TIMING_OUTPUT_ENABLED
+ // Set GPIO high to indicate general task has begun executing
+ setCPLDLampGreen( PIN_SIGNAL_HIGH );
+#endif
+
+ // Check in with watchdog manager
+ checkInWithWatchdogMgmt( TASK_GENERAL ); // Do this first to keep timing consistent with watchdog management
+
+ // Manage data received from other sub-systems
+ execSystemCommRx();
+
+ // Prevent most processing until UI has started communicating or if DG is active and alarm (ALARM_ID_HD_UI_COMM_POST_FAILED) is raised
+ // proceed to further operations since UI likely failed to come up.
+// if ( ( TRUE == uiCommunicated() ) ||
+// ( ( FALSE == isOnlyCANNode() ) && ( TRUE == isAlarmActive( ALARM_ID_HD_UI_COMM_POST_FAILED ) ) ) )
+ {
+// // Monitor voltages
+// execVoltagesMonitor();
+//
+// // Monitor DG
+// execDGInterfaceMonitor();
+//
+// // Monitor pressure/occlusion sensors
+// execPresOccl();
+//
+// // Monitor switches
+// execSwitches();
+//
+// // Monitor temperatures
+// execTemperatures();
+//
+// // Monitor processor RAM status
+// execRAMMonitor();
+
+ // Run operation mode state machine
+ execOperationModes();
+
+// // Control air trap valve
+// execAirTrapController();
+//
+// // Control blood pump
+// execBloodFlowController();
+//
+// // Control dialysate inlet pump
+// execDialInFlowController();
+//
+// // Control dialysate outlet pump (keep after call to BP and DPi controllers)
+// execDialOutFlowController();
+//
+// // Control Air Pump
+// execAirPumpController();
+//
+// // Monitor/Control fans
+// execFans();
+//
+// // Manage NVDataMgmt process record state machine
+// execNVDataMgmtProcessRecord();
+
+ // Manage alarm state
+ execAlarmMgmt();
+
+ // Manage data to be transmitted to other sub-systems
+ execSystemCommTx();
+ }
+
+#ifdef TASK_TIMING_OUTPUT_ENABLED
+ // Set GPIO low to indicate general task has finished executing
+ setCPLDLampGreen( PIN_SIGNAL_LOW );
+#endif
+}
+
+/**@}*/
Index: firmware/App/Tasks/TaskGeneral.h
===================================================================
diff -u
--- firmware/App/Tasks/TaskGeneral.h (revision 0)
+++ firmware/App/Tasks/TaskGeneral.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,42 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TaskGeneral.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __TASK_GENERAL_H__
+#define __TASK_GENERAL_H__
+
+#include "../TDCommon.h"
+
+/**
+ * @defgroup TaskGeneral TaskGeneral
+ * @brief The general task is called by RTI interrupt every 50 ms and performs
+ * the bulk of sensor, actuator, mode, alarm & communication operations.
+ *
+ * @addtogroup TaskGeneral
+ * @{
+ */
+
+// Public definitions
+
+#define TASK_GENERAL_INTERVAL (50) ///< General task timer interrupt interval (in ms).
+
+// Public function prototypes
+
+void taskGeneral( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Tasks/TaskPriority.c
===================================================================
diff -u
--- firmware/App/Tasks/TaskPriority.c (revision 0)
+++ firmware/App/Tasks/TaskPriority.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,91 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TaskPriority.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+//#include "FPGA.h"
+#include "SystemCommTD.h"
+#include "TaskPriority.h"
+#include "WatchdogMgmt.h"
+
+/**
+ * @addtogroup TaskPriority
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief
+ * The taskPriority function handles the scheduled Priority Task interrupt.
+ * Calls the executive functions for FPGA, pumps, valves, and buttons.
+ * @details Inputs: none
+ * @details Outputs: Executives running in priority task are called.
+ * @return none
+ *************************************************************************/
+void taskPriority( void )
+{
+#ifdef TASK_TIMING_OUTPUT_ENABLED
+ // Set GPIO high to indicate priority task has begun executing
+ setCPLDLampRed( PIN_SIGNAL_HIGH );
+#endif
+
+ // Prevent most processing until UI has started communicating
+ if ( TRUE == uiCommunicated() )
+ {
+ // 1st pass for FPGA
+// execFPGAIn();
+
+ // Verify processor clock speed against FPGA clock
+// execFPGAClockSpeedTest();
+
+ // Monitor and process buttons
+// execButtons();
+
+ // Monitor internal ADC channels
+// execInternalADC();
+
+ // Monitor air trap level sensors
+// execAirTrapMonitor();
+
+#ifndef _RELEASE_
+// if ( getSoftwareConfigStatus( SW_CONFIG_DISABLE_SYRINGE_PUMP ) != SW_CONFIG_ENABLE_VALUE )
+#endif
+ {
+ // Control/Monitor syringe pump
+// execSyringePump();
+ }
+
+ // Monitor blood pump and flow
+// execBloodFlowMonitor();
+
+ // Monitor fluid leak detector
+// execFluidLeak();
+
+ // Monitor air bubble detectors
+// execBubbles();
+
+ // 2nd pass for FPGA
+// execFPGAOut();
+ }
+
+ // Check in with watchdog manager
+ checkInWithWatchdogMgmt( TASK_PRIORITY );
+
+#ifdef TASK_TIMING_OUTPUT_ENABLED
+ // Set GPIO low to indicate priority task has finished executing
+ setCPLDLampRed( PIN_SIGNAL_LOW );
+#endif
+}
+
+/**@}*/
Index: firmware/App/Tasks/TaskPriority.h
===================================================================
diff -u
--- firmware/App/Tasks/TaskPriority.h (revision 0)
+++ firmware/App/Tasks/TaskPriority.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,41 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TaskPriority.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __TASK_PRIORITY_H__
+#define __TASK_PRIORITY_H__
+
+/**
+ * @defgroup TaskPriority TaskPriority
+ * @brief The priority task is called by RTI interrupt every 10 ms and performs
+ * high priority and/or more urgent sensor/actuator processing as well as the
+ * interface to the FPGA.
+ *
+ * @addtogroup TaskPriority
+ * @{
+ */
+
+// Public definitions
+
+#define TASK_PRIORITY_INTERVAL (10) ///< Priority task timer interrupt interval (in ms).
+
+// Public function prototypes
+
+void taskPriority( void );
+
+/**@}*/
+
+#endif
Index: firmware/App/Tasks/TaskTimer.c
===================================================================
diff -u
--- firmware/App/Tasks/TaskTimer.c (revision 0)
+++ firmware/App/Tasks/TaskTimer.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,56 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TaskTimer.c
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+//#include "CPLD.h"
+#include "TaskTimer.h"
+#include "WatchdogMgmt.h"
+#include "Timers.h"
+
+/**
+ * @addtogroup TaskTimer
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief
+ * The taskTimer function handles the scheduled Timer Task interrupt.
+ * Calls the Timers executive to maintain a 1ms timer counter to
+ * support timer and timeout functions.
+ * @details Inputs: none
+ * @details Outputs: Executive for Timers called.
+ * @return none
+ *************************************************************************/
+void taskTimer( void )
+{
+#ifdef TASK_TIMING_OUTPUT_ENABLED
+ // Set GPIO high to indicate timer task has begun executing
+ setCPLDLampBlue( PIN_SIGNAL_HIGH );
+#endif
+
+ // Increment ms timer count
+ incMSTimerCount();
+
+ // Check in with watchdog manager
+ checkInWithWatchdogMgmt( TASK_TIMER );
+
+#ifdef TASK_TIMING_OUTPUT_ENABLED
+ // Set GPIO low to indicate timer task has finished executing
+ setCPLDLampBlue( PIN_SIGNAL_LOW );
+#endif
+}
+
+/**@}*/
Index: firmware/App/Tasks/TaskTimer.h
===================================================================
diff -u
--- firmware/App/Tasks/TaskTimer.h (revision 0)
+++ firmware/App/Tasks/TaskTimer.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,40 @@
+/**************************************************************************
+*
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
+*
+* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+*
+* @file TaskTimer.h
+*
+* @author (last) Sean
+* @date (last) 30-Jul-2024
+*
+* @author (original) Sean
+* @date (original) 30-Jul-2024
+*
+***************************************************************************/
+
+#ifndef __TASK_TIMER_H__
+#define __TASK_TIMER_H__
+
+/**
+ * @defgroup TaskTimer TaskTimer
+ * @brief Timer task is called by RTI interrupt every 1 ms to update the
+ * ms timer counter.
+ *
+ * @addtogroup TaskTimer
+ * @{
+ */
+
+// Public definitions
+
+#define TASK_TIMER_INTERVAL (1) ///< Timer task timer interrupt interval (in ms).
+
+// Public function prototypes
+
+void taskTimer( void );
+
+/**@}*/
+
+#endif
Index: firmware/TD.dil
===================================================================
diff -u
--- firmware/TD.dil (revision 0)
+++ firmware/TD.dil (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,10377 @@
+# RM46L852PGE 07/31/24 14:56:13
+#
+ARCH=RM46L852PGE
+#
+DRIVER.TOOLS.VAR.GCC.VALUE=0
+DRIVER.TOOLS.VAR.ARM.VALUE=0
+DRIVER.TOOLS.VAR.IAR.VALUE=0
+DRIVER.TOOLS.VAR.GHS.VALUE=0
+DRIVER.TOOLS.VAR.TI.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_0.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_NAME.VALUE=het2LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_NAME.VALUE=adc2Group2Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_NAME.VALUE=spi4HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_MAPPING.VALUE=2
+DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_1.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.EQEP2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MEMINIT_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_DATA_3_WAIT_STATE_FREQ.VALUE=220.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_MAPPING.VALUE=96
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_MAPPING.VALUE=88
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0xfcffffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SPI3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_BYPASS_ON_SLIP.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_NAME.VALUE=ecap5Interrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=256_KB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=FIQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=208.000
+DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=220.00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_MAPPING.VALUE=65
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_MAPPING.VALUE=57
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_MAPPING.VALUE=49
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_NAME.VALUE=dmaBTCAInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_NAME.VALUE=het1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CCM_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATE_AVAIL.VALUE=1
+DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.CLKT_PLL2_OUTPUT_DIV.VALUE=2
+DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x63ffffff
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_DP_PBISTCHECK_ENA.VALUE=0x00040000
+DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_NAME.VALUE=etpwm5TripZoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_MAPPING.VALUE=50
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_MAPPING.VALUE=42
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_MAPPING.VALUE=34
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_MAPPING.VALUE=26
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATEVALUE.VALUE=0x5
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=_irqDispatch
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0600
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_MAPPING.VALUE=11
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.LBIST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x003fffff
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=110.0
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08002800
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_NAME.VALUE=etpwm1Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_NAME.VALUE=dcc1DoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_NAME.VALUE=sciLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_NAME.VALUE=i2cInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_PMU_GLOBAL_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0xFF000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_DP_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=rtiCompare0Interrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER0_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENTRY.VALUE=_c_int00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x0F
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_NAME.VALUE=ecap6Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_MAPPING.VALUE=102
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_LENGTH.VALUE=0x00030000
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=64_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_VALUE_NEW.VALUE=0x00300020
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=dmaFTCAInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x203fffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE_VALUE.VALUE=0x0000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_MAPPING.VALUE=95
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_MAPPING.VALUE=87
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_MAPPING.VALUE=79
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_DP_PBISTCHECK_ENA.VALUE=0x00000040
+DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=etpwm6Interrupt
+DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.USB_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SCI_ALL_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0
+DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=24
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16
+DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=208.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x1000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_MAPPING.VALUE=64
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_MAPPING.VALUE=56
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_MAPPING.VALUE=48
+DRIVER.SYSTEM.VAR.CLKT_PLL1_REF_CLOCK_DIV.VALUE=6
+DRIVER.SYSTEM.VAR.FLASHW_BASE_ADDRESS.VALUE=0xFFF87000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_FIQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]"
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001
+DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_FREQ.VALUE=16.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_NAME.VALUE=etpwm1TripZoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_NAME.VALUE=dcc2DoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_MAPPING.VALUE=41
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_MAPPING.VALUE=33
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_MAPPING.VALUE=25
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x000C
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=rtiCompare1Interrupt
+DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATEVALUE.VALUE=0xA
+DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=2
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CLKT_PLL2_FM_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0x08400000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_CPUSELFTEST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.HET1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_RTI1_PRE_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.FLASH_MODE_VALUE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE_VALUE.VALUE=0x19
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_MAPPING.VALUE=10
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE.VALUE=128_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_DP_PBISTCHECK_ENA.VALUE=0x00001000
+DRIVER.SYSTEM.VAR.ECAP4_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_MAPPING.VALUE=124
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_MAPPING.VALUE=116
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_MAPPING.VALUE=108
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_NAME.VALUE=adc2Group0Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_NAME.VALUE=can2LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_NAME.VALUE=dmaLFSAInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_NAME.VALUE=mibspi1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=etpwm6TripZoneInterrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000400
+DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3
+DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_SP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_MAPPING.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_DIV.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.RAM_BASE_ADDRESS.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.CORE_PMU_EVENT_EXPORT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x17
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_MAPPING.VALUE=94
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_MAPPING.VALUE=86
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_MAPPING.VALUE=78
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE.VALUE=STRONGLYORDERED_SHAREABLE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08002c00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD3_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EFUSE_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_GHV_WAKUP_SOURCE.VALUE=OSC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE_VALUE.VALUE=0x0000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_MAPPING.VALUE=71
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_MAPPING.VALUE=63
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_MAPPING.VALUE=55
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_MAPPING.VALUE=47
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_MAPPING.VALUE=39
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_NAME.VALUE=rtiCompare2Interrupt
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08003400
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE.VALUE=8_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=165.0
+DRIVER.SYSTEM.VAR.RAM_STACK_BASE.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_NAME.VALUE=adc2Group1Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_MAPPING.VALUE=40
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_NAME.VALUE=can2HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_MAPPING.VALUE=32
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_NAME.VALUE=linLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_MAPPING.VALUE=24
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_NAME.VALUE=crcInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xf07fffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_2.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_3.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_4.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_NAME.VALUE=eqep1Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_NAME.VALUE=etpwm7Interrupt
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_5.VALUE=1
+DRIVER.SYSTEM.VAR.LBIST_STT.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_6.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_7.VALUE=1
+DRIVER.SYSTEM.VAR.ECAP2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_8.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_MAPPING.VALUE=123
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_MAPPING.VALUE=115
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_MAPPING.VALUE=107
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATEVALUE.VALUE=0x5
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00002000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0x0843ffff
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_SP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ETPWM_OLDCODE.VALUE=1
+DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x11
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x08020000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=STRONGLYORDERED_SHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_DP_PBISTCHECK_ENA.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=13.000
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=etpwm2TripZoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000400
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=rtiCompare3Interrupt
+DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00003400
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC
+DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0xffffffff
+DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=VCLKA4_DIVR
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=104.000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_MAPPING.VALUE=69
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ2.VALUE=27.500
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE.VALUE=16_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_BASE_ADDRESS.VALUE=0xFC000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_2_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=156
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_NAME.VALUE=adc1Group2Interrupt
+DRIVER.SYSTEM.VAR.CLKT_OSC_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE.VALUE=16_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_MAPPING.VALUE=70
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_MAPPING.VALUE=62
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_MAPPING.VALUE=54
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_MAPPING.VALUE=46
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_MAPPING.VALUE=38
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_SOURCE_ENABLE.VALUE=0x00000080
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_DP_PBISTCHECK_ENA.VALUE=0x00080000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=eqep2Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002cc00
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0802ffff
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_MAPPING.VALUE=31
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_MAPPING.VALUE=23
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_MAPPING.VALUE=15
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_5_6.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=165
+DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENTRY.VALUE=_prefetch
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_FREQ.VALUE=0.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_NAME.VALUE=etpwm3Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_BASE_ADDRESS.VALUE=0x60000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_AUTO_CLK_WAKE_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_7_8.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_0.VALUE=0x00000020
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_1.VALUE=0x00180000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE_VALUE.VALUE=0x08
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_MAPPING.VALUE=122
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_MAPPING.VALUE=114
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_MAPPING.VALUE=106
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_NAME.VALUE=rtiOverflow0Interrupt
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD5_STATEVALUE.VALUE=0x5
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER2_EVENT.VALUE=0x11
+DRIVER.SYSTEM.VAR.FLASH_DATA_WAIT_STATES.VALUE=3
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=165.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5
+DRIVER.SYSTEM.VAR.VIM_PARITY_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE
+DRIVER.SYSTEM.VAR.VIM_CHANNELS.VALUE=128
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_7.VALUE=0xF0200000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE.VALUE=512_BYTES
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD1_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_DP_PBISTCHECK_ENA.VALUE=0x00000010
+DRIVER.SYSTEM.VAR.ECAP_OLDCODE.VALUE=1
+DRIVER.SYSTEM.VAR.ESM_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_MAPPING.VALUE=99
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_NAME.VALUE=mibspi5HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_NAME.VALUE=can3HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_NAME.VALUE=mibspi3HighInterruptLevel
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_NAME.VALUE=can1LowLevelInterrupt
+DRIVER.SYSTEM.VAR.PMM_MEM_PD1_STATEVALUE.VALUE=0x5
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=64_KB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.EQEP1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_FREQ.VALUE=10.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE_VALUE.VALUE=0x11
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]"
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=OSC
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_NAME.VALUE=ecap1Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_MAPPING.VALUE=92
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_MAPPING.VALUE=84
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_MAPPING.VALUE=76
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_MAPPING.VALUE=68
+DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_DP_PBISTCHECK_ENA.VALUE=0x00020000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.SYSTEM_INIT.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_NAME.VALUE=esmLowInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_NAME.VALUE=mibspi1HighLevelInterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION.VALUE=PRIV_NA_USER_NA_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_TYPE.VALUE=FIQ
+DRIVER.SYSTEM.VAR.DMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION_VALUE.VALUE=0x1100
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION_VALUE.VALUE=0x1200
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_MAPPING.VALUE=61
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_MAPPING.VALUE=53
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_MAPPING.VALUE=45
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_MAPPING.VALUE=37
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00140000
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000400
+DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=etpwm3TripZoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_NAME.VALUE=EMACRxIntISR
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_DIVIDER.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0
+DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=55.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_MAPPING.VALUE=30
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_MAPPING.VALUE=22
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_MAPPING.VALUE=14
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_NAME.VALUE=rtiOverflow1Interrupt
+DRIVER.SYSTEM.VAR.PBIST_ALGO_2.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_RTI1_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_ESRAM_SELECTED.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=104.000
+DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0xfe0001ff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00002000
+DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_NAME.VALUE=spi4LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_NAME.VALUE=mibspi3LowLevelInterrupt
+DRIVER.SYSTEM.VAR.FEE_FLASH_ECC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE.VALUE=4_MB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE_AVAIL.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESERVED_ENTRY.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATE_AVAIL.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=ecap2Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87ffffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_GB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION_VALUE.VALUE=0x1300
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE_VALUE.VALUE=0x17
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_MAPPING.VALUE=98
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_NAME.VALUE=linHighLevelInterrupt
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATEVALUE.VALUE=0xA
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_FUN.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_BASE_ADDRESS.VALUE=0x20000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000800
+DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08003000
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08002000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.PMM_PMCTRL_PWRDN.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=etpwm4Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_MAPPING.VALUE=83
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_MAPPING.VALUE=75
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_MAPPING.VALUE=67
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_MAPPING.VALUE=59
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_2.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OINC_SHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803ffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD5_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_DP_PBISTCHECK_ENA.VALUE=0x00000008
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_4.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_5.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE_VALUE.VALUE=0x15
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_NAME.VALUE=rtiTimebaseInterrupt
+DRIVER.SYSTEM.VAR.ECLK_PRESCALER.VALUE=8
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_6.VALUE=SLEEP
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0xFE000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=104.000
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_MAPPING.VALUE=36
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_MAPPING.VALUE=28
+DRIVER.SYSTEM.VAR.CLKT_PLL1_BAND_WIDTH_ADJUSTMENT.VALUE=7
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_SOURCE_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL_VAL.VALUE=A400
+DRIVER.SYSTEM.VAR.CLKT_RTI1_POST_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_NAME.VALUE=het2HighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_NAME.VALUE=can3LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_NAME.VALUE=dmaHBCAInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_DP_PBISTCHECK_ENA.VALUE=0x00000400
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_DP_PBISTCHECK_ENA.VALUE=0x00000080
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_MAPPING.VALUE=13
+DRIVER.SYSTEM.VAR.CLKT_PLL2_REF_CLOCK_DIV.VALUE=6
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_RATE.VALUE=255
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_PRAGMA_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_SLIP.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE_VALUE.VALUE=0x0010
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_MAPPING.VALUE=127
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_MAPPING.VALUE=119
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_NAME.VALUE=ecap3nterrupt
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION.VALUE=PRIV_RW_USER_NA_NOEXEC
+DRIVER.SYSTEM.VAR.CLKT_PLL1_FM_ENABLE.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE.VALUE=4_MB
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_ROM_PBIST_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ECAP3_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_NAME.VALUE=adc1Group0Interrupt
+DRIVER.SYSTEM.VAR.CLKT_LPOLO_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PSL.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0xffffffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=_svc
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FLASHECC_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=etpwm4TripZoneInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_MAPPING.VALUE=3
+DRIVER.SYSTEM.VAR.CLKT_LPOHI_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RTP_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIV_FREQ.VALUE=110.0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_MAPPING.VALUE=97
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_MAPPING.VALUE=89
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_NAME.VALUE=gioHighLevelInterrupt
+DRIVER.SYSTEM.VAR.CLKT_PLL1_ENABLE.VALUE=TRUE
+DRIVER.SYSTEM.VAR.FLASH_BASE_ADDRESS.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_6_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_ENA.VALUE=0x08300020
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_ROM_PBIST_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SPI5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OINC_NONSHARED
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x0013FFE0
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00180000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_MAPPING.VALUE=90
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_MAPPING.VALUE=82
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_MAPPING.VALUE=74
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_MAPPING.VALUE=66
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_NAME.VALUE=sciHighLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_MAPPING.VALUE=58
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_NAME.VALUE=mibspi5LowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.PMM_LOGIC_PD3_STATEVALUE.VALUE=0x5
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_7_DISABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_1_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08002400
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.FEE_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_10.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM_VALUE.VALUE=16
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_NAME.VALUE=ecap4Interrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_MAPPING.VALUE=51
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_MAPPING.VALUE=43
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_MAPPING.VALUE=35
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_MAPPING.VALUE=27
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_MAPPING.VALUE=19
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_11.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_12.VALUE=1
+DRIVER.SYSTEM.VAR.CCM_MENU.VALUE=NONE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=256_KB
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE_NEW.VALUE=0xA
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_RAMPARITYCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_13.VALUE=1
+DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL_VAL.VALUE=9B00
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_14.VALUE=1
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK
+DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=208.00
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x1F
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt
+DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000400
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000400
+DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_DP_PBISTCHECK_ENA.VALUE=0x00000004
+DRIVER.SYSTEM.VAR.ETPWM6_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_ENDIAN_LITTLE.VALUE=1
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_SP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.OS_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE_VALUE.VALUE=0x15
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_MAPPING.VALUE=126
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_MAPPING.VALUE=118
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_NAME.VALUE=etpwm5Interrupt
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULL.VALUE=2
+DRIVER.SYSTEM.VAR.ECLK_SUSPEND.VALUE=0
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_AMOUNT.VALUE=61
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_5_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_VFP_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_DP_PBISTCHECK_ENA.VALUE=0x00000200
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FMCBUS2_SELFCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.ECAP1_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.AJSM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ECLK_OSCILLATOR_FREQ.VALUE=16.000
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM.VALUE=100.00
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_ENABLE.VALUE=FALSE
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_0_DISABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_RAMPARITYCHECK_ENA.VALUE=0
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_DP_PBISTCHECK_ENA.VALUE=0x00000000
+DRIVER.SYSTEM.VAR.CLKT_CRYSTAL_FREQ.VALUE=16.0
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE_VALUE.VALUE=0x0008
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_MAPPING.VALUE=111
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_MAPPING.VALUE=103
+DRIVER.SYSTEM.VAR.VIM_PHANTOM_NAME.VALUE=phantomInterrupt
+DRIVER.OS.VAR.OS_USERECERSIVEMUTEXES.VALUE=0
+DRIVER.OS.VAR.OS_USETIMERS.VALUE=0
+DRIVER.OS.VAR.OS_USECNTSEMAPHORE.VALUE=0
+DRIVER.OS.VAR.OS_GENERATERUNTIMESTATS.VALUE=0
+DRIVER.OS.VAR.OS_USEMPU.VALUE=0
+DRIVER.OS.VAR.OS_TOTALHEAPSIZE.VALUE=8192
+DRIVER.OS.VAR.OS_USEVERBOSESTACK.VALUE=2
+DRIVER.OS.VAR.OS_TIMERPRIORITY.VALUE=0
+DRIVER.OS.VAR.OS_SVCENABLE.VALUE=0
+DRIVER.OS.VAR.OS_MAXTASKNAMELEN.VALUE=16
+DRIVER.OS.VAR.OS_MAXPRIORITIES.VALUE=5
+DRIVER.OS.VAR.OS_TIMERTASKSTACKDEPTH.VALUE=0
+DRIVER.OS.VAR.OS_COROUTINEPRIORITIES.VALUE=2
+DRIVER.OS.VAR.OS_USECOROUTINES.VALUE=0
+DRIVER.OS.VAR.OS_USEMUTEXES.VALUE=0
+DRIVER.OS.VAR.OS_CPUCLOCKHZ.VALUE=80000000
+DRIVER.OS.VAR.OS_USEMALLOCFAILEDHOOK.VALUE=0
+DRIVER.OS.VAR.OS_MINSTACKSIZE.VALUE=128
+DRIVER.OS.VAR.OS_SYSTEM_MODE.VALUE=0x1F
+DRIVER.OS.VAR.OS_USEPREEMPTION.VALUE=1
+DRIVER.OS.VAR.OS_IDLESHOULDYIELD.VALUE=1
+DRIVER.OS.VAR.OS_USEIDLEHOOK.VALUE=0
+DRIVER.OS.VAR.OS_TICKRATEHZ.VALUE=1000
+DRIVER.OS.VAR.OS_TIMERPQUEUELENGTH.VALUE=0
+DRIVER.OS.VAR.OS_USETRACE.VALUE=0
+DRIVER.OS.VAR.OS_USESTACK.VALUE=0
+DRIVER.OS.VAR.OS_USETICKHOOK.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL21_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL13_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL57_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL62_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL54_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL46_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL38_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL1_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL7_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL10_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL6_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL59_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_LOW_TIME.VALUE=157.538
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL31_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL23_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL15_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL60_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL52_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL44_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL36_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL28_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_VCLK_FREQ.VALUE=104
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL1_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL57_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL10_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL7_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL51_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL43_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL35_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL27_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL19_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL62_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL54_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL46_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL38_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL21_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL13_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL7_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL10_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL6_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL59_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL1_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL62_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL54_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL46_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL38_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL31_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL23_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL15_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL31_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL23_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL15_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL60_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL52_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL44_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL36_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL28_INT_LEVEL.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL20_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL6_INT_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL59_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL60_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL52_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL44_ENABLE.VALUE=0
+DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL36_ENABLE.VALUE=0
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+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=19.231
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=9.615
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_NONE
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE.VALUE=0xFFF7FC00
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=20
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=9.615
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_NONE
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE_RAM.VALUE=0xFF0A0000
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_CSDEF.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_NONE
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=19.231
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_NONE
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BITERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE_PORT.VALUE=0xFFF7F418
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PARERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=9.615
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_NONE
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE.VALUE=0xFFF7F400
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_RXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=11
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ENABLE.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_NONE
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CSDEF.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_RXINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE.VALUE=0xFFF7F800
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_MASTER.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_LOCK.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=19.231
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_NONE
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTLVL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_MODE.VALUE=4
+DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAY.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGEVT.VALUE=TRG_ALWAYS
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD_LASTBUF.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI1_CSDEF.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_CS_ENCODE.VALUE=0xFF
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_USE_CS_ENCODE.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TXINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_WDEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=103
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGSRC.VALUE=TRG_DISABLED
+DRIVER.SPI.VAR.SPI5_PORT_BIT26_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT18_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI2_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=9.615
+DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT4_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=0
+DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI1_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT4_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI1_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT25_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT17_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT4_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT25_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT17_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=103
+DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=103
+DRIVER.SPI.VAR.SPI1_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT27_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT19_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=103
+DRIVER.SPI.VAR.SPI1_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=103
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618
+DRIVER.SPI.VAR.SPI5_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT25_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT17_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=19.231
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT5_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI4_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT26_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT18_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT5_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI1_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT5_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI1_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT26_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT18_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI4_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI4_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT4_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT25_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT17_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI1_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT27_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT19_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_FUN.VALUE=0
+DRIVER.SPI.VAR.SPI1_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT25_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT17_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT4_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT25_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT17_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=19.231
+DRIVER.SPI.VAR.SPI1_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT27_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT19_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT5_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT26_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT18_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT5_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=103
+DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=103
+DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=103
+DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=103
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=9.615
+DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI1_BASE.VALUE=0xFFF7F400
+DRIVER.SPI.VAR.SPI3_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT4_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT25_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT17_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI5_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI4_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT27_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT19_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI4_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT25_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT17_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI5_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT5_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI1_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_BASE_PORT.VALUE=0xFFF7FC18
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=9.615
+DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_BASE.VALUE=0xFFF7F600
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI3_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI3_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT26_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT18_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=19.231
+DRIVER.SPI.VAR.SPI5_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI3_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI4_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_BASE.VALUE=0xFFF7F800
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=103
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT4_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT25_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT17_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=103
+DRIVER.SPI.VAR.SPI3_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI3_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=103
+DRIVER.SPI.VAR.SPI3_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=103
+DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI1_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_BASE_PORT.VALUE=0xFFF7F818
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI2_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT27_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT19_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_BASE_RAM.VALUE=0xFF0C0000
+DRIVER.SPI.VAR.SPI3_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI3_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI1_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI1_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=9.615
+DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00
+DRIVER.SPI.VAR.SPI3_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT5_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI3_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI2_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI3_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=19.231
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=103
+DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=103
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=103
+DRIVER.SPI.VAR.SPI3_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=103
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI1_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_BASE_PORT.VALUE=0xFFF7F418
+DRIVER.SPI.VAR.SPI5_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI4_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_BASE.VALUE=0xFFF7FC00
+DRIVER.SPI.VAR.SPI2_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI2_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI5_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI5_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI5_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI2_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY0.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_WDELAY2.VALUE=0
+DRIVER.SPI.VAR.SPI4_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_WDELAY3.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_POLARITY0.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2TDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI1_POLARITY1.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_POLARITY2.VALUE=0
+DRIVER.SPI.VAR.SPI1_OVRNINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_DEYSNCENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_POLARITY3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=9.615
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI4_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_TXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI2_BASE_RAM.VALUE=0xFF0E0000
+DRIVER.SPI.VAR.SPI2_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT4_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI2_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI2_ENABLEHIGHZ.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_TIMEOUTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_BITERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_RXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_BITERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR0.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL0.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR1.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=19.231
+DRIVER.SPI.VAR.SPI3_SHIFTDIR2.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE1.VALUE=0
+DRIVER.SPI.VAR.SPI3_SHIFTDIR3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PARPOL3.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE2.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_PHASE3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT1_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT5_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI1_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=103
+DRIVER.SPI.VAR.SPI1_PORT_BIT10_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_C2EDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=103
+DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=103
+DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=103
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI3_PORT_BIT8_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_BASE_PORT.VALUE=0xFFF7FA18
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI5_OVRNINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_MASTER.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT4_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_DOUT.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT2_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_T2CDELAY.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_PORT_BIT11_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI5_BASE_RAM.VALUE=0xFF0A0000
+DRIVER.SPI.VAR.SPI5_CHARLEN0.VALUE=16
+DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI3_PORT_BIT2_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI5_CHARLEN1.VALUE=16
+DRIVER.SPI.VAR.SPI2_PARERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI5_CHARLEN2.VALUE=16
+DRIVER.SPI.VAR.SPI1_PORT_BIT4_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI5_CHARLEN3.VALUE=16
+DRIVER.SPI.VAR.SPI5_PORT_BIT25_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT17_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI4_PARERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_DIR.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_DLENERRENA.VALUE=0
+DRIVER.SPI.VAR.SPI4_RXINTENA.VALUE=0
+DRIVER.SPI.VAR.SPI3_RAM_PARITY_ENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA0.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT0_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA0.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA1.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0
+DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=0
+DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT5_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0
+DRIVER.SPI.VAR.SPI5_PARITYENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_WAITENA3.VALUE=0
+DRIVER.SPI.VAR.SPI1_PORT_BIT3_PSL.VALUE=1
+DRIVER.SPI.VAR.SPI3_PORT_BIT1_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULL.VALUE=2
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI4_BAUDRATE0.VALUE=1000.000
+DRIVER.SPI.VAR.SPI1_T2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI4_BAUDRATE1.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_BAUDRATE2.VALUE=1000.000
+DRIVER.SPI.VAR.SPI4_TXINTLVL.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT3_DIR.VALUE=1
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_BAUDRATE3.VALUE=1000.000
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.SPI.VAR.SPI1_TIMEOUTENA.VALUE=0
+DRIVER.SPI.VAR.SPI5_CLKMOD.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PORT_BIT9_DOUT.VALUE=0
+DRIVER.SPI.VAR.SPI3_PHASE0.VALUE=0
+DRIVER.SPI.VAR.SPI2_C2EDELAYACTUAL.VALUE=0.000
+DRIVER.SPI.VAR.SPI1_PORT_BIT5_PDR.VALUE=0
+DRIVER.SPI.VAR.SPI3_PHASE1.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=250
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ID.VALUE=9
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_RAMBASE.VALUE=0xFF1C0000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_RATE.VALUE=500.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=0
+DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00002000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000002
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_RATE.VALUE=500.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000040
+DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=75.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ID.VALUE=3
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_BASE.VALUE=0xFFF7DE00
+DRIVER.CAN.VAR.CAN_1_RAMBASE.VALUE=0xFF1E0000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ID.VALUE=4
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=250.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DIR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ID.VALUE=6
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_BASE.VALUE=0xFFF7E000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DOUT.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_TQ.VALUE=250.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ID.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=0x101
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000010
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ID.VALUE=9
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=0x102
+DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=16
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=0x103
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT_REFERENCE.VALUE=75
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=0x400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000200
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=0x401
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_BAUDRATE.VALUE=500
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=75.000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00004000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_BRPE.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000004
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=0x1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_BRP.VALUE=25
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ID.VALUE=10
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=0x2
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=0x4
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_BRP.VALUE=25
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ID.VALUE=12
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=0x8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MASK.VALUE=0x1FFFFFFF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=0x10
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_BRP.VALUE=25
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=6
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=0x11
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00001000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ID.VALUE=15
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=0x40
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ID.VALUE=16
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=0x41
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ID.VALUE=17
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=0x100
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_SJW.VALUE=4
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_BAUDRATE.VALUE=500
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000020
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ID.VALUE=26
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ID.VALUE=18
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DIR.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ID.VALUE=51
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ID.VALUE=43
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ID.VALUE=35
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ID.VALUE=27
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_SJW.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ID.VALUE=60
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ID.VALUE=52
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ID.VALUE=44
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ID.VALUE=36
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ID.VALUE=28
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
+DRIVER.CAN.VAR.CAN_1_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SHIFT.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA_REF.VALUE=0x00000001
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PULDIS.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=4.000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=3
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ID.VALUE=61
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ID.VALUE=53
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ID.VALUE=45
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ID.VALUE=37
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ID.VALUE=29
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_SJW.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=62.500
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ID.VALUE=46
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ID.VALUE=38
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ID.VALUE=3
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DOUT.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ID.VALUE=63
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ID.VALUE=55
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ID.VALUE=47
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ID.VALUE=39
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_RAMBASE.VALUE=0xFF1A0000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DIN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PDR.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ID.VALUE=4
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DOUT.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ID.VALUE=64
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ID.VALUE=56
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ID.VALUE=48
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000008
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_SYNC.VALUE=1
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PULL.VALUE=2
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ID.VALUE=10
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ID.VALUE=5
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ID.VALUE=57
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ID.VALUE=49
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ID.VALUE=11
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ID.VALUE=6
+DRIVER.CAN.VAR.CAN_3_PROPAGATION_DELAY.VALUE=700
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ID.VALUE=58
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PSL.VALUE=1
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000100
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=1
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TR.VALUE=0
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DLC.VALUE=8
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=0
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_RTR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00002000
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_PARITY_ENABLE.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000008
+DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=20
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=20
+DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=3.271
+DRIVER.ADC.VAR.ADC2_PORT_BIT0_DIR.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_ALT_TRIG.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_GROUP2_LENGTH.VALUE=32
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=384.60
+DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=2
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00040000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000800
+DRIVER.ADC.VAR.ADC1_BND.VALUE=2
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000100
+DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000020
+DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=503.22
+DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=3.271
+DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000002
+DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC2_BND.VALUE=2
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_PORT_BIT0_PDR.VALUE=0
+DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=96.15
+DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=2
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC2_GROUP1_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00010000
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=500.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_PORT_BIT0_PSL.VALUE=1
+DRIVER.ADC.VAR.ADC1_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_LENGTH.VALUE=64
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=2
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000040
+DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000
+DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8
+DRIVER.ADC.VAR.ADC1_PORT_BIT0_DOUT.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=919.340
+DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_BND.VALUE=8
+DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_ALT_TRIG_COMP.VALUE=1
+DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=250.00
+DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00400000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00004000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=32
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000010
+DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000
+DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000
+DRIVER.ADC.VAR.ADC1_PORT_BIT0_DIR.VALUE=0
+DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005
+DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=384.60
+DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=44
+DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=10
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00080000
+DRIVER.ADC.VAR.ADC2_PORT_BIT0_DOUT.VALUE=0
+DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=9
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00001000
+DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN16_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_PORT_BIT0_PDR.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000004
+DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=3.271
+DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=0
+DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULL.VALUE=2
+DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=500.00
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=76.403740
+DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=503.22
+DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_PORT_BIT0_PSL.VALUE=1
+DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=503.22
+DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN21_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00020000
+DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000400
+DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=250
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000080
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000001
+DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00
+DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=20
+DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1
+DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_RAM_PARITY_ENA.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN4_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN8_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_RESOLUTION.VALUE=12_BIT
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00800000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=25
+DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=384.60
+DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULL.VALUE=2
+DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN20_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN12_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000020
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=500.00
+DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN9_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC2_GROUP1_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN2_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00
+DRIVER.LIN.VAR.LIN_PORT_BIT0_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_PEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOAWUSINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOA3WUSINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_MAXPRESCALE.VALUE=4680
+DRIVER.LIN.VAR.LIN_LENGTH.VALUE=8
+DRIVER.LIN.VAR.LIN_PARITYENA.VALUE=0
+DRIVER.LIN.VAR.LIN_BREAKINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TX_MASK.VALUE=0x00
+DRIVER.LIN.VAR.LIN_MSTMOD.VALUE=0
+DRIVER.LIN.VAR.LIN_SDEL.VALUE=1
+DRIVER.LIN.VAR.LIN_PORT_BIT2_DOUT.VALUE=0
+DRIVER.LIN.VAR.LIN_TOAWUSINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_WAKEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_HGENCTRL.VALUE=0
+DRIVER.LIN.VAR.LIN_TOA3WUSINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PULL.VALUE=2
+DRIVER.LIN.VAR.LIN_CEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BREAKINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PBEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT0_FUN.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT2_DIR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PULL.VALUE=1
+DRIVER.LIN.VAR.LIN_WAKEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_OEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_FUN.VALUE=2
+DRIVER.LIN.VAR.LIN_NREINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_PORT_BIT2_FUN.VALUE=4
+DRIVER.LIN.VAR.LIN_CEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PSL.VALUE=1
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PULL.VALUE=1
+DRIVER.LIN.VAR.LIN_PBEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PDR.VALUE=0
+DRIVER.LIN.VAR.LIN_BASE_PORT.VALUE=0xFFF7E440
+DRIVER.LIN.VAR.LIN_ACTUALBAUDRATE.VALUE=20.000
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PSL.VALUE=0
+DRIVER.LIN.VAR.LIN_ISFEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_FEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PSL.VALUE=0
+DRIVER.LIN.VAR.LIN_OEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TXINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_NREINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_IDINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_SBREAK.VALUE=13
+DRIVER.LIN.VAR.LIN_TOINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BAUDRATE.VALUE=20.000
+DRIVER.LIN.VAR.LIN_RX_MASK.VALUE=0x00
+DRIVER.LIN.VAR.LIN_ISFEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_RXINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_BASE.VALUE=0xFFF7E400
+DRIVER.LIN.VAR.LIN_FEINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TXINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.LIN.VAR.LIN_IDINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_TOINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_MAXBAUDRATE.VALUE=22.222
+DRIVER.LIN.VAR.LIN_BEINTENA.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_RXINTLVL.VALUE=0x00000000
+DRIVER.LIN.VAR.LIN_PRESCALE.VALUE=324
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=103936
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=2
+DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_HRSHARE.VALUE=0x00000008
+DRIVER.HET.VAR.HET2_INT_X1.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT29_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_IGNORE_SUSPEND_ENABLE.VALUE=0x00020000
+DRIVER.HET.VAR.HET2_PWM3_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_PWM1_PIN_SELECT.VALUE=10
+DRIVER.HET.VAR.HET2_BIT12_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT3_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X2.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X3.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=500.923
+DRIVER.HET.VAR.HET2_INT_X4.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_PWM0_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT4_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_PWM3_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT4_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X5.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_IGNORE_SUSPEND_ENABLE.VALUE=0x00020000
+DRIVER.HET.VAR.HET1_BIT30_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT26_HRSHARE.VALUE=0x00002000
+DRIVER.HET.VAR.HET1_BIT22_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT18_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.615
+DRIVER.HET.VAR.HET2_BIT3_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X6.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=12
+DRIVER.HET.VAR.HET1_BIT28_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT7_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X7.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT7_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X8.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT18_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT10_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X9.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM4_PIN_SELECT.VALUE=16
+DRIVER.HET.VAR.HET2_PWM4_DUTYTIME.VALUE=500.923
+DRIVER.HET.VAR.HET1_RAM_BASE.VALUE=0xFF460000
+DRIVER.HET.VAR.HET2_EDGE6_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_PWM2_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE2_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_BIT11_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PIN_ENABLE.VALUE=0
+DRIVER.HET.VAR.HET1_CAP3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT24_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT16_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT19_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE6_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT24_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT16_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT2_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE5_PIN_SELECT.VALUE=10
+DRIVER.HET.VAR.HET2_BIT13_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT27_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT19_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_CAP5_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_PWM4_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT8_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_CAP2_PIN_SELECT.VALUE=4
+DRIVER.HET.VAR.HET2_BIT4_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_BIT29_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT8_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_PERIOD_PRESCALER.VALUE=103936
+DRIVER.HET.VAR.HET2_BIT1_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM7_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_PRESCALER.VALUE=103936
+DRIVER.HET.VAR.HET2_BIT18_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_BIT16_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_BIT0_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_ACTUALPERIOD.VALUE=1000.615
+DRIVER.HET.VAR.HET2_BIT6_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP5_PIN_SELECT.VALUE=26
+DRIVER.HET.VAR.HET1_BIT28_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE7_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT1_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE5_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_PWM5_DUTY_PRESCALER.VALUE=52224
+DRIVER.HET.VAR.HET1_BIT3_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE7_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE1_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE4_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_BIT5_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_MASTER.VALUE=1
+DRIVER.HET.VAR.HET2_EDGE5_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT2_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_ACTUALPERIOD.VALUE=1000.615
+DRIVER.HET.VAR.HET1_BIT8_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_LR_ACTUALTIME.VALUE=1230.769
+DRIVER.HET.VAR.HET1_PWM5_DUTYTIME.VALUE=500.923
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM4_DUTY_PRESCALER.VALUE=52224
+DRIVER.HET.VAR.HET2_BIT9_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT5_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_PIN_SELECT.VALUE=18
+DRIVER.HET.VAR.HET2_BIT13_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE7_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_BIT17_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM0_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT30_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT19_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT14_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM1_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_BIT7_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_EDGE5_PIN_SELECT.VALUE=21
+DRIVER.HET.VAR.HET1_BIT29_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT0_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET_DIS_BLACKBOX.VALUE=0
+DRIVER.HET.VAR.HET2_PWM7_DUTYTIME.VALUE=500.923
+DRIVER.HET.VAR.HET2_HR_ACTUALFREQUENCY.VALUE=104.000
+DRIVER.HET.VAR.HET2_PWM5_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_ACTION.VALUE=3
+DRIVER.HET.VAR.HET1_BIT25_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT17_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT4_DIR.VALUE=0x00000010
+DRIVER.HET.VAR.HET2_EDGE0_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_CAP6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT20_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT15_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X10.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_INT_X11.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X20.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X12.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_PRESCALER.VALUE=103936
+DRIVER.HET.VAR.HET2_PWM6_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT16_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X21.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X13.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_HR_PRESCALE.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM6_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_LR_PRESCALE.VALUE=7
+DRIVER.HET.VAR.HET2_PWM0_PIN_SELECT.VALUE=8
+DRIVER.HET.VAR.HET2_BIT6_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X30.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X22.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X14.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X31.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X23.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X15.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_PERIOD_PRESCALER.VALUE=103936
+DRIVER.HET.VAR.HET2_INT_X24.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X16.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BASE_PORT.VALUE=0xFFF7B84C
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X25.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X17.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_PWM3_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X26.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X18.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X27.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X19.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT18_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X28.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_DUTY_PRESCALER.VALUE=52224
+DRIVER.HET.VAR.HET2_PWM0_DUTY.VALUE=50
+DRIVER.HET.VAR.HET2_BIT18_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_INT_X29.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_CAP7_PIN_SELECT.VALUE=6
+DRIVER.HET.VAR.HET2_BIT8_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET1_PWM4_ACTUALPERIOD.VALUE=1000.615
+DRIVER.HET.VAR.HET1_PWM3_PIN_SELECT.VALUE=14
+DRIVER.HET.VAR.HET1_BIT11_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT1_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM0_DUTYTIME.VALUE=500.923
+DRIVER.HET.VAR.HET2_BIT2_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE6_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_BIT5_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM6_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_BIT14_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT20_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PIN_ENABLE.VALUE=0
+DRIVER.HET.VAR.HET2_BIT16_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT5_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM0_DUTY_PRESCALER.VALUE=52224
+DRIVER.HET.VAR.HET1_BIT6_PULL.VALUE=1
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+DRIVER.HET.VAR.HET1_PWM0_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT8_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE4_PIN_SELECT.VALUE=8
+DRIVER.HET.VAR.HET2_BIT7_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT9_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_BIT10_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_CAP1_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE6_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP1_PIN_SELECT.VALUE=2
+DRIVER.HET.VAR.HET2_BIT15_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT13_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE3_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_PWM6_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_ENA.VALUE=0
+DRIVER.HET.VAR.HET2_BIT9_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE0_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_PRESCALER.VALUE=103936
+DRIVER.HET.VAR.HET1_BIT26_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT18_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT6_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE3_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT16_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP4_PIN_SELECT.VALUE=24
+DRIVER.HET.VAR.HET1_BIT29_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT0_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM2_PERIOD_PRESCALER.VALUE=103936
+DRIVER.HET.VAR.HET2_EDGE3_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_HRSHARE.VALUE=0x00000002
+DRIVER.HET.VAR.HET2_PWM6_PERIOD.VALUE=1000.000
+DRIVER.HET.VAR.HET2_BIT8_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_ACTUALPERIOD.VALUE=1000.615
+DRIVER.HET.VAR.HET1_BIT4_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_HRSHARE.VALUE=0x00000004
+DRIVER.HET.VAR.HET1_BIT25_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT17_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT16_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM1_DUTYTIME.VALUE=500.923
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM2_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM1_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_PWM7_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_PWM3_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT24_HRSHARE.VALUE=0x00001000
+DRIVER.HET.VAR.HET1_BIT16_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT10_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_PIN_SELECT.VALUE=17
+DRIVER.HET.VAR.HET1_BIT20_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT12_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_BIT3_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X10.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X11.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT3_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_EDGE7_BOTH.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE0_LVL.VALUE=0x00020000
+DRIVER.HET.VAR.HET1_BIT7_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X20.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X12.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM5_DUTY.VALUE=50
+DRIVER.HET.VAR.HET1_BIT10_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X21.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X13.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM5_ACTUALPERIOD.VALUE=1000.615
+DRIVER.HET.VAR.HET2_BIT18_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_EDGE4_PIN_SELECT.VALUE=20
+DRIVER.HET.VAR.HET1_INT_X30.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X22.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X14.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_PWM3_DUTYTIME.VALUE=500.923
+DRIVER.HET.VAR.HET1_INT_X31.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X23.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X15.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE5_EVENT.VALUE=1
+DRIVER.HET.VAR.HET2_PWM1_DUTY_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM7_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY_PRESCALER.VALUE=52224
+DRIVER.HET.VAR.HET1_BIT7_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_INT_X24.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X16.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_CAP2_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X25.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X17.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT9_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT5_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X26.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X18.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X27.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_INT_X19.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT11_PULL.VALUE=1
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+DRIVER.HET.VAR.HET2_PWM2_PERIOD_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_RAM_SIZE.VALUE=160
+DRIVER.HET.VAR.HET1_EDGE2_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET1_INT_X29.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT17_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_DOUT.VALUE=0
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+DRIVER.HET.VAR.HET2_CAP4_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_BIT8_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT4_PULDIS.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM4_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_PWM0_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_BIT4_PSL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_EDGE1_LVL.VALUE=0x00040000
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_LVL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT27_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT19_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT8_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT14_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_CAP6_PIN_SELECT.VALUE=4
+DRIVER.HET.VAR.HET1_PWM2_PIN_SELECT.VALUE=12
+DRIVER.HET.VAR.HET1_BIT1_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_PWM3_ACTION.VALUE=3
+DRIVER.HET.VAR.HET2_PWM2_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET1_EDGE4_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT28_XORSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT6_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE0_BOTH.VALUE=0
+DRIVER.HET.VAR.HET2_EDGE6_POLARITY.VALUE=0
+DRIVER.HET.VAR.HET2_PWM5_DUTY_INTENA.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT8_HRSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT4_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE3_PIN_SELECT.VALUE=6
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+DRIVER.HET.VAR.HET2_BIT18_PSL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT8_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT21_DOUT.VALUE=0
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+DRIVER.HET.VAR.HET1_BIT5_PSL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT9_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT6_ANDSHARE.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_PWM6_DUTY.VALUE=50
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+DRIVER.HET.VAR.HET2_BIT7_DOUT.VALUE=0
+DRIVER.HET.VAR.HET1_PWM7_ACTION.VALUE=3
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+DRIVER.HET.VAR.HET2_BIT12_ANDSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_CAP3_PIN_SELECT.VALUE=6
+DRIVER.HET.VAR.HET1_BIT7_PDR.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT26_ANDSHARE.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT15_DOUT.VALUE=0
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+DRIVER.HET.VAR.HET1_EDGE4_EVENT.VALUE=1
+DRIVER.HET.VAR.HET1_BIT20_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT12_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT12_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_PWM6_ENA.VALUE=0
+DRIVER.HET.VAR.HET1_BIT6_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_EDGE1_EVENT.VALUE=1
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+DRIVER.HET.VAR.HET1_PWM3_POLARITY.VALUE=3
+DRIVER.HET.VAR.HET2_PWM4_PIN_SELECT.VALUE=16
+DRIVER.HET.VAR.HET1_BIT10_PDR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT2_DOUT.VALUE=0
+DRIVER.HET.VAR.HET2_BIT9_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BASE.VALUE=0xFFF7B800
+DRIVER.HET.VAR.HET2_EDGE1_BOTH.VALUE=0
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+DRIVER.HET.VAR.HET1_PWM7_PIN_SELECT.VALUE=19
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+DRIVER.HET.VAR.HET1_LR_ACTUALTIME.VALUE=1230.769
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+DRIVER.HET.VAR.HET2_MASTER.VALUE=1
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+DRIVER.HET.VAR.HET1_BIT9_PULL.VALUE=1
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+DRIVER.HET.VAR.HET2_CAP5_PIN_SELECT.VALUE=2
+DRIVER.HET.VAR.HET1_PWM1_PIN_SELECT.VALUE=10
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+DRIVER.HET.VAR.HET2_LR_TIME.VALUE=800.000
+DRIVER.HET.VAR.HET1_INT_X3.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_INT_X7.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BASE_PORT.VALUE=0xFFF7B94C
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+DRIVER.HET.VAR.HET2_BASE.VALUE=0xFFF7B900
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+DRIVER.HET.VAR.HET1_BIT11_PSL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET1_BIT9_PSL.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_BIT0_DIR.VALUE=0x00000001
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+DRIVER.HET.VAR.HET2_BIT0_PULDIS.VALUE=0x00000000
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+DRIVER.HET.VAR.HET2_PWM6_ACTION.VALUE=3
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+DRIVER.HET.VAR.HET1_EDGE2_PIN_SELECT.VALUE=30
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+DRIVER.HET.VAR.HET1_BIT25_DIR.VALUE=0x00000000
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+DRIVER.RTP.VAR.RTP_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT1_DIR.VALUE=1
+DRIVER.RTP.VAR.RTP_PORT_BIT6_PULL.VALUE=2
+DRIVER.RTP.VAR.RTP_PORT_BIT0_FUN.VALUE=1
+DRIVER.RTP.VAR.RTP_PORT_BIT9_DOUT.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT2_DIR.VALUE=1
+DRIVER.RTP.VAR.RTP_PORT_BIT12_PULL.VALUE=2
+DRIVER.RTP.VAR.RTP_PORT_BIT16_PULDIS.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT15_DOUT.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT0_PDR.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT0_DOUT.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT1_FUN.VALUE=1
+DRIVER.RTP.VAR.RTP_BASE.VALUE=0xFFFFFA00
+DRIVER.RTP.VAR.RTP_PORT_BIT3_DIR.VALUE=1
+DRIVER.RTP.VAR.RTP_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT1_PDR.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT7_PULL.VALUE=2
+DRIVER.RTP.VAR.RTP_PORT_BIT2_FUN.VALUE=1
+DRIVER.RTP.VAR.RTP_PORT_BIT0_PSL.VALUE=1
+DRIVER.RTP.VAR.RTP_PORT_BIT4_DIR.VALUE=0
+DRIVER.RTP.VAR.RTP_BASE_RAM.VALUE=0xFFF83000
+DRIVER.RTP.VAR.RTP_PORT_BIT13_PULL.VALUE=2
+DRIVER.RTP.VAR.RTP_PORT_BIT10_DIR.VALUE=1
+DRIVER.RTP.VAR.RTP_PORT_BIT16_DOUT.VALUE=0
+DRIVER.RTP.VAR.RTP_PORT_BIT2_PDR.VALUE=0
+DRIVER.USB.VAR.USB1_MANUFACTURING_STRING_COUNT.VALUE=1
+DRIVER.USB.VAR.USB1_MANUFACTURING_STRING.VALUE=0
+DRIVER.USB.VAR.USB1_SERIAL_NUM_STRING_COUNT.VALUE=1
+DRIVER.USB.VAR.USB1_CONTROL_INTERFACE_STRING_COUNT.VALUE=1
+DRIVER.USB.VAR.USB1_POWER_TYPE.VALUE=USB_CONF_ATTR_SELF_PWR
+DRIVER.USB.VAR.USB1_LANGUAGE.VALUE=USB_LANG_EN_UK
+DRIVER.USB.VAR.USB1_VENDORID.VALUE=0x0000
+DRIVER.USB.VAR.USB1_CONFIG_STRING_COUNT.VALUE=1
+DRIVER.USB.VAR.USB_BASE.VALUE=0xFCF78A00
+DRIVER.USB.VAR.USB1_CONTROL_INTERFACE_STRING.VALUE=0
+DRIVER.USB.VAR.USB1_CONFIG_STRING.VALUE=0
+DRIVER.USB.VAR.USB1_CDC.VALUE=1
+DRIVER.USB.VAR.USB1_PRODUCT_STRING_COUNT.VALUE=1
+DRIVER.USB.VAR.USB1_PRODUCTID.VALUE=0x0000
+DRIVER.USB.VAR.USB1_PRODUCT_STRING.VALUE=0
+DRIVER.USB.VAR.USB1_UART_BUFFER_SIZE.VALUE=0x0001
+DRIVER.USB.VAR.USB1_SERIAL_NUM_STRING.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT17_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT4_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT1_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT0_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT2_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT7_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT18_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT0_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_BASE.VALUE=0xFFFFF700
+DRIVER.DMM.VAR.DMM_PORT_BIT1_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT9_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT2_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT0_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT5_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT4_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT3_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_BASE_PORT.VALUE=0xFFFFF770
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT5_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT10_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT6_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT7_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT9_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT0_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT7_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT6_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT4_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT8_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT7_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT10_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT7_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT5_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT1_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT9_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT12_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT7_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT10_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT12_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT9_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT7_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT2_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT13_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT9_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT9_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT12_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT14_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT0_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT9_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT14_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT11_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT8_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT14_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT16_DIR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT1_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT4_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT15_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT15_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT12_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT17_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT16_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT14_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT18_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT2_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT6_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT5_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT13_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT16_DOUT.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PULDIS.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT18_FUN.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PSL.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PULL.VALUE=2
+DRIVER.DMM.VAR.DMM_PORT_BIT0_DIR.VALUE=1
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PDR.VALUE=0
+DRIVER.DMM.VAR.DMM_PORT_BIT6_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_DIR.VALUE=0
+DRIVER.I2C.VAR.I2C_STOPBITS.VALUE=2
+DRIVER.I2C.VAR.I2C_PORT_BIT1_DIR.VALUE=0
+DRIVER.I2C.VAR.I2C_ICXRDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_BASE_PORT.VALUE=0xFFF7D44C
+DRIVER.I2C.VAR.I2C_DATACOUNT.VALUE=8
+DRIVER.I2C.VAR.I2C_ADDRMODE.VALUE=7BIT_AMODE
+DRIVER.I2C.VAR.I2C_PORT_BIT0_FUN.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PDR.VALUE=1
+DRIVER.I2C.VAR.I2C_BC_VALUE.VALUE=0x0003
+DRIVER.I2C.VAR.I2C_PORT_BIT1_FUN.VALUE=0
+DRIVER.I2C.VAR.I2C_RM_ENA.VALUE=1
+DRIVER.I2C.VAR.I2C_BC.VALUE=8_BIT
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PDR.VALUE=1
+DRIVER.I2C.VAR.I2C_TXRX_VALUE.VALUE=0
+DRIVER.I2C.VAR.I2C_SCDLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PSL.VALUE=1
+DRIVER.I2C.VAR.I2C_STPCND.VALUE=1
+DRIVER.I2C.VAR.I2C_ALINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PRESCALE.VALUE=12
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PSL.VALUE=1
+DRIVER.I2C.VAR.I2C_TXRX.VALUE=TRANSMITTER
+DRIVER.I2C.VAR.I2C_PORT_BIT0_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_ALINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_RXDMA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PULDIS.VALUE=0
+DRIVER.I2C.VAR.I2C_BASE.VALUE=0xFFF7D400
+DRIVER.I2C.VAR.I2C_ARDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT1_DOUT.VALUE=0
+DRIVER.I2C.VAR.I2C_TXDMA.VALUE=0
+DRIVER.I2C.VAR.I2C_MSMODE.VALUE=1
+DRIVER.I2C.VAR.I2C_ICCH.VALUE=35
+DRIVER.I2C.VAR.I2C_AASLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_ICCL.VALUE=35
+DRIVER.I2C.VAR.I2C_AAS.VALUE=0
+DRIVER.I2C.VAR.I2C_BCM.VALUE=0
+DRIVER.I2C.VAR.I2C_ADDRMODE_VALUE.VALUE=0x0001
+DRIVER.I2C.VAR.I2C_ICRRDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_FDF.VALUE=0
+DRIVER.I2C.VAR.I2C_ARDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_PARITYENA.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PULL.VALUE=2
+DRIVER.I2C.VAR.I2C_LENGTH.VALUE=8
+DRIVER.I2C.VAR.I2C_NACKINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_SCD.VALUE=0
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PULL.VALUE=2
+DRIVER.I2C.VAR.I2C_ICRRDYINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_STACND.VALUE=1
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PULDIS.VALUE=0
+DRIVER.I2C.VAR.I2C_ICXRDYINTENA.VALUE=0
+DRIVER.I2C.VAR.I2C_NACKINTLVL.VALUE=0
+DRIVER.I2C.VAR.I2C_EVENPARITY.VALUE=0
+DRIVER.I2C.VAR.I2C_BAUDRATE.VALUE=100
+DRIVER.I2C.VAR.I2C_MODCLK.VALUE=8
+DRIVER.DCC.VAR.DCC1_ENABLE_KEY.VALUE=10
+DRIVER.DCC.VAR.PINMUX_BASE.VALUE=0xFFFFEA00
+DRIVER.DCC.VAR.DCC1_DETECTION_TIME.VALUE=2500.00
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_VALUE.VALUE=0x0002
+DRIVER.DCC.VAR.DCC1_ENABLE_ERROR_INTERRUPT.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40
+DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0
+DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0
+DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=2500.00
+DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002
+DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1
+DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0
+DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792
+DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00
+DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=208.00
+DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0
+DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5
+DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5
+DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400
+DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA
+DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0xA
+DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=39204
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1
+DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0
+DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=514800
+DRIVER.PINMUX.VAR.DMA_EIDXS_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_2.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_3.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=1
+DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_4.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_4.VALUE=0
+DRIVER.PINMUX.VAR.ETPWM_TIME_BASE_SELECT.VALUE=OFF
+DRIVER.PINMUX.VAR.MUX61_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX50_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_5.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_5.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_6.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_6.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_7.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_7.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_8.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX99_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_96_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_88_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_5_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_9.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=1
+DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_57_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_49_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX30_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX30_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_18_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_10.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_4.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX10.VALUE=PINMUX_PIN_86_AD1EVT
+DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=2
+DRIVER.PINMUX.VAR.DMA_PRITY_11.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_CHPR_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX11.VALUE=PINMUX_PIN_91_HET1_24
+DRIVER.PINMUX.VAR.DMA_PRITY_12.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX20.VALUE=PINMUX_PIN_130_MIBSPI1NCS_1
+DRIVER.PINMUX.VAR.PINMUX12.VALUE="PINMUX_PIN_92_HET1_26 | PINMUX_PIN_96_MIBSPI1NENA | PINMUX_PIN_97_MIBSPI5NENA"
+DRIVER.PINMUX.VAR.DMA_PRITY_13.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX21.VALUE=PINMUX_PIN_133_GIOB_1
+DRIVER.PINMUX.VAR.PINMUX13.VALUE="PINMUX_PIN_98_MIBSPI5SOMI_0 | PINMUX_PIN_99_MIBSPI5SIMO_0 | PINMUX_PIN_100_MIBSPI5CLK | PINMUX_PIN_105_MIBSPI1NCS_0"
+DRIVER.PINMUX.VAR.DMA_PRITY_14.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX14.VALUE="PINMUX_PIN_106_HET1_08 | PINMUX_PIN_107_HET1_28"
+DRIVER.PINMUX.VAR.MUX92_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_15.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_PRITY_16.VALUE=FIXED
+DRIVER.PINMUX.VAR.PINMUX33.VALUE="PINMUX_PIN_36_HET1_04 | PINMUX_PIN_51_MIBSPI3SOMI | PINMUX_PIN_52_MIBSPI3SIMO | PINMUX_PIN_53_MIBSPI3CLK"
+DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_PIN_118_HET1_10 | PINMUX_PIN_124_HET1_12"
+DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_HET1_18 | PINMUX_PIN_141_HET1_20"
+DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_PIN_125_HET1_14 | PINMUX_PIN_126_GIOB_0"
+DRIVER.PINMUX.VAR.DMA_ADDMR_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX35.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX27.VALUE=PINMUX_PIN_32_MIBSPI5NCS_0
+DRIVER.PINMUX.VAR.PINMUX19.VALUE=PINMUX_PIN_127_HET1_30
+DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_10.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX98_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_11.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_PRITY_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX98_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_20.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_12.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX100_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX98_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_21.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_13.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX100_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_30.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_22.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_14.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_0.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX100_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_109_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_31.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_23.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_15.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_1.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX100_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_24.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_16.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_2.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX100_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX91_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_25.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_17.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_3.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX91_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_26.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_18.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_4.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX91_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX61_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX53_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX45_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX37_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_102_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_27.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_19.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_5.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMR_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX91_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_28.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_6.VALUE=ENABLED
+DRIVER.PINMUX.VAR.ETPWM2_EQEPERR12.VALUE=EQEPERR12
+DRIVER.PINMUX.VAR.MUX91_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_29.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_FIDXS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_7.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXS_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_8.VALUE=ENABLED
+DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_9.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_10.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_10.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_11.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX60_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_20.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_12.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_21.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_13.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_13.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_30.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_22.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_14.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_14.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TTYPE_31.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_23.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_15.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_STADD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_24.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_16.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_25.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_17.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_26.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_18.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_STADD_4.VALUE=0
+DRIVER.PINMUX.VAR.MUX30_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX22_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_71_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_63_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_55_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_47_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_39_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_27.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_19.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX21_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_28.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_28.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_29.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_29.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_2.VALUE=0
+DRIVER.PINMUX.VAR.ETPWM7_EQEPERR12.VALUE=EQEPERR12
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_0.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.ETPWM_TBCLK_SELECT.VALUE=OFF
+DRIVER.PINMUX.VAR.DMA_TTYPE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_1.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_2.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_3.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_4.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_5.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_6.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_7.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_8.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMR_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_9.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5.VALUE=8BIT
+DRIVER.PINMUX.VAR.GATE_EMIF_CLK.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMW_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX97_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX97_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_107_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX90_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_DEBUGMODE.VALUE=IGNORE_SUSPEND
+DRIVER.PINMUX.VAR.MUX90_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_0.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ERRACT.VALUE=IGNORE
+DRIVER.PINMUX.VAR.MUX90_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_100_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_1.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHPR_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX90_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_2.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_BASE_PORT.VALUE=0xFFFFF040
+DRIVER.PINMUX.VAR.MUX90_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ADDMW_3.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.MUX58_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_4.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.MUX5_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_5.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX5_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_6.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_7.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_8.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_10.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=2
+DRIVER.PINMUX.VAR.DMA_ADDMR_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_9.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTEN_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.ALT_ADC_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.MUX98_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_92_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_84_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_76_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_68_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_1_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTEN_16.VALUE=1
+DRIVER.PINMUX.VAR.MUX20_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_61_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_53_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_45_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_37_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TTYPE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX20_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX20_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX100_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_30_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_22_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.PIN_MUX_14_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX10_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ENDADD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENDADD_4.VALUE=0
+DRIVER.PINMUX.VAR.ETHERNET_SELECT.VALUE=RMII
+DRIVER.PINMUX.VAR.MUX91_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX83_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX75_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX67_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX59_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTASS_1.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_INTASS_2.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.ETPWM5_EQEPERR12.VALUE=EQEPERR12
+DRIVER.PINMUX.VAR.CONCOUNT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTASS_3.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_INTASS_4.VALUE=TO_VIM
+DRIVER.PINMUX.VAR.DMA_ADDMR_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ACC_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_10.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_4.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_11.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMW_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_INTMP_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX96_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_20.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_12.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_6.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_21.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_13.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_30.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_22.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_14.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHAS_8.VALUE=0
+DRIVER.PINMUX.VAR.GIOB_DISABLE_SELECT.VALUE=OFF
+DRIVER.PINMUX.VAR.PIN_MUX_105_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_31.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_23.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMW_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_15.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_ADDMR_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_TRIG_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_24.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_16.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX81_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_25.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_17.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX81_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_26.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_18.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX60_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX52_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX44_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX36_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXS_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_27.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_FIDXS_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_19.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ENABLE1.VALUE=1
+DRIVER.PINMUX.VAR.MUX81_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_28.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_2.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXS_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_29.VALUE=ENABLED
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_10.VALUE=1
+DRIVER.PINMUX.VAR.ECAP.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX4_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX18_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX50_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_97_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_89_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ADDMR_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_1.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_BYP_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_2.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_3.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX50_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX42_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX34_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX18_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.DMA_PRITY_4.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX103_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_90_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_82_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_74_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_66_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_58_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_5.VALUE=FIXED
+DRIVER.PINMUX.VAR.DMA_PRITY_6.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_7.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_8.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX21_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX13_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=1
+DRIVER.PINMUX.VAR.PIN_MUX_51_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_43_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_35_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_27_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=4
+DRIVER.PINMUX.VAR.DMA_TTYPE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_9.VALUE=FIXED
+DRIVER.PINMUX.VAR.MUX11_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.ETPWM_TBCLK_SYNC_ENABLE.VALUE=0
+DRIVER.PINMUX.VAR.AD1.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.AD2.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_20_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_12_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX9_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX104_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_PRITY_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.ALT_ADC.VALUE=0
+DRIVER.PINMUX.VAR.I2C.VALUE=1
+DRIVER.PINMUX.VAR.MUX104_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX104_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX95_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX71_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_DEBUGMODE_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX95_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.ETPWM3_EQEPERR12.VALUE=EQEPERR12
+DRIVER.PINMUX.VAR.MUX95_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX87_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX79_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_10.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_103_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_13.VALUE=0
+DRIVER.PINMUX.VAR.HET1.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_10.VALUE=0
+DRIVER.PINMUX.VAR.HET2.VALUE=0
+DRIVER.PINMUX.VAR.MUX80_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_1.VALUE=1
+DRIVER.PINMUX.VAR.MUX80_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_2.VALUE=1
+DRIVER.PINMUX.VAR.MUX80_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX72_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX64_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX56_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_3.VALUE=1
+DRIVER.PINMUX.VAR.MUX56_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX48_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_EIDXD_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_10.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX3_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_11.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_AIM_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTASS_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX3_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_20.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_12.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_6.VALUE=1
+DRIVER.PINMUX.VAR.EMIF.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_21.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_13.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTEN_7.VALUE=1
+DRIVER.PINMUX.VAR.ETPWM_TZ1.VALUE=ASYNC
+DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_22.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_14.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_8.VALUE=1
+DRIVER.PINMUX.VAR.ETPWM_TZ2.VALUE=ASYNC
+DRIVER.PINMUX.VAR.MUX41_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX40_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_95_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_87_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_79_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_4_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ADDMR_31.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_23.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_15.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMR_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.ETPWM_TZ3.VALUE=ASYNC
+DRIVER.PINMUX.VAR.MUX41_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_24.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_16.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_12.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_25.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_17.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_13.VALUE=0
+DRIVER.PINMUX.VAR.MUX41_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX33_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_26.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_18.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX97_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX89_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_80_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_72_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_64_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_56_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_48_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_27.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_19.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_ADDMW_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.GIOA.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ADDMR_28.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12.VALUE=8BIT
+DRIVER.PINMUX.VAR.GIOB.VALUE=0
+DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ADDMR_29.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13.VALUE=8BIT
+DRIVER.PINMUX.VAR.GIOB_DISABLE.VALUE=0
+DRIVER.PINMUX.VAR.MUX10_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX10_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_28.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_29.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17.VALUE=8BIT
+DRIVER.PINMUX.VAR.MUX10_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18.VALUE=8BIT
+DRIVER.PINMUX.VAR.PIN_MUX_10_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_BYP_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_4.VALUE=1
+DRIVER.PINMUX.VAR.EQEP.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BYP_8.VALUE=1
+DRIVER.PINMUX.VAR.MUX90_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX82_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX74_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX66_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX58_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BYP_9.VALUE=1
+DRIVER.PINMUX.VAR.MIBSPI1.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MIBSPI3.VALUE=1
+DRIVER.PINMUX.VAR.MUX103_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.OHCI0.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MIBSPI5.VALUE=0
+DRIVER.PINMUX.VAR.DMM.VALUE=0
+DRIVER.PINMUX.VAR.W2FC.VALUE=1
+DRIVER.PINMUX.VAR.OHCI1.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX103_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_108_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX94_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX94_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX86_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX78_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_10.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=1
+DRIVER.PINMUX.VAR.PIN_MUX_101_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_11.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_PRITY_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX9_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_12.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_13.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_10.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_14.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX51_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX43_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX35_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_11.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_15.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX71_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_20.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_12.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_16.VALUE=HIGH
+DRIVER.PINMUX.VAR.ETPWM1_EQEPERR12.VALUE=EQEPERR12
+DRIVER.PINMUX.VAR.MUX71_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.DMA_ADDMW_21.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_13.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_3.VALUE=0
+DRIVER.PINMUX.VAR.MUX63_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX55_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX47_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX39_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_30.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_22.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_14.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_EIDXD_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_10.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX2_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=2
+DRIVER.PINMUX.VAR.DMA_ADDMW_31.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_23.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_15.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_CHANNEL_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXD_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_11.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX2_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_24.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_16.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_12.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX40_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_25.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_17.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_13.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.MUX40_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_26.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_18.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_14.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_93_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_85_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_77_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_69_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_2_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_27.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_ADDMW_19.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_15.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_PRITY_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX40_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_28.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_TRIG_16.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_29.VALUE=CONSTANT
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.MUX40_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX32_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX16_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_10.VALUE=1
+DRIVER.PINMUX.VAR.MUX102_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_70_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_62_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_54_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_46_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_38_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_11.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ERRACT_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MII.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_12.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_13.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_14.VALUE=1
+DRIVER.PINMUX.VAR.GATE_EMIF_CLK_SELECT.VALUE=OFF
+DRIVER.PINMUX.VAR.MUX20_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=2
+DRIVER.PINMUX.VAR.DMA_ADDMW_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_15.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHPR_1.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_16.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_2.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_CHPR_3.VALUE=HIGH
+DRIVER.PINMUX.VAR.ETPWM_TIME_BASE_SYNC_ENABLE.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_10.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_4.VALUE=HIGH
+DRIVER.PINMUX.VAR.MUX93_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_29_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_11.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_5.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_1.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.ETPWM_EPWM1SYNCI.VALUE=ASYNC
+DRIVER.PINMUX.VAR.DMA_INTMP_12.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_6.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_2.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.ETPWM6_EQEPERR12.VALUE=EQEPERR12
+DRIVER.PINMUX.VAR.DMA_INTMP_13.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_7.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_3.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTMP_14.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_8.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_4.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_CHANNEL_28_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_6_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_15.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_CHPR_9.VALUE=HIGH
+DRIVER.PINMUX.VAR.DMA_TRIG_5.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_1.VALUE=1
+DRIVER.PINMUX.VAR.SCI.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_16.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_TRIG_6.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_7.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_TRIG_8.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_4.VALUE=1
+DRIVER.PINMUX.VAR.MUX8_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_9_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_9.VALUE=HARDWARE_TRIGGER
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_1.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_6.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_2.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ENABLEPAR.VALUE=1
+DRIVER.PINMUX.VAR.MUX102_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_7.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_3.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX102_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_8.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_4.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX102_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_CHPR_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_5.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_TRIG_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_1.VALUE=ALL
+DRIVER.PINMUX.VAR.ETPWM.VALUE=1
+DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_6.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_2.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX102_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX93_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_7.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_3.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX93_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTMP_8.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.DMA_ACC_4.VALUE=ALL
+DRIVER.PINMUX.VAR.MUX93_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_106_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_0_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTMP_9.VALUE=GROUP_A
+DRIVER.PINMUX.VAR.MUX93_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX93_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX85_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX77_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=1
+DRIVER.PINMUX.VAR.DMA_BASE.VALUE=0xFFFFF000
+DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX38_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_20_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_12_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX70_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX70_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX62_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX54_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX46_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX38_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_98_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_7_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=1
+DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=1
+DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_75_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_67_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_59_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TRIG_8_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX31_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX31_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX23_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX96_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX88_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_60_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_52_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_44_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_36_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_28_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_0.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_21_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_13_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMW_10_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMR_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHPR_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_PRITY_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_BASE_RAM.VALUE=0xFFF80000
+DRIVER.PINMUX.VAR.DMA_EIDXS_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_25_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_AIM_17_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TTYPE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_5.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_1.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_6.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_2.VALUE=1
+DRIVER.PINMUX.VAR.SPI2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_7.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_3.VALUE=1
+DRIVER.PINMUX.VAR.DMA_FIDXD_8.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_4.VALUE=1
+DRIVER.PINMUX.VAR.SPI4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_24_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_16_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_9.VALUE=0
+DRIVER.PINMUX.VAR.DMA_AIM_2_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHAS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_5.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTASS_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.RMII.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHAS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_6.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_I2C_SCL | PINMUX_PIN_4_I2C_SDA"
+DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_7.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_MIBSPI3NCS_4"
+DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_8.VALUE=1
+DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_ETPWM1A"
+DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX65_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX57_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.MUX49_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_PRITY_14_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_9.VALUE=1
+DRIVER.PINMUX.VAR.DMA_INTMP_5_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ACC_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_PIN_15_W2FC_SE0O | PINMUX_PIN_16_GIOA_6"
+DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12.VALUE=8BIT
+DRIVER.PINMUX.VAR.ETPWM4_EQEPERR12.VALUE=EQEPERR12
+DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_PIN_22_ETPWM2A | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03"
+DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT
+DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_HET1_05"
+DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_0.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_ETPWM7A"
+DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_1_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_1.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHPR_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.ALT_ADC_A.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX7.VALUE="PINMUX_PIN_37_MIBSPI3NCS_1 | PINMUX_PIN_38_SCIRX"
+DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_20.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_12.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_2.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.ALT_ADC_B.VALUE=0
+DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_PIN_39_SCITX | PINMUX_PIN_40_MIBSPI1NCS_2 | PINMUX_PIN_41_HET1_15"
+DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_21.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_13.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_3.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_PIN_54_MIBSPI3NCS_5 | PINMUX_PIN_55_MIBSPI3NCS_0"
+DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_30.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_22.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_14.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_4.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX92_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX4_CONFLICT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_104_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_31.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_31_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_23.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_23_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_15.VALUE=0
+DRIVER.PINMUX.VAR.DMA_ADDMW_15_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_ADDMR_7_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_CHANNEL_5.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_4_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_TRIG_11_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.MUX92_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION3.VALUE=0
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_24.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_16.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_6.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX92_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29.VALUE=8BIT
+DRIVER.PINMUX.VAR.DMA_EIDXS_25.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_17.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_7.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.MUX7_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_26.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_18.VALUE=0
+DRIVER.PINMUX.VAR.DMA_FIDXD_10.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_8.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_0.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_0.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.DMA_EIDXS_27.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_27_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_EIDXS_19.VALUE=0
+DRIVER.PINMUX.VAR.DMA_TTYPE_19_VALUE.VALUE=0x0001
+DRIVER.PINMUX.VAR.DMA_FIDXD_11.VALUE=0
+DRIVER.PINMUX.VAR.DMA_CHANNEL_9.VALUE=CHANNEL0
+DRIVER.PINMUX.VAR.DMA_TTYPE_1.VALUE=FRAME_TRANSFER
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_1.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION3.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_PSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_CPB_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_PSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_TRDIR_1.VALUE=HET_TO_MAIN_MEM
+DRIVER.CRC.VAR.CRC_CH1_CCI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPBL_7_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DEBMOD_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_CFI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPAL_1_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ENABUS_1.VALUE=0
+DRIVER.CRC.VAR.HTU_CPA_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_WDTO.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_CCI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP1_ACC_1.VALUE=READ_ONLY
+DRIVER.CRC.VAR.HTU_CONTPAR_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_CFI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPB_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DCP0_EC_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_CPBFULADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPAL_6_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_DTE.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_FC_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_CVH.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PSSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_BASE.VALUE=0xFFF7A400
+DRIVER.CRC.VAR.CRC_CH1_CVL.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PSSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_3_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_DTE.VALUE=1
+DRIVER.CRC.VAR.CRC_CH2_CVH.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_CVL.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH1_PCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPA_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_SCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_DCP0_CPAFULADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPAL_2_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH2_PCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CPA_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_PSA.VALUE=1
+DRIVER.CRC.VAR.CRC_CH1_ORI.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_SCP.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP1_STADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH1_TOE.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPAL_7_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH2_PSA.VALUE=1
+DRIVER.CRC.VAR.CRC_CH2_ORI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CPB_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_MP0_ENA_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_MODE_VALUE.VALUE=0x0001
+DRIVER.CRC.VAR.CRC_CH1_URI.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_PSSIH.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_TOE.VALUE=0x00000000
+DRIVER.CRC.VAR.CRC_CH2_PSSIL.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_BCTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_ICPBL_4_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_PAR_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH2_URI.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_CONT_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ENAREQ_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP1_ERRENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_STADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPA_7_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_3_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_BCTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_DCP0_MMADD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.HTU_ENAINTMAP_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_MODE_VALUE.VALUE=0x0001
+DRIVER.CRC.VAR.HTU_ICPBL_0_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPB_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_MP1_ENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_HETADD.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_5_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_3_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPA_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_RES_1.VALUE=0
+DRIVER.CRC.VAR.HTU_DCP0_CPATMOD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.HTU_MP1_ENDADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_BASE.VALUE=0xFE000000
+DRIVER.CRC.VAR.HTU_ICPAL_4_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.CRC_CH1_MODE.VALUE=FULL_CPU
+DRIVER.CRC.VAR.HTU_CPA_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_VBHOLD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_ERRENA_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_1_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPB_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.CRC_CH2_MODE.VALUE=FULL_CPU
+DRIVER.CRC.VAR.HTU_DCP0_TRDAT_1.VALUE=32BIT
+DRIVER.CRC.VAR.HTU_ICPBL_6_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_4_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPB_0_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_0_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_CPA_1_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_DCP0_CPBTMOD_1.VALUE=POST_INCREMENT
+DRIVER.CRC.VAR.CRC_CH1_PSIH.VALUE=0
+DRIVER.CRC.VAR.HTU_MP0_ACC_1.VALUE=READ_ONLY
+DRIVER.CRC.VAR.CRC_CH1_PSIL.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPB_5_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ICPAL_5_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_DCP0_ADMOD_1.VALUE=INCREMENT_16BIT
+DRIVER.CRC.VAR.HTU_CPA_6_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_CPB_2_SEL_1.VALUE=ENABLE
+DRIVER.CRC.VAR.HTU_ENA_1.VALUE=0
+DRIVER.CRC.VAR.CRC_CH1_WDTO.VALUE=0x00000000
+DRIVER.CRC.VAR.HTU_MP0_ENDADD_1.VALUE=0
+DRIVER.CRC.VAR.HTU_ICPBL_2_SEL_1.VALUE=HIGH
+DRIVER.CRC.VAR.HTU_ICPA_0_SEL_1.VALUE=ENABLE
+DRIVER.EMAC.VAR.EMAC_ADD1.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD2.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD3.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD4.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD5.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_ADD6.VALUE=FF
+DRIVER.EMAC.VAR.EMAC_CTRL_BASE.VALUE=0xFCF78800
+DRIVER.EMAC.VAR.EMAC_LOOPBACK_ENA.VALUE=0
+DRIVER.EMAC.VAR.MDIO_BASE.VALUE=0xFCF78900
+DRIVER.EMAC.VAR.EMAC_BASE.VALUE=0xFCF78000
+DRIVER.EMAC.VAR.EMAC_BASE_PORT.VALUE=0xFFFFFFFF
+DRIVER.EMAC.VAR.EMAC_TRANSMIT_ENA.VALUE=1
+DRIVER.EMAC.VAR.EMAC_CHANNELNUMBER.VALUE=0
+DRIVER.EMAC.VAR.EMAC_RX_PBUF_ALLOC.VALUE=10
+DRIVER.EMAC.VAR.EMAC_UNICAST_ENA.VALUE=1
+DRIVER.EMAC.VAR.EMAC_FULL_DUPLEX_ENA.VALUE=1
+DRIVER.EMAC.VAR.EMAC_PHYADDRESS.VALUE=0
+DRIVER.EMAC.VAR.EMAC_MII_ENA.VALUE=1
+DRIVER.EMAC.VAR.EMAC_CTRL_RAM_BASE.VALUE=0xFC520000
+DRIVER.EMAC.VAR.EMAC_BROADCAST_ENA.VALUE=1
+DRIVER.EMAC.VAR.EMAC_RECEIVE_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TA.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TA.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ENA_SDRAM.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0
+DRIVER.EMIF.VAR.EMIF_AVAILABLE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=63
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1
+DRIVER.EMIF.VAR.EMIF_ASYNC1_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_BANKS.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_BASE.VALUE=0xFCFFE800
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=63
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=7
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_HOLD.VALUE=7
+DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_SETUP.VALUE=15
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=15
+DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_HOLD.VALUE=7
+DRIVER.EMIF.VAR.EMIF_SDRAM_INIT_TIME.VALUE=200
+DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_DEFAULT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TSU.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=15
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=63
+DRIVER.EMIF.VAR.EMIF_CLK.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=15
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_ASIZE.VALUE=8_bit
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_NOR_FLASH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_CAS_LATENCY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY0.VALUE=pin_low
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY1.VALUE=pin_high
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_SETUP.VALUE=15
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_STROBE.VALUE=63
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=15
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001
+DRIVER.EMIF.VAR.EMIF_NS.VALUE=0.000000001
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_EXTENDED_WAIT.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=7
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=63
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=7
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words
+DRIVER.EMIF.VAR.EMIF_ASYNC2_WAIT.VALUE=pin0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHEL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_VAL.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_HOLD.VALUE=7
+DRIVER.EMIF.VAR.EMIF_SDRAM_PAGE_SIZE.VALUE=elements_256
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TELEH.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY.VALUE=0
+DRIVER.EMIF.VAR.EMIF_IBANK.VALUE=0
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_STROBE.VALUE=63
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TA.VALUE=0
+DRIVER.POM.VAR.POM_OVRLY_START_ADD28.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD29.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_10_ENA.VALUE=0
+DRIVER.POM.VAR.POM_TIMEOUT_ENABLE.VALUE=0
+DRIVER.POM.VAR.POM_REGION_11_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_20_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_12_ENA.VALUE=0
+DRIVER.POM.VAR.POM_NO_OF_REGION.VALUE=1
+DRIVER.POM.VAR.POM_REGION_21_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_13_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_30_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_22_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_14_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_31_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_23_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_15_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_1_ENA.VALUE=1
+DRIVER.POM.VAR.POM_REGION_32_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_24_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_16_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_2_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_25_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_17_ENA.VALUE=0
+DRIVER.POM.VAR.POM_OVRLY_START_ADD1.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD2.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD3.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD4.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD5.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD6.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD7.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD8.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVLY_TRG_REGION.VALUE=INTERNAL_RAM
+DRIVER.POM.VAR.POM_OVRLY_START_ADD9.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_3_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_26_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_18_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_4_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_27_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_19_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_5_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_28_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_6_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_SIZE10.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE11.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE20.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE12.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_29_ENA.VALUE=0
+DRIVER.POM.VAR.POM_REGION_SIZE21.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE13.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE30.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE22.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE14.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE31.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE23.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE15.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE32.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE24.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE16.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE25.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE17.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE26.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE18.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE27.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE19.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE28.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE29.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_7_ENA.VALUE=0
+DRIVER.POM.VAR.POM_BASE.VALUE=0xFFA04000
+DRIVER.POM.VAR.POM_PROG_START_ADD10.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD11.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD20.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD12.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD21.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD13.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_8_ENA.VALUE=0
+DRIVER.POM.VAR.POM_PROG_START_ADD30.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD22.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD14.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD31.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD23.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD15.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD32.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD24.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD16.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD25.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD17.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD26.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD18.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD27.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD19.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE1.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_PROG_START_ADD28.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE2.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_PROG_START_ADD29.VALUE=0x00000000
+DRIVER.POM.VAR.POM_REGION_SIZE3.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE4.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE5.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE6.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE7.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE8.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_SIZE9.VALUE=SIZE_64BYTES
+DRIVER.POM.VAR.POM_REGION_9_ENA.VALUE=0
+DRIVER.POM.VAR.POM_PROG_START_ADD1.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD2.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD3.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD4.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD5.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD6.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD7.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD8.VALUE=0x00000000
+DRIVER.POM.VAR.POM_PROG_START_ADD9.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD10.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD11.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD20.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD12.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD21.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD13.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD30.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD22.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD14.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD31.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD23.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD15.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD32.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD24.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD16.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD25.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD17.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD26.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD18.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD27.VALUE=0x00000000
+DRIVER.POM.VAR.POM_OVRLY_START_ADD19.VALUE=0x00000000
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN2_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN5_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN3_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN3_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN1_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=40000
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_CLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_SOCA_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_INPUT.VALUE=PWMA_RED_FED
+DRIVER.ETPWM.VAR.ETPWM7_BASE.VALUE=0xFCF79200
+DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=103.335
+DRIVER.ETPWM.VAR.ETPWM6_DCBEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_DCBEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCA.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CBC.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCB.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM6_RDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0
+DRIVER.ETPWM.VAR.ETPWM7_SOCB_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_SOCB_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_MODE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=250000.000
+DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCA.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCB.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM5_DCAEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_DCAEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=38.462
+DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_OSHT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_OSHT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_SOCB_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_OSHT3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=503.218
+DRIVER.ETPWM.VAR.ETPWM3_CBC.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=103.335
+DRIVER.ETPWM.VAR.ETPWM1_FDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_OSHT4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_OSHT5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_OSHT6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_INPUT.VALUE=PWMA_RED_FED
+DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCA.VALUE=DCAEVT1
+DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCB.VALUE=DCBEVT1
+DRIVER.ETPWM.VAR.ETPWM6_SELECT_EVENT.VALUE=NO_EVENT
+DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM5_DCBEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_MODE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_CLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_TB_FREQUENCY.VALUE=110.000
+DRIVER.ETPWM.VAR.ETPWM4_CBC.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCA.VALUE=DCAEVT1
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCB.VALUE=DCBEVT1
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
+DRIVER.ETPWM.VAR.ETPWM6_FDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_RDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=38.709
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM3_SELECT_EVENT.VALUE=NO_EVENT
+DRIVER.ETPWM.VAR.ETPWM2_CLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=40000.000
+DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_INPUT.VALUE=PWMA_RED_FED
+DRIVER.ETPWM.VAR.ETPWM5_CBC.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CBC1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CBC2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CBC3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME_REG.VALUE=3
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_CBC4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CBC5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CBC6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_DCAEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=25999
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME_REG.VALUE=3
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_MODE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000
+DRIVER.ETPWM.VAR.ETPWM4_DCAEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=104.000
+DRIVER.ETPWM.VAR.ETPWM3_TB_FREQUENCY.VALUE=110.000
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME_REG.VALUE=3
+DRIVER.ETPWM.VAR.ETPWM2_OSHT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_INTERRUPT_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_OSHT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_OSHT3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_OSHT4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME_REG.VALUE=3
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_OSHT5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM2_OSHT6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_CBC.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=38.709
+DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM4_DCBEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_SOCA_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_DCBEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM7_OSHT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM7_OSHT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM7_CBC.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_OSHT3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_CBC1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_OSHT4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_CBC2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_OSHT5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_CBC3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_CLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_OSHT6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_SOCA_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_CLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_CBC6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_INPUT.VALUE=PWMA_RED_FED
+DRIVER.ETPWM.VAR.ETPWM6_INTERRUPT_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCA.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM1_BASE.VALUE=0xFCF78C00
+DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCB.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
+DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=104.000
+DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=76.923
+DRIVER.ETPWM.VAR.ETPWM6_SOCB_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=38.462
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_DCAEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_DCAEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_OST.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCA.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCB.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM5_RDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=503.218
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=25999
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_SOCB_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_CBC1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_SELECT_EVENT.VALUE=NO_EVENT
+DRIVER.ETPWM.VAR.ETPWM3_CBC2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_DCBEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_CBC3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_INTERRUPT_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM3_OST.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_DCBEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_CBC4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_INPUT.VALUE=PWMA_RED_FED
+DRIVER.ETPWM.VAR.ETPWM3_CBC5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_CBC6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM2_BASE.VALUE=0xFCF78D00
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY_NEW.VALUE=50.0
+DRIVER.ETPWM.VAR.ETPWM7_CLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_MODE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_OSHT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_OSHT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_TB_FREQUENCY.VALUE=110.000
+DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCA.VALUE=DCAEVT1
+DRIVER.ETPWM.VAR.ETPWM3_OSHT3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=38.709
+DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCB.VALUE=DCBEVT1
+DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=76.923
+DRIVER.ETPWM.VAR.ETPWM3_OSHT4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM3_OSHT5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM3_OSHT6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=103.335
+DRIVER.ETPWM.VAR.ETPWM5_CLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_OST.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCA.VALUE=DCAEVT1
+DRIVER.ETPWM.VAR.ETPWM4_SELECT_EVENT.VALUE=NO_EVENT
+DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCB.VALUE=DCBEVT1
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=40000.000
+DRIVER.ETPWM.VAR.ETPWM2_DCAEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_INTERRUPT_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_DCAEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_CBC1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM4_CBC2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_CBC3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_MODE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=40000
+DRIVER.ETPWM.VAR.ETPWM5_OST.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_CBC4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_CBC5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_TB_FREQUENCY.VALUE=110.000
+DRIVER.ETPWM.VAR.ETPWM4_CBC6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY_NEW.VALUE=50.0
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_FDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_BASE.VALUE=0xFCF78E00
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=38.709
+DRIVER.ETPWM.VAR.ETPWM2_RDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_DCBEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=996.758
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM2_DCBEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_SELECT_EVENT.VALUE=NO_EVENT
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=4159
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM7_SOCA_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_OST.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=103.335
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
+DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000
+DRIVER.ETPWM.VAR.ETPWM3_CLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM5_CBC3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY_NEW.VALUE=50.0
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_OST.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_CBC4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_CBC5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=38.709
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_INVERT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_CBC6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000
+DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_INPUT.VALUE=PWMA_RED_FED
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM4_BASE.VALUE=0xFCF78F00
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM4_OSHT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_DCAEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_OSHT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_SOCA_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_DCAEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_OSHT3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_OSHT4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=102
+DRIVER.ETPWM.VAR.ETPWM4_OSHT5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_OSHT6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCA.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCB.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_SOCB_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
+DRIVER.ETPWM.VAR.ETPWM2_INTERRUPT_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM2_FDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=52
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME_REG.VALUE=3
+DRIVER.ETPWM.VAR.ETPWM1_DCBEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM1_DCBEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=103.335
+DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCA.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCB.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME_REG.VALUE=3
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY_NEW.VALUE=50.0
+DRIVER.ETPWM.VAR.ETPWM6_CBC1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM6_CBC2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_CBC3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME_REG.VALUE=3
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_CBC4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_SOCB_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_CBC5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_CBC6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=4159
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_MODE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=250000.000
+DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCA.VALUE=DCAEVT1
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM5_BASE.VALUE=0xFCF79000
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCB.VALUE=DCBEVT1
+DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM1_CLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_FDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_RDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM7_DCAEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM7_DCAEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_CLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
+DRIVER.ETPWM.VAR.ETPWM1_INTERRUPT_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCA.VALUE=DCAEVT1
+DRIVER.ETPWM.VAR.ETPWM5_SELECT_EVENT.VALUE=NO_EVENT
+DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCB.VALUE=DCBEVT1
+DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY_NEW.VALUE=50.0
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM7_DCBEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_MODE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_DCBEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=76.923
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM7_CBC1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM5_TB_FREQUENCY.VALUE=110.000
+DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCA.VALUE=DCAEVT1
+DRIVER.ETPWM.VAR.ETPWM7_CBC2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCB.VALUE=DCBEVT1
+DRIVER.ETPWM.VAR.ETPWM7_CBC3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=102
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_CBC4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM7_CBC5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_CBC6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=52
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091
+DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_ENA.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM5_OSHT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM5_OSHT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_INPUT.VALUE=PWMA_RED_FED
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=996.758
+DRIVER.ETPWM.VAR.ETPWM5_OSHT3.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_OSHT4.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM2_SELECT_EVENT.VALUE=NO_EVENT
+DRIVER.ETPWM.VAR.ETPWM5_OSHT5.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM5_OSHT6.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=76.923
+DRIVER.ETPWM.VAR.ETPWM6_CLKDIV.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY_NEW.VALUE=50.0
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM2_TB_FREQUENCY.VALUE=110.000
+DRIVER.ETPWM.VAR.ETPWM6_DCAEVT1.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_POLARITY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_SOCA_PERIOD.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM6_DCAEVT2.VALUE=0x0000
+DRIVER.ETPWM.VAR.ETPWM4_FDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_RDELAY_SOURCE.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=0.000
+DRIVER.ECAP.VAR.ECAP1_PRESCALE_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP2_ENA_PWM.VALUE=0
+DRIVER.ECAP.VAR.ECAP4_PRD.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP5_PWM_DUTY.VALUE=50
+DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP4_CAP2_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP5_PRESCALE.VALUE=0
+DRIVER.ECAP.VAR.ECAP5_PRD.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP6_PWM_COMPARE.VALUE=50
+DRIVER.ECAP.VAR.ECAP5_CAP4_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP5_ENA_LOAD.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_WRAP_COUNTER.VALUE=CAPTURE_EVENT1
+DRIVER.ECAP.VAR.ECAP3_PWM_COMPARE.VALUE=50
+DRIVER.ECAP.VAR.ECAP2_CAP1_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP6_PRD.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_PWM_DUTYTIME.VALUE=500.000
+DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP3_CAP3_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP1_ENA_PWM.VALUE=0
+DRIVER.ECAP.VAR.ECAP3_WRAP_COUNTER.VALUE=CAPTURE_EVENT1
+DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER.VALUE=0
+DRIVER.ECAP.VAR.ECAP5_CEVT1.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_CAPTURE_MODE.VALUE=ONE_SHOT
+DRIVER.ECAP.VAR.ECAP5_CEVT2.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP5_CEVT3.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP5_CEVT4.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP1_PWM_DUTY.VALUE=50
+DRIVER.ECAP.VAR.ECAP1_CAP2_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP1_PWM_DUTYTIME.VALUE=500.000
+DRIVER.ECAP.VAR.ECAP5_CNTOVF.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP5_PRESCALE_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP2_CAP4_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP1_PRESCALE.VALUE=0
+DRIVER.ECAP.VAR.ECAP1_ENA_LOAD.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_CAP2_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP1_CAPTURE_MODE.VALUE=ONE_SHOT
+DRIVER.ECAP.VAR.ECAP2_PRESCALE_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP4_PWM_DUTY.VALUE=50
+DRIVER.ECAP.VAR.ECAP6_PWM_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP4_CAP1_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP1_CEVT1.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP1_CEVT2.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP1_CEVT3.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER.VALUE=0
+DRIVER.ECAP.VAR.ECAP1_CEVT4.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_PRESCALE.VALUE=0
+DRIVER.ECAP.VAR.ECAP5_CAP3_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP4_ENA_LOAD.VALUE=0
+DRIVER.ECAP.VAR.ECAP3_CNTOVF.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP6_CEVT1.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_CEVT2.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP6_CEVT3.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP6_CEVT4.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP5_PWM_COMPARE.VALUE=50
+DRIVER.ECAP.VAR.ECAP5_PWM_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP6_ENA_PWM.VALUE=0
+DRIVER.ECAP.VAR.ECAP3_CAP2_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP5_PWM_DUTYTIME.VALUE=500.000
+DRIVER.ECAP.VAR.ECAP1_BASE.VALUE=0xFCF79300
+DRIVER.ECAP.VAR.ECAP4_CAP4_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP2_PWM_COMPARE.VALUE=50
+DRIVER.ECAP.VAR.ECAP4_WRAP_COUNTER.VALUE=CAPTURE_EVENT1
+DRIVER.ECAP.VAR.ECAP5_CAPTURE_MODE.VALUE=ONE_SHOT
+DRIVER.ECAP.VAR.ECAP1_CAP1_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP4_PWM_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP1_CNTOVF.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_PWM_DUTYTIME.VALUE=500.000
+DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP2_CAP3_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP6_PRESCALE_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP2_BASE.VALUE=0xFCF79400
+DRIVER.ECAP.VAR.ECAP2_CEVT1.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_CEVT2.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP2_CEVT3.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_CEVT4.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP1_WRAP_COUNTER.VALUE=CAPTURE_EVENT1
+DRIVER.ECAP.VAR.ECAP6_CAP1_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP5_ENA_PWM.VALUE=0
+DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER.VALUE=0
+DRIVER.ECAP.VAR.ECAP2_CAPTURE_MODE.VALUE=ONE_SHOT
+DRIVER.ECAP.VAR.ECAP3_PWM_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP3_PWM_DUTY.VALUE=50
+DRIVER.ECAP.VAR.ECAP3_PRESCALE_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP1_CAP4_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP3_PRESCALE.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_CNTOVF.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP3_BASE.VALUE=0xFCF79500
+DRIVER.ECAP.VAR.ECAP5_CAP2_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP3_ENA_LOAD.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_CAP4_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP1_CMP.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_PWM_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP4_ENA_PWM.VALUE=0
+DRIVER.ECAP.VAR.ECAP3_CAP1_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_PWM_DUTY.VALUE=50
+DRIVER.ECAP.VAR.ECAP2_CMP.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP6_PWM_DUTYTIME.VALUE=500.000
+DRIVER.ECAP.VAR.ECAP4_CAP3_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP4_BASE.VALUE=0xFCF79600
+DRIVER.ECAP.VAR.ECAP6_PRESCALE.VALUE=0
+DRIVER.ECAP.VAR.ECAP4_PWM_COMPARE.VALUE=50
+DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP3_CEVT1.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP3_CEVT2.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP3_CEVT3.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP3_CEVT4.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP6_ENA_LOAD.VALUE=0
+DRIVER.ECAP.VAR.ECAP5_WRAP_COUNTER.VALUE=CAPTURE_EVENT1
+DRIVER.ECAP.VAR.ECAP4_CNTOVF.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP3_CMP.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP1_PWM_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_CAPTURE_MODE.VALUE=ONE_SHOT
+DRIVER.ECAP.VAR.ECAP1_PWM_COMPARE.VALUE=50
+DRIVER.ECAP.VAR.ECAP2_CAP2_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP3_PWM_DUTYTIME.VALUE=500.000
+DRIVER.ECAP.VAR.ECAP3_CAP4_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP4_CMP.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP1_PRD.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD.VALUE=1000.000
+DRIVER.ECAP.VAR.ECAP5_BASE.VALUE=0xFCF79700
+DRIVER.ECAP.VAR.ECAP3_ENA_PWM.VALUE=0
+DRIVER.ECAP.VAR.ECAP2_WRAP_COUNTER.VALUE=CAPTURE_EVENT1
+DRIVER.ECAP.VAR.ECAP3_CAPTURE_MODE.VALUE=ONE_SHOT
+DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE
+DRIVER.ECAP.VAR.ECAP5_CMP.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_PRD.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_PWM_DUTY.VALUE=50
+DRIVER.ECAP.VAR.ECAP1_CAP3_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP4_PRESCALE_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP2_PRESCALE.VALUE=0
+DRIVER.ECAP.VAR.ECAP2_CNTOVF.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP5_CAP1_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD_REG.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_CMP.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP2_ENA_LOAD.VALUE=0
+DRIVER.ECAP.VAR.ECAP3_PRD.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER.VALUE=0
+DRIVER.ECAP.VAR.ECAP6_BASE.VALUE=0xFCF79800
+DRIVER.ECAP.VAR.ECAP6_CAP3_POLARITY.VALUE=RISING_EDGE
+DRIVER.ECAP.VAR.ECAP4_CEVT1.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_CEVT2.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_CEVT3.VALUE=0x0000
+DRIVER.ECAP.VAR.ECAP4_CEVT4.VALUE=0x0000
+DRIVER.EQEP.VAR.EQEP2_QUPRD.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_INIT_ENABLE.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_IGATE.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_QPE_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_PC_RST_MODE.VALUE=MAX_POSITION
+DRIVER.EQEP.VAR.EQEP1_UTO_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_SEL_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_SELECT.VALUE=RISING_EDGE
+DRIVER.EQEP.VAR.EQEP2_PCE_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_PCU_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_BASE.VALUE=0xFCF79900
+DRIVER.EQEP.VAR.EQEP1_INV_QEPS_POL.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_INV_QEPA_POL.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_PCSHDW.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_PC_INIT_VALUE.VALUE=0x00000000
+DRIVER.EQEP.VAR.EQEP2_PCR_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_BASE.VALUE=0xFCF79A00
+DRIVER.EQEP.VAR.EQEP1_ENABLE_CAPTURE.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_INV_QEPB_POL.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_MAXPC_VALUE.VALUE=0x00000000
+DRIVER.EQEP.VAR.EQEP1_PCM_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_PCPOL.VALUE=ACTIVE_HIGH
+DRIVER.EQEP.VAR.EQEP2_UNIT_POS_PRESCALER.VALUE=PS_512
+DRIVER.EQEP.VAR.EQEP2_CAP_CLK_PRESCALER.VALUE=PS_8
+DRIVER.EQEP.VAR.EQEP1_PCSPW.VALUE=0x000
+DRIVER.EQEP.VAR.EQEP1_POSCMP.VALUE=0x00000000
+DRIVER.EQEP.VAR.EQEP2_PC_MODE.VALUE=DIRECTION_COUNT
+DRIVER.EQEP.VAR.EQEP1_PCE_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_INV_QEPS_POL.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_SET_INIT_AT_STARTUP.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_ENABLE_CAPTURE.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT
+DRIVER.EQEP.VAR.EQEP2_PCPOL.VALUE=ACTIVE_HIGH
+DRIVER.EQEP.VAR.EQEP2_INV_QEPA_POL.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_CAP_CLK_PRESCALER.VALUE=PS_8
+DRIVER.EQEP.VAR.EQEP2_QDC_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_QCLM.VALUE=ON_POSITION_COUNTER_READ
+DRIVER.EQEP.VAR.EQEP1_PC_MODE.VALUE=DIRECTION_COUNT
+DRIVER.EQEP.VAR.EQEP2_WTO_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_SWI_ENABLE.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_PCR_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_INV_QEPB_POL.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_IEL.VALUE=RISING_EDGE
+DRIVER.EQEP.VAR.EQEP2_PCSPW.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_PC_INIT_VALUE.VALUE=0x00000000
+DRIVER.EQEP.VAR.EQEP1_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP
+DRIVER.EQEP.VAR.EQEP2_IEL_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_IEL.VALUE=RISING_EDGE
+DRIVER.EQEP.VAR.EQEP1_MAXPC_VALUE.VALUE=0x00000000
+DRIVER.EQEP.VAR.EQEP1_INV_QEPI_POL.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_QCLM.VALUE=ON_POSITION_COUNTER_READ
+DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_INIT_ENABLE.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_PCO_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_INIT_ENABLE.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_EXT_CLK_RATE.VALUE=RESOLUTION_1x
+DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT
+DRIVER.EQEP.VAR.EQEP1_UNIT_POS_PRESCALER.VALUE=PS_512
+DRIVER.EQEP.VAR.EQEP1_WDPRD.VALUE=0x0000
+DRIVER.EQEP.VAR.EQEP1_SEL.VALUE=RISING_EDGE
+DRIVER.EQEP.VAR.EQEP1_SOEN.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_QPE_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_PC_RST_MODE.VALUE=MAX_POSITION
+DRIVER.EQEP.VAR.EQEP1_WDE.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_SET_INIT_AT_STARTUP.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_UTO_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_SWI_ENABLE.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_POSITIVE_ROTATION.VALUE=CLOCKWISE
+DRIVER.EQEP.VAR.EQEP2_SEL_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_SEL.VALUE=RISING_EDGE
+DRIVER.EQEP.VAR.EQEP2_PCU_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_WDE.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_SPSEL.VALUE=INDEX_PIN
+DRIVER.EQEP.VAR.EQEP1_PCSHDW.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_SWAP.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_SOEN.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_POSCMP.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_QUPRD.VALUE=0x00000000
+DRIVER.EQEP.VAR.EQEP1_IGATE.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_QDC_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_SWAP.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_WDPRD.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_WTO_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_POSITIVE_ROTATION.VALUE=CLOCKWISE
+DRIVER.EQEP.VAR.EQEP2_INV_QEPI_POL.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_PCM_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP1_IEL_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_EXT_CLK_RATE.VALUE=RESOLUTION_1x
+DRIVER.EQEP.VAR.EQEP2_SPSEL.VALUE=INDEX_PIN
+DRIVER.EQEP.VAR.EQEP1_PCO_INT_ENA.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_SELECT.VALUE=RISING_EDGE
+DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_INIT_ENABLE.VALUE=0
+DRIVER.EQEP.VAR.EQEP2_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP
+DRIVER.FEE.VAR.FEE_START_SECTOR.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_BANK.VALUE=7
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_READ_CYCLE_COUNT.VALUE=10
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_NUMBER_OF_VIRTUAL_SECTORS.VALUE=4
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX15_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX4_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_FLASH_CRC_ENABLE.VALUE=STD_ON
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_NUMBER.VALUE=12
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_BANK.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_NUMBER.VALUE=3
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_NUMBER.VALUE=5
+DRIVER.FEE.VAR.FEE_SECTORS_EEP1.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_START.VALUE=4
+DRIVER.FEE.VAR.FEE_BLOCK_NUMBER.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_DRIVER_INDEX.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_VS5_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX9_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX13_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX2_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_NUMBER.VALUE=10
+DRIVER.FEE.VAR.FEE_NUMBER_OF_EEPS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_NUMBER.VALUE=8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_NUMBER.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_DEVICE_INDEX.VALUE=0
+DRIVER.FEE.VAR.FEE_PAGE_OVERHEAD.VALUE=0
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_NUMBER.VALUE=3
+DRIVER.FEE.VAR.FEE_TI_FEE_SW_MAJOR_VERSION.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_END.VALUE=0
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_START.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_SECTOR_NUMBER.VALUE=1
+DRIVER.FEE.VAR.FEE_VIRTUALPAGE_SIZE.VALUE=8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_VS3_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX7_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_END.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX11_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_FLASH_WRITECOUNTER_SAVE.VALUE=STD_ON
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_VS_INDEX.VALUE=2
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_NUMBER.VALUE=15
+DRIVER.FEE.VAR.FEE_TI_FEE_SW_PATCH_VERSION.VALUE=0
+DRIVER.FEE.VAR.FEE_JOBERROR_NOTIFICATION.VALUE=JobErrorNotification
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_NUMBER.VALUE=6
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_END.VALUE=2
+DRIVER.FEE.VAR.FEE_BLOCK_SIZE.VALUE=0x10
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_TOTAL_BLOCKS_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_NUMBER.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_SIZE.VALUE=8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_END.VALUE=3
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_MAXIMUM_BLOCKING_TIME.VALUE=600
+DRIVER.FEE.VAR.FEE_VS1_ENABLE.VALUE=1
+DRIVER.FEE.VAR.FEE_NO_OF_UNCONFIGURED_BLOCKS_TO_COPY.VALUE=0
+DRIVER.FEE.VAR.FEE_FLASH_BANK_NUM.VALUE=7
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX16_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX5_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_NUMBER.VALUE=13
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_END.VALUE=4
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_START.VALUE=1
+DRIVER.FEE.VAR.FEE_SECTOR_OVERHEAD.VALUE=16
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_NUMBER.VALUE=4
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_TI_FEE_SW_MINOR_VERSION.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_VERSIONINFO_API.VALUE=STD_ON
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DATASETS.VALUE=1
+DRIVER.FEE.VAR.MAX_BLOCK_TIME.VALUE=600
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_WRITE_CYCLES.VALUE=10
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_OFFSET.VALUE=16
+DRIVER.FEE.VAR.FEE_NUMBER_OF_BLOCKS.VALUE=1
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_BANK.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX14_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX3_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_NUMBER_OF_EIGHTBYTEWRITES.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_NUMBER.VALUE=11
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_NUMBER.VALUE=9
+DRIVER.FEE.VAR.FEE_END_SECTOR.VALUE=0
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_1_BANK.VALUE=7
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_NUMBER.VALUE=2
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_HANDLING.VALUE=TI_Fee_None
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_NUMBER.VALUE=4
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_DEVERROR_DETECT.VALUE=STD_ON
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_START.VALUE=2
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_VS4_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX8_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_MAX_NUMBER_OF_LINKS.VALUE=256
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_EEP.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX12_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX1_ENABLE.VALUE=1
+DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_ENABLE.VALUE=STD_ON
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_BANK.VALUE=7
+DRIVER.FEE.VAR.FEE_DATASELECT_BITS.VALUE=0
+DRIVER.FEE.VAR.FEE_OPERATING_FREQ.VALUE=208.000
+DRIVER.FEE.VAR.FEE_TOTAL_SECTORS.VALUE=4
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_NUMBER.VALUE=16
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_NUMBER.VALUE=7
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_NUMBER.VALUE=2
+DRIVER.FEE.VAR.FEE_JOBEND_NOTIFICATION.VALUE=JobEndNotification
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_ENABLE_ECC.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_OVERHEAD.VALUE=24
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DATASETS.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_OFFSET.VALUE=0
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_BANK.VALUE=7
+DRIVER.FEE.VAR.FEE_VS2_ENABLE.VALUE=1
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX6_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DEVICE_INDEX.VALUE=0x00000000
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_SIZE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX10_ENABLE.VALUE=0
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_NUMBER.VALUE=14
+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_START.VALUE=3
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_IMED_DATA.VALUE=TRUE
+DRIVER.FEE.VAR.FEE_CHECK_BANK7_ACCESS.VALUE=STD_OFF
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_WRITE_CYCLES.VALUE=0x8
+DRIVER.FEE.VAR.FEE_POLLING_MODE.VALUE=STD_ON
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_NUMBER.VALUE=5
+DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_SIZE.VALUE=0
+DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_2.VALUE=0xFFFDFFFE
+DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_3.VALUE=0xFFEFFFFF
+DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_0.VALUE=0xEFFDFFFF
+DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_1.VALUE=0xFFFFFFFF
+DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_2.VALUE=0xFFFDFFFE
+DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_3.VALUE=0xFFEFFFFF
+DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_0.VALUE=PATTERN_NOT_REQUIRED
+DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_0.VALUE=0xED
+DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_1.VALUE=PATTERN_NOT_REQUIRED
+DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_1.VALUE=0xC0
+DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_2.VALUE=PATTERN_NOT_REQUIRED
+DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_3.VALUE=PATTERN_NOT_REQUIRED
+DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_0.VALUE=0xED
+DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_1.VALUE=0xC0
+DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN.VALUE=PATTERN_NOT_REQUIRED
+DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_0.VALUE=0xEFFDFFFF
+DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_1.VALUE=0xFFFFFFFF
Index: firmware/TD.hcg
===================================================================
diff -u
--- firmware/TD.hcg (revision 0)
+++ firmware/TD.hcg (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,879 @@
+
+
+
+ RM46x
+ RM46L852PGE
+ TD.dil
+ ti
+
+
+ 04.07.01
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ hal_stdtypes.h
+ include\hal_stdtypes.h
+
+
+ sys_common.h
+ include\sys_common.h
+
+
+ reg_system.h
+ include\reg_system.h
+
+
+ reg_flash.h
+ include\reg_flash.h
+
+
+ reg_tcram.h
+ include\reg_tcram.h
+
+
+ reg_vim.h
+ include\reg_vim.h
+
+
+ reg_pbist.h
+ include\reg_pbist.h
+
+
+ reg_stc.h
+ include\reg_stc.h
+
+
+ reg_efc.h
+ include\reg_efc.h
+
+
+ reg_pcr.h
+ include\reg_pcr.h
+
+
+ reg_pmm.h
+ include\reg_pmm.h
+
+
+ reg_dma.h
+ include\reg_dma.h
+
+
+ system.h
+ include\system.h
+
+
+ sys_vim.h
+ include\sys_vim.h
+
+
+ sys_core.h
+ include\sys_core.h
+
+
+ sys_mpu.h
+ include\sys_mpu.h
+
+
+ sys_pmu.h
+ include\sys_pmu.h
+
+
+ sys_pcr.h
+ include\sys_pcr.h
+
+
+ sys_pmm.h
+ include\sys_pmm.h
+
+
+ sys_dma.h
+ include\sys_dma.h
+
+
+ sys_selftest.h
+ include\sys_selftest.h
+
+
+ sys_core.asm
+ source\sys_core.asm
+
+
+ sys_intvecs.asm
+ source\sys_intvecs.asm
+
+
+ sys_mpu.asm
+ source\sys_mpu.asm
+
+
+ sys_pmu.asm
+ source\sys_pmu.asm
+
+
+ dabort.asm
+ source\dabort.asm
+
+
+ sys_pcr.c
+ source\sys_pcr.c
+
+
+ sys_pmm.c
+ source\sys_pmm.c
+
+
+ sys_dma.c
+ source\sys_dma.c
+
+
+ system.c
+ source\system.c
+
+
+ sys_phantom.c
+ source\sys_phantom.c
+
+
+ sys_startup.c
+ source\sys_startup.c
+
+
+ sys_selftest.c
+ source\sys_selftest.c
+
+
+ sys_vim.c
+ source\sys_vim.c
+
+
+ sys_main.c
+ source\sys_main.c
+
+
+ notification.c
+ source\notification.c
+
+
+ sys_link.cmd
+ source\sys_link.cmd
+
+
+ HL_Test.h
+
+
+ errata_SSWF021_45.h
+ include\errata_SSWF021_45.h
+
+
+ errata_SSWF021_45_defs.h
+ include\errata_SSWF021_45_defs.h
+
+
+ errata_SSWF021_45.c
+ source\errata_SSWF021_45.c
+
+
+ reg_pinmux.h
+
+
+ pinmux.h
+
+
+ pinmux.c
+
+
+ reg_rti.h
+
+
+ rti.h
+
+
+ rti.c
+
+
+ reg_gio.h
+
+
+ gio.h
+
+
+ gio.c
+
+
+ reg_sci.h
+
+
+ sci.h
+
+
+ sci.c
+
+
+ reg_lin.h
+
+
+ lin.h
+
+
+
+ reg_mibspi.h
+
+
+ mibspi.h
+
+
+ mibspi.c
+
+
+ reg_spi.h
+
+
+ spi.h
+
+
+
+ reg_can.h
+
+
+ can.h
+
+
+ can.c
+
+
+ reg_adc.h
+
+
+ adc.h
+
+
+ adc.c
+
+
+
+
+
+
+
+
+ std_nhet.h
+
+
+ reg_het.h
+
+
+ het.h
+
+
+ het.c
+
+
+ reg_htu.h
+
+
+ htu.h
+
+
+
+
+
+
+
+
+ reg_esm.h
+
+
+ esm.h
+
+
+ esm.c
+
+
+ reg_i2c.h
+
+
+ i2c.h
+
+
+ i2c.c
+
+
+ emac.h
+
+
+ hw_emac.h
+
+
+ hw_emac_ctrl.h
+
+
+ hw_mdio.h
+
+
+ hw_reg_access.h
+
+
+ mdio.h
+
+
+ phy_dp83640.h
+
+
+
+
+
+ reg_dcc.h
+
+
+ dcc.h
+
+
+
+ reg_pom.h
+
+
+ pom.h
+
+
+
+ usbcdc.h
+
+
+ usb_serial_structs.h
+
+
+ usbdcdc.h
+
+
+ usbdevice.h
+
+
+ usbdevicepriv.h
+
+
+ usb-ids.h
+
+
+ usblib.h
+
+
+ usb.h
+
+
+ hw_usb.h
+
+
+
+
+
+
+
+
+
+
+
+ reg_crc.h
+
+
+ crc.h
+
+
+
+ reg_etpwm.h
+
+
+ etpwm.h
+
+
+ etpwm.c
+
+
+ reg_ecap.h
+
+
+ ecap.h
+
+
+
+ reg_eqep.h
+
+
+ eqep.h
+
+
+
+ Device_RM46.h
+
+
+ Device_header.h
+
+
+ Device_types.h
+
+
+ ti_fee_cfg.h
+
+
+ MemMap.h
+
+
+ ti_fee_types.h
+
+
+ ti_fee.h
+
+
+ fee_interface.h
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ include\reg_pinmux.h
+
+
+ include\pinmux.h
+
+
+ source\pinmux.c
+
+
+
+
+
+
+ include\reg_rti.h
+
+
+ include\rti.h
+
+
+ source\rti.c
+
+
+
+
+
+
+ include\reg_gio.h
+
+
+ include\gio.h
+
+
+ source\gio.c
+
+
+
+
+
+
+ include\reg_sci.h
+
+
+ include\sci.h
+
+
+ source\sci.c
+
+
+
+
+
+
+ include\reg_lin.h
+
+
+ include\lin.h
+
+
+
+
+
+
+
+
+
+ include\reg_mibspi.h
+
+
+ include\mibspi.h
+
+
+ source\mibspi.c
+
+
+
+
+
+
+ include\reg_spi.h
+
+
+ include\spi.h
+
+
+
+
+
+
+
+
+
+ include\reg_can.h
+
+
+ include\can.h
+
+
+ source\can.c
+
+
+
+
+
+
+ include\reg_adc.h
+
+
+ include\adc.h
+
+
+ source\adc.c
+
+
+
+
+
+
+ include\std_nhet.h
+
+
+ include\reg_het.h
+
+
+ include\het.h
+
+
+ source\het.c
+
+
+ include\reg_htu.h
+
+
+ include\htu.h
+
+
+
+
+
+
+ include\reg_esm.h
+
+
+ include\esm.h
+
+
+ source\esm.c
+
+
+
+
+
+
+ include\reg_i2c.h
+
+
+ include\i2c.h
+
+
+ source\i2c.c
+
+
+
+
+
+
+ include\emac.h
+
+
+ include\hw_emac.h
+
+
+ include\hw_emac_ctrl.h
+
+
+ include\hw_mdio.h
+
+
+ include\hw_reg_access.h
+
+
+ include\mdio.h
+
+
+ include\phy_dp83640.h
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ include\reg_dcc.h
+
+
+ include\dcc.h
+
+
+
+
+
+
+
+
+
+ include\reg_pom.h
+
+
+ include\pom.h
+
+
+
+
+
+
+
+
+
+ include\usbcdc.h
+
+
+ include\usb_serial_structs.h
+
+
+ include\usbdcdc.h
+
+
+ include\usbdevice.h
+
+
+ include\usbdevicepriv.h
+
+
+ include\usb-ids.h
+
+
+ include\usblib.h
+
+
+ include\usb.h
+
+
+ include\hw_usb.h
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ include\reg_crc.h
+
+
+ include\crc.h
+
+
+
+
+
+
+
+
+
+ include\reg_etpwm.h
+
+
+ include\etpwm.h
+
+
+ source\etpwm.c
+
+
+
+
+
+
+ include\reg_ecap.h
+
+
+ include\ecap.h
+
+
+
+
+
+
+
+
+
+ include\reg_eqep.h
+
+
+ include\eqep.h
+
+
+
+
+
+
+
+
+
+ include\Device_RM46.h
+
+
+ include\Device_header.h
+
+
+ include\Device_types.h
+
+
+ include\ti_fee_cfg.h
+
+
+ include\MemMap.h
+
+
+ include\ti_fee_types.h
+
+
+ include\ti_fee.h
+
+
+ include\fee_interface.h
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: firmware/checkAlarms.sh
===================================================================
diff -u
--- firmware/checkAlarms.sh (revision 0)
+++ firmware/checkAlarms.sh (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,89 @@
+#!/bin/bash
+###########################################################################
+#
+# Copyright (c) 2021-2024 Diality Inc. - All Rights Reserved.
+#
+# THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+# WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+#
+# @file checkAlarms.sh
+#
+# @author (last) Dara Navaei
+# @date (last) 17-Nov-2022
+# @author (original) Quang Nguyen
+# @date (original) 27-May-2021
+#
+############################################################################
+
+lineno=$(grep -n "ALARM_ID_NO_ALARM = 0" ../Common/AlarmDefs.h)
+lineno=${lineno%%:*}
+
+alarmRankLineNo=$(grep -n "ALARM_RANK_TABLE" ../Common/AlarmDefs.h)
+alarmRankLineNo=${alarmRankLineNo%%:*}
+
+alarmManualLineNo=$(grep -n "ALARM_MANUAL_TABLE" ../Common/AlarmDefs.h)
+alarmManualLineNo=${alarmManualLineNo%%:*}
+
+echo "
+#include
+#include
+
+#define __ALARM_MGMT_C__
+#define __MANUAL_ALARMS__
+#include \"Common.h\"
+#include \"AlarmDefs.h\"
+
+int main()
+{
+ ALARM_ID_T alarm;
+ U32 lineNumber = $lineno;
+ U32 alarmRankLineNumber = $alarmRankLineNo;
+ U32 alarmManualLineNumber = $alarmManualLineNo;
+ U32 index;
+
+ for ( alarm = ALARM_ID_NO_ALARM; alarm < NUM_OF_ALARM_IDS; alarm++ )
+ {
+ if ( alarm != ALARM_TABLE[ alarm ].alarmID )
+ {
+ lineNumber += alarm;
+ printf(\"\\\"AlarmDefs.h\\\", line %d: error #9999: Alarm %i NOT MATCH Alarm Table ID %i!\n\", lineNumber, alarm, ALARM_TABLE[ alarm ].alarmID);
+ exit(1);
+ }
+ }
+ printf(\"Alarm table check completed!\n\");
+
+ for ( alarm = ALARM_ID_NO_ALARM; alarm < NUM_OF_ALARM_IDS; alarm++ )
+ {
+ if ( ALARM_RANK_TABLE[ alarm ].alarmSubRank != ALARM_TABLE[ ALARM_RANK_TABLE[ alarm ].alarmID ].alarmSubRank )
+ {
+ printf(\"\\\"AlarmDefs.h\\\", line %d: error #9999: Alarm has different rank from alarm property table!\n\", alarmRankLineNumber + alarm + 2 );
+ exit(1);
+ }
+ }
+
+ for ( index = 1; index < NUM_OF_ALARM_IDS; index++ )
+ {
+ if ( ALARM_RANK_TABLE[ index - 1 ].alarmSubRank > ALARM_RANK_TABLE[ index ].alarmSubRank )
+ {
+ alarmRankLineNumber += index + 1;
+ printf(\"\\\"AlarmDefs.h\\\", line %d: error #9999: Alarm Rank Index %i has higher rank than Index %i!\n\", alarmRankLineNumber, index, index - 1);
+ exit(1);
+ }
+ }
+
+ for ( alarm = ALARM_ID_NO_ALARM; alarm < NUM_OF_ALARM_IDS; alarm++ )
+ {
+ if ( alarm != ALARM_MANUAL_TABLE[ alarm ].alarmID )
+ {
+ // The current alarm number is the starting line number of the ALARM_MANUAL_TABLE + 2 since the alarms enum start from 0
+ alarmManualLineNumber += alarm + 2;
+ printf(\"\\\"AlarmDefs.h\\\", line %d: error #9999: Alarm %i NOT MATCH Alarm Table ID %i!\n\", alarmManualLineNumber, alarm, ALARM_TABLE[ alarm ].alarmID);
+ exit(1);
+ }
+ }
+
+ printf(\"Alarm rank table check completed!\n\");
+}" > alarmCheck.c
+
+gcc -o alarmCheck alarmCheck.c -I../App -I../App/Services -I../Common -I../FWCommon -I../include
+./alarmCheck
Index: firmware/include/Device_RM46.h
===================================================================
diff -u
--- firmware/include/Device_RM46.h (revision 0)
+++ firmware/include/Device_RM46.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,111 @@
+/**********************************************************************************************************************
+ * FILE DESCRIPTION
+ * -------------------------------------------------------------------------------------------------------------------
+ * File: Device_RM46.c
+ * Project: Tms570_TIFEEDriver
+ * Module: TIFEEDriver
+ * Generator: None
+ *
+ * Description: This file defines the number of sectors.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author: Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version Date Author Change ID Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 01.15.00 06Jun2014 Vishwanath Reddy History Added.
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+ /*********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+
+#ifndef DEVICE_RM46_H
+#define DEVICE_RM46_H
+
+
+/** @def DEVICE_CONFIGURATION_VERSION
+* @brief Device Configuration Version
+*
+* @note Indicates the current version of the device files
+*/
+#define DEVICE_CONFIGURATION_VERSION 0U /* Indicates the current version of the device files */
+
+/** @def DEVICE_NUMBER_OF_FLASH_BANKS
+* @brief Number of Flash Banks
+*
+* @note Defines the number of Flash Banks on the device
+*/
+#define DEVICE_NUMBER_OF_FLASH_BANKS 1U /* Defines the number of Flash Banks on the device */
+
+
+/** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS
+* @brief Maximum number of Sectors
+*
+* @note Defines the maxium number of sectors in all banks
+*/
+#define DEVICE_BANK_MAX_NUMBER_OF_SECTORS 4U /* Defines the maxium number of sectors in all banks */
+
+/** @def DEVICE_BANK1_NUMBER_OF_SECTORS
+* @brief Number of Sectors
+*
+* @note Defines the number of sectors in bank1
+*/
+#define DEVICE_BANK1_NUMBER_OF_SECTORS 4U /* Defines the number of sectors in bank1 */
+
+
+/** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS
+* @brief Number of Sectors
+*
+* @note Defines the number of Read Cycle Thresholds
+*/
+#define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS 4U /* Defines the number of Read Cycle Thresholds */
+
+
+/* Include Files */
+#ifndef _PLATFORM_TYPES_H_
+#define _PLATFORM_TYPES_H_
+#endif
+#include "F021.h"
+#include "hal_stdtypes.h"
+#include "Device_types.h"
+
+#endif /* DEVICE_RM46_H */
+
+/* End of File */
Index: firmware/include/Device_header.h
===================================================================
diff -u
--- firmware/include/Device_header.h (revision 0)
+++ firmware/include/Device_header.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,67 @@
+/**********************************************************************************************************************
+ * FILE DESCRIPTION
+ * -------------------------------------------------------------------------------------------------------------------
+ * File: Device_header.h
+ * Project: Tms570_TIFEEDriver
+ * Module: TIFEEDriver
+ * Generator: None
+ *
+ * Description: This file includes the header file.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author: Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version Date Author Change ID Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 01.15.00 06Jun2014 Vishwanath Reddy History Added.
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+ /*********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+
+#ifndef TI_FEE_DEVICEHEADER_H
+#define TI_FEE_DEVICEHEADER_H
+
+/* Uncomment the appropriate include file depending on the device you are using */
+#include "Device_RM46.h"
+
+/* End of file */
+#endif
+
Index: firmware/include/Device_types.h
===================================================================
diff -u
--- firmware/include/Device_types.h (revision 0)
+++ firmware/include/Device_types.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,116 @@
+/**********************************************************************************************************************
+ * FILE DESCRIPTION
+ * -------------------------------------------------------------------------------------------------------------------
+ * File: Device_types.h
+ * Project: Tms570_TIFEEDriver
+ * Module: TIFEEDriver
+ * Generator: None
+ *
+ * Description: This file defines the structures.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author: Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version Date Author Change ID Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 01.15.00 06Jun2014 Vishwanath Reddy History Added.
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+ /*********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+
+
+#ifndef DEVICE_TYPES_H
+#define DEVICE_TYPES_H
+
+#include "hal_stdtypes.h"
+
+/* Enum to describe the type of error handling on the device */
+typedef enum
+{
+ Device_ErrorHandlingNone, /* Device has no error handling */
+ Device_ErrorHandlingParity, /* Device has parity error handling */
+ Device_ErrorHandlingEcc /* Device has ECC error handling */
+} Device_FlashErrorCorrectionProcessType;
+
+/* Enum to describe the ARM core on the device*/
+typedef enum
+{
+ Device_CoreNone, /* To indicate that the device has a single core */
+ Device_Arm7, /* To indicate that the device has a ARM7 core */
+ Device_CortexR4, /* To indicate that the device has a CortexR4 core */
+ Device_CortexM3 /* To indicate that the device has a CortexM3 core */
+}Device_ArmCoreType;
+
+/* Structure defines an individual sector within a bank */
+typedef struct
+{
+ Fapi_FlashSectorType Device_Sector; /* Sector number */
+ uint32 Device_SectorStartAddress; /* Starting address of the sector */
+ uint32 Device_SectorLength; /* Length of the sector */
+ uint32 Device_MaxWriteCycles; /* Number of cycles the sector is rated for */
+ uint32 Device_EccAddress;
+ uint32 Device_EccLength;
+} Device_SectorType;
+
+/* Structure defines an individual bank */
+typedef struct
+{
+ Fapi_FmcRegistersType * Device_ControlRegister;
+ Fapi_FlashBankType Device_Core; /* Core number for this bank */
+ Device_SectorType Device_SectorInfo[DEVICE_BANK_MAX_NUMBER_OF_SECTORS]; /* Array of the Sectors within a bank */
+} Device_BankType;
+
+/* Structure defines the Flash structure of the device */
+typedef struct
+{
+ uint8 Device_DeviceName[12]; /* Device name */
+ uint32 Device_EngineeringId; /* Device Engineering ID */
+ Device_FlashErrorCorrectionProcessType Device_FlashErrorHandlingProcessInfo; /* Indicates which type of bit Error handling is on the device */
+ Device_ArmCoreType Device_MasterCore; /* Indicates the Master core type on the device */
+ boolean Device_SupportsInterrupts; /* Indicates if the device supports Flash interrupts for processing Flash */
+ uint32 Device_NominalWriteTime; /* Nominal time for one write command operation in uS */
+ uint32 Device_MaximumWriteTime; /* Maximum time for one write command operation in uS */
+ Device_BankType Device_BankInfo[DEVICE_NUMBER_OF_FLASH_BANKS]; /* Array of Banks on the device */
+} Device_FlashType;
+
+#endif /* DEVICE_TYPES_H */
+
+/* End of File */
Index: firmware/include/MemMap.h
===================================================================
diff -u
--- firmware/include/MemMap.h (revision 0)
+++ firmware/include/MemMap.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,70 @@
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef __MEM_MAP_H__
+#define __MEM_MAP_H__
+/*FEE*/
+#ifdef FEE_START_SEC_VAR_INIT_UNSPECIFIED
+#pragma SET_DATA_SECTION("FEE_DATA_SECTION")
+#undef FEE_START_SEC_VAR_INIT_UNSPECIFIED
+#endif
+
+#ifdef FEE_STOP_SEC_VAR_INIT_UNSPECIFIED
+#pragma SET_DATA_SECTION()
+#undef FEE_STOP_SEC_VAR_INIT_UNSPECIFIED
+#endif
+
+#ifdef FEE_START_SEC_CONST_UNSPECIFIED
+#pragma SET_DATA_SECTION("FEE_CONST_SECTION")
+#undef FEE_START_SEC_CONST_UNSPECIFIED
+#endif
+
+#ifdef FEE_STOP_SEC_CONST_UNSPECIFIED
+#pragma SET_DATA_SECTION()
+#undef FEE_STOP_SEC_CONST_UNSPECIFIED
+#endif
+
+#ifdef FEE_START_SEC_CODE
+#pragma SET_CODE_SECTION("FEE_TEXT_SECTION")
+#undef FEE_START_SEC_CODE
+#endif
+
+#ifdef FEE_STOP_SEC_CODE
+#pragma SET_CODE_SECTION()
+#undef FEE_STOP_SEC_CODE
+#endif
+
+
+#endif /* __MEM_MAP_H__ */
Index: firmware/include/adc.h
===================================================================
diff -u
--- firmware/include/adc.h (revision 0)
+++ firmware/include/adc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,311 @@
+/** @file adc.h
+* @brief ADC Driver Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the ADC driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+#include "reg_adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* ADC General Definitions */
+
+/** @def adcGROUP0
+* @brief Alias name for ADC event group
+*
+* @note This value should be used for API argument @a group
+*/
+#define adcGROUP0 0U
+
+/** @def adcGROUP1
+* @brief Alias name for ADC group 1
+*
+* @note This value should be used for API argument @a group
+*/
+#define adcGROUP1 1U
+
+/** @def adcGROUP2
+* @brief Alias name for ADC group 2
+*
+* @note This value should be used for API argument @a group
+*/
+#define adcGROUP2 2U
+
+/** @def ADC_12_BIT_MODE
+* @brief Alias name for ADC 12-bit mode of operation
+*/
+#define ADC_12_BIT_MODE 0x80000000U
+
+/** @enum adcResolution
+* @brief Alias names for data resolution
+* This enumeration is used to provide alias names for the data resolution:
+* - 12 bit resolution
+* - 10 bit resolution
+* - 8 bit resolution
+*/
+enum adcResolution
+{
+ ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */
+ ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */
+ ADC_8_BIT = 0x00000200U /**< Alias for 8 bit data resolution */
+};
+
+/** @enum adcFiFoStatus
+* @brief Alias names for FiFo status
+* This enumeration is used to provide alias names for the current FiFo states:
+* - FiFo is not full
+* - FiFo is full
+* - FiFo overflow occurred
+*/
+
+enum adcFiFoStatus
+{
+ ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full */
+ ADC_FIFO_IS_FULL = 1U, /**< Alias for FiFo is full */
+ ADC_FIFO_OVERFLOW = 3U /**< Alias for FiFo overflow occurred */
+};
+
+/** @enum adcConversionStatus
+* @brief Alias names for conversion status
+* This enumeration is used to provide alias names for the current conversion states:
+* - Conversion is not finished
+* - Conversion is finished
+*/
+
+enum adcConversionStatus
+{
+ ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished */
+ ADC_CONVERSION_IS_FINISHED = 8U /**< Alias for current conversion is finished */
+};
+
+/** @enum adc1HwTriggerSource
+* @brief Alias names for hardware trigger source
+* This enumeration is used to provide alias names for the hardware trigger sources:
+*/
+
+enum adc1HwTriggerSource
+{
+ ADC1_EVENT = 0U, /**< Alias for event pin */
+ ADC1_HET1_8 = 1U, /**< Alias for HET1 pin 8 */
+ ADC1_HET1_10 = 2U, /**< Alias for HET1 pin 10 */
+ ADC1_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */
+ ADC1_HET1_12 = 4U, /**< Alias for HET1 pin 12 */
+ ADC1_HET1_14 = 5U, /**< Alias for HET1 pin 14 */
+ ADC1_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */
+ ADC1_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */
+
+ ADC1_HET2_5 = 1U, /**< Alias for HET2 pin 5 */
+ ADC1_HET1_27 = 2U, /**< Alias for HET1 pin 27 */
+ ADC1_HET1_17 = 4U, /**< Alias for HET1 pin 17 */
+ ADC1_HET1_19 = 5U, /**< Alias for HET1 pin 19 */
+ ADC1_HET1_11 = 6U, /**< Alias for HET1 pin 11 */
+ ADC1_HET2_13 = 7U, /**< Alias for HET2 pin 13 */
+
+ ADC1_EPWM_B = 1U, /**< Alias for B Signal EPWM */
+ ADC1_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */
+ ADC1_HET2_1 = 5U, /**< Alias for HET2 pin 1 */
+ ADC1_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */
+ ADC1_EPWM_AB = 7U /**< Alias for AB Signal EPWM */
+
+};
+
+/** @enum adc2HwTriggerSource
+* @brief Alias names for hardware trigger source
+* This enumeration is used to provide alias names for the hardware trigger sources:
+*/
+
+enum adc2HwTriggerSource
+{
+ ADC2_EVENT = 0U, /**< Alias for event pin */
+ ADC2_HET1_8 = 1U, /**< Alias for HET1 pin 8 */
+ ADC2_HET1_10 = 2U, /**< Alias for HET1 pin 10 */
+ ADC2_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */
+ ADC2_HET1_12 = 4U, /**< Alias for HET1 pin 12 */
+ ADC2_HET1_14 = 5U, /**< Alias for HET1 pin 14 */
+ ADC2_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */
+ ADC2_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */
+ ADC2_HET2_5 = 1U, /**< Alias for HET2 pin 5 */
+ ADC2_HET1_27 = 2U, /**< Alias for HET1 pin 27 */
+ ADC2_HET1_17 = 4U, /**< Alias for HET1 pin 17 */
+ ADC2_HET1_19 = 5U, /**< Alias for HET1 pin 19 */
+ ADC2_HET1_11 = 6U, /**< Alias for HET1 pin 11 */
+ ADC2_HET2_13 = 7U, /**< Alias for HET2 pin 13 */
+
+ ADC2_EPWM_B = 1U, /**< Alias for B Signal EPWM */
+ ADC2_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */
+ ADC2_HET2_1 = 5U, /**< Alias for HET2 pin 1 */
+ ADC2_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */
+ ADC2_EPWM_AB = 7U /**< Alias for AB Signal EPWM */
+
+};
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @struct adcData
+* @brief ADC Conversion data structure
+*
+* This type is used to pass adc conversion data.
+*/
+/** @typedef adcData_t
+* @brief ADC Data Type Definition
+*/
+typedef struct adcData
+{
+ uint32 id; /**< Channel/Pin Id */
+ uint16 value; /**< Conversion data value */
+} adcData_t;
+
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+typedef struct adc_config_reg
+{
+ uint32 CONFIG_OPMODECR;
+ uint32 CONFIG_CLOCKCR;
+ uint32 CONFIG_GxMODECR[3U];
+ uint32 CONFIG_G0SRC;
+ uint32 CONFIG_G1SRC;
+ uint32 CONFIG_G2SRC;
+ uint32 CONFIG_BNDCR;
+ uint32 CONFIG_BNDEND;
+ uint32 CONFIG_G0SAMP;
+ uint32 CONFIG_G1SAMP;
+ uint32 CONFIG_G2SAMP;
+ uint32 CONFIG_G0SAMPDISEN;
+ uint32 CONFIG_G1SAMPDISEN;
+ uint32 CONFIG_G2SAMPDISEN;
+ uint32 CONFIG_PARCR;
+}adc_config_reg_t;
+
+#define ADC1_OPMODECR_CONFIGVALUE 0x81140001U
+#define ADC1_CLOCKCR_CONFIGVALUE (25U)
+
+#define ADC1_G0MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U)
+#define ADC1_G1MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000020U | (uint32)0x00000000U | (uint32)0x00000000U)
+#define ADC1_G2MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U)
+
+#define ADC1_G0SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT)
+#define ADC1_G1SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT)
+#define ADC1_G2SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT)
+
+#define ADC1_BNDCR_CONFIGVALUE ((uint32)((uint32)0U << 16U)|(0U + 10U))
+#define ADC1_BNDEND_CONFIGVALUE (2U)
+
+#define ADC1_G0SAMP_CONFIGVALUE (0U)
+#define ADC1_G1SAMP_CONFIGVALUE (0U)
+#define ADC1_G2SAMP_CONFIGVALUE (0U)
+
+#define ADC1_G0SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U)
+#define ADC1_G1SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U)
+#define ADC1_G2SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U)
+
+#define ADC1_PARCR_CONFIGVALUE (0x00000005U)
+
+
+/**
+ * @defgroup ADC ADC
+ * @brief Analog To Digital Converter Module.
+ *
+ * The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit resolution
+ *
+ * Related Files
+ * - reg_adc.h
+ * - adc.h
+ * - adc.c
+ * @addtogroup ADC
+ * @{
+ */
+
+/* ADC Interface Functions */
+
+void adcInit(void);
+void adcStartConversion(adcBASE_t *adc, uint32 group);
+void adcStopConversion(adcBASE_t *adc, uint32 group);
+void adcResetFiFo(adcBASE_t *adc, uint32 group);
+uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t *data);
+uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group);
+uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group);
+void adcEnableNotification(adcBASE_t *adc, uint32 group);
+void adcDisableNotification(adcBASE_t *adc, uint32 group);
+void adcCalibration(adcBASE_t *adc);
+uint32 adcMidPointCalibration(adcBASE_t *adc);
+void adcSetEVTPin(adcBASE_t *adc, uint32 value);
+uint32 adcGetEVTPin(adcBASE_t *adc);
+
+void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type);
+void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void adcNotification(adcBASE_t *adc, uint32 group)
+* @brief Group notification
+* @param[in] adc Pointer to ADC node:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group number of ADC node:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* @note This function has to be provide by the user.
+*/
+void adcNotification(adcBASE_t *adc, uint32 group);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif
Index: firmware/include/can.h
===================================================================
diff -u
--- firmware/include/can.h (revision 0)
+++ firmware/include/can.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1008 @@
+/** @file can.h
+* @brief CAN Driver Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the CAN driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __CAN_H__
+#define __CAN_H__
+
+#include "reg_can.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* CAN General Definitions */
+
+/** @def canLEVEL_ACTIVE
+* @brief Alias name for CAN error operation level active (Error counter 0-31)
+*/
+#define canLEVEL_ACTIVE 0x00U
+
+/** @def canLEVEL_PASSIVE
+* @brief Alias name for CAN error operation level passive (Error counter 32-63)
+*/
+#define canLEVEL_PASSIVE 0x20U
+
+/** @def canLEVEL_WARNING
+* @brief Alias name for CAN error operation level warning (Error counter 64-127)
+*/
+#define canLEVEL_WARNING 0x40U
+
+/** @def canLEVEL_BUS_OFF
+* @brief Alias name for CAN error operation level bus off (Error counter 128-255)
+*/
+#define canLEVEL_BUS_OFF 0x80U
+
+/** @def canLEVEL_PARITY_ERR
+* @brief Alias name for CAN Parity error (Error counter 256-511)
+*/
+#define canLEVEL_PARITY_ERR 0x100U
+
+/** @def canLEVEL_TxOK
+* @brief Alias name for CAN Sucessful Transmission
+*/
+#define canLEVEL_TxOK 0x08U
+
+/** @def canLEVEL_RxOK
+* @brief Alias name for CAN Sucessful Reception
+*/
+#define canLEVEL_RxOK 0x10U
+
+/** @def canLEVEL_WakeUpPnd
+* @brief Alias name for CAN Initiated a WakeUp to system
+*/
+#define canLEVEL_WakeUpPnd 0x200U
+
+/** @def canLEVEL_PDA
+* @brief Alias name for CAN entered low power mode successfully.
+*/
+#define canLEVEL_PDA 0x400U
+
+/** @def canERROR_NO
+* @brief Alias name for no CAN error occurred
+*/
+#define canERROR_OK 0U
+
+/** @def canERROR_STUFF
+* @brief Alias name for CAN stuff error an RX message
+*/
+#define canERROR_STUFF 1U
+
+/** @def canERROR_FORMAT
+* @brief Alias name for CAN form/format error an RX message
+*/
+#define canERROR_FORMAT 2U
+
+/** @def canERROR_ACKNOWLEDGE
+* @brief Alias name for CAN TX message wasn't acknowledged
+*/
+#define canERROR_ACKNOWLEDGE 3U
+
+/** @def canERROR_BIT1
+* @brief Alias name for CAN TX message sending recessive level but monitoring dominant
+*/
+#define canERROR_BIT1 4U
+
+/** @def canERROR_BIT0
+* @brief Alias name for CAN TX message sending dominant level but monitoring recessive
+*/
+#define canERROR_BIT0 5U
+
+/** @def canERROR_CRC
+* @brief Alias name for CAN RX message received wrong CRC
+*/
+#define canERROR_CRC 6U
+
+/** @def canERROR_NO
+* @brief Alias name for CAN no message has send or received since last call of CANGetLastError
+*/
+#define canERROR_NO 7U
+
+/** @def canMESSAGE_BOX1
+* @brief Alias name for CAN message box 1
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX1 1U
+
+/** @def canMESSAGE_BOX2
+* @brief Alias name for CAN message box 2
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX2 2U
+
+/** @def canMESSAGE_BOX3
+* @brief Alias name for CAN message box 3
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX3 3U
+
+/** @def canMESSAGE_BOX4
+* @brief Alias name for CAN message box 4
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX4 4U
+
+/** @def canMESSAGE_BOX5
+* @brief Alias name for CAN message box 5
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX5 5U
+
+/** @def canMESSAGE_BOX6
+* @brief Alias name for CAN message box 6
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX6 6U
+
+/** @def canMESSAGE_BOX7
+* @brief Alias name for CAN message box 7
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX7 7U
+
+/** @def canMESSAGE_BOX8
+* @brief Alias name for CAN message box 8
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX8 8U
+
+/** @def canMESSAGE_BOX9
+* @brief Alias name for CAN message box 9
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX9 9U
+
+/** @def canMESSAGE_BOX10
+* @brief Alias name for CAN message box 10
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX10 10U
+
+/** @def canMESSAGE_BOX11
+* @brief Alias name for CAN message box 11
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX11 11U
+
+/** @def canMESSAGE_BOX12
+* @brief Alias name for CAN message box 12
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX12 12U
+
+/** @def canMESSAGE_BOX13
+* @brief Alias name for CAN message box 13
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX13 13U
+
+/** @def canMESSAGE_BOX14
+* @brief Alias name for CAN message box 14
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX14 14U
+
+/** @def canMESSAGE_BOX15
+* @brief Alias name for CAN message box 15
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX15 15U
+
+/** @def canMESSAGE_BOX16
+* @brief Alias name for CAN message box 16
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX16 16U
+
+/** @def canMESSAGE_BOX17
+* @brief Alias name for CAN message box 17
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX17 17U
+
+/** @def canMESSAGE_BOX18
+* @brief Alias name for CAN message box 18
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX18 18U
+
+/** @def canMESSAGE_BOX19
+* @brief Alias name for CAN message box 19
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX19 19U
+
+/** @def canMESSAGE_BOX20
+* @brief Alias name for CAN message box 20
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX20 20U
+
+/** @def canMESSAGE_BOX21
+* @brief Alias name for CAN message box 21
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX21 21U
+
+/** @def canMESSAGE_BOX22
+* @brief Alias name for CAN message box 22
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX22 22U
+
+/** @def canMESSAGE_BOX23
+* @brief Alias name for CAN message box 23
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX23 23U
+
+/** @def canMESSAGE_BOX24
+* @brief Alias name for CAN message box 24
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX24 24U
+
+/** @def canMESSAGE_BOX25
+* @brief Alias name for CAN message box 25
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX25 25U
+
+/** @def canMESSAGE_BOX26
+* @brief Alias name for CAN message box 26
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX26 26U
+
+/** @def canMESSAGE_BOX27
+* @brief Alias name for CAN message box 27
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX27 27U
+
+/** @def canMESSAGE_BOX28
+* @brief Alias name for CAN message box 28
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX28 28U
+
+/** @def canMESSAGE_BOX29
+* @brief Alias name for CAN message box 29
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX29 29U
+
+/** @def canMESSAGE_BOX30
+* @brief Alias name for CAN message box 30
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX30 30U
+
+/** @def canMESSAGE_BOX31
+* @brief Alias name for CAN message box 31
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX31 31U
+
+/** @def canMESSAGE_BOX32
+* @brief Alias name for CAN message box 32
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX32 32U
+
+/** @def canMESSAGE_BOX33
+* @brief Alias name for CAN message box 33
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX33 33U
+
+/** @def canMESSAGE_BOX34
+* @brief Alias name for CAN message box 34
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX34 34U
+
+/** @def canMESSAGE_BOX35
+* @brief Alias name for CAN message box 35
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX35 35U
+
+/** @def canMESSAGE_BOX36
+* @brief Alias name for CAN message box 36
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX36 36U
+
+/** @def canMESSAGE_BOX37
+* @brief Alias name for CAN message box 37
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX37 37U
+
+/** @def canMESSAGE_BOX38
+* @brief Alias name for CAN message box 38
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX38 38U
+
+/** @def canMESSAGE_BOX39
+* @brief Alias name for CAN message box 39
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX39 39U
+
+/** @def canMESSAGE_BOX40
+* @brief Alias name for CAN message box 40
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX40 40U
+
+/** @def canMESSAGE_BOX41
+* @brief Alias name for CAN message box 41
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX41 41U
+
+/** @def canMESSAGE_BOX42
+* @brief Alias name for CAN message box 42
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX42 42U
+
+/** @def canMESSAGE_BOX43
+* @brief Alias name for CAN message box 43
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX43 43U
+
+/** @def canMESSAGE_BOX44
+* @brief Alias name for CAN message box 44
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX44 44U
+
+/** @def canMESSAGE_BOX45
+* @brief Alias name for CAN message box 45
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX45 45U
+
+/** @def canMESSAGE_BOX46
+* @brief Alias name for CAN message box 46
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX46 46U
+
+/** @def canMESSAGE_BOX47
+* @brief Alias name for CAN message box 47
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX47 47U
+
+/** @def canMESSAGE_BOX48
+* @brief Alias name for CAN message box 48
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX48 48U
+
+/** @def canMESSAGE_BOX49
+* @brief Alias name for CAN message box 49
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX49 49U
+
+/** @def canMESSAGE_BOX50
+* @brief Alias name for CAN message box 50
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX50 50U
+
+/** @def canMESSAGE_BOX51
+* @brief Alias name for CAN message box 51
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX51 51U
+
+/** @def canMESSAGE_BOX52
+* @brief Alias name for CAN message box 52
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX52 52U
+
+/** @def canMESSAGE_BOX53
+* @brief Alias name for CAN message box 53
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX53 53U
+
+/** @def canMESSAGE_BOX54
+* @brief Alias name for CAN message box 54
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX54 54U
+
+/** @def canMESSAGE_BOX55
+* @brief Alias name for CAN message box 55
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX55 55U
+
+/** @def canMESSAGE_BOX56
+* @brief Alias name for CAN message box 56
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX56 56U
+
+/** @def canMESSAGE_BOX57
+* @brief Alias name for CAN message box 57
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX57 57U
+
+/** @def canMESSAGE_BOX58
+* @brief Alias name for CAN message box 58
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX58 58U
+
+/** @def canMESSAGE_BOX59
+* @brief Alias name for CAN message box 59
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX59 59U
+
+/** @def canMESSAGE_BOX60
+* @brief Alias name for CAN message box 60
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX60 60U
+
+/** @def canMESSAGE_BOX61
+* @brief Alias name for CAN message box 61
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX61 61U
+
+/** @def canMESSAGE_BOX62
+* @brief Alias name for CAN message box 62
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX62 62U
+
+/** @def canMESSAGE_BOX63
+* @brief Alias name for CAN message box 63
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX63 63U
+
+/** @def canMESSAGE_BOX64
+* @brief Alias name for CAN message box 64
+*
+* @note This value should be used for API argument @a messageBox
+*/
+#define canMESSAGE_BOX64 64U
+
+
+/** @enum canloopBackType
+* @brief canLoopback type definition
+*/
+/** @typedef canloopBackType_t
+* @brief canLoopback type Type Definition
+*
+* This type is used to select the can module Loopback type Digital or Analog loopback.
+*/
+typedef enum canloopBackType
+{
+ Internal_Lbk = 0x00000010U,
+ External_Lbk = 0x00000100U,
+ Internal_Silent_Lbk = 0x00000018U
+}canloopBackType_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* Configuration registers */
+typedef struct can_config_reg
+{
+ uint32 CONFIG_CTL;
+ uint32 CONFIG_ES;
+ uint32 CONFIG_BTR;
+ uint32 CONFIG_TEST;
+ uint32 CONFIG_ABOTR;
+ uint32 CONFIG_INTMUX0;
+ uint32 CONFIG_INTMUX1;
+ uint32 CONFIG_INTMUX2;
+ uint32 CONFIG_INTMUX3;
+ uint32 CONFIG_TIOC;
+ uint32 CONFIG_RIOC;
+} can_config_reg_t;
+
+
+/* Configuration registers initial value for CAN1*/
+#define CAN1_CTL_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)((uint32)0x00000005U << 10U) | 0x00020002U)
+#define CAN1_ES_CONFIGVALUE 0x00000007U
+#define CAN1_BTR_CONFIGVALUE ((uint32)((uint32)0U << 16U) \
+ | (uint32)((uint32)(6U - 1U) << 12U) \
+ | (uint32)((uint32)((3U + 6U) - 1U) << 8U) \
+ | (uint32)((uint32)(4U - 1U) << 6U) | (uint32)25U)
+#define CAN1_TEST_CONFIGVALUE 0x00000080U
+#define CAN1_ABOTR_CONFIGVALUE ((uint32)(0U))
+#define CAN1_INTMUX0_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000002U \
+ | (uint32)0x00000004U \
+ | (uint32)0x00000008U \
+ | (uint32)0x00000010U \
+ | (uint32)0x00000020U \
+ | (uint32)0x00000040U \
+ | (uint32)0x00000080U \
+ | (uint32)0x00000100U \
+ | (uint32)0x00000200U \
+ | (uint32)0x00000400U \
+ | (uint32)0x00000800U \
+ | (uint32)0x00001000U \
+ | (uint32)0x00002000U \
+ | (uint32)0x00004000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define CAN1_INTMUX1_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define CAN1_INTMUX2_CONFIGVALUE 0x00000000U
+#define CAN1_INTMUX3_CONFIGVALUE 0x00000000U
+#define CAN1_TIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \
+ |(uint32)((uint32)0U << 17U ) \
+ |(uint32)((uint32)0U << 16U ) \
+ |(uint32)((uint32)1U << 3U ) \
+ |(uint32)((uint32)1U << 2U ) \
+ |(uint32)((uint32)1U << 1U ))
+#define CAN1_RIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \
+ |(uint32)((uint32)0U << 17U ) \
+ |(uint32)((uint32)0U << 16U ) \
+ |(uint32)((uint32)1U << 3U ) \
+ |(uint32)((uint32)0U << 2U ) \
+ |(uint32)((uint32)0U << 1U ))
+
+
+/* Configuration registers initial value for CAN2*/
+#define CAN2_CTL_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)((uint32)0x00000005U << 10U) | 0x00020002U)
+#define CAN2_ES_CONFIGVALUE 0x00000007U
+#define CAN2_BTR_CONFIGVALUE ((uint32)((uint32)0U << 16U) \
+ | (uint32)((uint32)(2U - 1U) << 12U) \
+ | (uint32)((uint32)((3U + 2U) - 1U) << 8U) \
+ | (uint32)((uint32)(2U - 1U) << 6U) | (uint32)25U)
+#define CAN2_TEST_CONFIGVALUE 0x00000080U
+#define CAN2_ABOTR_CONFIGVALUE ((uint32)(0U))
+#define CAN2_INTMUX0_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define CAN2_INTMUX1_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define CAN2_INTMUX2_CONFIGVALUE 0x00000000U
+#define CAN2_INTMUX3_CONFIGVALUE 0x00000000U
+#define CAN2_TIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \
+ |(uint32)((uint32)0U << 17U ) \
+ |(uint32)((uint32)0U << 16U )\
+ |(uint32)((uint32)0U << 3U ) \
+ |(uint32)((uint32)1U << 2U ) \
+ |(uint32)((uint32)1U << 1U ))
+#define CAN2_RIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \
+ |(uint32)((uint32)0U << 17U ) \
+ |(uint32)((uint32)0U << 16U )\
+ |(uint32)((uint32)0U << 3U ) \
+ |(uint32)((uint32)1U << 2U ) \
+ |(uint32)((uint32)0U << 1U ))
+
+/* Configuration registers initial value for CAN3*/
+#define CAN3_CTL_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)((uint32)0x00000005U << 10U) | 0x00020002U)
+#define CAN3_ES_CONFIGVALUE 0x00000007U
+#define CAN3_BTR_CONFIGVALUE ((uint32)((uint32)0U << 16U) \
+ | (uint32)((uint32)(2U - 1U) << 12U) \
+ | (uint32)((uint32)((3U + 2U) - 1U) << 8U) \
+ | (uint32)((uint32)(2U - 1U) << 6U) | (uint32)25U)
+#define CAN3_TEST_CONFIGVALUE 0x00000080U
+#define CAN3_ABOTR_CONFIGVALUE ((uint32)(0U))
+#define CAN3_INTMUX0_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define CAN3_INTMUX1_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define CAN3_INTMUX2_CONFIGVALUE 0x00000000U
+#define CAN3_INTMUX3_CONFIGVALUE 0x00000000U
+#define CAN3_TIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \
+ |(uint32)((uint32)0U << 17U ) \
+ |(uint32)((uint32)0U << 16U )\
+ |(uint32)((uint32)0U << 3U ) \
+ |(uint32)((uint32)1U << 2U ) \
+ |(uint32)((uint32)1U << 1U ))
+#define CAN3_RIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \
+ |(uint32)((uint32)0U << 17U ) \
+ |(uint32)((uint32)0U << 16U )\
+ |(uint32)((uint32)0U << 3U ) \
+ |(uint32)((uint32)1U << 2U ) \
+ |(uint32)((uint32)0U << 1U ))
+
+/**
+ * @defgroup CAN CAN
+ * @brief Controller Area Network Module.
+ *
+ * The Controller Area Network is a high-integrity, serial, multi-master communication protocol for distributed
+ * real-time applications. This CAN module is implemented according to ISO 11898-1 and is suitable for
+ * industrial, automotive and general embedded communications
+ *
+ * Related Files
+ * - reg_can.h
+ * - can.h
+ * - can.c
+ * @addtogroup CAN
+ * @{
+ */
+
+/* CAN Interface Functions */
+
+void canInit(void);
+uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data);
+uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data);
+uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox);
+uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * data);
+uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox);
+uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox);
+uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox);
+uint32 canGetLastError(canBASE_t *node);
+uint32 canGetErrorLevel(canBASE_t *node);
+void canEnableErrorNotification(canBASE_t *node);
+void canDisableErrorNotification(canBASE_t *node);
+void canEnableStatusChangeNotification(canBASE_t *node);
+void canDisableStatusChangeNotification(canBASE_t *node);
+void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype);
+void canDisableloopback(canBASE_t *node);
+void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir);
+void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue);
+uint32 canIoTxGetBit(canBASE_t *node);
+uint32 canIoRxGetBit(canBASE_t *node);
+uint32 canGetID(canBASE_t *node, uint32 messageBox);
+void canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal);
+void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type);
+void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type);
+void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void canErrorNotification(canBASE_t *node, uint32 notification)
+* @brief Error notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] notification Error notification code:
+* - canLEVEL_PASSIVE (0x20) : When RX- or TX error counter are between 32 and 63
+* - canLEVEL_WARNING (0x40) : When RX- or TX error counter are between 64 and 127
+* - canLEVEL_BUS_OFF (0x80) : When RX- or TX error counter are between 128 and 255
+* - canLEVEL_PARITY_ERR (0x100): When RX- or TX error counter are above 256
+*
+* @note This function has to be provide by the user.
+*/
+void canErrorNotification(canBASE_t *node, uint32 notification);
+
+/** @fn void canStatusChangeNotification(canBASE_t *node, uint32 notification)
+* @brief Status Change notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] notification Status change notification code:
+* - canLEVEL_TxOK (0x08) : When successful transmission
+* - canLEVEL_RxOK (0x10) : When successful reception
+* - canLEVEL_WakeUpPnd (0x200): When successful WakeUp to system initiated
+* - canLEVEL_PDA (0x400): When successful low power mode entrance
+*
+* @note This function has to be provide by the user.
+*/
+void canStatusChangeNotification(canBASE_t *node, uint32 notification);
+
+/** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox)
+* @brief Message notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+*
+* @note This function has to be provide by the user.
+*/
+void canMessageNotification(canBASE_t *node, uint32 messageBox);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/crc.h
===================================================================
diff -u
--- firmware/include/crc.h (revision 0)
+++ firmware/include/crc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,326 @@
+/** @file CRC.h
+* @brief CRC Driver Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the CRC driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#include "reg_crc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* CRC General Definitions */
+
+/** @def CRCLEVEL_ACTIVE
+* @brief Alias name for CRC error operation level active
+*/
+#define CRCLEVEL_ACTIVE 0x00U
+
+
+/** @def CRC_AUTO
+* @brief Alias name for CRC auto mode
+*/
+#define CRC_AUTO 0x00000001U
+
+
+/** @def CRC_SEMI_CPU
+* @brief Alias name for semi cpu mode setting
+*/
+#define CRC_SEMI_CPU 0x00000002U
+
+
+/** @def CRC_FULL_CPU
+* @brief Alias name for CRC cpu full mode
+*/
+#define CRC_FULL_CPU 0x00000003U
+
+
+/** @def CRC_CH4_TO
+* @brief Alias name for channel4 time out interrupt flag
+*/
+#define CRC_CH4_TO 0x10000000U
+
+/** @def CRC_CH4_UR
+* @brief Alias name for channel4 underrun interrupt flag
+*/
+#define CRC_CH4_UR 0x08000000U
+
+/** @def CRC_CH4_OR
+* @brief Alias name for channel4 overrun interrupt flag
+*/
+#define CRC_CH4_OR 0x04000000U
+
+/** @def CRC_CH4_FAIL
+* @brief Alias name for channel4 crc fail interrupt flag
+*/
+#define CRC_CH4_FAIL 0x02000000U
+
+/** @def CRC_CH4_CC
+* @brief Alias name for channel4 compression complete interrupt flag
+*/
+#define CRC_CH4_CC 0x01000000U
+
+/** @def CRC_CH3_TO
+* @brief Alias name for channel3 time out interrupt flag
+*/
+#define CRC_CH3_TO 0x00100000U
+
+/** @def CRC_CH3_UR
+* @brief Alias name for channel3 underrun interrupt flag
+*/
+#define CRC_CH3_UR 0x00080000U
+
+/** @def CRC_CH3_OR
+* @brief Alias name for channel3 overrun interrupt flag
+*/
+#define CRC_CH3_OR 0x00040000U
+
+/** @def CRC_CH3_FAIL
+* @brief Alias name for channel3 crc fail interrupt flag
+*/
+#define CRC_CH3_FAIL 0x00020000U
+
+/** @def CRC_CH3_CC
+* @brief Alias name for channel3 compression complete interrupt flag
+*/
+#define CRC_CH3_CC 0x00010000U
+
+/** @def CRC_CH2_TO
+* @brief Alias name for channel2 time out interrupt flag
+*/
+#define CRC_CH2_TO 0x00001000U
+
+/** @def CRC_CH2_UR
+* @brief Alias name for channel2 underrun interrupt flag
+*/
+#define CRC_CH2_UR 0x00000800U
+
+/** @def CRC_CH2_OR
+* @brief Alias name for channel2 overrun interrupt flag
+*/
+#define CRC_CH2_OR 0x00000400U
+
+/** @def CRC_CH2_FAIL
+* @brief Alias name for channel2 crc fail interrupt flag
+*/
+#define CRC_CH2_FAIL 0x00000200U
+
+/** @def CRC_CH2_CC
+* @brief Alias name for channel2 compression complete interrupt flag
+*/
+#define CRC_CH2_CC 0x00000100U
+
+/** @def CRC_CH1_TO
+* @brief Alias name for channel1 time out interrupt flag
+*/
+#define CRC_CH1_TO 0x00000010U
+
+/** @def CRC_CH1_UR
+* @brief Alias name for channel1 underrun interrupt flag
+*/
+#define CRC_CH1_UR 0x00000008U
+
+
+/** @def CRC_CH1_OR
+* @brief Alias name for channel1 overrun interrupt flag
+*/
+#define CRC_CH1_OR 0x00000004U
+
+/** @def CRC_CH1_FAIL
+* @brief Alias name for channel1 crc fail interrupt flag
+*/
+#define CRC_CH1_FAIL 0x00000002U
+
+/** @def CRC_CH1_CC
+* @brief Alias name for channel1 compression complete interrupt flag
+*/
+#define CRC_CH1_CC 0x00000001U
+
+/** @def CRC_CH1
+* @brief Alias name for channel1
+*/
+#define CRC_CH1 0x00000000U
+
+/** @def CRC_CH1
+* @brief Alias name for channel2
+*/
+#define CRC_CH2 0x00000001U
+
+/** @def CRC_CH3
+* @brief Alias name for channel3
+*/
+#define CRC_CH3 0x00000002U
+
+/** @def CRC_CH4
+* @brief Alias name for channel4
+*/
+#define CRC_CH4 0x00000003U
+
+/** @struct crcModConfig
+* @brief CRC mode specific parameters
+*
+* This type is used to pass crc mode specific parameters
+*/
+/** @typedef crcModConfig_t
+* @brief CRC Data Type Definition
+*/
+typedef struct crcModConfig
+{
+ uint32 mode; /**< Mode of operation */
+ uint32 crc_channel; /**< CRC channel-0,1 */
+ uint64 * src_data_pat; /**< Pattern data */
+ uint32 data_length; /**< Pattern data length.Number of 64 bit size word*/
+} crcModConfig_t;
+
+/** @struct crcConfig
+* @brief CRC configuration for different modes
+*
+* This type is used to pass crc configuration
+*/
+/** @typedef crcConfig_t
+* @brief CRC Data Type Definition
+*/
+typedef struct crcConfig
+{
+ uint32 crc_channel; /**< CRC channel-0,1 */
+ uint32 mode; /**< Mode of operation */
+ uint32 pcount; /**< Pattern count*/
+ uint32 scount; /**< Sector count */
+ uint32 wdg_preload; /**< Watchdog period */
+ uint32 block_preload; /**< Block period*/
+
+} crcConfig_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+typedef struct crc_config_reg
+{
+ uint32 CONFIG_CTRL0;
+ uint32 CONFIG_CTRL1;
+ uint32 CONFIG_CTRL2;
+ uint32 CONFIG_INTS;
+ uint32 CONFIG_PCOUNT_REG1;
+ uint32 CONFIG_SCOUNT_REG1;
+ uint32 CONFIG_WDTOPLD1;
+ uint32 CONFIG_BCTOPLD1;
+ uint32 CONFIG_PCOUNT_REG2;
+ uint32 CONFIG_SCOUNT_REG2;
+ uint32 CONFIG_WDTOPLD2;
+ uint32 CONFIG_BCTOPLD2;
+}crc_config_reg_t;
+
+#define CRC_CTRL0_CONFIGVALUE 0x00000000U
+#define CRC_CTRL1_CONFIGVALUE 0x00000000U
+#define CRC_CTRL2_CONFIGVALUE ((uint32)((uint32)0U << 4U) | (uint32)(CRC_FULL_CPU) | (uint32)((uint32)CRC_FULL_CPU << 8U))
+#define CRC_INTS_CONFIGVALUE (0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U)
+#define CRC_PCOUNT_REG1_CONFIGVALUE (0x00000000U)
+#define CRC_SCOUNT_REG1_CONFIGVALUE (0x00000000U)
+#define CRC_WDTOPLD1_CONFIGVALUE (0x00000000U)
+#define CRC_BCTOPLD1_CONFIGVALUE (0x00000000U)
+#define CRC_PCOUNT_REG2_CONFIGVALUE (0x00000000U)
+#define CRC_SCOUNT_REG2_CONFIGVALUE (0x00000000U)
+#define CRC_WDTOPLD2_CONFIGVALUE (0x00000000U)
+#define CRC_BCTOPLD2_CONFIGVALUE (0x00000000U)
+
+/**
+ * @defgroup CRC CRC
+ * @brief Cyclic Redundancy Check Controller Module.
+ *
+ * The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) to verify the
+ * integrity of memory system. A signature representing the contents of the memory is obtained when the
+ * contents of the memory are read into CRC controller. The responsibility of CRC controller is to calculate
+ * the signature for a set of data and then compare the calculated signature value against a pre-determined
+ * good signature value. CRC controller supports two channels to perform CRC calculation on multiple
+ * memories in parallel and can be used on any memory system.
+ *
+ * Related Files
+ * - reg_crc.h
+ * - crc.h
+ * - crc.c
+ * @addtogroup CRC
+ * @{
+ */
+
+/* CRC Interface Functions */
+void crcInit(void);
+void crcSendPowerDown(crcBASE_t *crc);
+void crcSignGen(crcBASE_t *crc,crcModConfig_t *param);
+void crcSetConfig(crcBASE_t *crc,crcConfig_t *param);
+uint64 crcGetPSASig(crcBASE_t *crc,uint32 channel);
+uint64 crcGetSectorSig(crcBASE_t *crc,uint32 channel);
+uint32 crcGetFailedSector(crcBASE_t *crc,uint32 channel);
+uint32 crcGetIntrPend(crcBASE_t *crc,uint32 channel);
+void crcChannelReset(crcBASE_t *crc,uint32 channel);
+void crcEnableNotification(crcBASE_t *crc, uint32 flags);
+void crcDisableNotification(crcBASE_t *crc, uint32 flags);
+void crcGetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void crcNotification(crcBASE_t *crc, uint32 flags)
+* @brief Interrupt callback
+* @param[in] crc - crc module base address
+* @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt. The parameter passed to the callback is a copy of the
+* interrupt flag register.
+*/
+void crcNotification(crcBASE_t *crc, uint32 flags);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
Index: firmware/include/dcc.h
===================================================================
diff -u
--- firmware/include/dcc.h (revision 0)
+++ firmware/include/dcc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,306 @@
+/** @file dcc.h
+* @brief DCC Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __DCC_H__
+#define __DCC_H__
+
+#include "reg_dcc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* DCC General Definitions */
+
+/** @def dcc1CNT0_CLKSRC_HFLPO
+* @brief Alias name for DCC1 Counter 0 Clock Source HFLPO
+*
+* This is an alias name for the Clock Source HFLPO for DCC1 Counter 0.
+*
+* @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U
+
+/** @def dcc1CNT0_CLKSRC_TCK
+* @brief Alias name for DCC1 Counter 0 Clock Source TCK
+*
+* This is an alias name for the Clock Source TCK for DCC1 Counter 0.
+*
+* @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_TCK 0x0000000AU
+
+/** @def dcc1CNT0_CLKSRC_OSCIN
+* @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
+*
+* This is an alias name for the Clock Source OSCIN for DCC1 Counter 0.
+*
+* @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU
+
+/** @def dcc1CNT1_CLKSRC_PLL1
+* @brief Alias name for DCC1 Counter 1 Clock Source PLL1
+*
+* This is an alias name for the Clock Source PLL for DCC1 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U
+
+/** @def dcc1CNT1_CLKSRC_PLL2
+* @brief Alias name for DCC1 Counter 1 Clock Source PLL2
+*
+* This is an alias name for the Clock Source OSCIN for DCC1 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U
+
+/** @def dcc1CNT1_CLKSRC_LFLPO
+* @brief Alias name for DCC1 Counter 1 Clock Source LFLPO
+*
+* This is an alias name for the Clock Source LFLPO for DCC1 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_LFLPO 0x0000A002U
+
+/** @def dcc1CNT1_CLKSRC_HFLPO
+* @brief Alias name for DCC1 Counter 1 Clock Source HFLPO
+*
+* This is an alias name for the Clock Source HFLPO for DCC1 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_HFLPO 0x0000A003U
+
+/** @def dcc1CNT1_CLKSRC_EXTCLKIN1
+* @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1
+*
+* This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A005U
+
+/** @def dcc1CNT1_CLKSRC_EXTCLKIN2
+* @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2
+*
+* This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A006U
+
+/** @def dcc1CNT1_CLKSRC_VCLK
+* @brief Alias name for DCC1 Counter 1 Clock Source VCLK
+*
+* This is an alias name for the Clock Source VCLK for DCC1 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_VCLK 0x0000A008U
+
+/** @def dcc1CNT1_CLKSRC_N2HET1_31
+* @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31
+*
+* This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc1CNT1_CLKSRC_N2HET1_31 0x0000500FU
+
+/** @def dcc2CNT0_CLKSRC_TCK
+* @brief Alias name for DCC2 Counter 0 Clock Source TCK
+*
+* This is an alias name for the Clock Source TCK for DCC2 Counter 0.
+*
+* @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc2CNT0_CLKSRC_TCK 0x0000000AU
+
+/** @def dcc1CNT0_CLKSRC_OSCIN
+* @brief Alias name for DCC1 Counter 0 Clock Source OSCIN
+*
+* This is an alias name for the Clock Source OSCIN for DCC2 Counter 0.
+*
+* @note This value should be used for API argument @a cnt0_Clock_Source
+*/
+#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU
+
+/** @def dcc2CNT1_CLKSRC_VCLK
+* @brief Alias name for DCC2 Counter 1 Clock Source VCLK
+*
+* This is an alias name for the Clock Source VCLK for DCC2 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc2CNT1_CLKSRC_VCLK 0x0000A008U
+
+/** @def dcc2CNT1_CLKSRC_N2HET1_0
+* @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0
+*
+* This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1.
+*
+* @note This value should be used for API argument @a cnt1_Clock_Source
+*/
+#define dcc2CNT1_CLKSRC_N2HET1_0 0x0000500FU
+
+/** @def dccNOTIFICATION_DONE
+* @brief Alias name for DCC Done notification
+*
+* This is an alias name for the DCC Done notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define dccNOTIFICATION_DONE 0x0000A000U
+
+/** @def dccNOTIFICATION_ERROR
+* @brief Alias name for DCC Error notification
+*
+* This is an alias name for the DCC Error notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define dccNOTIFICATION_ERROR 0x000000A0U
+
+
+/** @enum dcc1clocksource
+* @brief Alias names for dcc clock sources
+*
+* This enumeration is used to provide alias names for the clock sources:
+*/
+enum dcc1clocksource
+{
+ DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
+ DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/
+ DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
+
+ DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/
+ DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/
+ DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/
+ DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/
+ DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/
+ DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/
+ DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
+ DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
+};
+
+/** @enum dcc2clocksource
+* @brief Alias names for dcc clock sources
+*
+* This enumeration is used to provide alias names for the clock sources:
+*/
+enum dcc2clocksource
+{
+ DCC2_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/
+ DCC2_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/
+
+ DCC2_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/
+ DCC2_CNT1_N2HET2_0 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/
+};
+
+/* Configuration registers */
+typedef struct dcc_config_reg
+{
+ uint32 CONFIG_GCTRL;
+ uint32 CONFIG_CNT0SEED;
+ uint32 CONFIG_VALID0SEED;
+ uint32 CONFIG_CNT1SEED;
+ uint32 CONFIG_CNT1CLKSRC;
+ uint32 CONFIG_CNT0CLKSRC;
+} dcc_config_reg_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/**
+ * @defgroup DCC DCC
+ * @brief Dual-Clock Comparator Module
+ *
+ * The primary purpose of a DCC module is to measure the frequency of a clock signal using a second
+ * known clock signal as a reference. This capability can be used to ensure the correct frequency range for
+ * several different device clock sources, thereby enhancing the system safety metrics.
+ *
+ * Related Files
+ * - reg_dcc.h
+ * - dcc.h
+ * - dcc.c
+ * @addtogroup DCC
+ * @{
+ */
+
+/* DCC Interface Functions */
+void dccInit(void);
+void dccSetCounter0Seed(dccBASE_t *dcc, uint32 cnt0seed);
+void dccSetTolerance(dccBASE_t *dcc, uint32 valid0seed);
+void dccSetCounter1Seed(dccBASE_t *dcc, uint32 cnt1seed);
+void dccSetSeed(dccBASE_t *dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed);
+void dccSelectClockSource(dccBASE_t *dcc, uint32 cnt0_Clock_Source, uint32 cnt1_Clock_Source);
+void dccEnable(dccBASE_t *dcc);
+void dccDisable(dccBASE_t *dcc);
+uint32 dccGetErrStatus(dccBASE_t *dcc);
+
+void dccEnableNotification(dccBASE_t *dcc, uint32 notification);
+void dccDisableNotification(dccBASE_t *dcc, uint32 notification);
+void dcc1GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type);
+void dcc2GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void dccNotification(dccBASE_t *dcc,uint32 flags)
+* @brief Interrupt callback
+* @param[in] dcc - dcc module base address
+* @param[in] flags - status flags
+*
+* This is a callback function provided by the application. It is call when
+* a dcc is complete or detected error.
+*/
+void dccNotification(dccBASE_t *dcc,uint32 flags);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/ecap.h
===================================================================
diff -u
--- firmware/include/ecap.h (revision 0)
+++ firmware/include/ecap.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,260 @@
+/** @file ecap.h
+* @brief ECAP Driver Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the ECAP driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __ECAP_H__
+#define __ECAP_H__
+
+#include "reg_ecap.h"
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+/** @brief Enumeration to define the capture (CAP) interrupts
+*/
+typedef enum
+{
+ ecapInt_CTR_CMP = 0x0080U, /*< Denotes CTR = CMP interrupt */
+ ecapInt_CTR_PRD = 0x0040U, /*< Denotes CTR = PRD interrupt */
+ ecapInt_CTR_OVF = 0x0020U, /*< Denotes CTROVF interrupt */
+ ecapInt_CEVT4 = 0x0010U, /*< Denotes CEVT4 interrupt */
+ ecapInt_CEVT3 = 0x0008U, /*< Denotes CEVT3 interrupt */
+ ecapInt_CEVT2 = 0x0004U, /*< Denotes CEVT2 interrupt */
+ ecapInt_CEVT1 = 0x0002U, /*< Denotes CEVT1 interrupt */
+ ecapInt_Global = 0x0001U, /*< Denotes Capture global interrupt */
+ ecapInt_All = 0x00FFU /*< Denotes All interrupts */
+} ecapInterrupt_t;
+
+/** @brief Enumeration to define the capture (CAP) prescaler values
+*/
+typedef enum
+{
+ ecapPrescale_By_1 = ((uint16)0U << 9U), /*< Divide by 1 */
+ ecapPrescale_By_2 = ((uint16)1U << 9U), /*< Divide by 2 */
+ ecapPrescale_By_4 = ((uint16)2U << 9U), /*< Divide by 4 */
+ ecapPrescale_By_6 = ((uint16)3U << 9U), /*< Divide by 6 */
+ ecapPrescale_By_8 = ((uint16)4U << 9U), /*< Divide by 8 */
+ ecapPrescale_By_10 = ((uint16)5U << 9U), /*< Divide by 10 */
+ ecapPrescale_By_12 = ((uint16)6U << 9U), /*< Divide by 12 */
+ ecapPrescale_By_14 = ((uint16)7U << 9U), /*< Divide by 14 */
+ ecapPrescale_By_16 = ((uint16)8U << 9U), /*< Divide by 16 */
+ ecapPrescale_By_18 = ((uint16)9U << 9U), /*< Divide by 18 */
+ ecapPrescale_By_20 = ((uint16)10U << 9U), /*< Divide by 20 */
+ ecapPrescale_By_22 = ((uint16)11U << 9U), /*< Divide by 22 */
+ ecapPrescale_By_24 = ((uint16)12U << 9U), /*< Divide by 24 */
+ ecapPrescale_By_26 = ((uint16)13U << 9U), /*< Divide by 26 */
+ ecapPrescale_By_28 = ((uint16)14U << 9U), /*< Divide by 28 */
+ ecapPrescale_By_30 = ((uint16)15U << 9U), /*< Divide by 30 */
+ ecapPrescale_By_32 = ((uint16)16U << 9U), /*< Divide by 32 */
+ ecapPrescale_By_34 = ((uint16)17U << 9U), /*< Divide by 34 */
+ ecapPrescale_By_36 = ((uint16)18U << 9U), /*< Divide by 36 */
+ ecapPrescale_By_38 = ((uint16)19U << 9U), /*< Divide by 38 */
+ ecapPrescale_By_40 = ((uint16)20U << 9U), /*< Divide by 40 */
+ ecapPrescale_By_42 = ((uint16)21U << 9U), /*< Divide by 42 */
+ ecapPrescale_By_44 = ((uint16)22U << 9U), /*< Divide by 44 */
+ ecapPrescale_By_46 = ((uint16)23U << 9U), /*< Divide by 46 */
+ ecapPrescale_By_48 = ((uint16)24U << 9U), /*< Divide by 48 */
+ ecapPrescale_By_50 = ((uint16)25U << 9U), /*< Divide by 50 */
+ ecapPrescale_By_52 = ((uint16)26U << 9U), /*< Divide by 52 */
+ ecapPrescale_By_54 = ((uint16)27U << 9U), /*< Divide by 54 */
+ ecapPrescale_By_56 = ((uint16)28U << 9U), /*< Divide by 56 */
+ ecapPrescale_By_58 = ((uint16)29U << 9U), /*< Divide by 58 */
+ ecapPrescale_By_60 = ((uint16)30U << 9U), /*< Divide by 60 */
+ ecapPrescale_By_62 = ((uint16)31U << 9U) /*< Divide by 62 */
+} ecapPrescale_t;
+
+/** @brief Enumeration to define the Sync Out options
+*/
+typedef enum
+{
+ SyncOut_SyncIn = ((uint16)0U << 6U), /*< Sync In used for Sync Out */
+ SyncOut_CTRPRD = ((uint16)1U << 6U), /*< CTR = PRD used for Sync Out */
+ SyncOut_None = ((uint16)2U << 6U) /*< Disables Sync Out */
+} ecapSyncOut_t;
+
+/** @brief Enumeration to define the Polarity
+*/
+typedef enum
+{
+ RISING_EDGE = 0U,
+ FALLING_EDGE = 1U
+}ecapEdgePolarity_t;
+
+typedef enum
+{
+ ACTIVE_HIGH = 0U,
+ ACTIVE_LOW = 1U
+}ecapAPWMPolarity_t;
+
+/** @brief Enumeration to define the Mode of operation
+*/
+typedef enum
+{
+ CONTINUOUS = 0U,
+ ONE_SHOT = 1U
+}ecapMode_t;
+
+/** @brief Enumeration to define the capture events
+*/
+typedef enum
+{
+ CAPTURE_EVENT1 = 0U,
+ CAPTURE_EVENT2 = 1U,
+ CAPTURE_EVENT3 = 2U,
+ CAPTURE_EVENT4 = 3U
+}ecapEvent_t ;
+
+typedef enum
+{
+ RESET_ENABLE = 1U,
+ RESET_DISABLE = 0U
+}ecapReset_t ;
+
+typedef struct ecap_config_reg
+ {
+ uint32 CONFIG_CTRPHS;
+ uint16 CONFIG_ECCTL1;
+ uint16 CONFIG_ECCTL2;
+ uint16 CONFIG_ECEINT;
+}ecap_config_reg_t;
+
+#define ECAP1_CTRPHS_CONFIGVALUE 0x00000000U
+#define ECAP1_ECCTL1_CONFIGVALUE ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP1_ECCTL2_CONFIGVALUE ((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP1_ECEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+
+#define ECAP2_CTRPHS_CONFIGVALUE 0x00000000U
+#define ECAP2_ECCTL1_CONFIGVALUE ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP2_ECCTL2_CONFIGVALUE ((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP2_ECEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+
+#define ECAP3_CTRPHS_CONFIGVALUE 0x00000000U
+#define ECAP3_ECCTL1_CONFIGVALUE ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP3_ECCTL2_CONFIGVALUE ((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP3_ECEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+
+#define ECAP4_CTRPHS_CONFIGVALUE 0x00000000U
+#define ECAP4_ECCTL1_CONFIGVALUE ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP4_ECCTL2_CONFIGVALUE ((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP4_ECEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+
+#define ECAP5_CTRPHS_CONFIGVALUE 0x00000000U
+#define ECAP5_ECCTL1_CONFIGVALUE ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP5_ECCTL2_CONFIGVALUE ((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP5_ECEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+
+#define ECAP6_CTRPHS_CONFIGVALUE 0x00000000U
+#define ECAP6_ECCTL1_CONFIGVALUE ((uint16)((uint16)RISING_EDGE << 0U) | (uint16)((uint16)RESET_DISABLE << 1U) | (uint16)((uint16)RISING_EDGE << 2U) | (uint16)((uint16)RESET_DISABLE << 3U) | (uint16)((uint16)RISING_EDGE << 4U)| (uint16)((uint16)RESET_DISABLE << 5U) | (uint16)((uint16)RISING_EDGE << 6U) | (uint16)((uint16)RESET_DISABLE << 7U) | (uint16)((uint16)0U << 8U) | (uint16)((uint16)0U << 9U))
+#define ECAP6_ECCTL2_CONFIGVALUE ((uint16)((uint16)ONE_SHOT << 0U) | (uint16)((uint16)CAPTURE_EVENT1 << 1U) | (uint16)((uint16)0U << 9U) | (uint16)0x00000010U)
+#define ECAP6_ECEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
+
+/**
+ * @defgroup eCAP eCAP
+ * @brief Enhanced Capture Module.
+ *
+ * The enhanced Capture (eCAP) module is essential in systems where accurate timing of external events is
+ * important. This microcontroller implements 6 instances of the eCAP module.
+ *
+ * Related Files
+ * - reg_ecap.h
+ * - ecap.h
+ * - ecap.c
+ * @addtogroup eCAP
+ * @{
+ */
+void ecapInit(void);
+void ecapSetCounter(ecapBASE_t *ecap, uint32 value);
+void ecapEnableCounterLoadOnSync(ecapBASE_t *ecap, uint32 phase);
+void ecapDisableCounterLoadOnSync(ecapBASE_t *ecap);
+void ecapSetEventPrescaler(ecapBASE_t *ecap, ecapPrescale_t prescale);
+void ecapSetCaptureEvent1(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable);
+void ecapSetCaptureEvent2(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable);
+void ecapSetCaptureEvent3(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable);
+void ecapSetCaptureEvent4(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable);
+void ecapSetCaptureMode(ecapBASE_t *ecap, ecapMode_t capMode, ecapEvent_t event);
+void ecapEnableCapture(ecapBASE_t *ecap);
+void ecapDisableCapture(ecapBASE_t *ecap);
+void ecapStartCounter(ecapBASE_t *ecap);
+void ecapStopCounter(ecapBASE_t *ecap);
+void ecapSetSyncOut(ecapBASE_t *ecap, ecapSyncOut_t syncOutSrc);
+void ecapEnableAPWMmode(ecapBASE_t *ecap, ecapAPWMPolarity_t pwmPolarity, uint32 period, uint32 duty);
+void ecapDisableAPWMMode(ecapBASE_t *ecap);
+void ecapEnableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts);
+void ecapDisableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts);
+uint16 ecapGetEventStatus(ecapBASE_t *ecap, ecapInterrupt_t events);
+void ecapClearFlag(ecapBASE_t *ecap, ecapInterrupt_t events);
+uint32 ecapGetCAP1(ecapBASE_t *ecap);
+uint32 ecapGetCAP2(ecapBASE_t *ecap);
+uint32 ecapGetCAP3(ecapBASE_t *ecap);
+uint32 ecapGetCAP4(ecapBASE_t *ecap);
+void ecap1GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap2GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap3GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap4GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap5GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+void ecap6GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type);
+
+/** @brief Interrupt callback
+* @param[in] ecap Handle to CAP object
+* @param[in] flags Copy of interrupt flags
+*/
+void ecapNotification(ecapBASE_t *ecap,uint16 flags);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+#endif /*end of _CAP_H_ definition */
Index: firmware/include/emac.h
===================================================================
diff -u
--- firmware/include/emac.h (revision 0)
+++ firmware/include/emac.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,404 @@
+/**
+ * \file emac.h
+ *
+ * \brief EMAC APIs and macros.
+ *
+ * This file contains the driver API prototypes and macro definitions.
+ */
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __EMAC_H__
+#define __EMAC_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+#include "hw_reg_access.h"
+#include "hw_emac.h"
+#include "hw_emac_ctrl.h"
+#include "mdio.h"
+#include "phy_dp83640.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/*****************************************************************************/
+/*
+** Macros which can be used as speed parameter to the API EMACRMIISpeedSet
+*/
+#define EMAC_RMIISPEED_10MBPS (0x00000000U)
+#define EMAC_RMIISPEED_100MBPS (0x00008000U)
+
+/* Macros for enabling taken as inputs from HALCoGen GUI. */
+#define EMAC_TX_ENABLE (1U)
+#define EMAC_RX_ENABLE (1U)
+#define EMAC_MII_ENABLE (1U)
+#define EMAC_FULL_DUPLEX_ENABLE (1U)
+#define EMAC_LOOPBACK_ENABLE (0U)
+#define EMAC_BROADCAST_ENABLE (1U)
+#define EMAC_UNICAST_ENABLE (1U)
+#define EMAC_CHANNELNUMBER (0U)
+#define EMAC_PHYADDRESS (0U)
+
+/*
+ * Macros to indicate EMAC Channel Numbers
+ */
+#define EMAC_CHANNEL_0 (0x00000000U)
+#define EMAC_CHANNEL_1 (0x00000001U)
+#define EMAC_CHANNEL_2 (0x00000002U)
+#define EMAC_CHANNEL_3 (0x00000003U)
+#define EMAC_CHANNEL_4 (0x00000004U)
+#define EMAC_CHANNEL_5 (0x00000005U)
+#define EMAC_CHANNEL_6 (0x00000006U)
+#define EMAC_CHANNEL_7 (0x00000007U)
+/* Macros which can be used as duplexMode parameter to the API
+** EMACDuplexSet
+*/
+#define EMAC_DUPLEX_FULL (0x00000001U)
+#define EMAC_DUPLEX_HALF (0x00000000U)
+
+/*
+** Macros which can be used as matchFilt parameters to the API
+** EMACMACAddrSet
+*/
+/* Address not used to match/filter incoming packets */
+#define EMAC_MACADDR_NO_MATCH_NO_FILTER (0x00000000U)
+
+/* Address will be used to filter incoming packets */
+#define EMAC_MACADDR_FILTER (0x00100000U)
+
+/* Address will be used to match incoming packets */
+#define EMAC_MACADDR_MATCH (0x00180000U)
+
+/*
+** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API
+*/
+#define EMAC_INT_CORE0_RX (0x1U)
+#define EMAC_INT_CORE1_RX (0x5U)
+#define EMAC_INT_CORE2_RX (0x9U)
+
+/*
+** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API
+*/
+#define EMAC_INT_CORE0_TX (0x2U)
+#define EMAC_INT_CORE1_TX (0x6U)
+#define EMAC_INT_CORE2_TX (0xAU)
+/* Base Addresses */
+#define EMAC_CTRL_RAM_0_BASE 0xFC520000U
+#define EMAC_0_BASE 0xFCF78000U
+#define EMAC_CTRL_0_BASE 0xFCF78800U
+#define MDIO_0_BASE 0xFCF78900U
+
+/*MAC address length*/
+#define EMAC_HWADDR_LEN 6U
+#define MAX_EMAC_INSTANCE 1U
+#define SIZE_EMAC_CTRL_RAM 0x2000U
+#define MAX_TRANSFER_UNIT 1514U
+#define MAX_RX_PBUF_ALLOC (10U)
+#define MIN_PKT_LEN 60U
+#define MIN_PACKET_SIZE (46U)
+
+
+
+
+#define EMAC_BUF_DESC_OWNER 0x20000000U
+#define EMAC_BUF_DESC_SOP 0x80000000U
+#define EMAC_BUF_DESC_EOP 0x40000000U
+#define EMAC_BUF_DESC_EOQ 0x10000000U
+
+#define EMAC_NETSTATREGS(n) ((uint32)0x200U + (uint32)((n)*4U))
+
+/* Error Signalling Macros */
+#define EMAC_ERR_CONNECT 0x2U /* Not connected. */
+#define EMAC_ERR_OK 0x1U /* No error, everything OK. */
+
+
+/* Macros for Configuration Value Registers */
+#define EMAC_TXCONTROL_CONFIGVALUE 0x00000001U
+#define EMAC_RXCONTROL_CONFIGVALUE 0x00000001U
+#define EMAC_TXINTMASKSET_CONFIGVALUE 0x00000001U
+#define EMAC_TXINTMASKCLEAR_CONFIGVALUE 0x00000001U
+#define EMAC_RXINTMASKSET_CONFIGVALUE 0x00000001U
+#define EMAC_RXINTMASKCLEAR_CONFIGVALUE 0x00000001U
+#define EMAC_MACSRCADDRHI_CONFIGVALUE ((uint32)((uint32)0xFFU << 24U) | (uint32)((uint32)0xFFU << 16U) | (uint32)((uint32)0xFFU << 8U) | (uint32)((uint32)0xFFU))
+#define EMAC_MACSRCADDRLO_CONFIGVALUE ((uint32)((uint32)0xFFU << 8U) | (uint32)((uint32)0xFFU))
+#define EMAC_MDIOCONTROL_CONFIGVALUE 0x4114001FU
+#define EMAC_C0RXEN_CONFIGVALUE 0x00000001U
+#define EMAC_C0TXEN_CONFIGVALUE 0x00000001U
+
+/* Structure to store pending status from the Tx Interrupt Status Registers. */
+typedef struct emac_tx_int_status{
+ volatile uint32 intstatmasked; /* Pending interrupt status read from the Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) */
+ volatile uint32 intstatraw; /* Pending interrupt status read from the Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) */
+}emac_tx_int_status_t;
+
+/* Structure to store pending status from the Rx Interrupt Status Registers. */
+typedef struct emac_rx_int_status{
+
+ volatile uint32 intstatmasked_pend; /* Reads RXnPEND value from the Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) */
+ volatile uint32 intstatmasked_threshpend; /* Reads RXnTRHESHPEND value from the Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) */
+
+ volatile uint32 intstatraw_pend; /* Reads RXnPEND value from the Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) */
+ volatile uint32 intstatraw_threshpend; /* Reads RXnTRHESHPEND value from the Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) */
+
+}emac_rx_int_status_t;
+
+/* EMAC TX Buffer descriptor data structure - Refer TRM for details about the buffer descriptor structure.*/
+typedef struct emac_tx_bd {
+ volatile struct emac_tx_bd *next;
+ volatile uint32 bufptr; /* Pointer to the actual Buffer storing the data to be transmitted. */
+ volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each) */
+ volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/
+}emac_tx_bd_t;
+
+/* EMAC RX Buffer descriptor data structure - Refer TRM for details about the buffer descriptor structure. */
+typedef struct emac_rx_bd {
+ volatile struct emac_rx_bd *next; /*Used as a pointer for next element in the linked list of descriptors.*/
+ volatile uint32 bufptr; /*Pointer to the actual Buffer which will store the received data.*/
+ volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each)*/
+ volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/
+}emac_rx_bd_t;
+
+/**
+ * Helper struct to hold the data used to operate on a particular
+ * receive channel
+ */
+typedef struct rxch_struct {
+ volatile emac_rx_bd_t *free_head; /*Used to point to the free buffer descriptor which can receive new data.*/
+ volatile emac_rx_bd_t *active_head; /*Used to point to the active descriptor in the chain which is receiving.*/
+ volatile emac_rx_bd_t *active_tail; /*Used to point to the last descriptor in the chain.*/
+}rxch_t;
+
+/**
+ * Helper struct to hold the data used to operate on a particular
+ * transmit channel
+ */
+typedef struct txch_struct {
+ volatile emac_tx_bd_t *free_head; /*Used to point to the free buffer descriptor which can transmit new data.*/
+ volatile emac_tx_bd_t *active_tail; /*Used to point to the last descriptor in the chain.*/
+ volatile emac_tx_bd_t *next_bd_to_process; /*Used to point to the next descriptor in the chain to be processed.*/
+}txch_t;
+/**
+ * Helper struct to hold private data used to operate the ethernet interface.
+ */
+typedef struct hdkif_struct {
+ /* MAC Address of the Module. */
+ uint8_t mac_addr[6];
+
+ /* emac base address */
+ uint32 emac_base;
+
+ /* emac controller base address */
+ volatile uint32 emac_ctrl_base;
+ volatile uint32 emac_ctrl_ram;
+
+ /* mdio base address */
+ volatile uint32 mdio_base;
+
+ /* phy parameters for this instance - for future use */
+ uint32 phy_addr;
+ boolean (*phy_autoneg)(uint32 param1, uint32 param2, uint16 param3);
+ boolean (*phy_partnerability)(uint32 param4, uint32 param5, uint16* param6);
+
+ /* The tx/rx channels for the interface */
+ txch_t txchptr;
+ rxch_t rxchptr;
+}hdkif_t;
+
+/*Ethernet Frame Structure */
+typedef struct ethernet_frame
+{
+ uint8 dest_addr[6]; /* Destination MAC Address */
+ uint8 src_addr[6]; /*Source MAC Address. */
+ uint16 frame_length; /* Data Frame Length */
+ uint8 data[1500]; /* Data */
+}ethernet_frame_t;
+
+/* Struct used to take packet data input from the user for transmit APIs. */
+typedef struct pbuf_struct {
+ /** next pbuf in singly linked pbuf chain */
+ struct pbuf_struct *next;
+
+ /**
+ * Pointer to the actual ethernet packet/packet fragment to be transmitted.
+ * The packet needs to be in the following format:
+ * |Destination MAC Address (6 bytes)| Source MAC Address (6 bytes)| Length/Type (2 bytes)| Data (46- 1500 bytes)
+ * The data can be split up over multiple pbufs which are linked as a linked list.
+ **/
+ uint8 *payload;
+
+ /**
+ * total length of this buffer and all next buffers in chain
+ * belonging to the same packet.
+ *
+ * For non-queue packet chains this is the invariant:
+ * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+ */
+ uint16 tot_len;
+
+ /** length of this buffer */
+ uint16 len;
+
+}pbuf_t;
+
+/* Structure to hold the values of the EMAC Configuration Registers. */
+typedef struct emac_config_reg_struct {
+/* EMAC Module Register Values */
+uint32 TXCONTROL; /* Transmit Control Register. */
+uint32 RXCONTROL; /* Receive Control Register */
+uint32 TXINTMASKSET; /* Transmit Interrupt Mask Set Register */
+uint32 TXINTMASKCLEAR; /* Transmit Interrupt Clear Register */
+uint32 RXINTMASKSET; /* Receive Interrupt Mask Set Register */
+uint32 RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/
+uint32 MACSRCADDRHI; /*MAC Source Address High Bytes Register*/
+uint32 MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/
+
+/*MDIO Module Registers */
+uint32 MDIOCONTROL; /*MDIO Control Register. */
+
+/* EMAC Control Module Registers */
+uint32 C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/
+uint32 C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/
+}emac_config_reg_t;
+/*****************************************************************************/
+/**
+ * @defgroup EMACMDIO EMAC/MDIO
+ * @brief Ethernet Media Access Controller/Management Data Input/Output.
+ *
+ * The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY
+ * configuration and status monitoring.
+ *
+ * Both the EMAC and the MDIO modules interface to the system core through a custom interface that
+ * allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
+ * module and is considered integral to the EMAC/MDIO peripheral
+ *
+ * Related Files
+ * - emac.h
+ * - emac.c
+ * - hw_emac.h
+ * - hw_emac_ctrl.h
+ * - hw_mdio.h
+ * - hw_reg_access.h
+ * - mdio.h
+ * - mdio.c
+ * @addtogroup EMACMDIO
+ * @{
+ */
+/*
+** Prototypes for the APIs
+*/
+extern uint32 EMACLinkSetup(hdkif_t *hdkif);
+extern void EMACInstConfig(hdkif_t *hdkif);
+extern void EMACTxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase,
+ uint32 ctrlCore, uint32 channel);
+extern void EMACTxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase,
+ uint32 ctrlCore, uint32 channel);
+extern void EMACRxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase,
+ uint32 ctrlCore, uint32 channel);
+extern void EMACRxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase,
+ uint32 ctrlCore, uint32 channel);
+extern void EMACRMIISpeedSet(uint32 emacBase, uint32 speed);
+extern void EMACDuplexSet(uint32 emacBase, uint32 duplexMode);
+extern void EMACTxEnable(uint32 emacBase);
+extern void EMACTxDisable(uint32 emacBase);
+extern void EMACRxEnable(uint32 emacBase);
+extern void EMACRxDisable(uint32 emacBase);
+extern void EMACTxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
+ uint32 channel);
+extern void EMACRxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr,
+ uint32 channel);
+extern void EMACInit(uint32 emacCtrlBase, uint32 emacBase);
+extern void EMACMACSrcAddrSet(uint32 emacBase, uint8 macAddr[6]);
+extern void EMACMACAddrSet(uint32 emacBase, uint32 channel,
+ uint8 macAddr[6], uint32 matchFilt);
+extern void EMACMIIEnable(uint32 emacBase);
+extern void EMACMIIDisable(uint32 emacBase);
+extern void EMACRxUnicastSet(uint32 emacBase, uint32 channel);
+extern void EMACRxUnicastClear(uint32 emacBase, uint32 channel);
+extern void EMACCoreIntAck(uint32 emacBase, uint32 eoiFlag);
+extern void EMACTxCPWrite(uint32 emacBase, uint32 channel,
+ uint32 comPtr);
+extern void EMACRxCPWrite(uint32 emacBase, uint32 channel,
+ uint32 comPtr);
+extern void EMACRxBroadCastEnable(uint32 emacBase, uint32 channel);
+extern void EMACRxBroadCastDisable(uint32 emacBase, uint32 channel);
+extern void EMACRxMultiCastEnable(uint32 emacBase, uint32 channel);
+extern void EMACRxMultiCastDisable(uint32 emacBase, uint32 channel);
+extern void EMACNumFreeBufSet(uint32 emacBase, uint32 channel,
+ uint32 nBuf);
+extern uint32 EMACIntVectorGet(uint32 emacBase);
+uint32 EMACHWInit(uint8_t macaddr[6U]);
+void EMACTxTeardown(uint32 emacBase, uint32 channel);
+void EMACRxTeardown(uint32 emacBase, uint32 channel);
+void EMACFrameSelect(uint32 emacBase, uint64 hashTable);
+void EMACTxPrioritySelect(uint32 emacBase, uint32 txPType);
+void EMACSoftReset(uint32 emacCtrlBase, uint32 emacBase);
+void EMACEnableIdleState(uint32 emacBase);
+void EMACDisableIdleState(uint32 emacBase);
+void EMACEnableLoopback(uint32 emacBase);
+void EMACDisableLoopback(uint32 emacBase);
+void EMACTxFlowControlEnable(uint32 emacBase);
+void EMACTxFlowControlDisable(uint32 emacBase);
+void EMACRxFlowControlEnable(uint32 emacBase);
+void EMACRxFlowControlDisable(uint32 emacBase);
+void EMACRxSetFlowThreshold(uint32 emacBase, uint32 channel, uint32 threshold);
+uint32 EMACReadNetStatRegisters(uint32 emacBase, uint32 statRegNo);
+void EMACDMAInit(hdkif_t *hdkif);
+boolean EMACTransmit(hdkif_t *hdkif, pbuf_t *pbuf);
+void EMACTxIntHandler(hdkif_t *hdkif);
+void EMACReceive(hdkif_t *hdkif);
+/* Notification Function to which received packets are passed after processing */
+void emacTxNotification(hdkif_t *hdkif);
+void emacRxNotification(hdkif_t *hdkif);
+void EMACTxIntStat(uint32 emacBase, uint32 channel, emac_tx_int_status_t *txintstat);
+void EMACRxIntStat(uint32 emacBase, uint32 channel, emac_rx_int_status_t *rxintstat);
+void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* __EMAC_H__ */
Index: firmware/include/eqep.h
===================================================================
diff -u
--- firmware/include/eqep.h (revision 0)
+++ firmware/include/eqep.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,716 @@
+/** @file eqep.h
+* @brief EQEP Driver Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __eQEP_H__
+#define __eQEP_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "reg_eqep.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/*QDECCTL Register */
+#define eQEP_QDECCTL_QSRC ((uint16)((uint16)3U << 14U)) /* "Reason - TI_Fee_Fix is a symbolic constant."*/
+#define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_Fix
+#else
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_Fee_None is a symbolic constant."*/
+#define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_None
+#endif
+
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_MAXIMUM_BLOCKING_TIME is a symbolic constant"*/
+#define TI_FEE_MAXIMUM_BLOCKING_TIME FEE_MAXIMUM_BLOCKING_TIME
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_OPERATING_FREQUENCY is a symbolic constant."*/
+#define TI_FEE_OPERATING_FREQUENCY FEE_OPERATING_FREQUENCY
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_ERROR_CORRECTION_ENABLE is a symbolic constant."*/
+#define TI_FEE_FLASH_ERROR_CORRECTION_ENABLE FEE_FLASH_ERROR_CORRECTION_ENABLE
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_CHECKSUM_ENABLE is a symbolic constant."*/
+#define TI_FEE_FLASH_CHECKSUM_ENABLE FEE_FLASH_CHECKSUM_ENABLE
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_WRITECOUNTER_SAVE is a symbolic constant."*/
+#define TI_FEE_FLASH_WRITECOUNTER_SAVE FEE_FLASH_WRITECOUNTER_SAVE
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - NVM_DATASET_SELECTION_BITS is a symbolic constant."*/
+#define TI_FEE_DATASELECT_BITS NVM_DATASET_SELECTION_BITS
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EEPS is a symbolic constant."*/
+#define TI_FEE_NUMBER_OF_EEPS FEE_NUMBER_OF_EEPS
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_INDEX is a symbolic constant."*/
+#define TI_FEE_INDEX FEE_INDEX
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PAGE_OVERHEAD is a symbolic constant."*/
+#define TI_FEE_PAGE_OVERHEAD FEE_PAGE_OVERHEAD
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_BLOCK_OVERHEAD is a symbolic constant."*/
+#define TI_FEE_BLOCK_OVERHEAD FEE_BLOCK_OVERHEAD
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_PAGE_SIZE is a symbolic constant."*/
+#define TI_FEE_VIRTUAL_PAGE_SIZE FEE_VIRTUAL_PAGE_SIZE
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_SECTOR_OVERHEAD is a symbolic constant."*/
+#define TI_FEE_VIRTUAL_SECTOR_OVERHEAD FEE_VIRTUAL_SECTOR_OVERHEAD
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY is a symbolic constant."*/
+#define TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EIGHTBYTEWRITES is a symbolic constant."*/
+#define TI_FEE_NUMBER_OF_EIGHTBYTEWRITES FEE_NUMBER_OF_EIGHTBYTEWRITES
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_END_NOTIFICATION is a symbolic constant."*/
+#define TI_FEE_NVM_JOB_END_NOTIFICATION FEE_NVM_JOB_END_NOTIFICATION
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_ERROR_NOTIFICATION is a symbolic constant."*/
+#define TI_FEE_NVM_JOB_ERROR_NOTIFICATION FEE_NVM_JOB_ERROR_NOTIFICATION
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_POLLING_MODE is a symbolic constant."*/
+#define TI_FEE_POLLING_MODE FEE_POLLING_MODE
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a symbolic constant."*/
+#ifndef FEE_CHECK_BANK7_ACCESS
+#define TI_FEE_CHECK_BANK7_ACCESS STD_ON
+#else
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a symbolic constant."*/
+#define TI_FEE_CHECK_BANK7_ACCESS STD_ON
+#endif
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_TOTAL_BLOCKS_DATASETS is a symbolic constant."*/
+#define TI_FEE_TOTAL_BLOCKS_DATASETS FEE_TOTAL_BLOCKS_DATASETS
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUALSECTOR_SIZE is a symbolic constant."*/
+#define TI_FEE_VIRTUALSECTOR_SIZE FEE_VIRTUALSECTOR_SIZE
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PHYSICALSECTOR_SIZE is a symbolic constant."*/
+#define TI_FEE_PHYSICALSECTOR_SIZE FEE_PHYSICALSECTOR_SIZE
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC is a symbolic constant."*/
+#define TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_USEPARTIALERASEDSECTOR is a symbolic constant."*/
+#define TI_FEE_USEPARTIALERASEDSECTOR FEE_USEPARTIALERASEDSECTOR
+
+/*----------------------------------------------------------------------------*/
+/* Virtual Sector Configuration */
+
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS is a symbolic constant."*/
+/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is required here."*/
+#define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS FEE_NUMBER_OF_VIRTUAL_SECTORS
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 is a symbolic constant."*/
+/*SAFETYMCUSW 384 S MR:1.4,5.1 "Reason - Similar Identifier name is required here."*/
+/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is required here."*/
+#define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1
+
+
+/*----------------------------------------------------------------------------*/
+/* Block Configuration */
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_BLOCKS is a symbolic constant."*/
+#define TI_FEE_NUMBER_OF_BLOCKS FEE_NUMBER_OF_BLOCKS
+/*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_FEE_VARIABLE_DATASETS is a symbolic constant."*/
+#define TI_FEE_VARIABLE_DATASETS STD_ON
+
+
+#endif /* TI_FEE_DRIVER */
+
+#endif /* FEE_INTERFACE_H */
+/**********************************************************************************************************************
+ * END OF FILE: fee_interface.h
+ *********************************************************************************************************************/
Index: firmware/include/gio.h
===================================================================
diff -u
--- firmware/include/gio.h (revision 0)
+++ firmware/include/gio.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,174 @@
+/** @file gio.h
+* @brief GIO Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __GIO_H__
+#define __GIO_H__
+
+#include "reg_gio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+typedef struct gio_config_reg
+{
+ uint32 CONFIG_INTDET;
+ uint32 CONFIG_POL;
+ uint32 CONFIG_INTENASET;
+ uint32 CONFIG_LVLSET;
+
+ uint32 CONFIG_PORTADIR;
+ uint32 CONFIG_PORTAPDR;
+ uint32 CONFIG_PORTAPSL;
+ uint32 CONFIG_PORTAPULDIS;
+
+ uint32 CONFIG_PORTBDIR;
+ uint32 CONFIG_PORTBPDR;
+ uint32 CONFIG_PORTBPSL;
+ uint32 CONFIG_PORTBPULDIS;
+}gio_config_reg_t;
+
+#define GIO_INTDET_CONFIGVALUE 0U
+#define GIO_POL_CONFIGVALUE ((uint32)((uint32)0U << 0U) \
+ | (uint32)((uint32)0U << 1U) \
+ | (uint32)((uint32)0U << 2U) \
+ | (uint32)((uint32)0U << 3U) \
+ | (uint32)((uint32)0U << 4U) \
+ | (uint32)((uint32)0U << 5U) \
+ | (uint32)((uint32)0U << 6U) \
+ | (uint32)((uint32)0U << 7U) \
+ | (uint32)((uint32)0U << 8U) \
+ | (uint32)((uint32)0U << 9U) \
+ | (uint32)((uint32)0U << 10U)\
+ | (uint32)((uint32)0U << 11U)\
+ | (uint32)((uint32)0U << 12U)\
+ | (uint32)((uint32)0U << 13U)\
+ | (uint32)((uint32)0U << 14U)\
+ | (uint32)((uint32)0U << 15U))
+
+
+#define GIO_INTENASET_CONFIGVALUE ((uint32)((uint32)0U << 0U) \
+ | (uint32)((uint32)0U << 1U) \
+ | (uint32)((uint32)0U << 2U) \
+ | (uint32)((uint32)0U << 3U) \
+ | (uint32)((uint32)0U << 4U) \
+ | (uint32)((uint32)0U << 5U) \
+ | (uint32)((uint32)0U << 6U) \
+ | (uint32)((uint32)0U << 7U) \
+ | (uint32)((uint32)0U << 8U) \
+ | (uint32)((uint32)0U << 9U) \
+ | (uint32)((uint32)0U << 10U)\
+ | (uint32)((uint32)0U << 11U)\
+ | (uint32)((uint32)0U << 12U)\
+ | (uint32)((uint32)0U << 13U)\
+ | (uint32)((uint32)0U << 14U)\
+ | (uint32)((uint32)0U << 15U))
+
+#define GIO_LVLSET_CONFIGVALUE ((uint32)((uint32)0U << 0U) \
+ | (uint32)((uint32)0U << 1U) \
+ | (uint32)((uint32)0U << 2U) \
+ | (uint32)((uint32)0U << 3U) \
+ | (uint32)((uint32)0U << 4U) \
+ | (uint32)((uint32)0U << 5U) \
+ | (uint32)((uint32)0U << 6U) \
+ | (uint32)((uint32)0U << 7U) \
+ | (uint32)((uint32)0U << 8U) \
+ | (uint32)((uint32)0U << 9U) \
+ | (uint32)((uint32)0U << 10U)\
+ | (uint32)((uint32)0U << 11U)\
+ | (uint32)((uint32)0U << 12U)\
+ | (uint32)((uint32)0U << 13U)\
+ | (uint32)((uint32)0U << 14U)\
+ | (uint32)((uint32)0U << 15U))
+
+#define GIO_PORTADIR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTAPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTAPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTAPULDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U))
+
+#define GIO_PORTBDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTBPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTBPSL_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTBPULDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+
+
+/**
+ * @defgroup GIO GIO
+ * @brief General-Purpose Input/Output Module.
+ *
+ * The GIO module provides the family of devices with input/output (I/O) capability.
+ * The I/O pins are bidirectional and bit-programmable.
+ * The GIO module also supports external interrupt capability.
+ *
+ * Related Files
+ * - reg_gio.h
+ * - gio.h
+ * - gio.c
+ * @addtogroup GIO
+ * @{
+ */
+
+/* GIO Interface Functions */
+void gioInit(void);
+void gioSetDirection(gioPORT_t *port, uint32 dir);
+void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value);
+void gioSetPort(gioPORT_t *port, uint32 value);
+uint32 gioGetBit(gioPORT_t *port, uint32 bit);
+uint32 gioGetPort(gioPORT_t *port);
+void gioToggleBit(gioPORT_t *port, uint32 bit);
+void gioEnableNotification(gioPORT_t *port, uint32 bit);
+void gioDisableNotification(gioPORT_t *port, uint32 bit);
+void gioNotification(gioPORT_t *port, uint32 bit);
+void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
Index: firmware/include/hal_stdtypes.h
===================================================================
diff -u
--- firmware/include/hal_stdtypes.h (revision 0)
+++ firmware/include/hal_stdtypes.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,196 @@
+/** @file hal_stdtypes.h
+* @brief HALCoGen standard types header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Type and Global definitions which are relevant for all drivers.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __HAL_STDTYPES_H__
+#define __HAL_STDTYPES_H__
+
+#include
+#include
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+/************************************************************/
+/* Type Definitions */
+/************************************************************/
+#ifndef _UINT64_DECLARED
+typedef uint64_t uint64;
+#define _UINT64_DECLARED
+#endif
+
+#ifndef _UINT32_DECLARED
+typedef uint32_t uint32;
+#define _UINT32_DECLARED
+#endif
+
+#ifndef _UINT16_DECLARED
+typedef uint16_t uint16;
+#define _UINT16_DECLARED
+#endif
+
+#ifndef _UINT8_DECLARED
+typedef uint8_t uint8;
+#define _UINT8_DECLARED
+#endif
+
+#ifndef _BOOLEAN_DECLARED
+#ifdef __cplusplus
+typedef bool boolean;
+#else
+typedef _Bool boolean;
+#endif
+#define _BOOLEAN_DECLARED
+#endif
+
+#ifndef _SINT64_DECLARED
+typedef int64_t sint64;
+#define _SINT64_DECLARED
+#endif
+
+#ifndef _SINT32_DECLARED
+typedef int32_t sint32;
+#define _SINT32_DECLARED
+#endif
+
+#ifndef _SINT16_DECLARED
+typedef int16_t sint16;
+#define _SINT16_DECLARED
+#endif
+
+#ifndef _SINT8_DECLARED
+typedef int8_t sint8;
+#define _SINT8_DECLARED
+#endif
+
+#ifndef _FLOAT32_DECLARED
+typedef float float32;
+#define _FLOAT32_DECLARED
+#endif
+
+#ifndef _FLOAT64_DECLARED
+typedef double float64;
+#define _FLOAT64_DECLARED
+#endif
+
+
+typedef uint8 Std_ReturnType;
+
+typedef struct
+{
+ uint16 vendorID;
+ uint16 moduleID;
+ uint8 instanceID;
+ uint8 sw_major_version;
+ uint8 sw_minor_version;
+ uint8 sw_patch_version;
+} Std_VersionInfoType;
+
+/*****************************************************************************/
+/* SYMBOL DEFINITIONS */
+/*****************************************************************************/
+#ifndef STATUSTYPEDEFINED
+ #define STATUSTYPEDEFINED
+ #define E_OK 0x00U
+
+ typedef unsigned char StatusType;
+#endif
+
+#ifndef E_NOT_OK
+#define E_NOT_OK 0x01U
+#endif
+
+#ifndef STD_ON
+#define STD_ON 0x01U
+#endif
+
+#ifndef STD_OFF
+#define STD_OFF 0x00U
+#endif
+
+
+/************************************************************/
+/* Global Definitions */
+/************************************************************/
+/** @def NULL
+* @brief NULL definition
+*/
+
+#ifndef NULL
+ /*SAFETYMCUSW 218 S MR:20.2 "Custom Type Definition." */
+ #define NULL ((void *) 0U)
+#endif
+
+/*****************************************************************************/
+/* Define: NULL_PTR */
+/* Description: Void pointer to 0 */
+/*****************************************************************************/
+#ifndef NULL_PTR
+ #define NULL_PTR ((void *)0x0)
+#endif
+
+/** @def TRUE
+* @brief definition for TRUE
+*/
+#ifndef TRUE
+ #define TRUE true
+#endif
+
+/** @def FALSE
+* @brief BOOLEAN definition for FALSE
+*/
+#ifndef FALSE
+ #define FALSE false
+#endif
+
+/*****************************************************************************/
+/* Define: NULL_PTR */
+/* Description: Void pointer to 0 */
+/*****************************************************************************/
+#ifndef NULL_PTR
+#define NULL_PTR ((void *)0x0U)
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#endif /* __HAL_STDTYPES_H__ */
Index: firmware/include/het.h
===================================================================
diff -u
--- firmware/include/het.h (revision 0)
+++ firmware/include/het.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,671 @@
+/** @file het.h
+* @brief HET Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __HET_H__
+#define __HET_H__
+
+#include "reg_het.h"
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def pwm0
+* @brief Pwm signal 0
+*
+* Alias for pwm signal 0
+*/
+#define pwm0 0U
+
+/** @def pwm1
+* @brief Pwm signal 1
+*
+* Alias for pwm signal 1
+*/
+#define pwm1 1U
+
+/** @def pwm2
+* @brief Pwm signal 2
+*
+* Alias for pwm signal 2
+*/
+#define pwm2 2U
+
+/** @def pwm3
+* @brief Pwm signal 3
+*
+* Alias for pwm signal 3
+*/
+#define pwm3 3U
+
+/** @def pwm4
+* @brief Pwm signal 4
+*
+* Alias for pwm signal 4
+*/
+#define pwm4 4U
+
+/** @def pwm5
+* @brief Pwm signal 5
+*
+* Alias for pwm signal 5
+*/
+#define pwm5 5U
+
+/** @def pwm6
+* @brief Pwm signal 6
+*
+* Alias for pwm signal 6
+*/
+#define pwm6 6U
+
+/** @def pwm7
+* @brief Pwm signal 7
+*
+* Alias for pwm signal 7
+*/
+#define pwm7 7U
+
+
+/** @def edge0
+* @brief Edge signal 0
+*
+* Alias for edge signal 0
+*/
+#define edge0 0U
+
+/** @def edge1
+* @brief Edge signal 1
+*
+* Alias for edge signal 1
+*/
+#define edge1 1U
+
+/** @def edge2
+* @brief Edge signal 2
+*
+* Alias for edge signal 2
+*/
+#define edge2 2U
+
+/** @def edge3
+* @brief Edge signal 3
+*
+* Alias for edge signal 3
+*/
+#define edge3 3U
+
+/** @def edge4
+* @brief Edge signal 4
+*
+* Alias for edge signal 4
+*/
+#define edge4 4U
+
+/** @def edge5
+* @brief Edge signal 5
+*
+* Alias for edge signal 5
+*/
+#define edge5 5U
+
+/** @def edge6
+* @brief Edge signal 6
+*
+* Alias for edge signal 6
+*/
+#define edge6 6U
+
+/** @def edge7
+* @brief Edge signal 7
+*
+* Alias for edge signal 7
+*/
+#define edge7 7U
+
+
+/** @def cap0
+* @brief Capture signal 0
+*
+* Alias for capture signal 0
+*/
+#define cap0 0U
+
+/** @def cap1
+* @brief Capture signal 1
+*
+* Alias for capture signal 1
+*/
+#define cap1 1U
+
+/** @def cap2
+* @brief Capture signal 2
+*
+* Alias for capture signal 2
+*/
+#define cap2 2U
+
+/** @def cap3
+* @brief Capture signal 3
+*
+* Alias for capture signal 3
+*/
+#define cap3 3U
+
+/** @def cap4
+* @brief Capture signal 4
+*
+* Alias for capture signal 4
+*/
+#define cap4 4U
+
+/** @def cap5
+* @brief Capture signal 5
+*
+* Alias for capture signal 5
+*/
+#define cap5 5U
+
+/** @def cap6
+* @brief Capture signal 6
+*
+* Alias for capture signal 6
+*/
+#define cap6 6U
+
+/** @def cap7
+* @brief Capture signal 7
+*
+* Alias for capture signal 7
+*/
+#define cap7 7U
+
+/** @def pwmEND_OF_DUTY
+* @brief Pwm end of duty
+*
+* Alias for pwm end of duty notification
+*/
+#define pwmEND_OF_DUTY 2U
+
+/** @def pwmEND_OF_PERIOD
+* @brief Pwm end of period
+*
+* Alias for pwm end of period notification
+*/
+#define pwmEND_OF_PERIOD 4U
+
+/** @def pwmEND_OF_BOTH
+* @brief Pwm end of duty and period
+*
+* Alias for pwm end of duty and period notification
+*/
+#define pwmEND_OF_BOTH 6U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @struct hetBase
+* @brief HET Register Definition
+*
+* This structure is used to access the HET module registers.
+*/
+/** @typedef hetBASE_t
+* @brief HET Register Frame Type Definition
+*
+* This type is used to access the HET Registers.
+*/
+
+enum hetPinSelect
+{
+ PIN_HET_0 = 0U,
+ PIN_HET_1 = 1U,
+ PIN_HET_2 = 2U,
+ PIN_HET_3 = 3U,
+ PIN_HET_4 = 4U,
+ PIN_HET_5 = 5U,
+ PIN_HET_6 = 6U,
+ PIN_HET_7 = 7U,
+ PIN_HET_8 = 8U,
+ PIN_HET_9 = 9U,
+ PIN_HET_10 = 10U,
+ PIN_HET_11 = 11U,
+ PIN_HET_12 = 12U,
+ PIN_HET_13 = 13U,
+ PIN_HET_14 = 14U,
+ PIN_HET_15 = 15U,
+ PIN_HET_16 = 16U,
+ PIN_HET_17 = 17U,
+ PIN_HET_18 = 18U,
+ PIN_HET_19 = 19U,
+ PIN_HET_20 = 20U,
+ PIN_HET_21 = 21U,
+ PIN_HET_22 = 22U,
+ PIN_HET_23 = 23U,
+ PIN_HET_24 = 24U,
+ PIN_HET_25 = 25U,
+ PIN_HET_26 = 26U,
+ PIN_HET_27 = 27U,
+ PIN_HET_28 = 28U,
+ PIN_HET_29 = 29U,
+ PIN_HET_30 = 30U,
+ PIN_HET_31 = 31U
+};
+
+
+/** @struct hetSignal
+* @brief HET Signal Definition
+*
+* This structure is used to define a pwm signal.
+*/
+/** @typedef hetSIGNAL_t
+* @brief HET Signal Type Definition
+*
+* This type is used to access HET Signal Information.
+*/
+typedef struct hetSignal
+{
+ uint32 duty; /**< Duty cycle in % of the period */
+ float64 period; /**< Period in us */
+} hetSIGNAL_t;
+
+
+/* Configuration registers */
+typedef struct het_config_reg
+{
+ uint32 CONFIG_GCR;
+ uint32 CONFIG_PFR;
+ uint32 CONFIG_INTENAS;
+ uint32 CONFIG_INTENAC;
+ uint32 CONFIG_PRY;
+ uint32 CONFIG_AND;
+ uint32 CONFIG_HRSH;
+ uint32 CONFIG_XOR;
+ uint32 CONFIG_DIR;
+ uint32 CONFIG_PDR;
+ uint32 CONFIG_PULDIS;
+ uint32 CONFIG_PSL;
+ uint32 CONFIG_PCR;
+} het_config_reg_t;
+
+/* Configuration registers initial value for HET1*/
+#define HET1_DIR_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00400000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00040000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000010U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_PDR_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_PULDIS_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_PSL_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00400000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_HRSH_CONFIGVALUE ((uint32)0x00008000U \
+ | (uint32)0x00004000U \
+ | (uint32)0x00002000U \
+ | (uint32)0x00001000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000008U \
+ | (uint32)0x00000004U \
+ | (uint32)0x00000002U \
+ | (uint32)0x00000001U)
+
+#define HET1_AND_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_XOR_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_PFR_CONFIGVALUE (((uint32)7U << 8U) | (uint32)0U)
+
+
+#define HET1_PRY_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00020000U \
+ | (uint32)0x00040000U \
+ | (uint32)0x00080000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_INTENAC_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00020000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_INTENAS_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00020000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U \
+ | (uint32)0x00000000U)
+
+#define HET1_PCR_CONFIGVALUE ((uint32)0x00000005U)
+#define HET1_GCR_CONFIGVALUE 0x00030001U
+
+
+
+
+/**
+ * @defgroup HET HET
+ * @brief HighEnd Timer Module.
+ *
+ * The HET is a software-controlled timer with a dedicated specialized timer micromachine and a set of 30 instructions.
+ * The HET micromachine is connected to a port of up to 32 input/output (I/O) pins.
+ *
+ * Related Files
+ * - reg_het.h
+ * - het.h
+ * - het.c
+ * - reg_htu.h
+ * - htu.h
+ * - std_nhet.h
+ * @addtogroup HET
+ * @{
+ */
+
+/* HET Interface Functions */
+void hetInit(void);
+
+/* PWM Interface Functions */
+void pwmStart(hetRAMBASE_t * hetRAM,uint32 pwm);
+void pwmStop(hetRAMBASE_t * hetRAM,uint32 pwm);
+void pwmSetDuty(hetRAMBASE_t * hetRAM,uint32 pwm, uint32 pwmDuty);
+void pwmSetSignal(hetRAMBASE_t * hetRAM,uint32 pwm, hetSIGNAL_t signal);
+void pwmGetSignal(hetRAMBASE_t * hetRAM,uint32 pwm, hetSIGNAL_t *signal);
+void pwmEnableNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+void pwmDisableNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+void pwmNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification);
+
+/* Edge Interface Functions */
+void edgeResetCounter(hetRAMBASE_t * hetRAM,uint32 edge);
+uint32 edgeGetCounter(hetRAMBASE_t * hetRAM,uint32 edge);
+void edgeEnableNotification(hetBASE_t * hetREG,uint32 edge);
+void edgeDisableNotification(hetBASE_t * hetREG,uint32 edge);
+void edgeNotification(hetBASE_t * hetREG,uint32 edge);
+
+/* Captured Signal Interface Functions */
+void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t *signal);
+
+/* Timestamp Interface Functions */
+void hetResetTimestamp(hetRAMBASE_t * hetRAM);
+uint32 hetGetTimestamp(hetRAMBASE_t * hetRAM);
+void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void hetNotification(hetBASE_t *het, uint32 offset)
+* @brief het interrupt callback
+* @param[in] het - Het module base address
+* - hetREG1: HET1 module base address pointer
+* - hetREG2: HET2 module base address pointer
+* @param[in] offset - het interrupt offset / Source number
+*
+* @note This function has to be provide by the user.
+*
+* This is a interrupt callback that is provided by the application and is call upon
+* an het interrupt. The parameter passed to the callback is a copy of the interrupt
+* offset register which is used to decode the interrupt source.
+*/
+void hetNotification(hetBASE_t *het, uint32 offset);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
Index: firmware/include/htu.h
===================================================================
diff -u
--- firmware/include/htu.h (revision 0)
+++ firmware/include/htu.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,71 @@
+/** @file htu.h
+* @brief HTU Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __HTU_H__
+#define __HTU_H__
+
+#include "reg_htu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* HTU General Definitions */
+
+#define HTU1PARLOC (*(volatile uint32 *)0xFF4E0200U)
+#define HTU2PARLOC (*(volatile uint32 *)0xFF4C0200U)
+
+#define HTU1RAMLOC (*(volatile uint32 *)0xFF4E0000U)
+#define HTU2RAMLOC (*(volatile uint32 *)0xFF4C0000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
Index: firmware/include/hw_emac.h
===================================================================
diff -u
--- firmware/include/hw_emac.h (revision 0)
+++ firmware/include/hw_emac.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1489 @@
+/*
+ * hw_emac1.h
+ */
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_EMAC_H_
+#define _HW_EMAC_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#define EMAC_BASE (0xFCF78000U)
+#define EMAC_CTRL_BASE (0xFCF78800U)
+#define EMAC_CTRL_RAM_BASE (0xFC520000U)
+
+#define EMAC_TXREVID (0x0U)
+#define EMAC_TXCONTROL (0x4U)
+#define EMAC_TXTEARDOWN (0x8U)
+#define EMAC_RXREVID (0x10U)
+#define EMAC_RXCONTROL (0x14U)
+#define EMAC_RXTEARDOWN (0x18U)
+#define EMAC_TXINTSTATRAW (0x80U)
+#define EMAC_TXINTSTATMASKED (0x84U)
+#define EMAC_TXINTMASKSET (0x88U)
+#define EMAC_TXINTMASKCLEAR (0x8CU)
+#define EMAC_MACINVECTOR (0x90U)
+#define EMAC_MACEOIVECTOR (0x94U)
+#define EMAC_RXINTSTATRAW (0xA0U)
+#define EMAC_RXINTSTATMASKED (0xA4U)
+#define EMAC_RXINTMASKSET (0xA8U)
+#define EMAC_RXINTMASKCLEAR (0xACU)
+#define EMAC_MACINTSTATRAW (0xB0U)
+#define EMAC_MACINTSTATMASKED (0xB4U)
+#define EMAC_MACINTMASKSET (0xB8U)
+#define EMAC_MACINTMASKCLEAR (0xBCU)
+#define EMAC_RXMBPENABLE (0x100U)
+#define EMAC_RXUNICASTSET (0x104U)
+#define EMAC_RXUNICASTCLEAR (0x108U)
+#define EMAC_RXMAXLEN (0x10CU)
+#define EMAC_RXBUFFEROFFSET (0x110U)
+#define EMAC_RXFILTERLOWTHRESH (0x114U)
+#define EMAC_RXFLOWTHRESH(n) ((uint32)0x120U + (uint32)((n) * 4U))
+#define EMAC_RXFREEBUFFER(n) ((uint32)0x140U + (uint32)((n) * 4U))
+#define EMAC_MACCONTROL (0x160U)
+#define EMAC_MACSTATUS (0x164U)
+#define EMAC_EMCONTROL (0x168U)
+#define EMAC_FIFOCONTROL (0x16CU)
+#define EMAC_MACCONFIG (0x170U)
+#define EMAC_SOFTRESET (0x174U)
+#define EMAC_MACSRCADDRLO (0x1D0U)
+#define EMAC_MACSRCADDRHI (0x1D4U)
+#define EMAC_MACHASH1 (0x1D8U)
+#define EMAC_MACHASH2 (0x1DCU)
+#define EMAC_BOFFTEST (0x1E0U)
+#define EMAC_TPACETEST (0x1E4U)
+#define EMAC_RXPAUSE (0x1E8U)
+#define EMAC_TXPAUSE (0x1ECU)
+#define EMAC_RXGOODFRAMES (0x200U)
+#define EMAC_RXBCASTFRAMES (0x204U)
+#define EMAC_RXMCASTFRAMES (0x208U)
+#define EMAC_RXPAUSEFRAMES (0x20CU)
+#define EMAC_RXCRCERRORS (0x210U)
+#define EMAC_RXALIGNCODEERRORS (0x214U)
+#define EMAC_RXOVERSIZED (0x218U)
+#define EMAC_RXJABBER (0x21CU)
+#define EMAC_RXUNDERSIZED (0x220U)
+#define EMAC_RXFRAGMENTS (0x224U)
+#define EMAC_RXFILTERED (0x228U)
+#define EMAC_RXQOSFILTERED (0x22CU)
+#define EMAC_RXOCTETS (0x230U)
+#define EMAC_TXGOODFRAMES (0x234U)
+#define EMAC_TXBCASTFRAMES (0x238U)
+#define EMAC_TXMCASTFRAMES (0x23CU)
+#define EMAC_TXPAUSEFRAMES (0x240U)
+#define EMAC_TXDEFERRED (0x244U)
+#define EMAC_TXCOLLISION (0x248U)
+#define EMAC_TXSINGLECOLL (0x24CU)
+#define EMAC_TXMULTICOLL (0x250U)
+#define EMAC_TXEXCESSIVECOLL (0x254U)
+#define EMAC_TXLATECOLL (0x258U)
+#define EMAC_TXUNDERRUN (0x25CU)
+#define EMAC_TXCARRIERSENSE (0x260U)
+#define EMAC_TXOCTETS (0x264U)
+#define EMAC_FRAME64 (0x268U)
+#define EMAC_FRAME65T127 (0x26CU)
+#define EMAC_FRAME128T255 (0x270U)
+#define EMAC_FRAME256T511 (0x274U)
+#define EMAC_FRAME512T1023 (0x278U)
+#define EMAC_FRAME1024TUP (0x27CU)
+#define EMAC_NETOCTETS (0x208U)
+#define EMAC_RXSOFOVERRUNS (0x284U)
+#define EMAC_RXMOFOVERRUNS (0x288U)
+#define EMAC_RXDMAOVERRUNS (0x28CU)
+#define EMAC_MACADDRLO (0x500U)
+#define EMAC_MACADDRHI (0x504U)
+#define EMAC_MACINDEX (0x508U)
+#define EMAC_TXHDP(n) ((uint32)0x600U + (uint32)((n) * 4U))
+#define EMAC_RXHDP(n) ((uint32)0x620U + (uint32)((n) * 4U))
+#define EMAC_TXCP(n) ((uint32)0x640U + (uint32)((n) * 4U))
+#define EMAC_RXCP(n) ((uint32)0x660U + (uint32)((n) * 4U))
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* TXREVID */
+
+#define EMAC_TXREVID_TXREV (0xFFFFFFFFU)
+#define EMAC_TXREVID_TXREV_SHIFT (0x00000000U)
+
+
+/* TXCONTROL */
+
+
+#define EMAC_TXCONTROL_TXEN (0x00000001U)
+#define EMAC_TXCONTROL_TXEN_SHIFT (0x00000000U)
+#define EMAC_TXCONTROL_TXDIS (0x00000000U)
+
+
+/* TXTEARDOWN */
+
+#define EMAC_TXTEARDOWN_TXTDNCH (0x00000007U)
+#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT (0x00000000U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 (0x00000000U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 (0x00000001U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 (0x00000002U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 (0x00000003U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 (0x00000004U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 (0x00000005U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 (0x00000006U)
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 (0x00000007U)
+
+
+/* RXREVID */
+
+#define EMAC_RXREVID_RXREV (0xFFFFFFFFU)
+#define EMAC_RXREVID_RXREV_SHIFT (0x00000000U)
+
+
+/* RXCONTROL */
+
+
+#define EMAC_RXCONTROL_RXEN (0x00000001U)
+#define EMAC_RXCONTROL_RXEN_SHIFT (0x00000000U)
+#define EMAC_RXCONTROL_RXDIS (0x00000000U)
+
+/* RXTEARDOWN */
+
+
+
+#define EMAC_RXTEARDOWN_RXTDNCH (0x00000007U)
+#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT (0x00000000U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 (0x00000000U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 (0x00000001U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 (0x00000002U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 (0x00000003U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 (0x00000004U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 (0x00000005U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 (0x00000006U)
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 (0x00000007U)
+
+
+/* TXINTSTATRAW */
+
+
+#define EMAC_TXINTSTATRAW_TX7PEND (0x00000080U)
+#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_TXINTSTATRAW_TX6PEND (0x00000040U)
+#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_TXINTSTATRAW_TX5PEND (0x00000020U)
+#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_TXINTSTATRAW_TX4PEND (0x00000010U)
+#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_TXINTSTATRAW_TX3PEND (0x00000008U)
+#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_TXINTSTATRAW_TX2PEND (0x00000004U)
+#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_TXINTSTATRAW_TX1PEND (0x00000002U)
+#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_TXINTSTATRAW_TX0PEND (0x00000001U)
+#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT (0x00000000U)
+
+
+/* TXINTSTATMASKED */
+
+
+#define EMAC_TXINTSTATMASKED_TX7PEND (0x00000080U)
+#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_TXINTSTATMASKED_TX6PEND (0x00000040U)
+#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_TXINTSTATMASKED_TX5PEND (0x00000020U)
+#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_TXINTSTATMASKED_TX4PEND (0x00000010U)
+#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_TXINTSTATMASKED_TX3PEND (0x00000008U)
+#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_TXINTSTATMASKED_TX2PEND (0x00000004U)
+#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_TXINTSTATMASKED_TX1PEND (0x00000002U)
+#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_TXINTSTATMASKED_TX0PEND (0x00000001U)
+#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT (0x00000000U)
+
+
+/* TXINTMASKSET */
+
+
+#define EMAC_TXINTMASKSET_TX7MASK (0x00000080U)
+#define EMAC_TXINTMASKSET_TX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_TXINTMASKSET_TX6MASK (0x00000040U)
+#define EMAC_TXINTMASKSET_TX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_TXINTMASKSET_TX5MASK (0x00000020U)
+#define EMAC_TXINTMASKSET_TX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_TXINTMASKSET_TX4MASK (0x00000010U)
+#define EMAC_TXINTMASKSET_TX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_TXINTMASKSET_TX3MASK (0x00000008U)
+#define EMAC_TXINTMASKSET_TX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_TXINTMASKSET_TX2MASK (0x00000004U)
+#define EMAC_TXINTMASKSET_TX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_TXINTMASKSET_TX1MASK (0x00000002U)
+#define EMAC_TXINTMASKSET_TX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_TXINTMASKSET_TX0MASK (0x00000001U)
+#define EMAC_TXINTMASKSET_TX0MASK_SHIFT (0x00000000U)
+
+
+/* TXINTMASKCLEAR */
+
+
+#define EMAC_TXINTMASKCLEAR_TX7MASK (0x00000080U)
+#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_TXINTMASKCLEAR_TX6MASK (0x00000040U)
+#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_TXINTMASKCLEAR_TX5MASK (0x00000020U)
+#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_TXINTMASKCLEAR_TX4MASK (0x00000010U)
+#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_TXINTMASKCLEAR_TX3MASK (0x00000008U)
+#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_TXINTMASKCLEAR_TX2MASK (0x00000004U)
+#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_TXINTMASKCLEAR_TX1MASK (0x00000002U)
+#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_TXINTMASKCLEAR_TX0MASK (0x00000001U)
+#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT (0x00000000U)
+
+
+/* MACINVECTOR */
+
+
+#define EMAC_MACINVECTOR_STATPEND (0x08000000U)
+#define EMAC_MACINVECTOR_STATPEND_SHIFT (0x0000001BU)
+
+#define EMAC_MACINVECTOR_HOSTPEND (0x04000000U)
+#define EMAC_MACINVECTOR_HOSTPEND_SHIFT (0x0000001AU)
+
+#define EMAC_MACINVECTOR_LINKINT0 (0x02000000U)
+#define EMAC_MACINVECTOR_LINKINT0_SHIFT (0x00000019U)
+
+#define EMAC_MACINVECTOR_USERINT0 (0x01000000U)
+#define EMAC_MACINVECTOR_USERINT0_SHIFT (0x00000018U)
+
+#define EMAC_MACINVECTOR_TXPEND (0x00FF0000U)
+#define EMAC_MACINVECTOR_TXPEND_SHIFT (0x00000010U)
+
+#define EMAC_MACINVECTOR_RXTHRESHPEND (0x0000FF00U)
+#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_MACINVECTOR_RXPEND (0x000000FFU)
+#define EMAC_MACINVECTOR_RXPEND_SHIFT (0x00000000U)
+
+
+/* MACEOIVECTOR */
+
+
+#define EMAC_MACEOIVECTOR_INTVECT (0x0000001FU)
+#define EMAC_MACEOIVECTOR_INTVECT_SHIFT (0x00000000U)
+/*----INTVECT Tokens----*/
+#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH (0x00000000U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0RX (0x00000001U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0TX (0x00000002U)
+#define EMAC_MACEOIVECTOR_INTVECT_C0MISC (0x00000003U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH (0x00000004U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1RX (0x00000005U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1TX (0x00000006U)
+#define EMAC_MACEOIVECTOR_INTVECT_C1MISC (0x00000007U)
+
+
+/* RXINTSTATRAW */
+
+
+#define EMAC_RXINTSTATRAW_RX7THRESHPEND (0x00008000U)
+#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTSTATRAW_RX6THRESHPEND (0x00004000U)
+#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTSTATRAW_RX5THRESHPEND (0x00002000U)
+#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTSTATRAW_RX4THRESHPEND (0x00001000U)
+#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTSTATRAW_RX3THRESHPEND (0x00000800U)
+#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTSTATRAW_RX2THRESHPEND (0x00000400U)
+#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTSTATRAW_RX1THRESHPEND (0x00000200U)
+#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT (0x00000009U)
+
+#define EMAC_RXINTSTATRAW_RX0THRESHPEND (0x00000100U)
+#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_RXINTSTATRAW_RX7PEND (0x00000080U)
+#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_RXINTSTATRAW_RX6PEND (0x00000040U)
+#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_RXINTSTATRAW_RX5PEND (0x00000020U)
+#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_RXINTSTATRAW_RX4PEND (0x00000010U)
+#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_RXINTSTATRAW_RX3PEND (0x00000008U)
+#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_RXINTSTATRAW_RX2PEND (0x00000004U)
+#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_RXINTSTATRAW_RX1PEND (0x00000002U)
+#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_RXINTSTATRAW_RX0PEND (0x00000001U)
+#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT (0x00000000U)
+
+
+/* RXINTSTATMASKED */
+
+
+#define EMAC_RXINTSTATMASKED_RX7THRESHPEND (0x00008000U)
+#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTSTATMASKED_RX6THRESHPEND (0x00004000U)
+#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTSTATMASKED_RX5THRESHPEND (0x00002000U)
+#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTSTATMASKED_RX4THRESHPEND (0x00001000U)
+#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTSTATMASKED_RX3THRESHPEND (0x00000800U)
+#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTSTATMASKED_RX2THRESHPEND (0x00000400U)
+#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTSTATMASKED_RX1THRESHPEND (0x00000200U)
+#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT (0x00000009U)
+
+#define EMAC_RXINTSTATMASKED_RX0THRESHPEND (0x00000100U)
+#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT (0x00000008U)
+
+#define EMAC_RXINTSTATMASKED_RX7PEND (0x00000080U)
+#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT (0x00000007U)
+
+#define EMAC_RXINTSTATMASKED_RX6PEND (0x00000040U)
+#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT (0x00000006U)
+
+#define EMAC_RXINTSTATMASKED_RX5PEND (0x00000020U)
+#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT (0x00000005U)
+
+#define EMAC_RXINTSTATMASKED_RX4PEND (0x00000010U)
+#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT (0x00000004U)
+
+#define EMAC_RXINTSTATMASKED_RX3PEND (0x00000008U)
+#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT (0x00000003U)
+
+#define EMAC_RXINTSTATMASKED_RX2PEND (0x00000004U)
+#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT (0x00000002U)
+
+#define EMAC_RXINTSTATMASKED_RX1PEND (0x00000002U)
+#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT (0x00000001U)
+
+#define EMAC_RXINTSTATMASKED_RX0PEND (0x00000001U)
+#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT (0x00000000U)
+
+
+/* RXINTMASKSET */
+
+
+#define EMAC_RXINTMASKSET_RX7THRESHMASK (0x00008000U)
+#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTMASKSET_RX6THRESHMASK (0x00004000U)
+#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTMASKSET_RX5THRESHMASK (0x00002000U)
+#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTMASKSET_RX4THRESHMASK (0x00001000U)
+#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTMASKSET_RX3THRESHMASK (0x00000800U)
+#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTMASKSET_RX2THRESHMASK (0x00000400U)
+#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTMASKSET_RX1THRESHMASK (0x00000200U)
+#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT (0x00000009U)
+
+#define EMAC_RXINTMASKSET_RX0THRESHMASK (0x00000100U)
+#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT (0x00000008U)
+
+#define EMAC_RXINTMASKSET_RX7MASK (0x00000080U)
+#define EMAC_RXINTMASKSET_RX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_RXINTMASKSET_RX6MASK (0x00000040U)
+#define EMAC_RXINTMASKSET_RX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_RXINTMASKSET_RX5MASK (0x00000020U)
+#define EMAC_RXINTMASKSET_RX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_RXINTMASKSET_RX4MASK (0x00000010U)
+#define EMAC_RXINTMASKSET_RX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_RXINTMASKSET_RX3MASK (0x00000008U)
+#define EMAC_RXINTMASKSET_RX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_RXINTMASKSET_RX2MASK (0x00000004U)
+#define EMAC_RXINTMASKSET_RX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_RXINTMASKSET_RX1MASK (0x00000002U)
+#define EMAC_RXINTMASKSET_RX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_RXINTMASKSET_RX0MASK (0x00000001U)
+#define EMAC_RXINTMASKSET_RX0MASK_SHIFT (0x00000000U)
+
+
+/* RXINTMASKCLEAR */
+
+
+#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK (0x00008000U)
+#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT (0x0000000FU)
+
+#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK (0x00004000U)
+#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT (0x0000000EU)
+
+#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK (0x00002000U)
+#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT (0x0000000DU)
+
+#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK (0x00001000U)
+#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT (0x0000000CU)
+
+#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK (0x00000800U)
+#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT (0x0000000BU)
+
+#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK (0x00000400U)
+#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT (0x0000000AU)
+
+#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK (0x00000200U)
+#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT (0x00000009U)
+
+#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK (0x00000100U)
+#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT (0x00000008U)
+
+#define EMAC_RXINTMASKCLEAR_RX7MASK (0x00000080U)
+#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT (0x00000007U)
+
+#define EMAC_RXINTMASKCLEAR_RX6MASK (0x00000040U)
+#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT (0x00000006U)
+
+#define EMAC_RXINTMASKCLEAR_RX5MASK (0x00000020U)
+#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT (0x00000005U)
+
+#define EMAC_RXINTMASKCLEAR_RX4MASK (0x00000010U)
+#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT (0x00000004U)
+
+#define EMAC_RXINTMASKCLEAR_RX3MASK (0x00000008U)
+#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT (0x00000003U)
+
+#define EMAC_RXINTMASKCLEAR_RX2MASK (0x00000004U)
+#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT (0x00000002U)
+
+#define EMAC_RXINTMASKCLEAR_RX1MASK (0x00000002U)
+#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT (0x00000001U)
+
+#define EMAC_RXINTMASKCLEAR_RX0MASK (0x00000001U)
+#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT (0x00000000U)
+
+
+/* MACINTSTATRAW */
+
+
+#define EMAC_MACINTSTATRAW_HOSTPEND (0x00000002U)
+#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT (0x00000001U)
+
+#define EMAC_MACINTSTATRAW_STATPEND (0x00000001U)
+#define EMAC_MACINTSTATRAW_STATPEND_SHIFT (0x00000000U)
+
+
+/* MACINTSTATMASKED */
+
+
+#define EMAC_MACINTSTATMASKED_HOSTPEND (0x00000002U)
+#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT (0x00000001U)
+
+#define EMAC_MACINTSTATMASKED_STATPEND (0x00000001U)
+#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT (0x00000000U)
+
+
+/* MACINTMASKSET */
+
+
+#define EMAC_MACINTMASKSET_HOSTMASK (0x00000002U)
+#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT (0x00000001U)
+
+#define EMAC_MACINTMASKSET_STATMASK (0x00000001U)
+#define EMAC_MACINTMASKSET_STATMASK_SHIFT (0x00000000U)
+
+
+/* MACINTMASKCLEAR */
+
+
+#define EMAC_MACINTMASKCLEAR_HOSTMASK (0x00000002U)
+#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT (0x00000001U)
+
+#define EMAC_MACINTMASKCLEAR_STATMASK (0x00000001U)
+#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT (0x00000000U)
+
+
+/* RXMBPENABLE */
+
+
+#define EMAC_RXMBPENABLE_RXPASSCRC (0x40000000U)
+#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT (0x0000001EU)
+#define EMAC_RXMBPENABLE_RXQOSEN (0x20000000U)
+#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT (0x0000001DU)
+#define EMAC_RXMBPENABLE_RXNOCHAIN (0x10000000U)
+#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT (0x0000001CU)
+#define EMAC_RXMBPENABLE_RXCMFEN (0x01000000U)
+#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT (0x00000018U)
+#define EMAC_RXMBPENABLE_RXCSFEN (0x00800000U)
+#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT (0x00000017U)
+#define EMAC_RXMBPENABLE_RXCEFEN (0x00400000U)
+#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT (0x00000016U)
+#define EMAC_RXMBPENABLE_RXCAFEN (0x00200000U)
+#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT (0x00000015U)
+/*----RXCAFEN Tokens----*/
+#define EMAC_RXMBPENABLE_RXPROMCH (0x00070000U)
+#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT (0x00000010U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 (0x00000007U)
+
+
+#define EMAC_RXMBPENABLE_RXBROADEN (0x00002000U)
+#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT (0x0000000DU)
+#define EMAC_RXMBPENABLE_RXBROADCH (0x00000700U)
+#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT (0x00000008U)
+/*----RXBROADCH Tokens----*/
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 (0x00000007U)
+
+
+#define EMAC_RXMBPENABLE_RXMULTEN (0x00000020U)
+#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT (0x00000005U)
+#define EMAC_RXMBPENABLE_RXMULTCH (0x00000007U)
+#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT (0x00000000U)
+/*----RXMULTCH Tokens----*/
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 (0x00000000U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 (0x00000001U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 (0x00000002U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 (0x00000003U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 (0x00000004U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 (0x00000005U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 (0x00000006U)
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 (0x00000007U)
+
+
+/* RXUNICASTSET */
+
+
+#define EMAC_RXUNICASTSET_RXCH7EN (0x00000080U)
+#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT (0x00000007U)
+#define EMAC_RXUNICASTSET_RXCH6EN (0x00000040U)
+#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT (0x00000006U)
+#define EMAC_RXUNICASTSET_RXCH5EN (0x00000020U)
+#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT (0x00000005U)
+#define EMAC_RXUNICASTSET_RXCH4EN (0x00000010U)
+#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT (0x00000004U)
+#define EMAC_RXUNICASTSET_RXCH3EN (0x00000008U)
+#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT (0x00000003U)
+#define EMAC_RXUNICASTSET_RXCH2EN (0x00000004U)
+#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT (0x00000002U)
+#define EMAC_RXUNICASTSET_RXCH1EN (0x00000002U)
+#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT (0x00000001U)
+#define EMAC_RXUNICASTSET_RXCH0EN (0x00000001U)
+#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT (0x00000000U)
+
+/* RXUNICASTCLEAR */
+
+
+#define EMAC_RXUNICASTCLEAR_RXCH7EN (0x00000080U)
+#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT (0x00000007U)
+#define EMAC_RXUNICASTCLEAR_RXCH6EN (0x00000040U)
+#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT (0x00000006U)
+#define EMAC_RXUNICASTCLEAR_RXCH5EN (0x00000020U)
+#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT (0x00000005U)
+#define EMAC_RXUNICASTCLEAR_RXCH4EN (0x00000010U)
+#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT (0x00000004U)
+#define EMAC_RXUNICASTCLEAR_RXCH3EN (0x00000008U)
+#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT (0x00000003U)
+#define EMAC_RXUNICASTCLEAR_RXCH2EN (0x00000004U)
+#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT (0x00000002U)
+#define EMAC_RXUNICASTCLEAR_RXCH1EN (0x00000002U)
+#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT (0x00000001U)
+#define EMAC_RXUNICASTCLEAR_RXCH0EN (0x00000001U)
+#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT (0x00000000U)
+
+/* RXMAXLEN */
+
+
+#define EMAC_RXMAXLEN_RXMAXLEN (0x0000FFFFU)
+#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT (0x00000000U)
+
+
+/* RXBUFFEROFFSET */
+
+
+#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET (0x0000FFFFU)
+#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT (0x00000000U)
+
+
+/* RXFILTERLOWTHRESH */
+
+
+#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH (0x000000FFU)
+#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT (0x00000000U)
+
+
+/* RX0FLOWTHRESH */
+
+
+#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH (0x000000FFU)
+#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX1FLOWTHRESH */
+
+
+#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH (0x000000FFU)
+#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX2FLOWTHRESH */
+
+
+#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH (0x000000FFU)
+#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX3FLOWTHRESH */
+
+
+#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH (0x000000FFU)
+#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX4FLOWTHRESH */
+
+
+#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH (0x000000FFU)
+#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX5FLOWTHRESH */
+
+
+#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH (0x000000FFU)
+#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX6FLOWTHRESH */
+
+
+#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH (0x000000FFU)
+#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX7FLOWTHRESH */
+
+
+#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH (0x000000FFU)
+#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT (0x00000000U)
+
+
+/* RX0FREEBUFFER */
+
+
+#define EMAC_RX0FREEBUFFER_RX0FREEBUF (0x0000FFFFU)
+#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX1FREEBUFFER */
+
+
+#define EMAC_RX1FREEBUFFER_RX1FREEBUF (0x0000FFFFU)
+#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX2FREEBUFFER */
+
+
+#define EMAC_RX2FREEBUFFER_RX2FREEBUF (0x0000FFFFU)
+#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX3FREEBUFFER */
+
+
+#define EMAC_RX3FREEBUFFER_RX3FREEBUF (0x0000FFFFU)
+#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX4FREEBUFFER */
+
+
+#define EMAC_RX4FREEBUFFER_RX4FREEBUF (0x0000FFFFU)
+#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX5FREEBUFFER */
+
+
+#define EMAC_RX5FREEBUFFER_RX5FREEBUF (0x0000FFFFU)
+#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX6FREEBUFFER */
+
+
+#define EMAC_RX6FREEBUFFER_RX6FREEBUF (0x0000FFFFU)
+#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT (0x00000000U)
+
+
+/* RX7FREEBUFFER */
+
+
+#define EMAC_RX7FREEBUFFER_RX7FREEBUF (0x0000FFFFU)
+#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT (0x00000000U)
+
+
+/* MACCONTROL */
+
+
+
+
+
+#define EMAC_MACCONTROL_RMIISPEED (0x00008000U)
+#define EMAC_MACCONTROL_RMIISPEED_SHIFT (0x0000000FU)
+#define EMAC_MACCONTROL_RXOFFLENBLOCK (0x00004000U)
+#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT (0x0000000EU)
+#define EMAC_MACCONTROL_RXOWNERSHIP (0x00002000U)
+#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT (0x0000000DU)
+#define EMAC_MACCONTROL_CMDIDLE (0x00000800U)
+#define EMAC_MACCONTROL_CMDIDLE_SHIFT (0x0000000BU)
+#define EMAC_MACCONTROL_TXSHORTGAPEN (0x00000400U)
+#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT (0x0000000AU)
+#define EMAC_MACCONTROL_TXPTYPE (0x00000200U)
+#define EMAC_MACCONTROL_TXPTYPE_SHIFT (0x00000009U)
+#define EMAC_MACCONTROL_TXPACE (0x00000040U)
+#define EMAC_MACCONTROL_TXPACE_SHIFT (0x00000006U)
+#define EMAC_MACCONTROL_GMIIEN (0x00000020U)
+#define EMAC_MACCONTROL_GMIIEN_SHIFT (0x00000005U)
+#define EMAC_MACCONTROL_TXFLOWEN (0x00000010U)
+#define EMAC_MACCONTROL_TXFLOWEN_SHIFT (0x00000004U)
+#define EMAC_MACCONTROL_RXBUFFERFLOWEN (0x00000008U)
+#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT (0x00000003U)
+#define EMAC_MACCONTROL_LOOPBACK (0x00000002U)
+#define EMAC_MACCONTROL_LOOPBACK_SHIFT (0x00000001U)
+#define EMAC_MACCONTROL_FULLDUPLEX (0x00000001U)
+#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT (0x00000000U)
+
+
+/* MACSTATUS */
+
+#define EMAC_MACSTATUS_IDLE (0x80000000U)
+#define EMAC_MACSTATUS_IDLE_SHIFT (0x0000001FU)
+#define EMAC_MACSTATUS_TXERRCODE (0x00F00000U)
+#define EMAC_MACSTATUS_TXERRCODE_SHIFT (0x00000014U)
+/*----TXERRCODE Tokens----*/
+#define EMAC_MACSTATUS_TXERRCODE_NOERROR (0x00000000U)
+#define EMAC_MACSTATUS_TXERRCODE_SOPERROR (0x00000001U)
+#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP (0x00000002U)
+#define EMAC_MACSTATUS_TXERRCODE_NOEOP (0x00000003U)
+#define EMAC_MACSTATUS_TXERRCODE_NULLPTR (0x00000004U)
+#define EMAC_MACSTATUS_TXERRCODE_NULLEN (0x00000005U)
+#define EMAC_MACSTATUS_TXERRCODE_LENERROR (0x00000006U)
+
+
+#define EMAC_MACSTATUS_TXERRCH (0x00070000U)
+#define EMAC_MACSTATUS_TXERRCH_SHIFT (0x00000010U)
+/*----TXERRCH Tokens----*/
+#define EMAC_MACSTATUS_TXERRCH_CHA0 (0x00000000U)
+#define EMAC_MACSTATUS_TXERRCH_CHA1 (0x00000001U)
+#define EMAC_MACSTATUS_TXERRCH_CHA2 (0x00000002U)
+#define EMAC_MACSTATUS_TXERRCH_CHA3 (0x00000003U)
+#define EMAC_MACSTATUS_TXERRCH_CHA4 (0x00000004U)
+#define EMAC_MACSTATUS_TXERRCH_CHA5 (0x00000005U)
+#define EMAC_MACSTATUS_TXERRCH_CHA6 (0x00000006U)
+#define EMAC_MACSTATUS_TXERRCH_CHA7 (0x00000007U)
+
+#define EMAC_MACSTATUS_RXERRCODE (0x0000F000U)
+#define EMAC_MACSTATUS_RXERRCODE_SHIFT (0x0000000CU)
+/*----RXERRCODE Tokens----*/
+#define EMAC_MACSTATUS_RXERRCODE_NOERROR (0x00000000U)
+#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP (0x00000002U)
+#define EMAC_MACSTATUS_RXERRCODE_NULLPTR (0x00000004U)
+
+
+#define EMAC_MACSTATUS_RXERRCH (0x00000700U)
+#define EMAC_MACSTATUS_RXERRCH_SHIFT (0x00000008U)
+/*----RXERRCH Tokens----*/
+#define EMAC_MACSTATUS_RXERRCH_CHA0 (0x00000000U)
+#define EMAC_MACSTATUS_RXERRCH_CHA1 (0x00000001U)
+#define EMAC_MACSTATUS_RXERRCH_CHA2 (0x00000002U)
+#define EMAC_MACSTATUS_RXERRCH_CHA3 (0x00000003U)
+#define EMAC_MACSTATUS_RXERRCH_CHA4 (0x00000004U)
+#define EMAC_MACSTATUS_RXERRCH_CHA5 (0x00000005U)
+#define EMAC_MACSTATUS_RXERRCH_CHA6 (0x00000006U)
+#define EMAC_MACSTATUS_RXERRCH_CHA7 (0x00000007U)
+
+
+
+
+#define EMAC_MACSTATUS_RXQOSACT (0x00000004U)
+#define EMAC_MACSTATUS_RXQOSACT_SHIFT (0x00000002U)
+#define EMAC_MACSTATUS_RXFLOWACT (0x00000002U)
+#define EMAC_MACSTATUS_RXFLOWACT_SHIFT (0x00000001U)
+#define EMAC_MACSTATUS_TXFLOWACT (0x00000001U)
+#define EMAC_MACSTATUS_TXFLOWACT_SHIFT (0x00000000U)
+
+/* EMCONTROL */
+
+
+#define EMAC_EMCONTROL_SOFT (0x00000002U)
+#define EMAC_EMCONTROL_SOFT_SHIFT (0x00000001U)
+
+#define EMAC_EMCONTROL_FREE (0x00000001U)
+#define EMAC_EMCONTROL_FREE_SHIFT (0x00000000U)
+
+
+/* FIFOCONTROL */
+
+
+#define EMAC_FIFOCONTROL_TXCELLTHRESH (0x00000003U)
+#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT (0x00000000U)
+
+
+/* MACCONFIG */
+
+#define EMAC_MACCONFIG_TXCELLDEPTH (0xFF000000U)
+#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT (0x00000018U)
+
+#define EMAC_MACCONFIG_RXCELLDEPTH (0x00FF0000U)
+#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT (0x00000010U)
+
+#define EMAC_MACCONFIG_ADDRESSTYPE (0x0000FF00U)
+#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT (0x00000008U)
+
+#define EMAC_MACCONFIG_MACCFIG (0x000000FFU)
+#define EMAC_MACCONFIG_MACCFIG_SHIFT (0x00000000U)
+
+
+/* SOFTRESET */
+
+
+#define EMAC_SOFTRESET_SOFTRESET (0x00000001U)
+#define EMAC_SOFTRESET_SOFTRESET_SHIFT (0x00000000U)
+
+/* MACSRCADDRLO */
+
+
+#define EMAC_MACSRCADDRLO_MACSRCADDR0 (0x0000FF00U)
+#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT (0x00000008U)
+#define EMAC_MACSRCADDRLO_MACSRCADDR1 (0x000000FFU)
+#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT (0x00000000U)
+
+
+/* MACSRCADDRHI */
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR2 (0xFF000000U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT (0x00000018U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR3 (0x00FF0000U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT (0x00000010U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR4 (0x0000FF00U)
+#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT (0x00000008U)
+
+#define EMAC_MACSRCADDRHI_MACSRCADDR5 (0x000000FFU)
+#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT (0x00000000U)
+
+
+/* MACHASH1 */
+
+#define EMAC_MACHASH1_MACHASH1 (0xFFFFFFFFU)
+#define EMAC_MACHASH1_MACHASH1_SHIFT (0x00000000U)
+
+
+/* MACHASH2 */
+
+#define EMAC_MACHASH2_MACHASH2 (0xFFFFFFFFU)
+#define EMAC_MACHASH2_MACHASH2_SHIFT (0x00000000U)
+
+
+/* BOFFTEST */
+
+
+#define EMAC_BOFFTEST_RNDNUM (0x03FF0000U)
+#define EMAC_BOFFTEST_RNDNUM_SHIFT (0x00000010U)
+
+#define EMAC_BOFFTEST_COLLCOUNT (0x0000F000U)
+#define EMAC_BOFFTEST_COLLCOUNT_SHIFT (0x0000000CU)
+
+
+#define EMAC_BOFFTEST_TXBACKOFF (0x000003FFU)
+#define EMAC_BOFFTEST_TXBACKOFF_SHIFT (0x00000000U)
+
+
+/* TPACETEST */
+
+
+#define EMAC_TPACETEST_PACEVAL (0x0000001FU)
+#define EMAC_TPACETEST_PACEVAL_SHIFT (0x00000000U)
+
+
+/* RXPAUSE */
+
+
+#define EMAC_RXPAUSE_PAUSETIMER (0x0000FFFFU)
+#define EMAC_RXPAUSE_PAUSETIMER_SHIFT (0x00000000U)
+
+
+/* TXPAUSE */
+
+
+#define EMAC_TXPAUSE_PAUSETIMER (0x0000FFFFU)
+#define EMAC_TXPAUSE_PAUSETIMER_SHIFT (0x00000000U)
+
+
+/* RXGOODFRAMES */
+
+#define EMAC_RXGOODFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXGOODFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXBCASTFRAMES */
+
+#define EMAC_RXBCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXBCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXMCASTFRAMES */
+
+#define EMAC_RXMCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXMCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXPAUSEFRAMES */
+
+#define EMAC_RXPAUSEFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* RXCRCERRORS */
+
+#define EMAC_RXCRCERRORS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXCRCERRORS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXALIGNCODEERRORS */
+
+#define EMAC_RXALIGNCODEERRORS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXOVERSIZED */
+
+#define EMAC_RXOVERSIZED_COUNT (0xFFFFFFFFU)
+#define EMAC_RXOVERSIZED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXJABBER */
+
+#define EMAC_RXJABBER_COUNT (0xFFFFFFFFU)
+#define EMAC_RXJABBER_COUNT_SHIFT (0x00000000U)
+
+
+/* RXUNDERSIZED */
+
+#define EMAC_RXUNDERSIZED_COUNT (0xFFFFFFFFU)
+#define EMAC_RXUNDERSIZED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXFRAGMENTS */
+
+#define EMAC_RXFRAGMENTS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXFRAGMENTS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXFILTERED */
+
+#define EMAC_RXFILTERED_COUNT (0xFFFFFFFFU)
+#define EMAC_RXFILTERED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXQOSFILTERED */
+
+#define EMAC_RXQOSFILTERED_COUNT (0xFFFFFFFFU)
+#define EMAC_RXQOSFILTERED_COUNT_SHIFT (0x00000000U)
+
+
+/* RXOCTETS */
+
+#define EMAC_RXOCTETS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXOCTETS_COUNT_SHIFT (0x00000000U)
+
+
+/* TXGOODFRAMES */
+
+#define EMAC_TXGOODFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXGOODFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXBCASTFRAMES */
+
+#define EMAC_TXBCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXBCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXMCASTFRAMES */
+
+#define EMAC_TXMCASTFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXMCASTFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXPAUSEFRAMES */
+
+#define EMAC_TXPAUSEFRAMES_COUNT (0xFFFFFFFFU)
+#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT (0x00000000U)
+
+
+/* TXDEFERRED */
+
+#define EMAC_TXDEFERRED_COUNT (0xFFFFFFFFU)
+#define EMAC_TXDEFERRED_COUNT_SHIFT (0x00000000U)
+
+
+/* TXCOLLISION */
+
+#define EMAC_TXCOLLISION_COUNT (0xFFFFFFFFU)
+#define EMAC_TXCOLLISION_COUNT_SHIFT (0x00000000U)
+
+
+/* TXSINGLECOLL */
+
+#define EMAC_TXSINGLECOLL_COUNT (0xFFFFFFFFU)
+#define EMAC_TXSINGLECOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXMULTICOLL */
+
+#define EMAC_TXMULTICOLL_COUNT (0xFFFFFFFFU)
+#define EMAC_TXMULTICOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXEXCESSIVECOLL */
+
+#define EMAC_TXEXCESSIVECOLL_COUNT (0xFFFFFFFFU)
+#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXLATECOLL */
+
+#define EMAC_TXLATECOLL_COUNT (0xFFFFFFFFU)
+#define EMAC_TXLATECOLL_COUNT_SHIFT (0x00000000U)
+
+
+/* TXUNDERRUN */
+
+#define EMAC_TXUNDERRUN_COUNT (0xFFFFFFFFU)
+#define EMAC_TXUNDERRUN_COUNT_SHIFT (0x00000000U)
+
+
+/* TXCARRIERSENSE */
+
+#define EMAC_TXCARRIERSENSE_COUNT (0xFFFFFFFFU)
+#define EMAC_TXCARRIERSENSE_COUNT_SHIFT (0x00000000U)
+
+
+/* TXOCTETS */
+
+#define EMAC_TXOCTETS_COUNT (0xFFFFFFFFU)
+#define EMAC_TXOCTETS_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME64 */
+
+#define EMAC_FRAME64_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME64_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME65T127 */
+
+#define EMAC_FRAME65T127_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME65T127_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME128T255 */
+
+#define EMAC_FRAME128T255_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME128T255_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME256T511 */
+
+#define EMAC_FRAME256T511_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME256T511_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME512T1023 */
+
+#define EMAC_FRAME512T1023_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME512T1023_COUNT_SHIFT (0x00000000U)
+
+
+/* FRAME1024TUP */
+
+#define EMAC_FRAME1024TUP_COUNT (0xFFFFFFFFU)
+#define EMAC_FRAME1024TUP_COUNT_SHIFT (0x00000000U)
+
+
+/* NETOCTETS */
+
+#define EMAC_NETOCTETS_COUNT (0xFFFFFFFFU)
+#define EMAC_NETOCTETS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXSOFOVERRUNS */
+
+#define EMAC_RXSOFOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXMOFOVERRUNS */
+
+#define EMAC_RXMOFOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* RXDMAOVERRUNS */
+
+#define EMAC_RXDMAOVERRUNS_COUNT (0xFFFFFFFFU)
+#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT (0x00000000U)
+
+
+/* MACADDRLO */
+
+
+#define EMAC_MACADDRLO_VALID (0x00100000U)
+#define EMAC_MACADDRLO_VALID_SHIFT (0x00000014U)
+#define EMAC_MACADDRLO_MATCHFILT (0x00080000U)
+#define EMAC_MACADDRLO_MATCHFILT_SHIFT (0x00000013U)
+#define EMAC_MACADDRLO_CHANNEL (0x00070000U)
+#define EMAC_MACADDRLO_CHANNEL_SHIFT (0x00000010U)
+#define EMAC_MACADDRLO_MACADDR0 (0x0000FF00U)
+#define EMAC_MACADDRLO_MACADDR0_SHIFT (0x00000008U)
+#define EMAC_MACADDRLO_MACADDR1 (0x000000FFU)
+#define EMAC_MACADDRLO_MACADDR1_SHIFT (0x00000000U)
+
+
+/* MACADDRHI */
+
+#define EMAC_MACADDRHI_MACADDR2 (0xFF000000U)
+#define EMAC_MACADDRHI_MACADDR2_SHIFT (0x00000018U)
+
+#define EMAC_MACADDRHI_MACADDR3 (0x00FF0000U)
+#define EMAC_MACADDRHI_MACADDR3_SHIFT (0x00000010U)
+
+#define EMAC_MACADDRHI_MACADDR4 (0x0000FF00U)
+#define EMAC_MACADDRHI_MACADDR4_SHIFT (0x00000008U)
+
+#define EMAC_MACADDRHI_MACADDR5 (0x000000FFU)
+#define EMAC_MACADDRHI_MACADDR5_SHIFT (0x00000000U)
+
+
+/* MACINDEX */
+
+
+#define EMAC_MACINDEX_MACINDEX (0x0000001FU)
+#define EMAC_MACINDEX_MACINDEX_SHIFT (0x00000000U)
+
+
+/* TX0HDP */
+
+#define EMAC_TX0HDP_TX0HDP (0xFFFFFFFFU)
+#define EMAC_TX0HDP_TX0HDP_SHIFT (0x00000000U)
+
+
+/* TX1HDP */
+
+#define EMAC_TX1HDP_TX1HDP (0xFFFFFFFFU)
+#define EMAC_TX1HDP_TX1HDP_SHIFT (0x00000000U)
+
+
+/* TX2HDP */
+
+#define EMAC_TX2HDP_TX2HDP (0xFFFFFFFFU)
+#define EMAC_TX2HDP_TX2HDP_SHIFT (0x00000000U)
+
+
+/* TX3HDP */
+
+#define EMAC_TX3HDP_TX3HDP (0xFFFFFFFFU)
+#define EMAC_TX3HDP_TX3HDP_SHIFT (0x00000000U)
+
+
+/* TX4HDP */
+
+#define EMAC_TX4HDP_TX4HDP (0xFFFFFFFFU)
+#define EMAC_TX4HDP_TX4HDP_SHIFT (0x00000000U)
+
+
+/* TX5HDP */
+
+#define EMAC_TX5HDP_TX5HDP (0xFFFFFFFFU)
+#define EMAC_TX5HDP_TX5HDP_SHIFT (0x00000000U)
+
+
+/* TX6HDP */
+
+#define EMAC_TX6HDP_TX6HDP (0xFFFFFFFFU)
+#define EMAC_TX6HDP_TX6HDP_SHIFT (0x00000000U)
+
+
+/* TX7HDP */
+
+#define EMAC_TX7HDP_TX7HDP (0xFFFFFFFFU)
+#define EMAC_TX7HDP_TX7HDP_SHIFT (0x00000000U)
+
+
+/* RX0HDP */
+
+#define EMAC_RX0HDP_RX0HDP (0xFFFFFFFFU)
+#define EMAC_RX0HDP_RX0HDP_SHIFT (0x00000000U)
+
+
+/* RX1HDP */
+
+#define EMAC_RX1HDP_RX1HDP (0xFFFFFFFFU)
+#define EMAC_RX1HDP_RX1HDP_SHIFT (0x00000000U)
+
+
+/* RX2HDP */
+
+#define EMAC_RX2HDP_RX2HDP (0xFFFFFFFFU)
+#define EMAC_RX2HDP_RX2HDP_SHIFT (0x00000000U)
+
+
+/* RX3HDP */
+
+#define EMAC_RX3HDP_RX3HDP (0xFFFFFFFFU)
+#define EMAC_RX3HDP_RX3HDP_SHIFT (0x00000000U)
+
+
+/* RX4HDP */
+
+#define EMAC_RX4HDP_RX4HDP (0xFFFFFFFFU)
+#define EMAC_RX4HDP_RX4HDP_SHIFT (0x00000000U)
+
+
+/* RX5HDP */
+
+#define EMAC_RX5HDP_RX5HDP (0xFFFFFFFFU)
+#define EMAC_RX5HDP_RX5HDP_SHIFT (0x00000000U)
+
+
+/* RX6HDP */
+
+#define EMAC_RX6HDP_RX6HDP (0xFFFFFFFFU)
+#define EMAC_RX6HDP_RX6HDP_SHIFT (0x00000000U)
+
+
+/* RX7HDP */
+
+#define EMAC_RX7HDP_RX7HDP (0xFFFFFFFFU)
+#define EMAC_RX7HDP_RX7HDP_SHIFT (0x00000000U)
+
+
+/* TX0CP */
+
+#define EMAC_TX0CP_TX0CP (0xFFFFFFFFU)
+#define EMAC_TX0CP_TX0CP_SHIFT (0x00000000U)
+
+
+/* TX1CP */
+
+#define EMAC_TX1CP_TX1CP (0xFFFFFFFFU)
+#define EMAC_TX1CP_TX1CP_SHIFT (0x00000000U)
+
+
+/* TX2CP */
+
+#define EMAC_TX2CP_TX2CP (0xFFFFFFFFU)
+#define EMAC_TX2CP_TX2CP_SHIFT (0x00000000U)
+
+
+/* TX3CP */
+
+#define EMAC_TX3CP_TX3CP (0xFFFFFFFFU)
+#define EMAC_TX3CP_TX3CP_SHIFT (0x00000000U)
+
+
+/* TX4CP */
+
+#define EMAC_TX4CP_TX4CP (0xFFFFFFFFU)
+#define EMAC_TX4CP_TX4CP_SHIFT (0x00000000U)
+
+
+/* TX5CP */
+
+#define EMAC_TX5CP_TX5CP (0xFFFFFFFFU)
+#define EMAC_TX5CP_TX5CP_SHIFT (0x00000000U)
+
+
+/* TX6CP */
+
+#define EMAC_TX6CP_TX6CP (0xFFFFFFFFU)
+#define EMAC_TX6CP_TX6CP_SHIFT (0x00000000U)
+
+
+/* TX7CP */
+
+#define EMAC_TX7CP_TX7CP (0xFFFFFFFFU)
+#define EMAC_TX7CP_TX7CP_SHIFT (0x00000000U)
+
+
+/* RX0CP */
+
+#define EMAC_RX0CP_RX0CP (0xFFFFFFFFU)
+#define EMAC_RX0CP_RX0CP_SHIFT (0x00000000U)
+
+
+/* RX1CP */
+
+#define EMAC_RX1CP_RX1CP (0xFFFFFFFFU)
+#define EMAC_RX1CP_RX1CP_SHIFT (0x00000000U)
+
+
+/* RX2CP */
+
+#define EMAC_RX2CP_RX2CP (0xFFFFFFFFU)
+#define EMAC_RX2CP_RX2CP_SHIFT (0x00000000U)
+
+
+/* RX3CP */
+
+#define EMAC_RX3CP_RX3CP (0xFFFFFFFFU)
+#define EMAC_RX3CP_RX3CP_SHIFT (0x00000000U)
+
+
+/* RX4CP */
+
+#define EMAC_RX4CP_RX4CP (0xFFFFFFFFU)
+#define EMAC_RX4CP_RX4CP_SHIFT (0x00000000U)
+
+
+/* RX5CP */
+
+#define EMAC_RX5CP_RX5CP (0xFFFFFFFFU)
+#define EMAC_RX5CP_RX5CP_SHIFT (0x00000000U)
+
+
+/* RX6CP */
+
+#define EMAC_RX6CP_RX6CP (0xFFFFFFFFU)
+#define EMAC_RX6CP_RX6CP_SHIFT (0x00000000U)
+
+
+/* RX7CP */
+
+#define EMAC_RX7CP_RX7CP (0xFFFFFFFFU)
+#define EMAC_RX7CP_RX7CP_SHIFT (0x00000000U)
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
Index: firmware/include/hw_emac_ctrl.h
===================================================================
diff -u
--- firmware/include/hw_emac_ctrl.h (revision 0)
+++ firmware/include/hw_emac_ctrl.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,91 @@
+/*
+ * hw_emac1.h
+ */
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_EMAC_CTRL_H_
+#define _HW_EMAC_CTRL_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#define EMAC_CTRL_REVID (0x0U)
+#define EMAC_CTRL_SOFTRESET (0x4U)
+#define EMAC_CTRL_INTCONTROL (0xCU)
+#define EMAC_CTRL_C0RXTHRESHEN (0x10U)
+#define EMAC_CTRL_CnRXEN(n) ((uint32)0x14u + (uint32)((uint32)(n) << 4))
+#define EMAC_CTRL_CnTXEN(n) ((uint32)0x18u + (uint32)((uint32)(n) << 4))
+#define EMAC_CTRL_CnMISCEN(n) ((uint32)0x1Cu + (uint32)((uint32)(n) << 4))
+#define EMAC_CTRL_CnRXTHRESHEN(n) ((uint32)0x20u + (uint32)((uint32)(n) << 4))
+#define EMAC_CTRL_C0RXTHRESHSTAT (0x40U)
+#define EMAC_CTRL_C0RXSTAT (0x44U)
+#define EMAC_CTRL_C0TXSTAT (0x48U)
+#define EMAC_CTRL_C0MISCSTAT (0x4CU)
+#define EMAC_CTRL_C1RXTHRESHSTAT (0x50U)
+#define EMAC_CTRL_C1RXSTAT (0x54U)
+#define EMAC_CTRL_C1TXSTAT (0x58U)
+#define EMAC_CTRL_C1MISCSTAT (0x5CU)
+#define EMAC_CTRL_C2RXTHRESHSTAT (0x60U)
+#define EMAC_CTRL_C2RXSTAT (0x64U)
+#define EMAC_CTRL_C2TXSTAT (0x68U)
+#define EMAC_CTRL_C2MISCSTAT (0x6CU)
+#define EMAC_CTRL_C0RXIMAX (0x70U)
+#define EMAC_CTRL_C0TXIMAX (0x74U)
+#define EMAC_CTRL_C1RXIMAX (0x78U)
+#define EMAC_CTRL_C1TXIMAX (0x7CU)
+#define EMAC_CTRL_C2RXIMAX (0x80U)
+#define EMAC_CTRL_C2TXIMAX (0x84U)
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
Index: firmware/include/hw_mdio.h
===================================================================
diff -u
--- firmware/include/hw_mdio.h (revision 0)
+++ firmware/include/hw_mdio.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,264 @@
+/*
+ * hw_mdio.h
+ */
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_MDIO_H_
+#define _HW_MDIO_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#define MDIO_BASE (0xFCF78900U)
+
+#define MDIO_REVID (0x0U)
+#define MDIO_CONTROL (0x4U)
+#define MDIO_ALIVE (0x8U)
+#define MDIO_LINK (0xCU)
+#define MDIO_LINKINTRAW (0x10U)
+#define MDIO_LINKINTMASKED (0x14U)
+#define MDIO_USERINTRAW (0x20U)
+#define MDIO_USERINTMASKED (0x24U)
+#define MDIO_USERINTMASKSET (0x28U)
+#define MDIO_USERINTMASKCLEAR (0x2CU)
+#define MDIO_USERACCESS0 (0x80U)
+#define MDIO_USERPHYSEL0 (0x84U)
+#define MDIO_USERACCESS1 (0x88U)
+#define MDIO_USERPHYSEL1 (0x8CU)
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVID */
+
+#define MDIO_REVID_REV (0xFFFFFFFFU)
+#define MDIO_REVID_REV_SHIFT (0x00000000U)
+
+
+/* CONTROL */
+
+#define MDIO_CONTROL_IDLE (0x80000000U)
+#define MDIO_CONTROL_IDLE_SHIFT (0x0000001FU)
+/*----IDLE Tokens----*/
+#define MDIO_CONTROL_IDLE_NO (0x00000000U)
+#define MDIO_CONTROL_IDLE_YES (0x00000001U)
+
+#define MDIO_CONTROL_ENABLE (0x40000000U)
+#define MDIO_CONTROL_ENABLE_SHIFT (0x0000001EU)
+
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F000000U)
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT (0x00000018U)
+
+
+#define MDIO_CONTROL_PREAMBLE (0x00100000U)
+#define MDIO_CONTROL_PREAMBLE_SHIFT (0x00000014U)
+/*----PREAMBLE Tokens----*/
+
+#define MDIO_CONTROL_FAULT (0x00080000U)
+#define MDIO_CONTROL_FAULT_SHIFT (0x00000013U)
+
+#define MDIO_CONTROL_FAULTENB (0x00040000U)
+#define MDIO_CONTROL_FAULTENB_SHIFT (0x00000012U)
+/*----FAULTENB Tokens----*/
+
+
+
+#define MDIO_CONTROL_CLKDIV (0x0000FFFFU)
+#define MDIO_CONTROL_CLKDIV_SHIFT (0x00000000U)
+/*----CLKDIV Tokens----*/
+
+
+/* ALIVE */
+
+#define MDIO_ALIVE_REGVAL (0xFFFFFFFFU)
+#define MDIO_ALIVE_REGVAL_SHIFT (0x00000000U)
+
+
+/* LINK */
+
+#define MDIO_LINK_REGVAL (0xFFFFFFFFU)
+#define MDIO_LINK_REGVAL_SHIFT (0x00000000U)
+
+
+/* LINKINTRAW */
+
+
+#define MDIO_LINKINTRAW_USERPHY1 (0x00000002U)
+#define MDIO_LINKINTRAW_USERPHY1_SHIFT (0x00000001U)
+
+#define MDIO_LINKINTRAW_USERPHY0 (0x00000001U)
+#define MDIO_LINKINTRAW_USERPHY0_SHIFT (0x00000000U)
+
+
+/* LINKINTMASKED */
+
+
+#define MDIO_LINKINTMASKED_USERPHY1 (0x00000002U)
+#define MDIO_LINKINTMASKED_USERPHY1_SHIFT (0x00000001U)
+
+#define MDIO_LINKINTMASKED_USERPHY0 (0x00000001U)
+#define MDIO_LINKINTMASKED_USERPHY0_SHIFT (0x00000000U)
+
+
+/* USERINTRAW */
+
+
+#define MDIO_USERINTRAW_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTRAW_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTRAW_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTRAW_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKED */
+
+
+#define MDIO_USERINTMASKED_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKED_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKED_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKED_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKSET */
+
+
+#define MDIO_USERINTMASKSET_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKSET_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERINTMASKCLEAR */
+
+
+#define MDIO_USERINTMASKCLEAR_USERACCESS1 (0x00000002U)
+#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT (0x00000001U)
+
+#define MDIO_USERINTMASKCLEAR_USERACCESS0 (0x00000001U)
+#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT (0x00000000U)
+
+
+/* USERACCESS0 */
+
+#define MDIO_USERACCESS0_GO (0x80000000U)
+#define MDIO_USERACCESS0_GO_SHIFT (0x0000001FU)
+
+#define MDIO_USERACCESS0_WRITE (0x40000000U)
+#define MDIO_USERACCESS0_READ (0x00000000U)
+#define MDIO_USERACCESS0_WRITE_SHIFT (0x0000001EU)
+
+#define MDIO_USERACCESS0_ACK (0x20000000U)
+#define MDIO_USERACCESS0_ACK_SHIFT (0x0000001DU)
+
+
+#define MDIO_USERACCESS0_REGADR (0x03E00000U)
+#define MDIO_USERACCESS0_REGADR_SHIFT (0x00000015U)
+
+#define MDIO_USERACCESS0_PHYADR (0x001F0000U)
+#define MDIO_USERACCESS0_PHYADR_SHIFT (0x00000010U)
+
+#define MDIO_USERACCESS0_DATA (0x0000FFFFU)
+#define MDIO_USERACCESS0_DATA_SHIFT (0x00000000U)
+
+
+/* USERPHYSEL0 */
+
+
+#define MDIO_USERPHYSEL0_LINKSEL (0x00000080U)
+#define MDIO_USERPHYSEL0_LINKSEL_SHIFT (0x00000007U)
+
+#define MDIO_USERPHYSEL0_LINKINTENB (0x00000040U)
+#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT (0x00000006U)
+
+
+#define MDIO_USERPHYSEL0_PHYADRMON (0x0000001FU)
+#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT (0x00000000U)
+
+
+/* USERACCESS1 */
+
+#define MDIO_USERACCESS1_GO (0x80000000U)
+#define MDIO_USERACCESS1_GO_SHIFT (0x0000001FU)
+
+#define MDIO_USERACCESS1_WRITE (0x40000000U)
+#define MDIO_USERACCESS1_WRITE_SHIFT (0x0000001EU)
+
+#define MDIO_USERACCESS1_ACK (0x20000000U)
+#define MDIO_USERACCESS1_ACK_SHIFT (0x0000001DU)
+
+
+#define MDIO_USERACCESS1_REGADR (0x03E00000U)
+#define MDIO_USERACCESS1_REGADR_SHIFT (0x00000015U)
+
+#define MDIO_USERACCESS1_PHYADR (0x001F0000U)
+#define MDIO_USERACCESS1_PHYADR_SHIFT (0x00000010U)
+
+#define MDIO_USERACCESS1_DATA (0x0000FFFFU)
+#define MDIO_USERACCESS1_DATA_SHIFT (0x00000000U)
+
+
+/* USERPHYSEL1 */
+
+
+#define MDIO_USERPHYSEL1_LINKSEL (0x00000080U)
+#define MDIO_USERPHYSEL1_LINKSEL_SHIFT (0x00000007U)
+
+#define MDIO_USERPHYSEL1_LINKINTENB (0x00000040U)
+#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT (0x00000006U)
+
+
+#define MDIO_USERPHYSEL1_PHYADRMON (0x0000001FU)
+#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0x00000000U)
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/hw_reg_access.h
===================================================================
diff -u
--- firmware/include/hw_reg_access.h (revision 0)
+++ firmware/include/hw_reg_access.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,81 @@
+/*
+ * hw_reg_access.h
+ */
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_REG_ACCESS_H_
+#define _HW_REG_ACCESS_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/*******************************************************************************
+*
+* Macros for hardware access, both direct and via the bit-band region.
+*
+*****************************************************************************/
+#define HWREG(x) \
+ (*((volatile uint32 *)(x)))
+#define HWREGH(x) \
+ (*((volatile uint16 *)(x)))
+#define HWREGB(x) \
+ (*((volatile uint8 *)(x)))
+#define HWREGBITW(x, b) \
+ (HWREG(((uint32)(x) & 0xF0000000U) | (uint32)0x02000000U | \
+ (((uint32)(x) & 0x000FFFFFU) << 5U) | (uint32)((uint32)(b) << 2U)))
+#define HWREGBITH(x, b) \
+ (HWREGH(((uint32)(x) & 0xF0000000U) | (uint32)0x02000000U | \
+ (((uint32)(x) & 0x000FFFFFU) << 5U) | (uint32)((uint32)(b) << 2U)))
+#define HWREGBITB(x, b) \
+ (HWREGB(((uint32)(x) & 0xF0000000U) | (uint32)0x02000000U | \
+ (((uint32)(x) & 0x000FFFFFU) << 5U) | (uint32)((uint32)(b) << 2U)))
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HW_TYPES_H__ */
Index: firmware/include/hw_usb.h
===================================================================
diff -u
--- firmware/include/hw_usb.h (revision 0)
+++ firmware/include/hw_usb.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,276 @@
+/******************************************************************************
+ *
+ * hw_usb.h - Macros for use in accessing the USB registers.
+ *
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+/** @brief Base address of memmory mapped Registers */
+#define USBD_0_BASE 0xFCF78A00u
+#define USB0_BASE USBD_0_BASE
+
+typedef volatile struct {
+ uint16 rev; /* Revision */
+
+ /** Endpoint registers ***************************************************/
+ uint16 epnum; /* Endpoint selection */
+ uint16 data; /* Data */
+ uint16 ctrl; /* Control */
+ uint16 stat_flag; /* Status */
+ uint16 rxf_stat; /* RX FIFO Status */
+ uint16 syscon1; /* System configuration 1 */
+ uint16 syscon2; /* System configuration 2 */
+ uint16 dev_stat; /* Device status */
+ uint16 sof; /* Start of frame */
+ uint16 irq_en; /* Interrupt enable */
+ uint16 dma_irqen; /* DMA Interrupt enable */
+ uint16 irqsrc; /* Interrupt source */
+ uint16 epn_stat; /* Non-ISO EP interrupt enable */
+ uint16 dman_stat; /* Non-ISO DMA interrupt enable */
+ uint16 _rsvd1[1]; /* Reserved for reg holes */
+
+ /** DMA Configuration ***************************************************/
+ uint16 rxdma_cfg; /* DMA Rx channels configuration */
+ uint16 txdma_cfg; /* DMA Tx channels configuration */
+ uint16 data_dma; /* DMA FIFO data */
+ uint16 txdma0; /* Transmit DMA control 0 */
+ uint16 txdma1; /* Transmit DMA control 1 */
+ uint16 txdma2; /* Transmit DMA control 2 */
+ uint16 _rsvd2[2]; /* Reserved for reg holes */
+
+ uint16 dman_rxdma0; /* Receive DMA control 0 */
+ uint16 dman_rxdma1; /* Receive DMA control 1 */
+ uint16 dman_rxdma2; /* Receive DMA control 2 */
+ uint16 _rsvd3[5]; /* Reserved */
+
+ /** Endpoint Configuration ***********************************************/
+ uint16 ep0; /* Endpoint 0 Configuration */
+
+ uint16 epn_rx[15]; /* RX EP configurations... */
+ uint16 _rsvd4[1]; /* Reserved for reg holes */
+
+ uint16 epn_tx[15]; /* TX EP configurations... */
+} usbdRegs;
+
+/******************************************************************************\
+* Register Bit Masks
+* (USBD___
+\******************************************************************************/
+
+/* Endpoint selection *********************************************************/
+#define USBD_EP_NUM_SETUP_SEL (0x0040u)
+#define USBD_EP_NUM_EP_SEL (0x0020u)
+#define USBD_EP_NUM_EP_DIR (0x0010u)
+#define USBD_EP_NUM_EP_NUM_MASK (0x000Fu)
+
+/* Data ***********************************************************************/
+#define USBD_DATA_DATA (0xFFFFu)
+
+/* Control ********************************************************************/
+#define USBD_CTRL_CLR_HALT (0x0080u)
+#define USBD_CTRL_SET_HALT (0x0040u)
+#define USBD_CTRL_SET_FIFO_EN (0x0004u)
+#define USBD_CTRL_CLR_EP (0x0002u)
+#define USBD_CTRL_RESET_EP (0x0001u)
+
+/* Status *********************************************************************/
+#define USBD_STAT_FLG_NO_RXPACKET (0x8000u)
+#define USBD_STAT_FLG_MISS_IN (0x4000u)
+#define USBD_STAT_FLG_DATA_FLUSH (0x2000u)
+#define USBD_STAT_FLG_ISO_ERR (0x1000u)
+#define USBD_STAT_FLG_ISO_FIFO_EMPTY (0x0200u)
+#define USBD_STAT_FLG_ISO_FIFO_FULL (0x0100u)
+#define USBD_STAT_FLG_EP_HALTED (0x0040u)
+#define USBD_STAT_FLG_STALL (0x0020u)
+#define USBD_STAT_FLG_NAK (0x0010u)
+#define USBD_STAT_FLG_ACK (0x0008u)
+#define USBD_STAT_FLG_FIFO_EN (0x0004u)
+#define USBD_STAT_FLG_NON_ISO_FIFO_EMPTY (0x0002u)
+#define USBD_STAT_FLG_NON_ISO_FIFO_FULL (0x0001u)
+
+/* RX FIFO Status */
+#define USBD_RXFSTAT_RXF_COUNT (0x03FFu)
+
+/* System configuration 1 *****************************************************/
+#define USBD_SYSCON1_CFG_LOCK (0x0100u)
+#define USBD_SYSCON1_DATA_ENDIAN (0x0080u)
+#define USBD_SYSCON1_DMA_ENDIAN (0x0040u)
+#define USBD_SYSCON1_NAK_EN (0x0010u)
+#define USBD_SYSCON1_AUTODEC_DIS (0x0008u)
+#define USBD_SYSCON1_SELF_PWR (0x0004u)
+#define USBD_SYSCON1_SOFF_DIS (0x0002u)
+#define USBD_SYSCON1_PULLUP_EN (0x0001u)
+
+/* System configuration 2 *****************************************************/
+#define USBD_SYSCON2_RMT_WKP (0x0040u)
+#define USBD_SYSCON2_STALL_CMD (0x0020u)
+#define USBD_SYSCON2_DEV_CFG (0x0008u)
+#define USBD_SYSCON2_CLR_CFG (0x0004u)
+
+/* Device status **************************************************************/
+#define USBD_DEVSTAT_B_HNP_ENABLE (0x0200u)
+#define USBD_DEVSTAT_A_HNP_SUPPORT (0x0100u)
+#define USBD_DEVSTAT_A_ALT_HNP_SUPPORT (0x0080u)
+#define USBD_DEVSTAT_R_WK_OK (0x0040u)
+#define USBD_DEVSTAT_USB_RESET (0x0020u)
+#define USBD_DEVSTAT_SUS (0x0010u)
+#define USBD_DEVSTAT_CFG (0x0008u)
+#define USBD_DEVSTAT_ADD (0x0004u)
+#define USBD_DEVSTAT_DEF (0x0002u)
+#define USBD_DEVSTAT_ATT (0x0001u)
+
+
+/* Start of frame *************************************************************/
+#define USBD_SOF_FT_LOCK (0x1000u)
+#define USBD_SOF_TS_OK (0x0800u)
+#define USBD_SOF_TS (0x07FFu)
+
+/* Interrupt enable ***********************************************************/
+#define USBD_IRQ_EN_SOF_IE (0x0080u)
+#define USBD_IRQ_EN_EPN_RX_IE (0x0020u)
+#define USBD_IRQ_EN_EPN_TX_IE (0x0010u)
+#define USBD_IRQ_EN_DS_CHG_IE (0x0008u)
+#define USBD_IRQ_EN_EP0_IE (0x0001u)
+
+/* DMA Interrupt enable *******************************************************/
+#define USBD_DMA_IRQ_EN_TX2_DONE_IE (0x0400u)
+#define USBD_DMA_IRQ_EN_RX2_CNT_IE (0x0200u)
+#define USBD_DMA_IRQ_EN_RX2_EOT_IE (0x0100u)
+#define USBD_DMA_IRQ_EN_TX1_DONE_IE (0x0040u)
+#define USBD_DMA_IRQ_EN_RX1_CNT_IE (0x0020u)
+#define USBD_DMA_IRQ_EN_RX1_EOT_IE (0x0010u)
+#define USBD_DMA_IRQ_EN_TX0_DONE_IE (0x0004u)
+#define USBD_DMA_IRQ_EN_RX0_CNT_IE (0x0002u)
+#define USBD_DMA_IRQ_EN_RX0_EOT_IE (0x0001u)
+
+/* Interrupt source ***********************************************************/
+#define USBD_IRQ_SRC_TXN_DONE (0x0400u)
+#define USBD_IRQ_SRC_RXN_CNT (0x0200u)
+#define USBD_IRQ_SRC_RXN_EOT (0x0100u)
+#define USBD_IRQ_SRC_SOF (0x0080u)
+#define USBD_IRQ_SRC_EPN_RX (0x0020u)
+#define USBD_IRQ_SRC_EPN_TX (0x0010u)
+#define USBD_IRQ_SRC_DS_CHG (0x0008u)
+#define USBD_IRQ_SRC_SETUP (0x0004u)
+#define USBD_IRQ_SRC_EP0_RX (0x0002u)
+#define USBD_IRQ_SRC_EP0_TX (0x0001u)
+
+/* Non-ISO endpoint interrupt enable ******************************************/
+#define USBD_EPN_STAT_RX_IT_SRC (0x0F00u)
+#define USBD_EPN_STAT_TX_IT_SRC (0x000Fu)
+
+/* Non-ISO DMA interrupt enable ***********************************************/
+#define USBD_DMAN_STAT_RX_SB (0x1000u)
+#define USBD_DMAN_STAT_RX_IT_SRC (0x0F00u)
+#define USBD_DMAN_STAT_TX_IT_SRC (0x000Fu)
+
+/* DMA Receive channels configuration *****************************************/
+#define USBD_RXDMA_CFG_RX_REQ (0x1000u)
+#define USBD_RXDMA_CFG_RXDMA2_EP (0x0F00u)
+#define USBD_RXDMA_CFG_RXDMA1_EP (0x00F0u)
+#define USBD_RXDMA_CFG_RXDMA0_EP (0x000Fu)
+
+/* DMA Transmit channels configuration ****************************************/
+#define USBD_TXDMA_CFG_TX_REQ (0x1000u)
+#define USBD_TXDMA_CFG_TXDMA2_EP (0x0F00u)
+#define USBD_TXDMA_CFG_TXDMA1_EP (0x00F0u)
+#define USBD_TXDMA_CFG_TXDMA0_EP (0x000Fu)
+
+/* DMA FIFO data **************************************************************/
+#define USBD_DATA_DMA_DATA_DMA (0xFFFFu)
+
+/* Transmit DMA control 0 *****************************************************/
+#define USBD_TXDMA0_TX0_EOT (0x8000u)
+#define USBD_TXDMA0_TX0_START (0x4000u)
+#define USBD_TXDMA0_TX0_TSC (0x03FFu)
+
+/* Transmit DMA control 1 *****************************************************/
+#define USBD_TXDMA1_TX1_EOT (0x8000u)
+#define USBD_TXDMA1_TX1_START (0x4000u)
+#define USBD_TXDMA1_TX1_TSC (0x03FFu)
+#define USBD_TXDMA1_TX1_TSC_SHIFT (0x0000u)
+
+/* Transmit DMA control 2 *****************************************************/
+#define USBD_TXDMA2_TX2_EOT (0x8000u)
+#define USBD_TXDMA2_TX2_START (0x4000u)
+#define USBD_TXDMA2_TX2_TSC (0x03FFu)
+
+/* Receive DMA control 0 ******************************************************/
+#define USBD_RXDMA0_RX0_STOP (0x8000u)
+#define USBD_RXDMA0_RX0_TC (0x00FFu)
+
+/* Receive DMA control 1 ******************************************************/
+#define USBD_RXDMA1_RX10_STOP (0x8000u)
+#define USBD_RXDMA1_RX1_TC (0x00FFu)
+
+/* Receive DMA control 2 ******************************************************/
+#define USBD_RXDMA2_RX2_STOP (0x8000u)
+#define USBD_RXDMA2_RX2_TC (0x00FFu)
+
+/* Endpoint 0 Configuration ***************************************************/
+#define USBD_EP0_SIZE (0x3000u)
+#define USBD_EP0_PTR (0x07FFu)
+
+/* Receive endpoint configurations... *****************************************/
+#define USBD_RX_EP_VALID (0x8000u)
+#define USBD_RX_EP_SIZEDB (0x4000u)
+#define USBD_RX_EP_SIZE (0x3000u)
+#define USBD_RX_EP_ISO (0x0800u)
+#define USBD_RX_EP_PTR (0x07FFu)
+
+/* Transmit endpoint configurations... ****************************************/
+#define USBD_TX_EP_VALID (0x8000u)
+#define USBD_TX_EP_SIZEDB (0x4000u)
+#define USBD_TX_EP_SIZE (0x3000u)
+#define USBD_TX_EP_ISO (0x0800u)
+#define USBD_TX_EP_PTR (0x07FFu)
+
+#define USBD_MAX_EP0_PTR (0xFFu)
+#define USBD_EP_RX_MAX (15u)
+#define USBD_EP_TX_MAX (15u)
+
+/** @brief Macro for setting a bit/s in a register (read, modify & write) */
+#define USBD_REG_BIT_SET(reg,bit) reg |= ((uint16)(bit))
+/** @brief Macro for clearing a bit/s in a register (read, modify & write) */
+#define USBD_REG_BIT_CLR(reg,bit) reg &= ((uint16)~((uint16)bit))
+/** @brief Macro for setting a bit/s in a register (write) */
+#define USBD_REG_SET_ONE(reg,value) reg = ((uint16)value)
+
+#endif /* __HW_USB_H__ */
Index: firmware/include/i2c.h
===================================================================
diff -u
--- firmware/include/i2c.h (revision 0)
+++ firmware/include/i2c.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,266 @@
+/** @file I2C.h
+* @brief I2C Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "reg_i2c.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @enum i2cMode
+* @brief Alias names for i2c modes
+* This enumeration is used to provide alias names for I2C modes:
+*/
+
+enum i2cMode
+{
+ I2C_FD_FORMAT = 0x0008U, /* Free Data Format */
+ I2C_START_BYTE = 0x0010U,
+ I2C_RESET_OUT = 0x0020U, I2C_RESET_IN = 0x0000U,
+ I2C_DLOOPBACK = 0x0040U,
+ I2C_REPEATMODE = 0x0080U, /* In Master Mode only */
+ I2C_10BIT_AMODE = 0x0100U, I2C_7BIT_AMODE = 0x0000U,
+ I2C_TRANSMITTER = 0x0200U, I2C_RECEIVER = 0x0000U,
+ I2C_MASTER = 0x0400U, I2C_SLAVE = 0x0000U,
+ I2C_STOP_COND = 0x0800U, /* In Master Mode only */
+ I2C_START_COND = 0x2000U, /* In Master Mode only */
+ I2C_FREE_RUN = 0x4000U,
+ I2C_NACK_MODE = 0x8000U
+};
+
+
+/** @enum i2cBitCount
+* @brief Alias names for i2c bit count
+* This enumeration is used to provide alias names for I2C bit count:
+*/
+
+enum i2cBitCount
+{
+ I2C_2_BIT = 0x2U,
+ I2C_3_BIT = 0x3U,
+ I2C_4_BIT = 0x4U,
+ I2C_5_BIT = 0x5U,
+ I2C_6_BIT = 0x6U,
+ I2C_7_BIT = 0x7U,
+ I2C_8_BIT = 0x0U
+};
+
+
+
+/** @enum i2cIntFlags
+* @brief Interrupt Flag Definitions
+*
+* Used with I2CEnableNotification, I2CDisableNotification
+*/
+enum i2cIntFlags
+{
+ I2C_AL_INT = 0x0001U, /* arbitration lost */
+ I2C_NACK_INT = 0x0002U, /* no acknowledgment */
+ I2C_ARDY_INT = 0x0004U, /* access ready */
+ I2C_RX_INT = 0x0008U, /* receive data ready */
+ I2C_TX_INT = 0x0010U, /* transmit data ready */
+ I2C_SCD_INT = 0x0020U, /* stop condition detect */
+ I2C_AAS_INT = 0x0040U /* address as slave */
+};
+
+
+/** @enum i2cStatFlags
+* @brief Interrupt Status Definitions
+*
+*/
+enum i2cStatFlags
+{
+ I2C_AL = 0x0001U, /* arbitration lost */
+ I2C_NACK = 0x0002U, /* no acknowledgement */
+ I2C_ARDY = 0x0004U, /* access ready */
+ I2C_RX = 0x0008U, /* receive data ready */
+ I2C_TX = 0x0010U, /* transmit data ready */
+ I2C_SCD = 0x0020U, /* stop condition detect */
+ I2C_AD0 = 0x0100U, /* address Zero Status */
+ I2C_AAS = 0x0200U, /* address as slave */
+ I2C_XSMT = 0x0400U, /* Transmit shift empty not */
+ I2C_RXFULL = 0x0800U, /* receive full */
+ I2C_BUSBUSY = 0x1000U, /* bus busy */
+ I2C_NACKSNT = 0x2000U, /* No Ack Sent */
+ I2C_SDIR = 0x4000U /* Slave Direction */
+};
+
+
+/** @enum i2cDMA
+* @brief I2C DMA definitions
+*
+* Used before i2c transfer
+*/
+enum i2cDMA
+{
+ I2C_TXDMA = 0x20U,
+ I2C_RXDMA = 0x10U
+};
+
+/* Configuration registers */
+typedef struct i2c_config_reg
+{
+ uint32 CONFIG_OAR;
+ uint32 CONFIG_IMR;
+ uint32 CONFIG_CLKL;
+ uint32 CONFIG_CLKH;
+ uint32 CONFIG_CNT;
+ uint32 CONFIG_SAR;
+ uint32 CONFIG_MDR;
+ uint32 CONFIG_EMDR;
+ uint32 CONFIG_PSC;
+ uint32 CONFIG_DMAC;
+ uint32 CONFIG_FUN;
+ uint32 CONFIG_DIR;
+ uint32 CONFIG_ODR;
+ uint32 CONFIG_PD;
+ uint32 CONFIG_PSL;
+} i2c_config_reg_t;
+
+
+/* Configuration registers initial value for I2C*/
+#define I2C_OAR_CONFIGVALUE 0x00000000U
+#define I2C_IMR_CONFIGVALUE (((uint32)0U << 6U) \
+ | ((uint32)0U << 5U) \
+ | ((uint32)0U << 4U) \
+ | ((uint32)0U << 3U) \
+ | ((uint32)0U << 2U) \
+ | ((uint32)0U << 1U) \
+ | ((uint32)0U))
+
+#define I2C_CLKL_CONFIGVALUE 35U
+#define I2C_CLKH_CONFIGVALUE 35U
+#define I2C_CNT_CONFIGVALUE 8U
+#define I2C_SAR_CONFIGVALUE 0x000003FFU
+#define I2C_MDR_CONFIGVALUE ((uint32)0x00000000U \
+ | (uint32)((uint32)1U <<11U) \
+ | (uint32)((uint32)1U <<10U) \
+ | (uint32)((uint32)I2C_TRANSMITTER) \
+ | (uint32)((uint32)I2C_7BIT_AMODE) \
+ | (uint32)((uint32)1U << 7U) \
+ | (uint32)((uint32)0U) \
+ | (uint32)((uint32)I2C_8_BIT) \
+ | (uint32)I2C_RESET_OUT)
+
+#define I2C_EMDR_CONFIGVALUE 0U
+#define I2C_PSC_CONFIGVALUE 12U
+#define I2C_DMAC_CONFIGVALUE 0x00000000U
+#define I2C_FUN_CONFIGVALUE 0U
+#define I2C_DIR_CONFIGVALUE ((uint32)((uint32)0U << 1U) \
+ | (uint32)((uint32)0U))
+#define I2C_ODR_CONFIGVALUE ((uint32)((uint32)1U << 1U) \
+ | (uint32)((uint32)1U))
+#define I2C_PD_CONFIGVALUE ((uint32)((uint32)0U << 1U) \
+ | (uint32)((uint32)0U))
+#define I2C_PSL_CONFIGVALUE ((uint32)((uint32)1U << 1U) \
+ | (uint32)((uint32)1U))
+
+
+/**
+ * @defgroup I2C I2C
+ * @brief Inter-Integrated Circuit Module.
+ *
+ * The I2C is a multi-master communication module providing an interface between the Texas Instruments (TI) microcontroller
+ * and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2Cbus.
+ * This module will support any slave or master I2C compatible device.
+ *
+ * Related Files
+ * - reg_i2c.h
+ * - i2c.h
+ * - i2c.c
+ * @addtogroup I2C
+ * @{
+ */
+
+/* I2C Interface Functions */
+void i2cInit(void);
+void i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd);
+void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd);
+void i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud);
+uint32 i2cIsTxReady(i2cBASE_t *i2c);
+void i2cSendByte(i2cBASE_t *i2c, uint8 byte);
+void i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data);
+uint32 i2cIsRxReady(i2cBASE_t *i2c);
+uint32 i2cIsStopDetected(i2cBASE_t *i2c);
+void i2cClearSCD(i2cBASE_t *i2c);
+uint32 i2cRxError(i2cBASE_t *i2c);
+uint8 i2cReceiveByte(i2cBASE_t *i2c);
+void i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data);
+void i2cEnableNotification(i2cBASE_t *i2c, uint32 flags);
+void i2cDisableNotification(i2cBASE_t *i2c, uint32 flags);
+void i2cSetStart(i2cBASE_t *i2c);
+void i2cSetStop(i2cBASE_t *i2c);
+void i2cSetCount(i2cBASE_t *i2c ,uint32 cnt);
+void i2cEnableLoopback(i2cBASE_t *i2c);
+void i2cDisableLoopback(i2cBASE_t *i2c);
+void i2cSetMode(i2cBASE_t *i2c, uint32 mode);
+void i2cGetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type);
+void i2cSetDirection(i2cBASE_t *i2c, uint32 dir);
+bool i2cIsMasterReady(i2cBASE_t *i2c);
+bool i2cIsBusBusy(i2cBASE_t *i2c);
+
+/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags)
+* @brief Interrupt callback
+* @param[in] i2c - I2C module base address
+* @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called apon
+* an interrupt. The parameter passed to the callback is a copy of the
+* interrupt flag register.
+*/
+void i2cNotification(i2cBASE_t *i2c, uint32 flags);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
Index: firmware/include/lin.h
===================================================================
diff -u
--- firmware/include/lin.h (revision 0)
+++ firmware/include/lin.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,333 @@
+/** @file lin.h
+* @brief LIN Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __LIN_H__
+#define __LIN_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "reg_lin.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @def LIN_BREAK_INT
+* @brief Alias for break detect interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_BREAK_INT 0x00000001U
+
+
+/** @def LIN_WAKEUP_INT
+* @brief Alias for wakeup interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_WAKEUP_INT 0x00000002U
+
+
+/** @def LIN_TO_INT
+* @brief Alias for time out interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TO_INT 0x00000010U
+
+
+/** @def LIN_TOAWUS_INT
+* @brief Alias for time out after wakeup signal interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TOAWUS_INT 0x00000040U
+
+
+/** @def LIN_TOA3WUS_INT
+* @brief Alias for time out after 3 wakeup signals interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_TOA3WUS_INT 0x00000080U
+
+
+/** @def LIN_TX_READY
+* @brief Alias for transmit buffer ready flag
+*
+* Used with linIsTxReady.
+*/
+#define LIN_TX_READY 0x00000100U
+
+
+/** @def LIN_RX_INT
+* @brief Alias for receive buffer ready interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_RX_INT 0x00000200U
+
+
+/** @def LIN_ID_INT
+* @brief Alias for received matching identifier interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_ID_INT 0x00002000U
+
+
+/** @def LIN_PE_INT
+* @brief Alias for parity error interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_PE_INT 0x01000000U
+
+
+/** @def LIN_OE_INT
+* @brief Alias for overrun error interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_OE_INT 0x02000000U
+
+
+/** @def LIN_FE_INT
+* @brief Alias for framing error interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_FE_INT 0x04000000U
+
+
+/** @def LIN_NRE_INT
+* @brief Alias for no response error interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_NRE_INT 0x08000000U
+
+
+/** @def LIN_ISFE_INT
+* @brief Alias for inconsistent sync field error interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_ISFE_INT 0x10000000U
+
+
+/** @def LIN_CE_INT
+* @brief Alias for checksum error interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_CE_INT 0x20000000U
+
+
+/** @def LIN_PBE_INT
+* @brief Alias for physical bus error interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_PBE_INT 0x40000000U
+
+
+/** @def LIN_BE_INT
+* @brief Alias for bit error interrupt flag
+*
+* Used with linEnableNotification, linDisableNotification.
+*/
+#define LIN_BE_INT 0x80000000U
+
+
+/** @struct linBase
+* @brief LIN Register Definition
+*
+* This structure is used to access the LIN module registers.
+*/
+/** @typedef linBASE_t
+* @brief LIN Register Frame Type Definition
+*
+* This type is used to access the LIN Registers.
+*/
+
+enum linPinSelect
+{
+ PIN_LIN_TX = 4U,
+ PIN_LIN_RX = 2U
+};
+
+/* Configuration registers */
+typedef struct lin_config_reg
+{
+ uint32 CONFIG_GCR0;
+ uint32 CONFIG_GCR1;
+ uint32 CONFIG_GCR2;
+ uint32 CONFIG_SETINT;
+ uint32 CONFIG_SETINTLVL;
+ uint32 CONFIG_FORMAT;
+ uint32 CONFIG_BRSR;
+ uint32 CONFIG_FUN;
+ uint32 CONFIG_DIR;
+ uint32 CONFIG_ODR;
+ uint32 CONFIG_PD;
+ uint32 CONFIG_PSL;
+ uint32 CONFIG_COMP;
+ uint32 CONFIG_MASK;
+ uint32 CONFIG_MBRSR;
+} lin_config_reg_t;
+
+/* Configuration registers initial value for LIN*/
+#define LIN_GCR0_CONFIGVALUE 0x00000001U
+#define LIN_GCR1_CONFIGVALUE (0x03000CC0U \
+ | (uint32)((uint32)0U << 12U) \
+ | (uint32)((uint32)0U << 2U)\
+ | (uint32)((uint32)0U << 5U))
+#define LIN_GCR2_CONFIGVALUE 0x00000000U
+#define LIN_SETINTLVL_CONFIGVALUE (0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U)
+
+#define LIN_SETINT_CONFIGVALUE (0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U)
+
+#define LIN_FORMAT_CONFIGVALUE ((uint32)((uint32)(8U - 1U) << 16U))
+#define LIN_BRSR_CONFIGVALUE (324U)
+#define LIN_COMP_CONFIGVALUE ((uint32)((uint32)(1U - 1U) << 8U) | (13U - 13U))
+#define LIN_MASK_CONFIGVALUE ((uint32)((uint32)0x00U << 16U) | 0x00U)
+#define LIN_MBRSR_CONFIGVALUE (4680U)
+#define LIN_FUN_CONFIGVALUE (4U | 2U | 0U)
+#define LIN_DIR_CONFIGVALUE (0U | 0U | 0U)
+#define LIN_ODR_CONFIGVALUE (0U | 0U | 0U)
+#define LIN_PD_CONFIGVALUE (0U | 0U | 0U)
+#define LIN_PSL_CONFIGVALUE (0U | 0U | 1U)
+
+/**
+ * @defgroup LIN LIN
+ * @brief Local Interconnect Network Module.
+ *
+ * The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
+ * single-master/multiple-slave with a message identification for multi-cast transmission between any network
+ * nodes.
+ *
+ * Related Files
+ * - reg_lin.h
+ * - lin.h
+ * - lin.c
+ * @addtogroup LIN
+ * @{
+ */
+
+/* LIN Interface Functions */
+void linInit(void);
+void linSetFunctional(linBASE_t *lin, uint32 port);
+void linSendHeader(linBASE_t *lin, uint8 identifier);
+void linSendWakupSignal(linBASE_t *lin);
+void linEnterSleep(linBASE_t *lin);
+void linSoftwareReset(linBASE_t *lin);
+uint32 linIsTxReady(linBASE_t *lin);
+void linSetLength(linBASE_t *lin, uint32 length);
+void linSend(linBASE_t *lin, uint8 * data);
+uint32 linIsRxReady(linBASE_t *lin);
+uint32 linTxRxError(linBASE_t *lin);
+uint32 linGetIdentifier(linBASE_t *lin);
+void linGetData(linBASE_t *lin, uint8 * const data);
+void linEnableNotification(linBASE_t *lin, uint32 flags);
+void linDisableNotification(linBASE_t *lin, uint32 flags);
+void linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype);
+void linDisableLoopback(linBASE_t *lin);
+void linGetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type);
+uint32 linGetStatusFlag(linBASE_t *lin);
+void linClearStatusFlag(linBASE_t *lin, uint32 flags);
+
+/** @fn void linNotification(linBASE_t *lin, uint32 flags)
+* @brief Interrupt callback
+* @param[in] lin - lin module base address
+* @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt. The parameter passed to the callback is a copy of the
+* interrupt flag register.
+*/
+void linNotification(linBASE_t *lin, uint32 flags);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/mdio.h
===================================================================
diff -u
--- firmware/include/mdio.h (revision 0)
+++ firmware/include/mdio.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,92 @@
+/**
+ * \file mdio.h
+ *
+ * \brief MDIO APIs and macros.
+ *
+ * This file contains the driver API prototypes and macro definitions.
+ */
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __MDIO_H__
+#define __MDIO_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+#include "system.h"
+#include "hw_mdio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* MDIO input and output frequencies in Hz */
+#define MDIO_FREQ_INPUT ((uint32)(VCLK3_FREQ * 1000000.00F))
+#define MDIO_FREQ_OUTPUT 1000000U
+/*****************************************************************************/
+
+/**
+ * @addtogroup EMACMDIO
+ * @{
+ */
+/*
+** Prototypes for the APIs
+*/
+extern uint32 MDIOPhyAliveStatusGet(uint32 baseAddr);
+extern uint32 MDIOPhyLinkStatusGet(uint32 baseAddr);
+extern void MDIOInit(uint32 baseAddr, uint32 mdioInputFreq,
+ uint32 mdioOutputFreq);
+extern boolean MDIOPhyRegRead(uint32 baseAddr, uint32 phyAddr,
+ uint32 regNum, volatile uint16 * dataPtr);
+extern void MDIOPhyRegWrite(uint32 baseAddr, uint32 phyAddr,
+ uint32 regNum, uint16 RegVal);
+extern void MDIOEnable(uint32 baseAddr);
+extern void MDIODisable(uint32 baseAddr);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+#endif /* __MDIO_H__ */
Index: firmware/include/mibspi.h
===================================================================
diff -u
--- firmware/include/mibspi.h (revision 0)
+++ firmware/include/mibspi.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,349 @@
+/** @file mibspi.h
+* @brief MIBSPI Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __MIBSPI_H__
+#define __MIBSPI_H__
+
+#include "reg_mibspi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @enum triggerEvent
+* @brief Transfer Group Trigger Event
+*/
+enum triggerEvent
+{
+ TRG_NEVER = 0U,
+ TRG_RISING = 1U,
+ TRG_FALLING = 2U,
+ TRG_BOTH = 3U,
+ TRG_HIGH = 5U,
+ TRG_LOW = 6U,
+ TRG_ALWAYS = 7U
+};
+
+/** @enum triggerSource
+* @brief Transfer Group Trigger Source
+*/
+enum triggerSource
+{
+ TRG_DISABLED,
+ TRG_GIOA0,
+ TRG_GIOA1,
+ TRG_GIOA2,
+ TRG_GIOA3,
+ TRG_GIOA4,
+ TRG_GIOA5,
+ TRG_GIOA6,
+ TRG_GIOA7,
+ TRG_HET1_8,
+ TRG_HET1_10,
+ TRG_HET1_12,
+ TRG_HET1_14,
+ TRG_HET1_16,
+ TRG_HET1_18,
+ TRG_TICK
+};
+
+
+/** @enum mibspiPinSelect
+* @brief mibspi Pin Select
+*/
+enum mibspiPinSelect
+{
+ PIN_CS0 = 0U,
+ PIN_CS1 = 1U,
+ PIN_CS2 = 2U,
+ PIN_CS3 = 3U,
+ PIN_CS4 = 4U,
+ PIN_CS5 = 5U,
+ PIN_CS6 = 6U,
+ PIN_CS7 = 7U,
+ PIN_ENA = 8U,
+ PIN_CLK = 9U,
+ PIN_SIMO = 10U,
+ PIN_SOMI = 11U,
+ PIN_SIMO_1 = 17U,
+ PIN_SIMO_2 = 18U,
+ PIN_SIMO_3 = 19U,
+ PIN_SIMO_4 = 20U,
+ PIN_SIMO_5 = 21U,
+ PIN_SIMO_6 = 22U,
+ PIN_SIMO_7 = 23U,
+ PIN_SOMI_1 = 25U,
+ PIN_SOMI_2 = 26U,
+ PIN_SOMI_3 = 27U,
+ PIN_SOMI_4 = 28U,
+ PIN_SOMI_5 = 29U,
+ PIN_SOMI_6 = 30U,
+ PIN_SOMI_7 = 31U
+};
+
+
+/** @enum chipSelect
+* @brief Transfer Group Chip Select
+*/
+enum chipSelect
+{
+ CS_NONE = 0xFFU,
+ CS_0 = 0xFEU,
+ CS_1 = 0xFDU,
+ CS_2 = 0xFBU,
+ CS_3 = 0xF7U,
+ CS_4 = 0xEFU,
+ CS_5 = 0xDFU,
+ CS_6 = 0xBFU,
+ CS_7 = 0x7FU
+};
+
+/** @typedef mibspiPmode_t
+* @brief Mibspi Parellel mode Type Definition
+*
+* This type is used to represent Mibspi Parellel mode.
+*/
+typedef enum mibspiPmode
+{
+ PMODE_NORMAL = 0x0U,
+ PMODE_2_DATALINE = 0x1U,
+ PMODE_4_DATALINE = 0x2U,
+ PMODE_8_DATALINE = 0x3U
+}mibspiPmode_t;
+
+/** @typedef mibspiDFMT_t
+* @brief Mibspi Data format selection Type Definition
+*
+* This type is used to represent Mibspi Data format selection.
+*/
+typedef enum mibspiDFMT
+{
+ DATA_FORMAT0 = 0x0U,
+ DATA_FORMAT1 = 0x1U,
+ DATA_FORMAT2 = 0x2U,
+ DATA_FORMAT3 = 0x3U
+}mibspiDFMT_t;
+
+typedef struct mibspi_config_reg
+{
+ uint32 CONFIG_GCR1;
+ uint32 CONFIG_INT0;
+ uint32 CONFIG_LVL;
+ uint32 CONFIG_PCFUN;
+ uint32 CONFIG_PCDIR;
+ uint32 CONFIG_PCPDR;
+ uint32 CONFIG_PCDIS;
+ uint32 CONFIG_PCPSL;
+ uint32 CONFIG_DELAY;
+ uint32 CONFIG_FMT0;
+ uint32 CONFIG_FMT1;
+ uint32 CONFIG_FMT2;
+ uint32 CONFIG_FMT3;
+ uint32 CONFIG_MIBSPIE;
+ uint32 CONFIG_LTGPEND;
+ uint32 CONFIG_TGCTRL[8U];
+ uint32 CONFIG_UERRCTRL;
+}mibspi_config_reg_t;
+
+#define MIBSPI1_GCR1_CONFIGVALUE (0x01000000U | (uint32)((uint32)1U << 1U) | 1U)
+#define MIBSPI1_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+#define MIBSPI1_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI1_PCFUN_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U))
+#define MIBSPI1_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
+#define MIBSPI1_PCPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
+#define MIBSPI1_PCDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
+#define MIBSPI1_PCPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U))
+
+#define MIBSPI1_DELAY_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI1_FMT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI1_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI1_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI1_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+
+#define MIBSPI1_MIBSPIE_CONFIGVALUE 1U
+#define MIBSPI1_LTGPEND_CONFIGVALUE ((uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U))
+
+#define MIBSPI1_TGCTRL0_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)0U << 8U)))
+#define MIBSPI1_TGCTRL1_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)8U << 8U)))
+#define MIBSPI1_TGCTRL2_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U) << 8U)))
+#define MIBSPI1_TGCTRL3_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U) << 8U)))
+#define MIBSPI1_TGCTRL4_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U) << 8U)))
+#define MIBSPI1_TGCTRL5_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI1_TGCTRL6_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI1_TGCTRL7_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U)))
+
+#define MIBSPI1_UERRCTRL_CONFIGVALUE (0x00000005U)
+
+
+#define MIBSPI3_GCR1_CONFIGVALUE (0x01000000U | (uint32)((uint32)1U << 1U) | 1U)
+#define MIBSPI3_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 0U))
+#define MIBSPI3_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI3_PCFUN_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
+#define MIBSPI3_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
+
+#define MIBSPI3_DELAY_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI3_FMT0_CONFIGVALUE ((uint32)((uint32)20U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)8U << 0U))
+#define MIBSPI3_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI3_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI3_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+
+#define MIBSPI3_MIBSPIE_CONFIGVALUE 1U
+#define MIBSPI3_LTGPEND_CONFIGVALUE ((uint32)((uint32)((11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U))
+
+#define MIBSPI3_TGCTRL0_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)0U << 8U)))
+#define MIBSPI3_TGCTRL1_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)11U << 8U)))
+#define MIBSPI3_TGCTRL2_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U) << 8U)))
+#define MIBSPI3_TGCTRL3_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL4_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL5_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL6_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL7_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U)))
+
+#define MIBSPI3_UERRCTRL_CONFIGVALUE (0x00000005U)
+
+#define MIBSPI5_GCR1_CONFIGVALUE (0x01000000U | (uint32)((uint32)1U << 1U) | 1U)
+#define MIBSPI5_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+#define MIBSPI5_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI5_PCFUN_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U))
+#define MIBSPI5_PCDIR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
+#define MIBSPI5_PCPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
+#define MIBSPI5_PCDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
+#define MIBSPI5_PCPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U))
+
+#define MIBSPI5_DELAY_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI5_FMT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI5_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI5_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI5_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U))
+
+#define MIBSPI5_MIBSPIE_CONFIGVALUE 1U
+#define MIBSPI5_LTGPEND_CONFIGVALUE ((uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U))
+
+#define MIBSPI5_TGCTRL0_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)0U << 8U)))
+#define MIBSPI5_TGCTRL1_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)8U << 8U)))
+#define MIBSPI5_TGCTRL2_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U) << 8U)))
+#define MIBSPI5_TGCTRL3_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U) << 8U)))
+#define MIBSPI5_TGCTRL4_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U) << 8U)))
+#define MIBSPI5_TGCTRL5_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI5_TGCTRL6_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI5_TGCTRL7_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U)))
+
+#define MIBSPI5_UERRCTRL_CONFIGVALUE (0x00000005U)
+
+/**
+ * @defgroup MIBSPI MIBSPI
+ * @brief Multi-Buffered Serial Peripheral Interface Module.
+ *
+ * The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a serial bit stream of
+ * programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
+ * The MibSPI has a programmable buffer memory that enables programmed transmission to be completed
+ * without CPU intervention
+ *
+ * Related Files
+ * - reg_mibspi.h
+ * - mibspi.h
+ * - mibspi.c
+ * @addtogroup MIBSPI
+ * @{
+ */
+
+/* MIBSPI Interface Functions */
+void mibspiInit(void);
+void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port);
+void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data);
+uint32 mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data);
+void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group);
+boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group);
+void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 level);
+void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group);
+void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype);
+void mibspiDisableLoopback(mibspiBASE_t *mibspi);
+void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT);
+void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type);
+void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type);
+void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
+* @brief Error interrupt callback
+* @param[in] mibspi - mibSpi module base address
+* @param[in] flags - Copy of error interrupt flags
+*
+* This is a error callback that is provided by the application and is call upon
+* an error interrupt. The paramer passed to the callback is a copy of the error
+* interrupt flag register.
+*/
+void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags);
+
+
+/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group)
+* @brief Transfer complete notification callback
+* @param[in] mibspi - mibSpi module base address
+* @param[in] group - Transfer group
+*
+* This is a callback function provided by the application. It is call when
+* a transfer is complete. The parameter is the transfer group that triggered
+* the interrupt.
+*/
+void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/phy_dp83640.h
===================================================================
diff -u
--- firmware/include/phy_dp83640.h (revision 0)
+++ firmware/include/phy_dp83640.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,132 @@
+/*
+ * DP83640.h
+ */
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _PHY_DP83640_H_
+#define _PHY_DP83640_H_
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @enum PHY_timestamp
+* @brief Alias names for transmit and receive timestamps
+* This enumeration is used to provide alias names for getting the transmit and receive timestamps from the Dp83640GetTimeStamp API.
+*/
+typedef enum phyTimeStamp
+{
+ Txtimestamp = 1, /*Transmit Timestamp*/
+ Rxtimestamp = 2 /*Receive Timestamp */
+}phyTimeStamp_t;
+/* PHY register offset definitions */
+#define PHY_BCR (0u)
+#define PHY_BSR (1u)
+#define PHY_ID1 (2u)
+#define PHY_ID2 (3u)
+#define PHY_AUTONEG_ADV (4u)
+#define PHY_LINK_PARTNER_ABLTY (5u)
+#define PHY_LINK_PARTNER_SPD (16u)
+#define PHY_TXTS (28u)
+#define PHY_RXTS (29u)
+
+/* PHY status definitions */
+#define PHY_ID_SHIFT (16u)
+#define PHY_SOFTRESET (0x8000U)
+#define PHY_AUTONEG_ENABLE (0x1000u)
+#define PHY_AUTONEG_RESTART (0x0200u)
+#define PHY_AUTONEG_COMPLETE (0x0020u)
+#define PHY_AUTONEG_INCOMPLETE (0x0000u)
+#define PHY_AUTONEG_STATUS (0x0020u)
+#define PHY_AUTONEG_ABLE (0x0008u)
+#define PHY_LPBK_ENABLE (0x4000u)
+#define PHY_LINK_STATUS (0x0004u)
+#define PHY_INVALID_TYPE (0x0u)
+
+
+/* PHY ID. The LSB nibble will vary between different phy revisions */
+#define DP83640_PHY_ID (0x0007C0F0u)
+#define DP83640_PHY_ID_REV_MASK (0x0000000Fu)
+
+/* Pause operations */
+#define DP83640_PAUSE_NIL (0x0000u)
+#define DP83640_PAUSE_SYM (0x0400u)
+#define DP83640_PAUSE_ASYM (0x0800u)
+#define DP83640_PAUSE_BOTH_SYM_ASYM (0x0C00u)
+
+/* 100 Base TX Full Duplex capablity */
+#define DP83640_100BTX_HD (0x0000u)
+#define DP83640_100BTX_FD (0x0100u)
+
+/* 100 Base TX capability */
+#define DP83640_NO_100BTX (0x0000u)
+#define DP83640_100BTX (0x0080u)
+
+/* 10 BaseT duplex capabilities */
+#define DP83640_10BT_HD (0x0000u)
+#define DP83640_10BT_FD (0x0040u)
+
+/* 10 BaseT ability*/
+#define DP83640_NO_10BT (0x0000u)
+#define DP83640_10BT (0x0020u)
+
+/**************************************************************************
+ API function Prototypes
+***************************************************************************/
+extern uint32 Dp83640IDGet(uint32 mdioBaseAddr, uint32 phyAddr);
+extern void Dp83640Reset(uint32 mdioBaseAddr, uint32 phyAddr);
+extern boolean Dp83640AutoNegotiate(uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal);
+extern boolean Dp83640PartnerAbilityGet(uint32 mdioBaseAddr, uint32 phyAddr,uint16 *ptnerAblty);
+extern boolean Dp83640LinkStatusGet(uint32 mdioBaseAddr, uint32 phyAddr,volatile uint32 retries);
+extern uint64 Dp83640GetTimeStamp(uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type);
+extern void Dp83640EnableLoopback(uint32 mdioBaseAddr, uint32 phyAddr);
+extern void Dp83640DisableLoopback(uint32 mdioBaseAddr, uint32 phyAddr);
+extern boolean Dp83640PartnerSpdGet(uint32 mdioBaseAddr, uint32 phyAddr, uint16 *ptnerAblty);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
Index: firmware/include/pinmux.h
===================================================================
diff -u
--- firmware/include/pinmux.h (revision 0)
+++ firmware/include/pinmux.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,575 @@
+/** @file pinmux.h
+* @brief PINMUX Driver Implementation File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __PINMUX_H__
+#define __PINMUX_H__
+
+#include "reg_pinmux.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define PINMUX_PIN_1_SHIFT 0U
+#define PINMUX_PIN_2_SHIFT 8U
+#define PINMUX_PIN_3_SHIFT 16U
+#define PINMUX_PIN_4_SHIFT 24U
+#define PINMUX_PIN_5_SHIFT 0U
+#define PINMUX_PIN_6_SHIFT 8U
+#define PINMUX_PIN_9_SHIFT 0U
+#define PINMUX_PIN_14_SHIFT 24U
+#define PINMUX_PIN_15_SHIFT 8U
+#define PINMUX_PIN_16_SHIFT 16U
+#define PINMUX_PIN_22_SHIFT 0U
+#define PINMUX_PIN_23_SHIFT 16U
+#define PINMUX_PIN_24_SHIFT 24U
+#define PINMUX_PIN_25_SHIFT 0U
+#define PINMUX_PIN_30_SHIFT 8U
+#define PINMUX_PIN_31_SHIFT 16U
+#define PINMUX_PIN_32_SHIFT 0U
+#define PINMUX_PIN_33_SHIFT 0U
+#define PINMUX_PIN_35_SHIFT 16U
+#define PINMUX_PIN_36_SHIFT 0U
+#define PINMUX_PIN_37_SHIFT 8U
+#define PINMUX_PIN_38_SHIFT 16U
+#define PINMUX_PIN_39_SHIFT 0U
+#define PINMUX_PIN_40_SHIFT 8U
+#define PINMUX_PIN_41_SHIFT 16U
+#define PINMUX_PIN_51_SHIFT 8U
+#define PINMUX_PIN_52_SHIFT 16U
+#define PINMUX_PIN_53_SHIFT 24U
+#define PINMUX_PIN_54_SHIFT 8U
+#define PINMUX_PIN_55_SHIFT 16U
+#define PINMUX_PIN_86_SHIFT 0U
+#define PINMUX_PIN_91_SHIFT 24U
+#define PINMUX_PIN_92_SHIFT 0U
+#define PINMUX_PIN_96_SHIFT 16U
+#define PINMUX_PIN_97_SHIFT 24U
+#define PINMUX_PIN_98_SHIFT 0U
+#define PINMUX_PIN_99_SHIFT 8U
+#define PINMUX_PIN_100_SHIFT 16U
+#define PINMUX_PIN_105_SHIFT 24U
+#define PINMUX_PIN_106_SHIFT 0U
+#define PINMUX_PIN_107_SHIFT 8U
+#define PINMUX_PIN_118_SHIFT 0U
+#define PINMUX_PIN_124_SHIFT 16U
+#define PINMUX_PIN_125_SHIFT 8U
+#define PINMUX_PIN_126_SHIFT 24U
+#define PINMUX_PIN_127_SHIFT 8U
+#define PINMUX_PIN_130_SHIFT 16U
+#define PINMUX_PIN_133_SHIFT 8U
+#define PINMUX_PIN_139_SHIFT 0U
+#define PINMUX_PIN_140_SHIFT 8U
+#define PINMUX_PIN_141_SHIFT 16U
+
+
+#define PINMUX_GATE_EMIF_CLK_SHIFT 8U
+#define PINMUX_GIOB_DISABLE_HET2_SHIFT 16U
+#define PINMUX_ALT_ADC_TRIGGER_SHIFT 0U
+#define PINMUX_ETHERNET_SHIFT 24U
+#define PINMUX_ETPWM1_SHIFT 0U
+#define PINMUX_ETPWM2_SHIFT 8U
+#define PINMUX_ETPWM3_SHIFT 16U
+#define PINMUX_ETPWM4_SHIFT 24U
+#define PINMUX_ETPWM5_SHIFT 0U
+#define PINMUX_ETPWM6_SHIFT 8U
+#define PINMUX_ETPWM7_SHIFT 16U
+#define PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT 24U
+#define PINMUX_ETPWM_TBCLK_SYNC_SHIFT 0U
+#define PINMUX_TZ1_SHIFT 16U
+#define PINMUX_TZ2_SHIFT 24U
+#define PINMUX_TZ3_SHIFT 0U
+#define PINMUX_EPWM1SYNCI_SHIFT 8U
+
+#define PINMUX_PIN_1_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_1_SHIFT))
+#define PINMUX_PIN_2_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_2_SHIFT))
+#define PINMUX_PIN_3_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_3_SHIFT))
+#define PINMUX_PIN_4_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_4_SHIFT))
+#define PINMUX_PIN_5_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_5_SHIFT))
+#define PINMUX_PIN_6_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_9_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_14_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_14_SHIFT))
+#define PINMUX_PIN_15_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_15_SHIFT))
+#define PINMUX_PIN_16_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_16_SHIFT))
+#define PINMUX_PIN_22_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_22_SHIFT))
+#define PINMUX_PIN_23_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_24_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_25_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_25_SHIFT))
+#define PINMUX_PIN_30_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_30_SHIFT))
+#define PINMUX_PIN_31_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_31_SHIFT))
+#define PINMUX_PIN_32_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_32_SHIFT))
+#define PINMUX_PIN_33_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_35_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_36_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_36_SHIFT))
+#define PINMUX_PIN_37_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_37_SHIFT))
+#define PINMUX_PIN_38_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_38_SHIFT))
+#define PINMUX_PIN_39_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_39_SHIFT))
+#define PINMUX_PIN_40_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_40_SHIFT))
+#define PINMUX_PIN_41_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_41_SHIFT))
+#define PINMUX_PIN_51_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_51_SHIFT))
+#define PINMUX_PIN_52_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_52_SHIFT))
+#define PINMUX_PIN_53_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_53_SHIFT))
+#define PINMUX_PIN_54_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_54_SHIFT))
+#define PINMUX_PIN_55_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_55_SHIFT))
+#define PINMUX_PIN_86_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_86_SHIFT))
+#define PINMUX_PIN_91_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_91_SHIFT))
+#define PINMUX_PIN_92_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_92_SHIFT))
+#define PINMUX_PIN_96_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_97_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_98_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_98_SHIFT))
+#define PINMUX_PIN_99_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_99_SHIFT))
+#define PINMUX_PIN_100_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_100_SHIFT))
+#define PINMUX_PIN_105_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_106_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_106_SHIFT))
+#define PINMUX_PIN_107_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_107_SHIFT))
+#define PINMUX_PIN_118_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_124_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_124_SHIFT))
+#define PINMUX_PIN_125_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_125_SHIFT))
+#define PINMUX_PIN_126_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_126_SHIFT))
+#define PINMUX_PIN_127_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_127_SHIFT))
+#define PINMUX_PIN_130_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_133_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_133_SHIFT))
+#define PINMUX_PIN_139_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_139_SHIFT))
+#define PINMUX_PIN_140_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_140_SHIFT))
+#define PINMUX_PIN_141_MASK (~(uint32)((uint32)0xFFU << PINMUX_PIN_141_SHIFT))
+
+#define PINMUX_GATE_EMIF_CLK_MASK (~(uint32)((uint32)0xFFU << PINMUX_GATE_EMIF_CLK_SHIFT))
+#define PINMUX_GIOB_DISABLE_HET2_MASK (~(uint32)((uint32)0xFFU << PINMUX_GIOB_DISABLE_HET2_SHIFT))
+#define PINMUX_ALT_ADC_TRIGGER_MASK (~(uint32)((uint32)0xFFU << PINMUX_ALT_ADC_TRIGGER_SHIFT))
+#define PINMUX_ETHERNET_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETHERNET_SHIFT))
+
+
+
+#define PINMUX_ETPWM1_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM1_SHIFT))
+#define PINMUX_ETPWM2_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM2_SHIFT))
+#define PINMUX_ETPWM3_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM3_SHIFT))
+#define PINMUX_ETPWM4_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM4_SHIFT))
+#define PINMUX_ETPWM5_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM5_SHIFT))
+#define PINMUX_ETPWM6_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM6_SHIFT))
+#define PINMUX_ETPWM7_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM7_SHIFT))
+#define PINMUX_ETPWM_TIME_BASE_SYNC_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT))
+#define PINMUX_ETPWM_TBCLK_SYNC_MASK (~(uint32)((uint32)0xFFU << PINMUX_ETPWM_TBCLK_SYNC_SHIFT))
+#define PINMUX_TZ1_MASK (~(uint32)((uint32)0xFFU << PINMUX_TZ1_SHIFT))
+#define PINMUX_TZ2_MASK (~(uint32)((uint32)0xFFU << PINMUX_TZ2_SHIFT))
+#define PINMUX_TZ3_MASK (~(uint32)((uint32)0xFFU << PINMUX_TZ3_SHIFT))
+#define PINMUX_EPWM1SYNCI_MASK (~(uint32)((uint32)0xFFU << PINMUX_EPWM1SYNCI_SHIFT))
+
+#define PINMUX_PIN_1_GIOB_3 ((uint32)((uint32)0x1U << PINMUX_PIN_1_SHIFT))
+#define PINMUX_PIN_1_OHCI_PRT_RcvData_1 ((uint32)((uint32)0x2U << PINMUX_PIN_1_SHIFT))
+#define PINMUX_PIN_1_W2FC_RXDI ((uint32)((uint32)0x4U << PINMUX_PIN_1_SHIFT))
+
+#define PINMUX_PIN_2_GIOA_0 ((uint32)((uint32)0x1U << PINMUX_PIN_2_SHIFT))
+#define PINMUX_PIN_2_OHCI_PRT_RcvDpls_1 ((uint32)((uint32)0x2U << PINMUX_PIN_2_SHIFT))
+#define PINMUX_PIN_2_W2FC_RXDPI ((uint32)((uint32)0x4U << PINMUX_PIN_2_SHIFT))
+
+#define PINMUX_PIN_3_MIBSPI3NCS_3 ((uint32)((uint32)0x1U << PINMUX_PIN_3_SHIFT))
+#define PINMUX_PIN_3_I2C_SCL ((uint32)((uint32)0x2U << PINMUX_PIN_3_SHIFT))
+#define PINMUX_PIN_3_HET1_29 ((uint32)((uint32)0x4U << PINMUX_PIN_3_SHIFT))
+#define PINMUX_PIN_3_nTZ1 ((uint32)((uint32)0x8U << PINMUX_PIN_3_SHIFT))
+
+#define PINMUX_PIN_4_MIBSPI3NCS_2 ((uint32)((uint32)0x1U << PINMUX_PIN_4_SHIFT))
+#define PINMUX_PIN_4_I2C_SDA ((uint32)((uint32)0x2U << PINMUX_PIN_4_SHIFT))
+#define PINMUX_PIN_4_HET1_27 ((uint32)((uint32)0x4U << PINMUX_PIN_4_SHIFT))
+#define PINMUX_PIN_4_nTZ2 ((uint32)((uint32)0x8U << PINMUX_PIN_4_SHIFT))
+
+#define PINMUX_PIN_5_GIOA_1 ((uint32)((uint32)0x1U << PINMUX_PIN_5_SHIFT))
+#define PINMUX_PIN_5_OHCI_PRT_RcvDmns_1 ((uint32)((uint32)0x2U << PINMUX_PIN_5_SHIFT))
+#define PINMUX_PIN_5_W2FC_RXDMI ((uint32)((uint32)0x4U << PINMUX_PIN_5_SHIFT))
+
+#define PINMUX_PIN_6_HET1_11 ((uint32)((uint32)0x1U << PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_MIBSPI3NCS_4 ((uint32)((uint32)0x2U << PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_HET2_18 ((uint32)((uint32)0x4U << PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_OHCI_PRT_OvrCurrent_1 ((uint32)((uint32)0x8U << PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_W2FC_VBUSI ((uint32)((uint32)0x10U << PINMUX_PIN_6_SHIFT))
+#define PINMUX_PIN_6_ETPWM1SYNCO ((uint32)((uint32)0x20U << PINMUX_PIN_6_SHIFT))
+
+#define PINMUX_PIN_9_GIOA_2 ((uint32)((uint32)0x1U << PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_9_OHCI_RCFG_txdPls_1 ((uint32)((uint32)0x2U << PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_9_W2FC_TXDO ((uint32)((uint32)0x4U << PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_9_HET2_0 ((uint32)((uint32)0x8U << PINMUX_PIN_9_SHIFT))
+#define PINMUX_PIN_9_EQEP2I ((uint32)((uint32)0x10U << PINMUX_PIN_9_SHIFT))
+
+#define PINMUX_PIN_14_GIOA_5 ((uint32)((uint32)0x1U << PINMUX_PIN_14_SHIFT))
+#define PINMUX_PIN_14_EXTCLKIN ((uint32)((uint32)0x2U << PINMUX_PIN_14_SHIFT))
+#define PINMUX_PIN_14_ETPWM1A ((uint32)((uint32)0x4U << PINMUX_PIN_14_SHIFT))
+
+#define PINMUX_PIN_15_HET1_22 ((uint32)((uint32)0x1U << PINMUX_PIN_15_SHIFT))
+#define PINMUX_PIN_15_OHCI_RCFG_txSe0_1 ((uint32)((uint32)0x2U << PINMUX_PIN_15_SHIFT))
+#define PINMUX_PIN_15_W2FC_SE0O ((uint32)((uint32)0x4U << PINMUX_PIN_15_SHIFT))
+
+#define PINMUX_PIN_16_GIOA_6 ((uint32)((uint32)0x1U << PINMUX_PIN_16_SHIFT))
+#define PINMUX_PIN_16_HET2_4 ((uint32)((uint32)0x2U << PINMUX_PIN_16_SHIFT))
+#define PINMUX_PIN_16_ETPWM1B ((uint32)((uint32)0x4U << PINMUX_PIN_16_SHIFT))
+
+#define PINMUX_PIN_22_GIOA_7 ((uint32)((uint32)0x1U << PINMUX_PIN_22_SHIFT))
+#define PINMUX_PIN_22_HET2_6 ((uint32)((uint32)0x2U << PINMUX_PIN_22_SHIFT))
+#define PINMUX_PIN_22_ETPWM2A ((uint32)((uint32)0x4U << PINMUX_PIN_22_SHIFT))
+
+#define PINMUX_PIN_23_HET1_01 ((uint32)((uint32)0x1U << PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_SPI4NENA ((uint32)((uint32)0x2U << PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_OHCI_RCFG_txEnL_1 ((uint32)((uint32)0x4U << PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_W2FC_PUENO ((uint32)((uint32)0x8U << PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_HET2_8 ((uint32)((uint32)0x10U << PINMUX_PIN_23_SHIFT))
+#define PINMUX_PIN_23_EQEP2A ((uint32)((uint32)0x20U << PINMUX_PIN_23_SHIFT))
+
+#define PINMUX_PIN_24_HET1_03 ((uint32)((uint32)0x1U << PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_SPI4NCS_0 ((uint32)((uint32)0x2U << PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_OHCI_RCFG_speed_1 ((uint32)((uint32)0x4U << PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_W2FC_PUENON ((uint32)((uint32)0x8U << PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_HET2_10 ((uint32)((uint32)0x10U << PINMUX_PIN_24_SHIFT))
+#define PINMUX_PIN_24_EQEP2B ((uint32)((uint32)0x20U << PINMUX_PIN_24_SHIFT))
+
+#define PINMUX_PIN_25_HET1_0 ((uint32)((uint32)0x1U << PINMUX_PIN_25_SHIFT))
+#define PINMUX_PIN_25_SPI4CLK ((uint32)((uint32)0x2U << PINMUX_PIN_25_SHIFT))
+#define PINMUX_PIN_25_ETPWM2B ((uint32)((uint32)0x4U << PINMUX_PIN_25_SHIFT))
+
+#define PINMUX_PIN_30_HET1_02 ((uint32)((uint32)0x1U << PINMUX_PIN_30_SHIFT))
+#define PINMUX_PIN_30_SPI4SIMO ((uint32)((uint32)0x2U << PINMUX_PIN_30_SHIFT))
+#define PINMUX_PIN_30_ETPWM3A ((uint32)((uint32)0x4U << PINMUX_PIN_30_SHIFT))
+
+#define PINMUX_PIN_31_HET1_05 ((uint32)((uint32)0x1U << PINMUX_PIN_31_SHIFT))
+#define PINMUX_PIN_31_SPI4SOMI ((uint32)((uint32)0x2U << PINMUX_PIN_31_SHIFT))
+#define PINMUX_PIN_31_HET2_12 ((uint32)((uint32)0x4U << PINMUX_PIN_31_SHIFT))
+#define PINMUX_PIN_31_ETPWM3B ((uint32)((uint32)0x8U << PINMUX_PIN_31_SHIFT))
+
+#define PINMUX_PIN_32_MIBSPI5NCS_0 ((uint32)((uint32)0x1U << PINMUX_PIN_32_SHIFT))
+#define PINMUX_PIN_32_ETPWM4A ((uint32)((uint32)0x4U << PINMUX_PIN_32_SHIFT))
+
+#define PINMUX_PIN_33_HET1_07 ((uint32)((uint32)0x1U << PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_33_OHCI_RCFG_PrtPower_1 ((uint32)((uint32)0x2U << PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_33_W2FC_GZO ((uint32)((uint32)0x4U << PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_33_HET2_14 ((uint32)((uint32)0x8U << PINMUX_PIN_33_SHIFT))
+#define PINMUX_PIN_33_ETPWM7B ((uint32)((uint32)0x10U << PINMUX_PIN_33_SHIFT))
+
+#define PINMUX_PIN_35_HET1_09 ((uint32)((uint32)0x1U << PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_35_HET2_16 ((uint32)((uint32)0x2U << PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_35_OHCI_RCFG_suspend_1 ((uint32)((uint32)0x4U << PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_35_W2FC_SUSPENDO ((uint32)((uint32)0x8U << PINMUX_PIN_35_SHIFT))
+#define PINMUX_PIN_35_ETPWM7A ((uint32)((uint32)0x10U << PINMUX_PIN_35_SHIFT))
+
+#define PINMUX_PIN_36_HET1_04 ((uint32)((uint32)0x1U << PINMUX_PIN_36_SHIFT))
+#define PINMUX_PIN_36_ETPWM4B ((uint32)((uint32)0x2U << PINMUX_PIN_36_SHIFT))
+
+#define PINMUX_PIN_37_MIBSPI3NCS_1 ((uint32)((uint32)0x1U << PINMUX_PIN_37_SHIFT))
+#define PINMUX_PIN_37_HET1_25 ((uint32)((uint32)0x2U << PINMUX_PIN_37_SHIFT))
+#define PINMUX_PIN_37_MDCLK ((uint32)((uint32)0x4U << PINMUX_PIN_37_SHIFT))
+
+#define PINMUX_PIN_38_HET1_06 ((uint32)((uint32)0x1U << PINMUX_PIN_38_SHIFT))
+#define PINMUX_PIN_38_SCIRX ((uint32)((uint32)0x2U << PINMUX_PIN_38_SHIFT))
+#define PINMUX_PIN_38_ETPWM5A ((uint32)((uint32)0x4U << PINMUX_PIN_38_SHIFT))
+
+#define PINMUX_PIN_39_HET1_13 ((uint32)((uint32)0x1U << PINMUX_PIN_39_SHIFT))
+#define PINMUX_PIN_39_SCITX ((uint32)((uint32)0x2U << PINMUX_PIN_39_SHIFT))
+#define PINMUX_PIN_39_ETPWM5B ((uint32)((uint32)0x4U << PINMUX_PIN_39_SHIFT))
+
+#define PINMUX_PIN_40_MIBSPI1NCS_2 ((uint32)((uint32)0x1U << PINMUX_PIN_40_SHIFT))
+#define PINMUX_PIN_40_HET1_19 ((uint32)((uint32)0x2U << PINMUX_PIN_40_SHIFT))
+#define PINMUX_PIN_40_MDIO ((uint32)((uint32)0x4U << PINMUX_PIN_40_SHIFT))
+
+#define PINMUX_PIN_41_HET1_15 ((uint32)((uint32)0x1U << PINMUX_PIN_41_SHIFT))
+#define PINMUX_PIN_41_MIBSPI1NCS_4 ((uint32)((uint32)0x2U << PINMUX_PIN_41_SHIFT))
+#define PINMUX_PIN_41_ECAP1 ((uint32)((uint32)0x4U << PINMUX_PIN_41_SHIFT))
+
+#define PINMUX_PIN_51_MIBSPI3SOMI ((uint32)((uint32)0x1U << PINMUX_PIN_51_SHIFT))
+#define PINMUX_PIN_51_AWM_EXT_ENA ((uint32)((uint32)0x2U << PINMUX_PIN_51_SHIFT))
+#define PINMUX_PIN_51_ECAP2 ((uint32)((uint32)0x4U << PINMUX_PIN_51_SHIFT))
+
+#define PINMUX_PIN_52_MIBSPI3SIMO ((uint32)((uint32)0x1U << PINMUX_PIN_52_SHIFT))
+#define PINMUX_PIN_52_AWM_EXT_SEL_0 ((uint32)((uint32)0x2U << PINMUX_PIN_52_SHIFT))
+#define PINMUX_PIN_52_ECAP3 ((uint32)((uint32)0x4U << PINMUX_PIN_52_SHIFT))
+
+#define PINMUX_PIN_53_MIBSPI3CLK ((uint32)((uint32)0x1U << PINMUX_PIN_53_SHIFT))
+#define PINMUX_PIN_53_AWM_EXT_SEL_1 ((uint32)((uint32)0x2U << PINMUX_PIN_53_SHIFT))
+#define PINMUX_PIN_53_EQEP1A ((uint32)((uint32)0x4U << PINMUX_PIN_53_SHIFT))
+
+#define PINMUX_PIN_54_MIBSPI3NENA ((uint32)((uint32)0x1U << PINMUX_PIN_54_SHIFT))
+#define PINMUX_PIN_54_MIBSPI3NCS_5 ((uint32)((uint32)0x2U << PINMUX_PIN_54_SHIFT))
+#define PINMUX_PIN_54_HET1_31 ((uint32)((uint32)0x4U << PINMUX_PIN_54_SHIFT))
+#define PINMUX_PIN_54_EQEP1B ((uint32)((uint32)0x8U << PINMUX_PIN_54_SHIFT))
+
+#define PINMUX_PIN_55_MIBSPI3NCS_0 ((uint32)((uint32)0x1U << PINMUX_PIN_55_SHIFT))
+#define PINMUX_PIN_55_AD2EVT ((uint32)((uint32)0x2U << PINMUX_PIN_55_SHIFT))
+#define PINMUX_PIN_55_GIOB_2 ((uint32)((uint32)0x4U << PINMUX_PIN_55_SHIFT))
+#define PINMUX_PIN_55_EQEP1I ((uint32)((uint32)0x8U << PINMUX_PIN_55_SHIFT))
+
+#define PINMUX_PIN_86_AD1EVT ((uint32)((uint32)0x1U << PINMUX_PIN_86_SHIFT))
+#define PINMUX_PIN_86_MII_RX_ER ((uint32)((uint32)0x2U << PINMUX_PIN_86_SHIFT))
+#define PINMUX_PIN_86_RMII_RX_ER ((uint32)((uint32)0x4U << PINMUX_PIN_86_SHIFT))
+
+#define PINMUX_PIN_91_HET1_24 ((uint32)((uint32)0x1U << PINMUX_PIN_91_SHIFT))
+#define PINMUX_PIN_91_MIBSPI1NCS_5 ((uint32)((uint32)0x2U << PINMUX_PIN_91_SHIFT))
+#define PINMUX_PIN_91_MII_RXD_0 ((uint32)((uint32)0x4U << PINMUX_PIN_91_SHIFT))
+#define PINMUX_PIN_91_RMII_RXD_0 ((uint32)((uint32)0x8U << PINMUX_PIN_91_SHIFT))
+
+#define PINMUX_PIN_92_HET1_26 ((uint32)((uint32)0x1U << PINMUX_PIN_92_SHIFT))
+#define PINMUX_PIN_92_MII_RXD_1 ((uint32)((uint32)0x2U << PINMUX_PIN_92_SHIFT))
+#define PINMUX_PIN_92_RMII_RXD_1 ((uint32)((uint32)0x4U << PINMUX_PIN_92_SHIFT))
+
+#define PINMUX_PIN_96_MIBSPI1NENA ((uint32)((uint32)0x1U << PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_96_HET1_23 ((uint32)((uint32)0x2U << PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_96_MII_RXD_2 ((uint32)((uint32)0x4U << PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_96_OHCI_PRT_RcvDpls_0 ((uint32)((uint32)0x8U << PINMUX_PIN_96_SHIFT))
+#define PINMUX_PIN_96_ECAP4 ((uint32)((uint32)0x10U << PINMUX_PIN_96_SHIFT))
+
+#define PINMUX_PIN_97_MIBSPI5NENA ((uint32)((uint32)0x1U << PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_97_MII_RXD_3 ((uint32)((uint32)0x4U << PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_97_OHCI_PRT_RcvDmns_0 ((uint32)((uint32)0x8U << PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_97_MIBSPI5SOMI_1 ((uint32)((uint32)0x10U << PINMUX_PIN_97_SHIFT))
+#define PINMUX_PIN_97_ECAP5 ((uint32)((uint32)0x20U << PINMUX_PIN_97_SHIFT))
+
+#define PINMUX_PIN_98_MIBSPI5SOMI_0 ((uint32)((uint32)0x1U << PINMUX_PIN_98_SHIFT))
+#define PINMUX_PIN_98_MII_TXD_0 ((uint32)((uint32)0x4U << PINMUX_PIN_98_SHIFT))
+#define PINMUX_PIN_98_RMII_TXD_0 ((uint32)((uint32)0x8U << PINMUX_PIN_98_SHIFT))
+
+#define PINMUX_PIN_99_MIBSPI5SIMO_0 ((uint32)((uint32)0x1U << PINMUX_PIN_99_SHIFT))
+#define PINMUX_PIN_99_MII_TXD_1 ((uint32)((uint32)0x4U << PINMUX_PIN_99_SHIFT))
+#define PINMUX_PIN_99_RMII_TXD_1 ((uint32)((uint32)0x8U << PINMUX_PIN_99_SHIFT))
+#define PINMUX_PIN_99_MIBSPI5SOMI_2 ((uint32)((uint32)0x10U << PINMUX_PIN_99_SHIFT))
+
+#define PINMUX_PIN_100_MIBSPI5CLK ((uint32)((uint32)0x1U << PINMUX_PIN_100_SHIFT))
+#define PINMUX_PIN_100_MII_TXEN ((uint32)((uint32)0x4U << PINMUX_PIN_100_SHIFT))
+#define PINMUX_PIN_100_RMII_TXEN ((uint32)((uint32)0x8U << PINMUX_PIN_100_SHIFT))
+
+#define PINMUX_PIN_105_MIBSPI1NCS_0 ((uint32)((uint32)0x1U << PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_105_MIBSPI1SOMI_1 ((uint32)((uint32)0x2U << PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_105_MII_TXD_2 ((uint32)((uint32)0x4U << PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_105_OHCI_PRT_RcvData_0 ((uint32)((uint32)0x8U << PINMUX_PIN_105_SHIFT))
+#define PINMUX_PIN_105_ECAP6 ((uint32)((uint32)0x10U << PINMUX_PIN_105_SHIFT))
+
+#define PINMUX_PIN_106_HET1_08 ((uint32)((uint32)0x1U << PINMUX_PIN_106_SHIFT))
+#define PINMUX_PIN_106_MIBSPI1SIMO_1 ((uint32)((uint32)0x2U << PINMUX_PIN_106_SHIFT))
+#define PINMUX_PIN_106_MII_TXD_3 ((uint32)((uint32)0x4U << PINMUX_PIN_106_SHIFT))
+#define PINMUX_PIN_106_OHCI_PRT_OvrCurrent_0 ((uint32)((uint32)0x8U << PINMUX_PIN_106_SHIFT))
+
+#define PINMUX_PIN_107_HET1_28 ((uint32)((uint32)0x1U << PINMUX_PIN_107_SHIFT))
+#define PINMUX_PIN_107_MII_RXCLK ((uint32)((uint32)0x2U << PINMUX_PIN_107_SHIFT))
+#define PINMUX_PIN_107_RMII_REFCLK ((uint32)((uint32)0x4U << PINMUX_PIN_107_SHIFT))
+#define PINMUX_PIN_107_MII_RX_AVCLK4 ((uint32)((uint32)0x8U << PINMUX_PIN_107_SHIFT))
+
+#define PINMUX_PIN_118_HET1_10 ((uint32)((uint32)0x1U << PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_118_MII_TX_CLK ((uint32)((uint32)0x2U << PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_118_OHCI_RCFG_txEnL_0 ((uint32)((uint32)0x4U << PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_118_MII_TX_AVCLK4 ((uint32)((uint32)0x8U << PINMUX_PIN_118_SHIFT))
+#define PINMUX_PIN_118_nTZ3 ((uint32)((uint32)0x10U << PINMUX_PIN_118_SHIFT))
+
+#define PINMUX_PIN_124_HET1_12 ((uint32)((uint32)0x1U << PINMUX_PIN_124_SHIFT))
+#define PINMUX_PIN_124_MII_CRS ((uint32)((uint32)0x2U << PINMUX_PIN_124_SHIFT))
+#define PINMUX_PIN_124_RMII_CRS_DV ((uint32)((uint32)0x4U << PINMUX_PIN_124_SHIFT))
+
+#define PINMUX_PIN_125_HET1_14 ((uint32)((uint32)0x1U << PINMUX_PIN_125_SHIFT))
+#define PINMUX_PIN_125_OHCI_RCFG_txSe0_0 ((uint32)((uint32)0x2U << PINMUX_PIN_125_SHIFT))
+
+#define PINMUX_PIN_126_GIOB_0 ((uint32)((uint32)0x1U << PINMUX_PIN_126_SHIFT))
+#define PINMUX_PIN_126_OHCI_RCFG_txDpls_0 ((uint32)((uint32)0x2U << PINMUX_PIN_126_SHIFT))
+
+#define PINMUX_PIN_127_HET1_30 ((uint32)((uint32)0x1U << PINMUX_PIN_127_SHIFT))
+#define PINMUX_PIN_127_MII_RX_DV ((uint32)((uint32)0x2U << PINMUX_PIN_127_SHIFT))
+#define PINMUX_PIN_127_OHCI_RCFG_speed_0 ((uint32)((uint32)0x4U << PINMUX_PIN_127_SHIFT))
+#define PINMUX_PIN_127_EQEP2S ((uint32)((uint32)0x8U << PINMUX_PIN_127_SHIFT))
+
+#define PINMUX_PIN_130_MIBSPI1NCS_1 ((uint32)((uint32)0x1U << PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_130_HET1_17 ((uint32)((uint32)0x2U << PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_130_MII_COL ((uint32)((uint32)0x4U << PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_130_OHCI_RCFG_suspend_0 ((uint32)((uint32)0x8U << PINMUX_PIN_130_SHIFT))
+#define PINMUX_PIN_130_EQEP1S ((uint32)((uint32)0x10U << PINMUX_PIN_130_SHIFT))
+
+#define PINMUX_PIN_133_GIOB_1 ((uint32)((uint32)0x1U << PINMUX_PIN_133_SHIFT))
+#define PINMUX_PIN_133_OHCI_RCFG_PrtPower_0 ((uint32)((uint32)0x2U << PINMUX_PIN_133_SHIFT))
+
+#define PINMUX_PIN_139_HET1_16 ((uint32)((uint32)0x1U << PINMUX_PIN_139_SHIFT))
+#define PINMUX_PIN_139_ETPWM1SYNCI ((uint32)((uint32)0x2U << PINMUX_PIN_139_SHIFT))
+#define PINMUX_PIN_139_ETPWM1SYNCO ((uint32)((uint32)0x4U << PINMUX_PIN_139_SHIFT))
+
+#define PINMUX_PIN_140_HET1_18 ((uint32)((uint32)0x1U << PINMUX_PIN_140_SHIFT))
+#define PINMUX_PIN_140_ETPWM6A ((uint32)((uint32)0x2U << PINMUX_PIN_140_SHIFT))
+
+#define PINMUX_PIN_141_HET1_20 ((uint32)((uint32)0x1U << PINMUX_PIN_141_SHIFT))
+#define PINMUX_PIN_141_ETPWM6B ((uint32)((uint32)0x2U << PINMUX_PIN_141_SHIFT))
+
+#define PINMUX_PIN_133_GIOB_1 ((uint32)((uint32)0x1U << PINMUX_PIN_133_SHIFT))
+
+#define PINMUX_PIN_1_GIOB_3 ((uint32)((uint32)0x1U << PINMUX_PIN_1_SHIFT))
+
+#define PINMUX_PIN_2_GIOA_0 ((uint32)((uint32)0x1U << PINMUX_PIN_2_SHIFT))
+
+#define PINMUX_PIN_5_GIOA_1 ((uint32)((uint32)0x1U << PINMUX_PIN_5_SHIFT))
+
+#define PINMUX_PIN_15_HET1_22 ((uint32)((uint32)0x1U << PINMUX_PIN_15_SHIFT))
+
+#define PINMUX_PIN_125_HET1_14 ((uint32)((uint32)0x1U << PINMUX_PIN_125_SHIFT))
+
+#define PINMUX_PIN_126_GIOB_0 ((uint32)((uint32)0x1U << PINMUX_PIN_126_SHIFT))
+
+#define PINMUX_GATE_EMIF_CLK_ON ((uint32)((uint32)0x0 << PINMUX_GATE_EMIF_CLK_SHIFT))
+#define PINMUX_GIOB_DISABLE_HET2_ON ((uint32)((uint32)0x1U << PINMUX_GIOB_DISABLE_HET2_SHIFT))
+#define PINMUX_GATE_EMIF_CLK_OFF ((uint32)((uint32)0x1U << PINMUX_GATE_EMIF_CLK_SHIFT))
+#define PINMUX_GIOB_DISABLE_HET2_OFF ((uint32)((uint32)0x0 << PINMUX_GIOB_DISABLE_HET2_SHIFT))
+#define PINMUX_ALT_ADC_TRIGGER_1 ((uint32)((uint32)0x1U << PINMUX_ALT_ADC_TRIGGER_SHIFT))
+#define PINMUX_ALT_ADC_TRIGGER_2 ((uint32)((uint32)0x2U << PINMUX_ALT_ADC_TRIGGER_SHIFT))
+#define PINMUX_ETHERNET_MII ((uint32)((uint32)0x0 << PINMUX_ETHERNET_SHIFT))
+#define PINMUX_ETHERNET_RMII ((uint32)((uint32)0x1U << PINMUX_ETHERNET_SHIFT))
+
+#define PINMUX_ETPWM1_EQEPERR12 ((uint32)((uint32)0x1U << PINMUX_ETPWM1_SHIFT))
+#define PINMUX_ETPWM1_EQEPERR1 ((uint32)((uint32)0x2U << PINMUX_ETPWM1_SHIFT))
+#define PINMUX_ETPWM1_EQEPERR2 ((uint32)((uint32)0x4U << PINMUX_ETPWM1_SHIFT))
+#define PINMUX_ETPWM2_EQEPERR12 ((uint32)((uint32)0x1U << PINMUX_ETPWM2_SHIFT))
+#define PINMUX_ETPWM2_EQEPERR1 ((uint32)((uint32)0x2U << PINMUX_ETPWM2_SHIFT))
+#define PINMUX_ETPWM2_EQEPERR2 ((uint32)((uint32)0x4U << PINMUX_ETPWM2_SHIFT))
+#define PINMUX_ETPWM3_EQEPERR12 ((uint32)((uint32)0x1U << PINMUX_ETPWM3_SHIFT))
+#define PINMUX_ETPWM3_EQEPERR1 ((uint32)((uint32)0x2U << PINMUX_ETPWM3_SHIFT))
+#define PINMUX_ETPWM3_EQEPERR2 ((uint32)((uint32)0x4U << PINMUX_ETPWM3_SHIFT))
+#define PINMUX_ETPWM4_EQEPERR12 ((uint32)((uint32)0x1U << PINMUX_ETPWM4_SHIFT))
+#define PINMUX_ETPWM4_EQEPERR1 ((uint32)((uint32)0x2U << PINMUX_ETPWM4_SHIFT))
+#define PINMUX_ETPWM4_EQEPERR2 ((uint32)((uint32)0x4U << PINMUX_ETPWM4_SHIFT))
+#define PINMUX_ETPWM5_EQEPERR12 ((uint32)((uint32)0x1U << PINMUX_ETPWM5_SHIFT))
+#define PINMUX_ETPWM5_EQEPERR1 ((uint32)((uint32)0x2U << PINMUX_ETPWM5_SHIFT))
+#define PINMUX_ETPWM5_EQEPERR2 ((uint32)((uint32)0x4U << PINMUX_ETPWM5_SHIFT))
+#define PINMUX_ETPWM6_EQEPERR12 ((uint32)((uint32)0x1U << PINMUX_ETPWM6_SHIFT))
+#define PINMUX_ETPWM6_EQEPERR1 ((uint32)((uint32)0x2U << PINMUX_ETPWM6_SHIFT))
+#define PINMUX_ETPWM6_EQEPERR2 ((uint32)((uint32)0x4U << PINMUX_ETPWM6_SHIFT))
+#define PINMUX_ETPWM7_EQEPERR12 ((uint32)((uint32)0x1U << PINMUX_ETPWM7_SHIFT))
+#define PINMUX_ETPWM7_EQEPERR1 ((uint32)((uint32)0x2U << PINMUX_ETPWM7_SHIFT))
+#define PINMUX_ETPWM7_EQEPERR2 ((uint32)((uint32)0x4U << PINMUX_ETPWM7_SHIFT))
+#define PINMUX_ETPWM_TIME_BASE_SYNC_ON ((uint32)((uint32)0x2U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT))
+#define PINMUX_ETPWM_TBCLK_SYNC_ON ((uint32)((uint32)0x2U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT))
+#define PINMUX_ETPWM_TIME_BASE_SYNC_OFF ((uint32)((uint32)0x0 << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT))
+#define PINMUX_ETPWM_TBCLK_SYNC_OFF ((uint32)((uint32)0x0 << PINMUX_ETPWM_TBCLK_SYNC_SHIFT))
+#define PINMUX_TZ1_ASYNC ((uint32)((uint32)0x1U << PINMUX_TZ1_SHIFT))
+#define PINMUX_TZ1_SYNC ((uint32)((uint32)0x2U << PINMUX_TZ1_SHIFT))
+#define PINMUX_TZ1_FILTERED ((uint32)((uint32)0x4U << PINMUX_TZ1_SHIFT))
+#define PINMUX_TZ2_ASYNC ((uint32)((uint32)0x1U << PINMUX_TZ2_SHIFT))
+#define PINMUX_TZ2_SYNC ((uint32)((uint32)0x2U << PINMUX_TZ2_SHIFT))
+#define PINMUX_TZ2_FILTERED ((uint32)((uint32)0x4U << PINMUX_TZ2_SHIFT))
+#define PINMUX_TZ3_ASYNC ((uint32)((uint32)0x1U << PINMUX_TZ3_SHIFT))
+#define PINMUX_TZ3_SYNC ((uint32)((uint32)0x2U << PINMUX_TZ3_SHIFT))
+#define PINMUX_TZ3_FILTERED ((uint32)((uint32)0x4U << PINMUX_TZ3_SHIFT))
+#define PINMUX_EPWM1SYNCI_ASYNC ((uint32)((uint32)0x1U << PINMUX_EPWM1SYNCI_SHIFT))
+#define PINMUX_EPWM1SYNCI_SYNC ((uint32)((uint32)0x2U << PINMUX_EPWM1SYNCI_SHIFT))
+#define PINMUX_EPWM1SYNCI_FILTERED ((uint32)((uint32)0x4U << PINMUX_EPWM1SYNCI_SHIFT))
+
+typedef struct pinmux_config_reg
+{
+ uint32 CONFIG_PINMMR0;
+ uint32 CONFIG_PINMMR1;
+ uint32 CONFIG_PINMMR2;
+ uint32 CONFIG_PINMMR3;
+ uint32 CONFIG_PINMMR4;
+ uint32 CONFIG_PINMMR5;
+ uint32 CONFIG_PINMMR6;
+ uint32 CONFIG_PINMMR7;
+ uint32 CONFIG_PINMMR8;
+ uint32 CONFIG_PINMMR9;
+ uint32 CONFIG_PINMMR10;
+ uint32 CONFIG_PINMMR11;
+ uint32 CONFIG_PINMMR12;
+ uint32 CONFIG_PINMMR13;
+ uint32 CONFIG_PINMMR14;
+ uint32 CONFIG_PINMMR15;
+ uint32 CONFIG_PINMMR16;
+ uint32 CONFIG_PINMMR17;
+ uint32 CONFIG_PINMMR18;
+ uint32 CONFIG_PINMMR19;
+ uint32 CONFIG_PINMMR20;
+ uint32 CONFIG_PINMMR21;
+ uint32 CONFIG_PINMMR22;
+ uint32 CONFIG_PINMMR23;
+ uint32 CONFIG_PINMMR24;
+ uint32 CONFIG_PINMMR25;
+ uint32 CONFIG_PINMMR26;
+ uint32 CONFIG_PINMMR27;
+ uint32 CONFIG_PINMMR28;
+ uint32 CONFIG_PINMMR29;
+ uint32 CONFIG_PINMMR30;
+ uint32 CONFIG_PINMMR31;
+ uint32 CONFIG_PINMMR32;
+ uint32 CONFIG_PINMMR33;
+ uint32 CONFIG_PINMMR34;
+ uint32 CONFIG_PINMMR35;
+ uint32 CONFIG_PINMMR36;
+ uint32 CONFIG_PINMMR37;
+ uint32 CONFIG_PINMMR38;
+ uint32 CONFIG_PINMMR39;
+ uint32 CONFIG_PINMMR40;
+ uint32 CONFIG_PINMMR41;
+ uint32 CONFIG_PINMMR42;
+ uint32 CONFIG_PINMMR43;
+ uint32 CONFIG_PINMMR44;
+ uint32 CONFIG_PINMMR45;
+ uint32 CONFIG_PINMMR46;
+ uint32 CONFIG_PINMMR47;
+}pinmux_config_reg_t;
+
+/**
+ * @defgroup IOMM IOMM
+ * @brief I/O Multiplexing and Control Module.
+ *
+ * The IOMM contains memory-mapped registers (MMR) that control device-specific multiplexed functions.
+ * The safety and diagnostic features of the IOMM are:
+ * - Kicker mechanism to protect the MMRs from accidental writes
+ * - Master-id checker to only allow the CPU to write to the MMRs
+ * - Error indication for access violations
+ *
+ * Related Files
+ * - reg_pinmux.h
+ * - pinmux.h
+ * - pinmux.c
+ * @addtogroup IOMM
+ * @{
+ */
+
+/** @fn void muxInit(void)
+* @brief Initializes the PINMUX Driver
+*
+* This function initializes the PINMUX module and configures the selected
+* pinmux settings as per the user selection in the GUI
+*/
+void muxInit(void);
+void pinmuxGetConfigValue(pinmux_config_reg_t *config_reg, config_value_type_t type);
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+#endif
Index: firmware/include/pom.h
===================================================================
diff -u
--- firmware/include/pom.h (revision 0)
+++ firmware/include/pom.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,242 @@
+/** @file pom.h
+* @brief POM Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __POM_H__
+#define __POM_H__
+
+#include "reg_pom.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @enum pom_region_size
+* @brief Alias names for pom region size
+* This enumeration is used to provide alias names for POM region size:
+*/
+enum pom_region_size
+{
+ SIZE_32BYTES = 0U,
+ SIZE_64BYTES = 1U,
+ SIZE_128BYTES = 2U,
+ SIZE_256BYTES = 3U,
+ SIZE_512BYTES = 4U,
+ SIZE_1KB = 5U,
+ SIZE_2KB = 6U,
+ SIZE_4KB = 7U,
+ SIZE_8KB = 8U,
+ SIZE_16KB = 9U,
+ SIZE_32KB = 10U,
+ SIZE_64KB = 11U,
+ SIZE_128KB = 12U,
+ SIZE_256KB = 13U
+};
+
+/** @def INTERNAL_RAM
+* @brief Alias name for Internal RAM
+*/
+#define INTERNAL_RAM 0x08000000U
+
+/** @def SDRAM
+* @brief Alias name for SD RAM
+*/
+#define SDRAM 0x80000000U
+
+/** @def ASYNC_MEMORY
+* @brief Alias name for Async RAM
+*/
+#define ASYNC_MEMORY 0x60000000U
+
+
+typedef uint32 REGION_t;
+
+/** @struct REGION_CONFIG_ST
+* @brief POM region configuration
+*/
+typedef struct
+{
+ uint32 Prog_Reg_Sta_Addr;
+ uint32 Ovly_Reg_Sta_Addr;
+ uint32 Reg_Size;
+}REGION_CONFIG_t;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* Configuration registers */
+typedef struct pom_config_reg
+{
+ uint32 CONFIG_POMGLBCTRL;
+ uint32 CONFIG_POMPROGSTART0;
+ uint32 CONFIG_POMOVLSTART0;
+ uint32 CONFIG_POMREGSIZE0;
+ uint32 CONFIG_POMPROGSTART1;
+ uint32 CONFIG_POMOVLSTART1;
+ uint32 CONFIG_POMREGSIZE1;
+ uint32 CONFIG_POMPROGSTART2;
+ uint32 CONFIG_POMOVLSTART2;
+ uint32 CONFIG_POMREGSIZE2;
+ uint32 CONFIG_POMPROGSTART3;
+ uint32 CONFIG_POMOVLSTART3;
+ uint32 CONFIG_POMREGSIZE3;
+ uint32 CONFIG_POMPROGSTART4;
+ uint32 CONFIG_POMOVLSTART4;
+ uint32 CONFIG_POMREGSIZE4;
+ uint32 CONFIG_POMPROGSTART5;
+ uint32 CONFIG_POMOVLSTART5;
+ uint32 CONFIG_POMREGSIZE5;
+ uint32 CONFIG_POMPROGSTART6;
+ uint32 CONFIG_POMOVLSTART6;
+ uint32 CONFIG_POMREGSIZE6;
+ uint32 CONFIG_POMPROGSTART7;
+ uint32 CONFIG_POMOVLSTART7;
+ uint32 CONFIG_POMREGSIZE7;
+ uint32 CONFIG_POMPROGSTART8;
+ uint32 CONFIG_POMOVLSTART8;
+ uint32 CONFIG_POMREGSIZE8;
+ uint32 CONFIG_POMPROGSTART9;
+ uint32 CONFIG_POMOVLSTART9;
+ uint32 CONFIG_POMREGSIZE9;
+ uint32 CONFIG_POMPROGSTART10;
+ uint32 CONFIG_POMOVLSTART10;
+ uint32 CONFIG_POMREGSIZE10;
+ uint32 CONFIG_POMPROGSTART11;
+ uint32 CONFIG_POMOVLSTART11;
+ uint32 CONFIG_POMREGSIZE11;
+ uint32 CONFIG_POMPROGSTART12;
+ uint32 CONFIG_POMOVLSTART12;
+ uint32 CONFIG_POMREGSIZE12;
+ uint32 CONFIG_POMPROGSTART13;
+ uint32 CONFIG_POMOVLSTART13;
+ uint32 CONFIG_POMREGSIZE13;
+ uint32 CONFIG_POMPROGSTART14;
+ uint32 CONFIG_POMOVLSTART14;
+ uint32 CONFIG_POMREGSIZE14;
+ uint32 CONFIG_POMPROGSTART15;
+ uint32 CONFIG_POMOVLSTART15;
+ uint32 CONFIG_POMREGSIZE15;
+ uint32 CONFIG_POMPROGSTART16;
+ uint32 CONFIG_POMOVLSTART16;
+ uint32 CONFIG_POMREGSIZE16;
+ uint32 CONFIG_POMPROGSTART17;
+ uint32 CONFIG_POMOVLSTART17;
+ uint32 CONFIG_POMREGSIZE17;
+ uint32 CONFIG_POMPROGSTART18;
+ uint32 CONFIG_POMOVLSTART18;
+ uint32 CONFIG_POMREGSIZE18;
+ uint32 CONFIG_POMPROGSTART19;
+ uint32 CONFIG_POMOVLSTART19;
+ uint32 CONFIG_POMREGSIZE19;
+ uint32 CONFIG_POMPROGSTART20;
+ uint32 CONFIG_POMOVLSTART20;
+ uint32 CONFIG_POMREGSIZE20;
+ uint32 CONFIG_POMPROGSTART21;
+ uint32 CONFIG_POMOVLSTART21;
+ uint32 CONFIG_POMREGSIZE21;
+ uint32 CONFIG_POMPROGSTART22;
+ uint32 CONFIG_POMOVLSTART22;
+ uint32 CONFIG_POMREGSIZE22;
+ uint32 CONFIG_POMPROGSTART23;
+ uint32 CONFIG_POMOVLSTART23;
+ uint32 CONFIG_POMREGSIZE23;
+ uint32 CONFIG_POMPROGSTART24;
+ uint32 CONFIG_POMOVLSTART24;
+ uint32 CONFIG_POMREGSIZE24;
+ uint32 CONFIG_POMPROGSTART25;
+ uint32 CONFIG_POMOVLSTART25;
+ uint32 CONFIG_POMREGSIZE25;
+ uint32 CONFIG_POMPROGSTART26;
+ uint32 CONFIG_POMOVLSTART26;
+ uint32 CONFIG_POMREGSIZE26;
+ uint32 CONFIG_POMPROGSTART27;
+ uint32 CONFIG_POMOVLSTART27;
+ uint32 CONFIG_POMREGSIZE27;
+ uint32 CONFIG_POMPROGSTART28;
+ uint32 CONFIG_POMOVLSTART28;
+ uint32 CONFIG_POMREGSIZE28;
+ uint32 CONFIG_POMPROGSTART29;
+ uint32 CONFIG_POMOVLSTART29;
+ uint32 CONFIG_POMREGSIZE29;
+ uint32 CONFIG_POMPROGSTART30;
+ uint32 CONFIG_POMOVLSTART30;
+ uint32 CONFIG_POMREGSIZE30;
+ uint32 CONFIG_POMPROGSTART31;
+ uint32 CONFIG_POMOVLSTART31;
+ uint32 CONFIG_POMREGSIZE31;
+} pom_config_reg_t;
+
+
+/**
+ * @defgroup POM POM
+ * @brief Parameter Overlay Module.
+ *
+ * The POM provides a mechanism to redirect accesses to non-volatile memory into a volatile memory
+ * internal or external to the device. The data requested by the CPU will be fetched from the overlay memory
+ * instead of the main non-volatile memory.
+ *
+ * Related Files
+ * - reg_pom.h
+ * - pom.h
+ * - pom.c
+ * @addtogroup POM
+ * @{
+ */
+
+/* POM Interface Functions */
+void POM_Region_Config(REGION_CONFIG_t *Reg_Config_Ptr,REGION_t Region_Num);
+void POM_Reset(void);
+void POM_Init(void);
+void POM_Enable(void);
+void pomGetConfigValue(pom_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+#endif /* __POM_H_*/
Index: firmware/include/reg_adc.h
===================================================================
diff -u
--- firmware/include/reg_adc.h (revision 0)
+++ firmware/include/reg_adc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,261 @@
+/** @file reg_adc.h
+* @brief ADC Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the ADC driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_ADC_H__
+#define __REG_ADC_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Adc Register Frame Definition */
+/** @struct adcBase
+* @brief ADC Register Frame Definition
+*
+* This type is used to access the ADC Registers.
+*/
+/** @typedef adcBASE_t
+* @brief ADC Register Frame Type Definition
+*
+* This type is used to access the ADC Registers.
+*/
+typedef volatile struct adcBase
+{
+ uint32 RSTCR; /**< 0x0000: Reset control register */
+ uint32 OPMODECR; /**< 0x0004: Operating mode control register */
+ uint32 CLOCKCR; /**< 0x0008: Clock control register */
+ uint32 CALCR; /**< 0x000C: Calibration control register */
+ uint32 GxMODECR[3U]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */
+ uint32 EVSRC; /**< 0x001C: Group 0 trigger source control register */
+ uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */
+ uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */
+ uint32 GxINTENA[3U]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register */
+ uint32 GxINTFLG[3U]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */
+ uint32 GxINTCR[3U]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */
+ uint32 EVDMACR; /**< 0x004C: Group 0 DMA control register */
+ uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */
+ uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */
+ uint32 BNDCR; /**< 0x0058: Buffer boundary control register */
+ uint32 BNDEND; /**< 0x005C: Buffer boundary end register */
+ uint32 EVSAMP; /**< 0x0060: Group 0 sample window register */
+ uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */
+ uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */
+ uint32 EVSR; /**< 0x006C: Group 0 status register */
+ uint32 G1SR; /**< 0x0070: Group 1 status register */
+ uint32 G2SR; /**< 0x0074: Group 2 status register */
+ uint32 GxSEL[3U]; /**< 0x0078-0x007C: Group 0-2 channel select register */
+ uint32 CALR; /**< 0x0084: Calibration register */
+ uint32 SMSTATE; /**< 0x0088: State machine state register */
+ uint32 LASTCONV; /**< 0x008C: Last conversion register */
+ struct
+ {
+ uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */
+ uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */
+ uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */
+ uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */
+ uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */
+ uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */
+ uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */
+ uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */
+ } GxBUF[3U];
+ uint32 EVEMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */
+ uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */
+ uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */
+ uint32 EVTDIR; /**< 0x00FC: Event pin direction register */
+ uint32 EVTOUT; /**< 0x0100: Event pin digital output register */
+ uint32 EVTIN; /**< 0x0104: Event pin digital input register */
+ uint32 EVTSET; /**< 0x0108: Event pin set register */
+ uint32 EVTCLR; /**< 0x010C: Event pin clear register */
+ uint32 EVTPDR; /**< 0x0110: Event pin open drain register */
+ uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */
+ uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */
+ uint32 EVSAMPDISEN; /**< 0x011C: Group 0 sample discharge register */
+ uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */
+ uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */
+ uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */
+ uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */
+ uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */
+ uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */
+ uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */
+ uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */
+ uint32 rsvd1; /**< 0x0140: Reserved */
+ uint32 rsvd2; /**< 0x0144: Reserved */
+ uint32 rsvd3; /**< 0x0148: Reserved */
+ uint32 rsvd4; /**< 0x014C: Reserved */
+ uint32 rsvd5; /**< 0x0150: Reserved */
+ uint32 rsvd6; /**< 0x0154: Reserved */
+ uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */
+ uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */
+ uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */
+ uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */
+ uint32 GxFIFORESETCR[3U]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register */
+ uint32 EVRAMADDR; /**< 0x0174: Group 0 RAM pointer register */
+ uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */
+ uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */
+ uint32 PARCR; /**< 0x0180: Parity control register */
+ uint32 PARADDR; /**< 0x0184: Parity error address register */
+ uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */
+ uint32 rsvd7; /**< 0x018C: Reserved */
+ uint32 ADEVCHNSELMODECTRL; /**< 0x0190: Event Group Channel Selection Mode Control Register */
+ uint32 ADG1CHNSELMODECTRL; /**< 0x0194: Group1 Channel Selection Mode Control Register */
+ uint32 ADG2CHNSELMODECTRL; /**< 0x0198: Group2 Channel Selection Mode Control Register */
+ uint32 ADEVCURRCOUNT; /**< 0x019C: Event Group Current Count Register */
+ uint32 ADEVMAXCOUNT; /**< 0x01A0: Event Group Max Count Register */
+ uint32 ADG1CURRCOUNT; /**< 0x01A4: Group1 Current Count Register */
+ uint32 ADG1MAXCOUNT; /**< 0x01A8: Group1 Max Count Register */
+ uint32 ADG2CURRCOUNT; /**< 0x01AC: Group2 Current Count Register */
+ uint32 ADG2MAXCOUNT; /**< 0x01B0: Group2 Max Count Register */
+} adcBASE_t;
+
+
+/** @struct adcLUTEntry
+* @brief ADC Look-Up Table Entry
+*
+* This type is used to access ADC Look-Up Table Entry
+*/
+/** @typedef adcLUTEntry_t
+* @brief ADC Look-Up Table Entry
+*
+* This type is used to access the Look-Up Table Entry.
+*/
+typedef struct adcLUTEntry
+{
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ uint8 EV_INT_CHN_MUX_SEL;
+ uint8 EV_EXT_CHN_MUX_SEL;
+ uint16 rsvd;
+#else
+ uint16 rsvd;
+ uint8 EV_EXT_CHN_MUX_SEL;
+ uint8 EV_INT_CHN_MUX_SEL;
+#endif
+}adcLUTEntry_t;
+
+
+/** @struct adcLUT
+* @brief ADC Look-Up Table
+*
+* This type is used to access ADC Look-Up Table
+*/
+/** @typedef adcLUT_t
+* @brief ADC Look-Up Table
+*
+* This type is used to access the ADC Look-Up Table.
+*/
+typedef volatile struct adcLUT
+{
+ adcLUTEntry_t eventGroup[32];
+ adcLUTEntry_t Group1[32];
+ adcLUTEntry_t Group2[32];
+} adcLUT_t;
+
+
+/** @def adcREG1
+* @brief ADC1 Register Frame Pointer
+*
+* This pointer is used by the ADC driver to access the ADC1 registers.
+*/
+#define adcREG1 ((adcBASE_t *)0xFFF7C000U)
+
+/** @def adcREG2
+* @brief ADC2 Register Frame Pointer
+*
+* This pointer is used by the ADC driver to access the ADC2 registers.
+*/
+#define adcREG2 ((adcBASE_t *)0xFFF7C200U)
+
+/** @def adcRAM1
+* @brief ADC1 RAM Pointer
+*
+* This pointer is used by the ADC driver to access the ADC1 RAM.
+*/
+#define adcRAM1 (*(volatile uint32 *)0xFF3E0000U)
+
+/** @def adcRAM2
+* @brief ADC2 RAM Pointer
+*
+* This pointer is used by the ADC driver to access the ADC2 RAM.
+*/
+#define adcRAM2 (*(volatile uint32 *)0xFF3A0000U)
+
+/** @def adcPARRAM1
+* @brief ADC1 Parity RAM Pointer
+*
+* This pointer is used by the ADC driver to access the ADC1 Parity RAM.
+*/
+#define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U))
+
+/** @def adcPARRAM2
+* @brief ADC2 Parity RAM Pointer
+*
+* This pointer is used by the ADC driver to access the ADC2 Parity RAM.
+*/
+#define adcPARRAM2 (*(volatile uint32 *)(0xFF3A0000U + 0x1000U))
+
+/** @def adcLUT1
+* @brief ADC1 Look-Up Table
+*
+* This pointer is used by the ADC driver to access the ADC1 Look-Up Table.
+*/
+#define adcLUT1 ((adcLUT_t *) 0xFF3E2000U)
+
+/** @def adcLUT2
+* @brief ADC2 Look-Up Table
+*
+* This pointer is used by the ADC driver to access the ADC2 Look-Up Table.
+*/
+#define adcLUT2 ((adcLUT_t *) 0xFF3A2000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_can.h
===================================================================
diff -u
--- firmware/include/reg_can.h (revision 0)
+++ firmware/include/reg_can.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,208 @@
+/** @file reg_can.h
+* @brief CAN Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the CAN driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_CAN_H__
+#define __REG_CAN_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Can Register Frame Definition */
+/** @struct canBase
+* @brief CAN Register Frame Definition
+*
+* This type is used to access the CAN Registers.
+*/
+/** @typedef canBASE_t
+* @brief CAN Register Frame Type Definition
+*
+* This type is used to access the CAN Registers.
+*/
+typedef volatile struct canBase
+{
+ uint32 CTL; /**< 0x0000: Control Register */
+ uint32 ES; /**< 0x0004: Error and Status Register */
+ uint32 EERC; /**< 0x0008: Error Counter Register */
+ uint32 BTR; /**< 0x000C: Bit Timing Register */
+ uint32 INT; /**< 0x0010: Interrupt Register */
+ uint32 TEST; /**< 0x0014: Test Register */
+ uint32 rsvd1; /**< 0x0018: Reserved */
+ uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */
+ uint32 rsvd2[24]; /**< 0x002C - 0x7C: Reserved */
+ uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */
+ uint32 TXRQX; /**< 0x0084: Transmission Request X Register */
+ uint32 TXRQx[4U]; /**< 0x0088-0x0094: Transmission Request Registers */
+ uint32 NWDATX; /**< 0x0098: New Data X Register */
+ uint32 NWDATx[4U]; /**< 0x009C-0x00A8: New Data Registers */
+ uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */
+ uint32 INTPNDx[4U]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */
+ uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */
+ uint32 MSGVALx[4U]; /**< 0x00C4-0x00D0: Message Valid Registers */
+ uint32 rsvd3; /**< 0x00D4: Reserved */
+ uint32 INTMUXx[4U]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */
+ uint32 rsvd4[6]; /**< 0x00E8: Reserved */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */
+ uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */
+ uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */
+ uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */
+#else
+ uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */
+ uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */
+ uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */
+ uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */
+#endif
+ uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */
+ uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */
+ uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */
+ uint8 IF1DATx[8U]; /**< 0x0110-0x0114: IF1 Data A and B Registers */
+ uint32 rsvd5[2]; /**< 0x0118: Reserved */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */
+ uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */
+ uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */
+ uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */
+#else
+ uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */
+ uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */
+ uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */
+ uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */
+#endif
+ uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */
+ uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */
+ uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */
+ uint8 IF2DATx[8U]; /**< 0x0130-0x0134: IF2 Data A and B Registers */
+ uint32 rsvd6[2]; /**< 0x0138: Reserved */
+ uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */
+ uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */
+ uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */
+ uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */
+ uint8 IF3DATx[8U]; /**< 0x0150-0x0154: IF3 Data A and B Registers */
+ uint32 rsvd7[2]; /**< 0x0158: Reserved */
+ uint32 IF3UEy[4U]; /**< 0x0160-0x016C: IF3 Update Enable Registers */
+ uint32 rsvd8[28]; /**< 0x0170: Reserved */
+ uint32 TIOC; /**< 0x01E0: TX IO Control Register */
+ uint32 RIOC; /**< 0x01E4: RX IO Control Register */
+} canBASE_t;
+
+
+/** @def canREG1
+* @brief CAN1 Register Frame Pointer
+*
+* This pointer is used by the CAN driver to access the CAN1 registers.
+*/
+#define canREG1 ((canBASE_t *)0xFFF7DC00U)
+
+/** @def canREG2
+* @brief CAN2 Register Frame Pointer
+*
+* This pointer is used by the CAN driver to access the CAN2 registers.
+*/
+#define canREG2 ((canBASE_t *)0xFFF7DE00U)
+
+/** @def canREG3
+* @brief CAN3 Register Frame Pointer
+*
+* This pointer is used by the CAN driver to access the CAN3 registers.
+*/
+#define canREG3 ((canBASE_t *)0xFFF7E000U)
+
+/** @def canRAM1
+* @brief CAN1 Mailbox RAM Pointer
+*
+* This pointer is used by the CAN driver to access the CAN1 RAM.
+*/
+#define canRAM1 (*(volatile uint32 *)0xFF1E0000U)
+
+/** @def canRAM2
+* @brief CAN2 Mailbox RAM Pointer
+*
+* This pointer is used by the CAN driver to access the CAN2 RAM.
+*/
+#define canRAM2 (*(volatile uint32 *)0xFF1C0000U)
+
+/** @def canRAM3
+* @brief CAN3 Mailbox RAM Pointer
+*
+* This pointer is used by the CAN driver to access the CAN3 RAM.
+*/
+#define canRAM3 (*(volatile uint32 *)0xFF1A0000U)
+
+/** @def canPARRAM1
+* @brief CAN1 Mailbox Parity RAM Pointer
+*
+* This pointer is used by the CAN driver to access the CAN1 Parity RAM
+* for testing RAM parity error detect logic.
+*/
+#define canPARRAM1 (*(volatile uint32 *)(0xFF1E0000U + 0x10U))
+
+/** @def canPARRAM2
+* @brief CAN2 Mailbox Parity RAM Pointer
+*
+* This pointer is used by the CAN driver to access the CAN2 Parity RAM
+* for testing RAM parity error detect logic.
+*/
+#define canPARRAM2 (*(volatile uint32 *)(0xFF1C0000U + 0x10U))
+
+/** @def canPARRAM3
+* @brief CAN3 Mailbox Parity RAM Pointer
+*
+* This pointer is used by the CAN driver to access the CAN3 Parity RAM
+* for testing RAM parity error detect logic.
+*/
+#define canPARRAM3 (*(volatile uint32 *)(0xFF1A0000U + 0x10U))
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_crc.h
===================================================================
diff -u
--- firmware/include/reg_crc.h (revision 0)
+++ firmware/include/reg_crc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,127 @@
+/** @file reg_crc.h
+* @brief CRC Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the CRC driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_CRC_H__
+#define __REG_CRC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Crc Register Frame Definition */
+/** @struct crcBase
+* @brief CRC Register Frame Definition
+*
+* This type is used to access the CRC Registers.
+*/
+/** @typedef crcBASE_t
+* @brief CRC Register Frame Type Definition
+*
+* This type is used to access the CRC Registers.
+*/
+typedef volatile struct crcBase
+{
+ uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/
+ uint32 rvd1; /**< 0x0004: reserved >**/
+ uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/
+ uint32 rvd2; /**< 0x000C: reserved >**/
+ uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/
+ uint32 rvd3; /**< 0x0014: reserved >**/
+ uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/
+ uint32 rvd4; /**< 0x001C: reserved >**/
+ uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/
+ uint32 rvd5; /**< 0x0024: reserved >**/
+ uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/
+ uint32 rvd6; /**< 0x002C: reserved >**/
+ uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/
+ uint32 rvd7; /**< 0x0034: reserved >**/
+ uint32 BUSY; /**< 0x0038: CRC Busy Register >**/
+ uint32 rvd8; /**< 0x003C: reserved >**/
+ uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/
+ uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/
+ uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/
+ uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/
+ uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/
+ uint32 rvd9[3]; /**< 0x0054: reserved >**/
+ uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/
+ uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/
+ uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/
+ uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/
+ uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/
+ uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/
+ uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/
+ uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/
+ uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/
+ uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/
+ uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/
+ uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/
+ uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/
+ uint32 rvd10[3]; /**< 0x0094: reserved >**/
+ uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/
+ uint32 PSA_SIGREGH2; /**< 0x00A4: Channel 2 PSA signature high register >**/
+ uint32 REGL2; /**< 0x00A8: Channel 2 CRC value low register >**/
+ uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/
+ uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/
+ uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/
+ uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/
+ uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/
+}crcBASE_t;
+
+/** @def crcREG
+* @brief CRC Register Frame Pointer
+*
+* This pointer is used by the CRC driver to access the CRC registers.
+*/
+#define crcREG ((crcBASE_t *)0xFE000000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_dcc.h
===================================================================
diff -u
--- firmware/include/reg_dcc.h (revision 0)
+++ firmware/include/reg_dcc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,103 @@
+/** @file reg_dcc.h
+* @brief DCC Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the DCC driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_DCC_H__
+#define __REG_DCC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Dcc Register Frame Definition */
+/** @struct dccBase
+* @brief DCC Base Register Definition
+*
+* This structure is used to access the DCC module registers.
+*/
+/** @typedef dccBASE_t
+* @brief DCC Register Frame Type Definition
+*
+* This type is used to access the DCC Registers.
+*/
+typedef volatile struct dccBase
+{
+ uint32 GCTRL; /**< 0x0000: DCC Control Register */
+ uint32 REV; /**< 0x0004: DCC Revision Id Register */
+ uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */
+ uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */
+ uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */
+ uint32 STAT; /**< 0x0014: DCC Status Register */
+ uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */
+ uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */
+ uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */
+ uint32 CNT1CLKSRC; /**< 0x0024: DCC Counter1 Clock Source Selection Register */
+ uint32 CNT0CLKSRC; /**< 0x0028: DCC Counter0 Clock Source Selection Register */
+} dccBASE_t;
+
+
+/** @def dccREG1
+* @brief DCC1 Register Frame Pointer
+*
+* This pointer is used by the DCC driver to access the dcc2 module registers.
+*/
+#define dccREG1 ((dccBASE_t *)0xFFFFEC00U)
+
+
+/** @def dccREG2
+* @brief DCC2 Register Frame Pointer
+*
+* This pointer is used by the DCC driver to access the dcc2 module registers.
+*/
+#define dccREG2 ((dccBASE_t *)0xFFFFF400U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_dma.h
===================================================================
diff -u
--- firmware/include/reg_dma.h (revision 0)
+++ firmware/include/reg_dma.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,185 @@
+/** @file reg_dma.h
+* @brief DMA Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the DMA driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_DMA_H__
+#define __REG_DMA_H__
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* DMA Register Frame Definition */
+/** @struct dmaBase
+* @brief DMA Register Frame Definition
+*
+* This type is used to access the DMA Registers.
+*/
+/** @struct dmaBASE_t
+* @brief DMA Register Definition
+*
+* This structure is used to access the DMA module egisters.
+*/
+typedef volatile struct dmaBase
+{
+
+ uint32 GCTRL; /**< 0x0000: Global Control Register */
+ uint32 PEND; /**< 0x0004: Channel Pending Register */
+ uint32 FBREG; /**< 0x0008: Fall Back Register */
+ uint32 DMASTAT; /**< 0x000C: Status Register */
+ uint32 rsvd1; /**< 0x0010: Reserved */
+ uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */
+ uint32 rsvd2; /**< 0x0018: Reserved */
+ uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */
+ uint32 rsvd3; /**< 0x0020: Reserved */
+ uint32 SWCHENAS; /**< 0x0024: SW Channel Enable Set */
+ uint32 rsvd4; /**< 0x0028: Reserved */
+ uint32 SWCHENAR; /**< 0x002C: SW Channel Enable Reset */
+ uint32 rsvd5; /**< 0x0030: Reserved */
+ uint32 CHPRIOS; /**< 0x0034: Channel Priority Set */
+ uint32 rsvd6; /**< 0x0038: Reserved */
+ uint32 CHPRIOR; /**< 0x003C: Channel Priority Reset */
+ uint32 rsvd7; /**< 0x0040: Reserved */
+ uint32 GCHIENAS; /**< 0x0044: Global Channel Interrupt Enable Set */
+ uint32 rsvd8; /**< 0x0048: Reserved */
+ uint32 GCHIENAR; /**< 0x004C: Global Channel Interrupt Enable Reset */
+ uint32 rsvd9; /**< 0x0050: Reserved */
+ uint32 DREQASI[8U]; /**< 0x0054 - 0x70: DMA Request Assignment Register */
+ uint32 rsvd10[8U]; /**< 0x0074 - 0x90: Reserved */
+ uint32 PAR[4U]; /**< 0x0094 - 0xA0: Port Assignment Register */
+ uint32 rsvd11[4U]; /**< 0x00A4 - 0xB0: Reserved */
+ uint32 FTCMAP; /**< 0x00B4: FTC Interrupt Mapping Register */
+ uint32 rsvd12; /**< 0x00B8: Reserved */
+ uint32 LFSMAP; /**< 0x00BC: LFS Interrupt Mapping Register */
+ uint32 rsvd13; /**< 0x00C0: Reserved */
+ uint32 HBCMAP; /**< 0x00C4: HBC Interrupt Mapping Register */
+ uint32 rsvd14; /**< 0x00C8: Reserved */
+ uint32 BTCMAP; /**< 0x00CC: BTC Interrupt Mapping Register */
+ uint32 rsvd15; /**< 0x00D0: Reserved */
+ uint32 BERMAP; /**< 0x00D4: BER Interrupt Mapping Register */
+ uint32 rsvd16; /**< 0x00D8: Reserved */
+ uint32 FTCINTENAS; /**< 0x00DC: FTC Interrupt Enable Set */
+ uint32 rsvd17; /**< 0x00E0: Reserved */
+ uint32 FTCINTENAR; /**< 0x00E4: FTC Interrupt Enable Reset */
+ uint32 rsvd18; /**< 0x00E8: Reserved */
+ uint32 LFSINTENAS; /**< 0x00EC: LFS Interrupt Enable Set */
+ uint32 rsvd19; /**< 0x00F0: Reserved */
+ uint32 LFSINTENAR; /**< 0x00F4: LFS Interrupt Enable Reset */
+ uint32 rsvd20; /**< 0x00F8: Reserved */
+ uint32 HBCINTENAS; /**< 0x00FC: HBC Interrupt Enable Set */
+ uint32 rsvd21; /**< 0x0100: Reserved */
+ uint32 HBCINTENAR; /**< 0x0104: HBC Interrupt Enable Reset */
+ uint32 rsvd22; /**< 0x0108: Reserved */
+ uint32 BTCINTENAS; /**< 0x010C: BTC Interrupt Enable Set */
+ uint32 rsvd23; /**< 0x0110: Reserved */
+ uint32 BTCINTENAR; /**< 0x0114: BTC Interrupt Enable Reset */
+ uint32 rsvd24; /**< 0x0118: Reserved */
+ uint32 GINTFLAG; /**< 0x011C: Global Interrupt Flag Register */
+ uint32 rsvd25; /**< 0x0120: Reserved */
+ uint32 FTCFLAG; /**< 0x0124: FTC Interrupt Flag Register */
+ uint32 rsvd26; /**< 0x0128: Reserved */
+ uint32 LFSFLAG; /**< 0x012C: LFS Interrupt Flag Register */
+ uint32 rsvd27; /**< 0x0130: Reserved */
+ uint32 HBCFLAG; /**< 0x0134: HBC Interrupt Flag Register */
+ uint32 rsvd28; /**< 0x0138: Reserved */
+ uint32 BTCFLAG; /**< 0x013C: BTC Interrupt Flag Register */
+ uint32 rsvd29; /**< 0x0140: Reserved */
+ uint32 BERFLAG; /**< 0x0144: BER Interrupt Flag Register */
+ uint32 rsvd30; /**< 0x0148: Reserved */
+ uint32 FTCAOFFSET; /**< 0x014C: FTCA Interrupt Channel Offset Register */
+ uint32 LFSAOFFSET; /**< 0x0150: LFSA Interrupt Channel Offset Register */
+ uint32 HBCAOFFSET; /**< 0x0154: HBCA Interrupt Channel Offset Register */
+ uint32 BTCAOFFSET; /**< 0x0158: BTCA Interrupt Channel Offset Register */
+ uint32 BERAOFFSET; /**< 0x015C: BERA Interrupt Channel Offset Register */
+ uint32 FTCBOFFSET; /**< 0x0160: FTCB Interrupt Channel Offset Register */
+ uint32 LFSBOFFSET; /**< 0x0164: LFSB Interrupt Channel Offset Register */
+ uint32 HBCBOFFSET; /**< 0x0168: HBCB Interrupt Channel Offset Register */
+ uint32 BTCBOFFSET; /**< 0x016C: BTCB Interrupt Channel Offset Register */
+ uint32 BERBOFFSET; /**< 0x0170: BERB Interrupt Channel Offset Register */
+ uint32 rsvd31; /**< 0x0174: Reserved */
+ uint32 PTCRL; /**< 0x0178: Port Control Register */
+ uint32 RTCTRL; /**< 0x017C: RAM Test Control Register */
+ uint32 DCTRL; /**< 0x0180: Debug Control */
+ uint32 WPR; /**< 0x0184: Watch Point Register */
+ uint32 WMR; /**< 0x0188: Watch Mask Register */
+ uint32 PAACSADDR; /**< 0x018C: */
+ uint32 PAACDADDR; /**< 0x0190: */
+ uint32 PAACTC; /**< 0x0194: */
+ uint32 PBACSADDR; /**< 0x0198: Port B Active Channel Source Address Register */
+ uint32 PBACDADDR; /**< 0x019C: Port B Active Channel Destination Address Register */
+ uint32 PBACTC; /**< 0x01A0: Port B Active Channel Transfer Count Register */
+ uint32 rsvd32; /**< 0x01A4: Reserved */
+ uint32 DMAPCR; /**< 0x01A8: Parity Control Register */
+ uint32 DMAPAR; /**< 0x01AC: DMA Parity Error Address Register */
+ uint32 DMAMPCTRL; /**< 0x01B0: DMA Memory Protection Control Register */
+ uint32 DMAMPST; /**< 0x01B4: DMA Memory Protection Status Register */
+ struct
+ {
+ uint32 STARTADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register */
+ uint32 ENDADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register */
+ }DMAMPR[4U];
+} dmaBASE_t;
+
+
+/** @def dmaREG
+* @brief DMA1 Register Frame Pointer
+*
+* This pointer is used by the DMA driver to access the DMA module registers.
+*/
+#define dmaREG ((dmaBASE_t *)0xFFFFF000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/reg_ecap.h
===================================================================
diff -u
--- firmware/include/reg_ecap.h (revision 0)
+++ firmware/include/reg_ecap.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,159 @@
+/** @file reg_ecap.h
+* @brief ECAP Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the ECAP driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_ECAP_H__
+#define __REG_ECAP_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Ecap Register Frame Definition */
+/** @struct ecapBASE
+* @brief ECAP Register Frame Definition
+*
+* This type is used to access the ECAP Registers.
+*/
+/** @typedef ecapBASE_t
+* @brief ECAP Register Frame Type Definition
+*
+* This type is used to access the ECAP Registers.
+*/
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+
+typedef volatile struct ecapBASE
+ {
+ uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/
+ uint32 CTRPHS; /**< 0x0004 Counter phase Register*/
+ uint32 CAP1; /**< 0x0008 Capture 1 Register*/
+ uint32 CAP2; /**< 0x000C Capture 2 Register*/
+ uint32 CAP3; /**< 0x0010 Capture 3 Register*/
+ uint32 CAP4; /**< 0x0014 Capture 4 Register*/
+ uint16 rsvd1[8U]; /**< 0x0018 Reserved*/
+ uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/
+ uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/
+ uint16 ECEINT; /**< 0x002C Interrupt enable Register*/
+ uint16 ECFLG; /**< 0x002E Interrupt flags Register*/
+ uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/
+ uint16 ECFRC; /**< 0x0032 Interrupt force Register*/
+ uint16 rsvd2[6U]; /**< 0x0034 Reserved*/
+
+}ecapBASE_t;
+
+#else
+
+typedef volatile struct ecapBASE
+ {
+ uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/
+ uint32 CTRPHS; /**< 0x0004 Counter phase Register*/
+ uint32 CAP1; /**< 0x0008 Capture 1 Register*/
+ uint32 CAP2; /**< 0x000C Capture 2 Register*/
+ uint32 CAP3; /**< 0x0010 Capture 3 Register*/
+ uint32 CAP4; /**< 0x0014 Capture 4 Register*/
+ uint16 rsvd1[8U]; /**< 0x0018 Reserved*/
+ uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/
+ uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/
+ uint16 ECFLG; /**< 0x002E Interrupt flags Register*/
+ uint16 ECEINT; /**< 0x002C Interrupt enable Register*/
+ uint16 ECFRC; /**< 0x0032 Interrupt force Register*/
+ uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/
+ uint16 rsvd2[6U]; /**< 0x0034 Reserved*/
+
+}ecapBASE_t;
+
+#endif
+/** @def ecapREG1
+* @brief ECAP1 Register Frame Pointer
+*
+* This pointer is used by the ECAP driver to access the ECAP1 registers.
+*/
+#define ecapREG1 ((ecapBASE_t *)0xFCF79300U)
+
+/** @def ecapREG2
+* @brief ECAP2 Register Frame Pointer
+*
+* This pointer is used by the ECAP driver to access the ECAP2 registers.
+*/
+#define ecapREG2 ((ecapBASE_t *)0xFCF79400U)
+
+/** @def ecapREG3
+* @brief ECAP3 Register Frame Pointer
+*
+* This pointer is used by the ECAP driver to access the ECAP3 registers.
+*/
+#define ecapREG3 ((ecapBASE_t *)0xFCF79500U)
+
+/** @def ecapREG4
+* @brief ECAP4 Register Frame Pointer
+*
+* This pointer is used by the ECAP driver to access the ECAP4 registers.
+*/
+#define ecapREG4 ((ecapBASE_t *)0xFCF79600U)
+
+/** @def ecapREG5
+* @brief ECAP5 Register Frame Pointer
+*
+* This pointer is used by the ECAP driver to access the ECAP5 registers.
+*/
+#define ecapREG5 ((ecapBASE_t *)0xFCF79700U)
+
+/** @def ecapREG6
+* @brief ECAP6 Register Frame Pointer
+*
+* This pointer is used by the ECAP driver to access the ECAP6 registers.
+*/
+#define ecapREG6 ((ecapBASE_t *)0xFCF79800U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_efc.h
===================================================================
diff -u
--- firmware/include/reg_efc.h (revision 0)
+++ firmware/include/reg_efc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,96 @@
+/** @file reg_efc.h
+* @brief EFC Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_EFC_H__
+#define __REG_EFC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Efc Register Frame Definition */
+/** @struct efcBase
+* @brief Efc Register Frame Definition
+*
+* This type is used to access the Efc Registers.
+*/
+/** @typedef efcBASE_t
+* @brief Efc Register Frame Type Definition
+*
+* This type is used to access the Efc Registers.
+*/
+typedef volatile struct efcBase
+{
+ uint32 INSTRUCTION; /* 0x0 INSTRUCTION AN DUMPWORD REGISTER */
+ uint32 ADDRESS; /* 0x4 ADDRESS REGISTER */
+ uint32 DATA_UPPER; /* 0x8 DATA UPPER REGISTER */
+ uint32 DATA_LOWER; /* 0xc DATA LOWER REGISTER */
+ uint32 SYSTEM_CONFIG; /* 0x10 SYSTEM CONFIG REGISTER */
+ uint32 SYSTEM_STATUS; /* 0x14 SYSTEM STATUS REGISTER */
+ uint32 ACCUMULATOR; /* 0x18 ACCUMULATOR REGISTER */
+ uint32 BOUNDARY; /* 0x1C BOUNDARY REGISTER */
+ uint32 KEY_FLAG; /* 0x20 KEY FLAG REGISTER */
+ uint32 KEY; /* 0x24 KEY REGISTER */
+ uint32 rsvd1; /* 0x28 RESERVED */
+ uint32 PINS; /* 0x2C PINS REGISTER */
+ uint32 CRA; /* 0x30 CRA */
+ uint32 READ; /* 0x34 READ REGISTER */
+ uint32 PROGRAMME; /* 0x38 PROGRAMME REGISTER */
+ uint32 ERROR; /* 0x3C ERROR STATUS REGISTER */
+ uint32 SINGLE_BIT; /* 0x40 SINGLE BIT ERROR */
+ uint32 TWO_BIT_ERROR; /* 0x44 DOUBLE BIT ERROR */
+ uint32 SELF_TEST_CYCLES; /* 0x48 SELF TEST CYCLEX */
+ uint32 SELF_TEST_SIGN; /* 0x4C SELF TEST SIGNATURE */
+} efcBASE_t;
+
+#define efcREG ((efcBASE_t *)0xFFF8C000U)
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_eqep.h
===================================================================
diff -u
--- firmware/include/reg_eqep.h (revision 0)
+++ firmware/include/reg_eqep.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,151 @@
+/** @file reg_eqep.h
+* @brief EQEP Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the EQEP driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_EQEP_H__
+#define __REG_EQEP_H__
+
+#include "sys_common.h"
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Eqep Register Frame Definition */
+/** @struct eqepBASE
+* @brief EQEP Register Frame Definition
+*
+* This type is used to access the EQEP Registers.
+*/
+/** @typedef eqepBASE_t
+* @brief EQEP Register Frame Type Definition
+*
+* This type is used to access the EQEP Registers.
+*/
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+
+typedef volatile struct eqepBASE
+{
+ uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/
+ uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/
+ uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/
+ uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/
+ uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/
+ uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/
+ uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/
+ uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/
+ uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/
+ uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/
+ uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/
+ uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/
+ uint16 QEPCTL; /*< 0x002A eQEP Control*/
+ uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/
+ uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/
+ uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/
+ uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/
+ uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/
+ uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/
+ uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/
+ uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/
+ uint16 QCPRD; /*< 0x003C eQEP Capture Period*/
+ uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/
+ uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/
+ uint16 rsvd_1; /*< 0x0042 Reserved*/
+} eqepBASE_t;
+
+#else
+
+typedef volatile struct eqepBASE
+{
+ uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/
+ uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/
+ uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/
+ uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/
+ uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/
+ uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/
+ uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/
+ uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/
+ uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/
+ uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/
+ uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/
+ uint16 QEPCTL; /*< 0x002A eQEP Control*/
+ uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/
+ uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/
+ uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/
+ uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/
+ uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/
+ uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/
+ uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/
+ uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/
+ uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/
+ uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/
+ uint16 QCPRD; /*< 0x003C eQEP Capture Period*/
+ uint16 rsvd_1; /*< 0x0042 Reserved*/
+ uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/
+} eqepBASE_t;
+
+#endif
+
+/** @def eqepREG1
+* @brief eQEP1 Register Frame Pointer
+*
+* This pointer is used by the eQEP driver to access the eQEP1 registers.
+*/
+#define eqepREG1 ((eqepBASE_t *)0xFCF79900U)
+
+/** @def eqepREG2
+* @brief eQEP2 Register Frame Pointer
+*
+* This pointer is used by the eQEP driver to access the eQEP2 registers.
+*/
+#define eqepREG2 ((eqepBASE_t *)0xFCF79A00U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_esm.h
===================================================================
diff -u
--- firmware/include/reg_esm.h (revision 0)
+++ firmware/include/reg_esm.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,106 @@
+/** @file reg_esm.h
+* @brief ESM Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the ESM driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_ESM_H__
+#define __REG_ESM_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Esm Register Frame Definition */
+/** @struct esmBase
+* @brief Esm Register Frame Definition
+*
+* This type is used to access the Esm Registers.
+*/
+/** @typedef esmBASE_t
+* @brief Esm Register Frame Type Definition
+*
+* This type is used to access the Esm Registers.
+*/
+typedef volatile struct esmBase
+{
+ uint32 EEPAPR1; /* 0x0000 */
+ uint32 DEPAPR1; /* 0x0004 */
+ uint32 IESR1; /* 0x0008 */
+ uint32 IECR1; /* 0x000C */
+ uint32 ILSR1; /* 0x0010 */
+ uint32 ILCR1; /* 0x0014 */
+ uint32 SR1[3U]; /* 0x0018, 0x001C, 0x0020 */
+ uint32 EPSR; /* 0x0024 */
+ uint32 IOFFHR; /* 0x0028 */
+ uint32 IOFFLR; /* 0x002C */
+ uint32 LTCR; /* 0x0030 */
+ uint32 LTCPR; /* 0x0034 */
+ uint32 EKR; /* 0x0038 */
+ uint32 SSR2; /* 0x003C */
+ uint32 IEPSR4; /* 0x0040 */
+ uint32 IEPCR4; /* 0x0044 */
+ uint32 IESR4; /* 0x0048 */
+ uint32 IECR4; /* 0x004C */
+ uint32 ILSR4; /* 0x0050 */
+ uint32 ILCR4; /* 0x0054 */
+ uint32 SR4[3U]; /* 0x0058, 0x005C, 0x0060 */
+} esmBASE_t;
+
+/** @def esmREG
+* @brief Esm Register Frame Pointer
+*
+* This pointer is used by the Esm driver to access the Esm registers.
+*/
+#define esmREG ((esmBASE_t *)0xFFFFF500U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_etpwm.h
===================================================================
diff -u
--- firmware/include/reg_etpwm.h (revision 0)
+++ firmware/include/reg_etpwm.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,225 @@
+/** @file reg_etpwm.h
+* @brief ETPWM Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the ETPWM driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_ETPWM_H__
+#define __REG_ETPWM_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* ETPWM Register Frame Definition */
+/** @struct etpwmBASE
+* @brief ETPWM Register Frame Definition
+*
+* This type is used to access the ETPWM Registers.
+*/
+/** @typedef etpwmBASE_t
+* @brief ETPWM Register Frame Type Definition
+*
+* This type is used to access the ETPWM Registers.
+*/
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+
+typedef volatile struct etpwmBASE
+{
+ uint16 TBCTL; /**< 0x0000 Time-Base Control Register*/
+ uint16 TBSTS; /**< 0x0002 Time-Base Status Register*/
+ uint16 rsvd1; /**< 0x0004 Reserved*/
+ uint16 TBPHS; /**< 0x0006 Time-Base Phase Register*/
+ uint16 TBCTR; /**< 0x0008 Time-Base Counter Register*/
+ uint16 TBPRD; /**< 0x000A Time-Base Period Register*/
+ uint16 rsvd2; /**< 0x000C Reserved*/
+ uint16 CMPCTL; /**< 0x000E Counter-Compare Control Register*/
+ uint16 rsvd3; /**< 0x0010 Reserved*/
+ uint16 CMPA; /**< 0x0012 Counter-Compare A Register*/
+ uint16 CMPB; /**< 0x0014 Counter-Compare B Register*/
+ uint16 AQCTLA; /**< 0x0016 Action-Qualifier Control Register for Output A (ETPWMxA)*/
+ uint16 AQCTLB; /**< 0x0018 Action-Qualifier Control Register for Output B (ETPWMxB)*/
+ uint16 AQSFRC; /**< 0x001A Action-Qualifier Software Force Register*/
+ uint16 AQCSFRC; /**< 0x001C Action-Qualifier Continuous S/W Force Register Set*/
+ uint16 DBCTL; /**< 0x001E Dead-Band Generator Control Register*/
+ uint16 DBRED; /**< 0x0020 Dead-Band Generator Rising Edge Delay Count Register*/
+ uint16 DBFED; /**< 0x0022 Dead-Band Generator Falling Edge Delay Count Register*/
+ uint16 TZSEL; /**< 0x0024 Trip-Zone Select Register*/
+ uint16 TZDCSEL; /**< 0x0026 Trip Zone Digital Compare Select Register*/
+ uint16 TZCTL; /**< 0x0028 Trip-Zone Control Register*/
+ uint16 TZEINT; /**< 0x002A Trip-Zone Enable Interrupt Register*/
+ uint16 TZFLG; /**< 0x002C Trip-Zone Flag Register*/
+ uint16 TZCLR; /**< 0x002E Trip-Zone Clear Register*/
+ uint16 TZFRC; /**< 0x0030 Trip-Zone Force Register*/
+ uint16 ETSEL; /**< 0x0032 Event-Trigger Selection Register*/
+ uint16 ETPS; /**< 0x0034 Event-Trigger Pre-Scale Register*/
+ uint16 ETFLG; /**< 0x0036 Event-Trigger Flag Register*/
+ uint16 ETCLR; /**< 0x0038 Event-Trigger Clear Register*/
+ uint16 ETFRC; /**< 0x003A Event-Trigger Force Register*/
+ uint16 PCCTL; /**< 0x003C PWM-Chopper Control Register*/
+ uint16 rsvd4; /**< 0x003E Reserved*/
+ uint16 rsvd5[16U]; /**< 0x0040 Reserved*/
+ uint16 DCTRIPSEL; /**< 0x0060 Digital Compare Trip Select Register*/
+ uint16 DCACTL; /**< 0x0062 Digital Compare A Control Register*/
+ uint16 DCBCTL; /**< 0x0064 Digital Compare B Control Register*/
+ uint16 DCFCTL; /**< 0x0066 Digital Compare Filter Control Register*/
+ uint16 DCCAPCTL; /**< 0x0068 Digital Compare Capture Control Register*/
+ uint16 DCFOFFSET; /**< 0x006A Digital Compare Filter Offset Register*/
+ uint16 DCFOFFSETCNT; /**< 0x006C Digital Compare Filter Offset Counter Register*/
+ uint16 DCFWINDOW; /**< 0x006E Digital Compare Filter Window Register*/
+ uint16 DCFWINDOWCNT; /**< 0x0070 Digital Compare Filter Window Counter Register*/
+ uint16 DCCAP; /**< 0x0072 Digital Compare Counter Capture Register*/
+} etpwmBASE_t;
+
+#else
+
+typedef volatile struct etpwmBASE
+{
+ uint16 TBSTS; /**< 0x0000 Time-Base Status Register*/
+ uint16 TBCTL; /**< 0x0002 Time-Base Control Register*/
+ uint16 TBPHS; /**< 0x0004 Time-Base Phase Register*/
+ uint16 rsvd1; /**< 0x0006 Reserved*/
+ uint16 TBPRD; /**< 0x0008 Time-Base Period Register*/
+ uint16 TBCTR; /**< 0x000A Time-Base Counter Register*/
+ uint16 CMPCTL; /**< 0x000C Counter-Compare Control Register*/
+ uint16 rsvd2; /**< 0x000E Reserved*/
+ uint16 CMPA; /**< 0x0010 Counter-Compare A Register*/
+ uint16 rsvd3; /**< 0x0012 Reserved*/
+ uint16 AQCTLA; /**< 0x0014 Action-Qualifier Control Register for Output A (ETPWMxA)*/
+ uint16 CMPB; /**< 0x0016 Counter-Compare B Register*/
+ uint16 AQSFRC; /**< 0x0018 Action-Qualifier Software Force Register*/
+ uint16 AQCTLB; /**< 0x001A Action-Qualifier Control Register for Output B (ETPWMxB)*/
+ uint16 DBCTL; /**< 0x001C Dead-Band Generator Control Register*/
+ uint16 AQCSFRC; /**< 0x001E Action-Qualifier Continuous S/W Force Register Set*/
+ uint16 DBFED; /**< 0x0020 Dead-Band Generator Falling Edge Delay Count Register*/
+ uint16 DBRED; /**< 0x0022 Dead-Band Generator Rising Edge Delay Count Register*/
+ uint16 TZDCSEL; /**< 0x0024 Trip Zone Digital Compare Select Register*/
+ uint16 TZSEL; /**< 0x0026 Trip-Zone Select Register*/
+ uint16 TZEINT; /**< 0x0028 Trip-Zone Enable Interrupt Register*/
+ uint16 TZCTL; /**< 0x002A Trip-Zone Control Register*/
+ uint16 TZCLR; /**< 0x002C Trip-Zone Clear Register*/
+ uint16 TZFLG; /**< 0x002E Trip-Zone Flag Register*/
+ uint16 ETSEL; /**< 0x0030 Event-Trigger Selection Register*/
+ uint16 TZFRC; /**< 0x0032 Trip-Zone Force Register*/
+ uint16 ETFLG; /**< 0x0034 Event-Trigger Flag Register*/
+ uint16 ETPS; /**< 0x0036 Event-Trigger Pre-Scale Register*/
+ uint16 ETFRC; /**< 0x0038 Event-Trigger Force Register*/
+ uint16 ETCLR; /**< 0x003A Event-Trigger Clear Register*/
+ uint16 rsvd4; /**< 0x003C Reserved*/
+ uint16 PCCTL; /**< 0x003E PWM-Chopper Control Register*/
+ uint16 rsvd5[16U]; /**< 0x0040 Reserved*/
+ uint16 DCACTL; /**< 0x0060 Digital Compare A Control Register*/
+ uint16 DCTRIPSEL; /**< 0x0062 Digital Compare Trip Select Register*/
+ uint16 DCFCTL; /**< 0x0064 Digital Compare Filter Control Register*/
+ uint16 DCBCTL; /**< 0x0066 Digital Compare B Control Register*/
+ uint16 DCFOFFSET; /**< 0x0068 Digital Compare Filter Offset Register*/
+ uint16 DCCAPCTL; /**< 0x006A Digital Compare Capture Control Register*/
+ uint16 DCFWINDOW; /**< 0x006C Digital Compare Filter Window Register*/
+ uint16 DCFOFFSETCNT; /**< 0x006E Digital Compare Filter Offset Counter Register*/
+ uint16 DCCAP; /**< 0x0070 Digital Compare Counter Capture Register*/
+ uint16 DCFWINDOWCNT; /**< 0x0072 Digital Compare Filter Window Counter Register*/
+} etpwmBASE_t;
+
+#endif
+
+
+
+/** @def etpwmREG1
+* @brief ETPWM1 Register Frame Pointer
+*
+* This pointer is used by the ETPWM driver to access the ETPWM1 registers.
+*/
+#define etpwmREG1 ((etpwmBASE_t *)0xFCF78C00U)
+
+/** @def etpwmREG2
+* @brief ETPWM2 Register Frame Pointer
+*
+* This pointer is used by the ETPWM driver to access the ETPWM2 registers.
+*/
+#define etpwmREG2 ((etpwmBASE_t *)0xFCF78D00U)
+
+/** @def etpwmREG3
+* @brief ETPWM3 Register Frame Pointer
+*
+* This pointer is used by the ETPWM driver to access the ETPWM3 registers.
+*/
+#define etpwmREG3 ((etpwmBASE_t *)0xFCF78E00U)
+
+/** @def etpwmREG4
+* @brief ETPWM4 Register Frame Pointer
+*
+* This pointer is used by the ETPWM driver to access the ETPWM4 registers.
+*/
+#define etpwmREG4 ((etpwmBASE_t *)0xFCF78F00U)
+
+/** @def etpwmREG5
+* @brief ETPWM5 Register Frame Pointer
+*
+* This pointer is used by the ETPWM driver to access the ETPWM5 registers.
+*/
+#define etpwmREG5 ((etpwmBASE_t *)0xFCF79000U)
+
+/** @def etpwmREG6
+* @brief ETPWM6 Register Frame Pointer
+*
+* This pointer is used by the ETPWM driver to access the ETPWM6 registers.
+*/
+#define etpwmREG6 ((etpwmBASE_t *)0xFCF79100U)
+
+/** @def etpwmREG7
+* @brief ETPWM7 Register Frame Pointer
+*
+* This pointer is used by the ETPWM driver to access the ETPWM7 registers.
+*/
+#define etpwmREG7 ((etpwmBASE_t *)0xFCF79200U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_flash.h
===================================================================
diff -u
--- firmware/include/reg_flash.h (revision 0)
+++ firmware/include/reg_flash.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,134 @@
+/** @file reg_flash.h
+* @brief Flash Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_FLASH_H__
+#define __REG_FLASH_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* Flash Register Frame Definition */
+/** @struct flashWBase
+* @brief Flash Wrapper Register Frame Definition
+*
+* This type is used to access the Flash Wrapper Registers.
+*/
+/** @typedef flashWBASE_t
+* @brief Flash Wrapper Register Frame Type Definition
+*
+* This type is used to access the Flash Wrapper Registers.
+*/
+typedef volatile struct flashWBase
+{
+ uint32 FRDCNTL; /* 0x0000 */
+ uint32 rsvd1; /* 0x0004 */
+ uint32 FEDACCTRL1; /* 0x0008 */
+ uint32 FEDACCTRL2; /* 0x000C */
+ uint32 FCORERRCNT; /* 0x0010 */
+ uint32 FCORERRADD; /* 0x0014 */
+ uint32 FCORERRPOS; /* 0x0018 */
+ uint32 FEDACSTATUS; /* 0x001C */
+ uint32 FUNCERRADD; /* 0x0020 */
+ uint32 FEDACSDIS; /* 0x0024 */
+ uint32 FPRIMADDTAG; /* 0x0028 */
+ uint32 FREDUADDTAG; /* 0x002C */
+ uint32 FBPROT; /* 0x0030 */
+ uint32 FBSE; /* 0x0034 */
+ uint32 FBBUSY; /* 0x0038 */
+ uint32 FBAC; /* 0x003C */
+ uint32 FBFALLBACK; /* 0x0040 */
+ uint32 FBPRDY; /* 0x0044 */
+ uint32 FPAC1; /* 0x0048 */
+ uint32 FPAC2; /* 0x004C */
+ uint32 FMAC; /* 0x0050 */
+ uint32 FMSTAT; /* 0x0054 */
+ uint32 FEMUDMSW; /* 0x0058 */
+ uint32 FEMUDLSW; /* 0x005C */
+ uint32 FEMUECC; /* 0x0060 */
+ uint32 FLOCK; /* 0x0064 */
+ uint32 FEMUADDR; /* 0x0068 */
+ uint32 FDIAGCTRL; /* 0x006C */
+ uint32 FRAWDATAH; /* 0x0070 */
+ uint32 FRAWDATAL; /* 0x0074 */
+ uint32 FRAWECC; /* 0x0078 */
+ uint32 FPAROVR; /* 0x007C */
+ uint32 rsvd2[16U]; /* 0x009C */
+ uint32 FEDACSDIS2; /* 0x00C0 */
+ uint32 rsvd3[15U]; /* 0x00C4 */
+ uint32 rsvd4[13U]; /* 0x0100 */
+ uint32 rsvd5[85U]; /* 0x0134 */
+ uint32 FSMWRENA; /* 0x0288 */
+ uint32 rsvd6[6U]; /* 0x028C */
+ uint32 FSMSECTOR; /* 0x02A4 */
+ uint32 rsvd7[4U]; /* 0x02A8 */
+ uint32 EEPROMCONFIG; /* 0x02B8 */
+ uint32 rsvd8[19U]; /* 0x02BC */
+ uint32 EECTRL1; /* 0x0308 */
+ uint32 EECTRL2; /* 0x030C */
+ uint32 EECORRERRCNT; /* 0x0310 */
+ uint32 EECORRERRADD; /* 0x0314 */
+ uint32 EECORRERRPOS; /* 0x0318 */
+ uint32 EESTATUS; /* 0x031C */
+ uint32 EEUNCERRADD; /* 0x0320 */
+} flashWBASE_t;
+
+/** @def flashWREG
+* @brief Flash Wrapper Register Frame Pointer
+*
+* This pointer is used by the system driver to access the flash wrapper registers.
+*/
+#define flashWREG ((flashWBASE_t *)(0xFFF87000U))
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
Index: firmware/include/reg_gio.h
===================================================================
diff -u
--- firmware/include/reg_gio.h (revision 0)
+++ firmware/include/reg_gio.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,134 @@
+/** @file reg_gio.h
+* @brief GIO Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the GIO driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_GIO_H__
+#define __REG_GIO_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Gio Register Frame Definition */
+/** @struct gioBase
+* @brief GIO Base Register Definition
+*
+* This structure is used to access the GIO module registers.
+*/
+/** @typedef gioBASE_t
+* @brief GIO Register Frame Type Definition
+*
+* This type is used to access the GIO Registers.
+*/
+typedef volatile struct gioBase
+{
+ uint32 GCR0; /**< 0x0000: Global Control Register */
+ uint32 rsvd; /**< 0x0004: Reserved*/
+ uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/
+ uint32 POL; /**< 0x000C: Interrupt Polarity Register */
+ uint32 ENASET; /**< 0x0010: Interrupt Enable Set Register */
+ uint32 ENACLR; /**< 0x0014: Interrupt Enable Clear Register */
+ uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */
+ uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */
+ uint32 FLG; /**< 0x0020: Interrupt Flag Register */
+ uint32 OFF1; /**< 0x0024: Interrupt Offset A Register */
+ uint32 OFF2; /**< 0x0028: Interrupt Offset B Register */
+ uint32 EMU1; /**< 0x002C: Emulation 1 Register */
+ uint32 EMU2; /**< 0x0030: Emulation 2 Register */
+} gioBASE_t;
+
+
+/** @struct gioPort
+* @brief GIO Port Register Definition
+*/
+/** @typedef gioPORT_t
+* @brief GIO Port Register Type Definition
+*
+* This type is used to access the GIO Port Registers.
+*/
+typedef volatile struct gioPort
+{
+ uint32 DIR; /**< 0x0000: Data Direction Register */
+ uint32 DIN; /**< 0x0004: Data Input Register */
+ uint32 DOUT; /**< 0x0008: Data Output Register */
+ uint32 DSET; /**< 0x000C: Data Output Set Register */
+ uint32 DCLR; /**< 0x0010: Data Output Clear Register */
+ uint32 PDR; /**< 0x0014: Open Drain Register */
+ uint32 PULDIS; /**< 0x0018: Pullup Disable Register */
+ uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */
+} gioPORT_t;
+
+
+/** @def gioREG
+* @brief GIO Register Frame Pointer
+*
+* This pointer is used by the GIO driver to access the gio module registers.
+*/
+#define gioREG ((gioBASE_t *)0xFFF7BC00U)
+
+/** @def gioPORTA
+* @brief GIO Port (A) Register Pointer
+*
+* Pointer used by the GIO driver to access PORTA
+*/
+#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)
+
+/** @def gioPORTB
+* @brief GIO Port (B) Register Pointer
+*
+* Pointer used by the GIO driver to access PORTB
+*/
+#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_het.h
===================================================================
diff -u
--- firmware/include/reg_het.h (revision 0)
+++ firmware/include/reg_het.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,203 @@
+/** @file reg_het.h
+* @brief HET Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the HET driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_HET_H__
+#define __REG_HET_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Het Register Frame Definition */
+/** @struct hetBase
+* @brief HET Base Register Definition
+*
+* This structure is used to access the HET module registers.
+*/
+/** @typedef hetBASE_t
+* @brief HET Register Frame Type Definition
+*
+* This type is used to access the HET Registers.
+*/
+
+typedef volatile struct hetBase
+{
+ uint32 GCR; /**< 0x0000: Global control register */
+ uint32 PFR; /**< 0x0004: Prescale factor register */
+ uint32 ADDR; /**< 0x0008: Current address register */
+ uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */
+ uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */
+ uint32 INTENAS; /**< 0x0014: Interrupt enable set register */
+ uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */
+ uint32 EXC1; /**< 0x001C: Exception control register 1 */
+ uint32 EXC2; /**< 0x0020: Exception control register 2 */
+ uint32 PRY; /**< 0x0024: Interrupt priority register */
+ uint32 FLG; /**< 0x0028: Interrupt flag register */
+ uint32 AND; /**< 0x002C: AND share control register */
+ uint32 rsvd1; /**< 0x0030: Reserved */
+ uint32 HRSH; /**< 0x0034: High resolution share register */
+ uint32 XOR; /**< 0x0038: XOR share register */
+ uint32 REQENS; /**< 0x003C: Request enable set register */
+ uint32 REQENC; /**< 0x0040: Request enable clear register */
+ uint32 REQDS; /**< 0x0044: Request destination select register */
+ uint32 rsvd2; /**< 0x0048: Reserved */
+ uint32 DIR; /**< 0x004C: Direction register */
+ uint32 DIN; /**< 0x0050: Data input register */
+ uint32 DOUT; /**< 0x0054: Data output register */
+ uint32 DSET; /**< 0x0058: Data output set register */
+ uint32 DCLR; /**< 0x005C: Data output clear register */
+ uint32 PDR; /**< 0x0060: Open drain register */
+ uint32 PULDIS; /**< 0x0064: Pull disable register */
+ uint32 PSL; /**< 0x0068: Pull select register */
+ uint32 rsvd3; /**< 0x006C: Reserved */
+ uint32 rsvd4; /**< 0x0070: Reserved */
+ uint32 PCR; /**< 0x0074: Parity control register */
+ uint32 PAR; /**< 0x0078: Parity address register */
+ uint32 PPR; /**< 0x007C: Parity pin select register */
+ uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */
+ uint32 SFENA; /**< 0x0084: Suppression filter enable register */
+ uint32 rsvd5; /**< 0x0088: Reserved */
+ uint32 LBPSEL; /**< 0x008C: Loop back pair select register */
+ uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */
+ uint32 PINDIS; /**< 0x0094: Pin disable register */
+} hetBASE_t;
+
+
+/** @struct hetInstructionBase
+* @brief HET Instruction Definition
+*
+* This structure is used to access the HET RAM.
+*/
+/** @typedef hetINSTRUCTION_t
+* @brief HET Instruction Type Definition
+*
+* This type is used to access a HET Instruction.
+*/
+typedef volatile struct hetInstructionBase
+{
+ uint32 Program;
+ uint32 Control;
+ uint32 Data;
+ uint32 rsvd1;
+} hetINSTRUCTION_t;
+
+
+/** @struct hetRamBase
+* @brief HET RAM Definition
+*
+* This structure is used to access the HET RAM.
+*/
+/** @typedef hetRAMBASE_t
+* @brief HET RAM Type Definition
+*
+* This type is used to access the HET RAM.
+*/
+typedef volatile struct het1RamBase
+{
+ hetINSTRUCTION_t Instruction[160U];
+} hetRAMBASE_t;
+
+
+/** @def hetREG1
+* @brief HET Register Frame Pointer
+*
+* This pointer is used by the HET driver to access the het module registers.
+*/
+#define hetREG1 ((hetBASE_t *)0xFFF7B800U)
+
+
+/** @def hetPORT1
+* @brief HET GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of HET1
+* (use the GIO drivers to access the port pins).
+*/
+#define hetPORT1 ((gioPORT_t *)0xFFF7B84CU)
+
+/** @def hetRAM1
+* @brief NHET1 RAM Pointer
+*
+* This pointer is used by the HET driver to access the NHET1 memory.
+*/
+#define hetRAM1 ((hetRAMBASE_t *)0xFF460000U)
+
+#define NHET1RAMPARLOC (*(volatile uint32 *)0xFF462000U)
+#define NHET1RAMLOC (*(volatile uint32 *)0xFF460000U)
+
+/** @def hetREG2
+* @brief HET2 Register Frame Pointer
+*
+* This pointer is used by the HET driver to access the het module registers.
+*/
+#define hetREG2 ((hetBASE_t *)0xFFF7B900U)
+
+/** @def hetPORT2
+* @brief HET2 GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of HET2
+* (use the GIO drivers to access the port pins).
+*/
+#define hetPORT2 ((gioPORT_t *)0xFFF7B94CU)
+
+/** @def hetRAM2
+* @brief NHET1 RAM Pointer
+*
+* This pointer is used by the HET driver to access the NHET2 memory.
+*/
+#define hetRAM2 ((hetRAMBASE_t *)0xFF440000U)
+
+#define NHET2RAMPARLOC (*(volatile uint32 *)0xFF442000U)
+#define NHET2RAMLOC (*(volatile uint32 *)0xFF440000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_htu.h
===================================================================
diff -u
--- firmware/include/reg_htu.h (revision 0)
+++ firmware/include/reg_htu.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,141 @@
+/** @file reg_htu.h
+* @brief HTU Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the HTU driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_HTU_H__
+#define __REG_HTU_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* htu Register Frame Definition */
+/** @struct htuBase
+* @brief HTU Base Register Definition
+*
+* This structure is used to access the HTU module registers.
+*/
+/** @typedef htuBASE_t
+* @brief HTU Register Frame Type Definition
+*
+* This type is used to access the HTU Registers.
+*/
+typedef volatile struct htuBase
+{
+ uint32 GC; /** 0x00 */
+ uint32 CPENA; /** 0x04 */
+ uint32 BUSY0; /** 0x08 */
+ uint32 BUSY1; /** 0x0C */
+ uint32 BUSY2; /** 0x10 */
+ uint32 BUSY3; /** 0x14 */
+ uint32 ACPE; /** 0x18 */
+ uint32 rsvd1; /** 0x1C */
+ uint32 RLBECTRL; /** 0x20 */
+ uint32 BFINTS; /** 0x24 */
+ uint32 BFINTC; /** 0x28 */
+ uint32 INTMAP; /** 0x2C */
+ uint32 rsvd2; /** 0x30 */
+ uint32 INTOFF0; /** 0x34 */
+ uint32 INTOFF1; /** 0x38 */
+ uint32 BIM; /** 0x3C */
+ uint32 RLOSTFL; /** 0x40 */
+ uint32 BFINTFL; /** 0x44 */
+ uint32 BERINTFL; /** 0x48 */
+ uint32 MP1S; /** 0x4C */
+ uint32 MP1E; /** 0x50 */
+ uint32 DCTRL; /** 0x54 */
+ uint32 WPR; /** 0x58 */
+ uint32 WMR; /** 0x5C */
+ uint32 ID; /** 0x60 */
+ uint32 PCR; /** 0x64 */
+ uint32 PAR; /** 0x68 */
+ uint32 rsvd3; /** 0x6C */
+ uint32 MPCS; /** 0x70 */
+ uint32 MP0S; /** 0x74 */
+ uint32 MP0E; /** 0x78 */
+} htuBASE_t;
+
+typedef volatile struct
+{
+ struct /* 0x00-0x7C */
+ {
+ uint32 IFADDRA;
+ uint32 IFADDRB;
+ uint32 IHADDRCT;
+ uint32 ITCOUNT;
+ }DCP[8U];
+
+ struct /* 0x80-0xFC */
+ {
+ uint32 res[32U];
+ } RESERVED;
+
+ struct /* 0x100-0x17C */
+ {
+ uint32 CFADDRA;
+ uint32 CFADDRB;
+ uint32 CFCOUNT;
+ uint32 rsvd4;
+ }CDCP[8U];
+
+} htuRAMBASE_t;
+
+#define htuREG1 ((htuBASE_t *)0xFFF7A400U)
+#define htuREG2 ((htuBASE_t *)0xFFF7A500U)
+
+#define htuRAM1 ((htuRAMBASE_t *)0xFF4E0000U)
+#define htuRAM2 ((htuRAMBASE_t *)0xFF4C0000U)
+
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_i2c.h
===================================================================
diff -u
--- firmware/include/reg_i2c.h (revision 0)
+++ firmware/include/reg_i2c.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,147 @@
+/** @file reg_i2c.h
+* @brief I2C Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the I2C driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_I2C_H__
+#define __REG_I2C_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* I2c Register Frame Definition */
+/** @struct i2cBase
+* @brief I2C Base Register Definition
+*
+* This structure is used to access the I2C module registers.
+*/
+/** @typedef i2cBASE_t
+* @brief I2C Register Frame Type Definition
+*
+* This type is used to access the I2C Registers.
+*/
+typedef volatile struct i2cBase
+{
+
+ uint32 OAR; /**< 0x0000 I2C Own Address register */
+ uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */
+ uint32 STR; /**< 0x0008 I2C Interrupt Status register */
+ uint32 CKL; /**< 0x000C I2C Clock Divider Low register */
+ uint32 CKH; /**< 0x0010 I2C Clock Divider High register */
+ uint32 CNT; /**< 0x0014 I2C Data Count register */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ uint8 DRR; /**< 0x0018: I2C Data Receive register, */
+ uint8 rsvd1; /**< 0x0018: I2C Data Receive register, Reserved */
+ uint8 rsvd2; /**< 0x0018: I2C Data Receive register, Reserved */
+ uint8 rsvd3; /**< 0x0018: I2C Data Receive register, Reserved */
+#else
+ uint8 rsvd3; /**< 0x0018: I2C Data Receive register, Reserved */
+ uint8 rsvd2; /**< 0x0018: I2C Data Receive register, Reserved */
+ uint8 rsvd1; /**< 0x0018: I2C Data Receive register, Reserved */
+ uint8 DRR; /**< 0x0018: I2C Data Receive register, */
+#endif
+ uint32 SAR; /**< 0x001C I2C Slave Address register */
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ uint8 DXR; /**< 0x0020: I2C Data Transmit register, */
+ uint8 rsvd4; /**< 0x0020: I2C Data Transmit register, Reserved */
+ uint8 rsvd5; /**< 0x0020: I2C Data Transmit register, Reserved */
+ uint8 rsvd6; /**< 0x0020: I2C Data Transmit register, Reserved */
+#else
+ uint8 rsvd6; /**< 0x0020: I2C Data Transmit register, Reserved */
+ uint8 rsvd5; /**< 0x0020: I2C Data Transmit register, Reserved */
+ uint8 rsvd4; /**< 0x0020: I2C Data Transmit register, Reserved */
+ uint8 DXR; /**< 0x0020: I2C Data Transmit register, */
+#endif
+ uint32 MDR; /**< 0x0024 I2C Mode register */
+ uint32 IVR; /**< 0x0028 I2C Interrupt Vector register */
+ uint32 EMDR; /**< 0x002C I2C Extended Mode register */
+ uint32 PSC; /**< 0x0030 I2C Prescaler register */
+ uint32 PID11; /**< 0x0034 I2C Peripheral ID register 1 */
+ uint32 PID12; /**< 0x0038 I2C Peripheral ID register 2 */
+ uint32 DMACR; /**< 0x003C I2C DMA Control Register */
+ uint32 rsvd7; /**< 0x0040 Reserved */
+ uint32 rsvd8; /**< 0x0044 Reserved */
+ uint32 PFNC; /**< 0x0048 Pin Function Register */
+ uint32 DIR; /**< 0x004C Pin Direction Register */
+ uint32 DIN; /**< 0x0050 Pin Data In Register */
+ uint32 DOUT; /**< 0x0054 Pin Data Out Register */
+ uint32 SET; /**< 0x0058 Pin Data Set Register */
+ uint32 CLR; /**< 0x005C Pin Data Clr Register */
+ uint32 PDR; /**< 0x0060 Pin Open Drain Output Enable Register */
+ uint32 PDIS; /**< 0x0064 Pin Pullup/Pulldown Disable Register */
+ uint32 PSEL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */
+ uint32 PSRS; /**< 0x006C Pin Slew Rate Select Register */
+} i2cBASE_t;
+
+
+/** @def i2cREG1
+* @brief I2C Register Frame Pointer
+*
+* This pointer is used by the I2C driver to access the I2C module registers.
+*/
+#define i2cREG1 ((i2cBASE_t *)0xFFF7D400U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @def i2cPORT1
+* @brief I2C GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of I2C
+* (use the GIO drivers to access the port pins).
+*/
+#define i2cPORT1 ((gioPORT_t *)0xFFF7D44CU)
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_lin.h
===================================================================
diff -u
--- firmware/include/reg_lin.h (revision 0)
+++ firmware/include/reg_lin.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,129 @@
+/** @file reg_lin.h
+* @brief LIN Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the LIN driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_LIN_H__
+#define __REG_LIN_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Lin Register Frame Definition */
+/** @struct linBase
+* @brief LIN Base Register Definition
+*
+* This structure is used to access the LIN module registers.
+*/
+/** @typedef linBASE_t
+* @brief LIN Register Frame Type Definition
+*
+* This type is used to access the LIN Registers.
+*/
+
+typedef volatile struct linBase
+{
+ uint32 GCR0; /**< 0x0000: Global control register 0 */
+ uint32 GCR1; /**< 0x0004: Global control register 1 */
+ uint32 GCR2; /**< 0x0008: Global control register 2 */
+ uint32 SETINT; /**< 0x000C: Set interrupt enable register */
+ uint32 CLEARINT; /**< 0x0010: Clear interrupt enable register */
+ uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */
+ uint32 CLEARINTLVL; /**< 0x0018: Set interrupt level register */
+ uint32 FLR; /**< 0x001C: interrupt flag register */
+ uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */
+ uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */
+ uint32 FORMAT; /**< 0x0028: Format Control Register */
+ uint32 BRS; /**< 0x002C: Baud rate selection register */
+ uint32 ED; /**< 0x0030: Emulation register */
+ uint32 RD; /**< 0x0034: Receive data register */
+ uint32 TD; /**< 0x0038: Transmit data register */
+ uint32 PIO0; /**< 0x003C: Pin function register */
+ uint32 PIO1; /**< 0x0040: Pin direction register */
+ uint32 PIO2; /**< 0x0044: Pin data in register */
+ uint32 PIO3; /**< 0x0048: Pin data out register */
+ uint32 PIO4; /**< 0x004C: Pin data set register */
+ uint32 PIO5; /**< 0x0050: Pin data clr register */
+ uint32 PIO6; /**< 0x0054: Pin open drain output enable register */
+ uint32 PIO7; /**< 0x0058: Pin pullup/pulldown disable register */
+ uint32 PIO8; /**< 0x005C: Pin pullup/pulldown selection register */
+ uint32 COMP; /**< 0x0060: Compare register */
+ uint8 RDx[8U]; /**< 0x0064-0x0068: RX buffer register */
+ uint32 MASK; /**< 0x006C: Mask register */
+ uint32 ID; /**< 0x0070: Identification Register */
+ uint8 TDx[8U]; /**< 0x0074-0x0078: TX buffer register */
+ uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */
+ uint32 rsvd1[4U]; /**< 0x0080 - 0x8C: Reserved */
+ uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */
+} linBASE_t;
+
+
+/** @def linREG
+* @brief LIN Register Frame Pointer
+*
+* This pointer is used by the LIN driver to access the lin module registers.
+*/
+#define linREG ((linBASE_t *)0xFFF7E400U)
+
+
+/** @def linPORT
+* @brief LIN GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of LIN
+* (use the GIO drivers to access the port pins).
+*/
+#define linPORT ((gioPORT_t *)0xFFF7E440U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_mibspi.h
===================================================================
diff -u
--- firmware/include/reg_mibspi.h (revision 0)
+++ firmware/include/reg_mibspi.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,257 @@
+/** @file reg_mibspi.h
+* @brief MIBSPI Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the MIBSPI driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_MIBSPI_H__
+#define __REG_MIBSPI_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Mibspi Register Frame Definition */
+/** @struct mibspiBase
+* @brief MIBSPI Register Definition
+*
+* This structure is used to access the MIBSPI module registers.
+*/
+/** @typedef mibspiBASE_t
+* @brief MIBSPI Register Frame Type Definition
+*
+* This type is used to access the MIBSPI Registers.
+*/
+typedef volatile struct mibspiBase
+{
+ uint32 GCR0; /**< 0x0000: Global Control 0 */
+ uint32 GCR1; /**< 0x0004: Global Control 1 */
+ uint32 INT0; /**< 0x0008: Interrupt Register */
+ uint32 LVL; /**< 0x000C: Interrupt Level */
+ uint32 FLG; /**< 0x0010: Interrupt flags */
+ uint32 PC0; /**< 0x0014: Function Pin Enable */
+ uint32 PC1; /**< 0x0018: Pin Direction */
+ uint32 PC2; /**< 0x001C: Pin Input Latch */
+ uint32 PC3; /**< 0x0020: Pin Output Latch */
+ uint32 PC4; /**< 0x0024: Output Pin Set */
+ uint32 PC5; /**< 0x0028: Output Pin Clr */
+ uint32 PC6; /**< 0x002C: Open Drain Output Enable */
+ uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */
+ uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */
+ uint32 DAT0; /**< 0x0038: Transmit Data */
+ uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
+ uint32 BUF; /**< 0x0040: Receive Buffer */
+ uint32 EMU; /**< 0x0044: Emulation Receive Buffer */
+ uint32 DELAY; /**< 0x0048: Delays */
+ uint32 DEF; /**< 0x004C: Default Chip Select */
+ uint32 FMT0; /**< 0x0050: Data Format 0 */
+ uint32 FMT1; /**< 0x0054: Data Format 1 */
+ uint32 FMT2; /**< 0x0058: Data Format 2 */
+ uint32 FMT3; /**< 0x005C: Data Format 3 */
+ uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */
+ uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */
+ uint32 SRSEL; /**< 0x0068: Slew Rate Select */
+ uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */
+ uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */
+ uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */
+ uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */
+ uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */
+ uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */
+ uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */
+ uint32 rsvd1[2U]; /**< 0x0088: Reserved */
+ uint32 TICKCNT; /**< 0x0090: Tick Counter */
+ uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */
+ uint32 TGCTRL[16U]; /**< 0x0098 - 0x00D4: Transfer Group Control */
+ uint32 DMACTRL[8U]; /**< 0x00D8 - 0x00F4: DMA Control */
+ uint32 DMACOUNT[8U]; /**< 0x00F8 - 0x0114: DMA Count */
+ uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */
+ uint32 rsvd2; /**< 0x011C: Reserved */
+ uint32 UERRCTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control */
+ uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */
+ uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */
+ uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */
+ uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */
+ uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
+ uint32 EXT_PRESCALE1; /**< 0x0138: */
+ uint32 EXT_PRESCALE2; /**< 0x013C: */
+} mibspiBASE_t;
+
+
+/** @def mibspiREG1
+* @brief MIBSPI1 Register Frame Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG1 ((mibspiBASE_t *)0xFFF7F400U)
+
+
+/** @def mibspiPORT1
+* @brief MIBSPI1 GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of MIBSPI1
+* (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT1 ((gioPORT_t *)0xFFF7F418U)
+
+/** @def mibspiREG3
+* @brief MIBSPI3 Register Frame Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG3 ((mibspiBASE_t *)0xFFF7F800U)
+
+
+/** @def mibspiPORT3
+* @brief MIBSPI3 GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of MIBSPI3
+* (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT3 ((gioPORT_t *)0xFFF7F818U)
+
+/** @def mibspiREG5
+* @brief MIBSPI5 Register Frame Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi module registers.
+*/
+#define mibspiREG5 ((mibspiBASE_t *)0xFFF7FC00U)
+
+
+/** @def mibspiPORT5
+* @brief MIBSPI5 GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of MIBSPI5
+* (use the GIO drivers to access the port pins).
+*/
+#define mibspiPORT5 ((gioPORT_t *)0xFFF7FC18U)
+
+
+/** @struct mibspiRamBase
+* @brief MIBSPI Buffer RAM Definition
+*
+* This structure is used to access the MIBSPI buffer memory.
+*/
+/** @typedef mibspiRAM_t
+* @brief MIBSPI RAM Type Definition
+*
+* This type is used to access the MIBSPI RAM.
+*/
+typedef volatile struct mibspiRamBase
+{
+ struct
+ {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ uint16 data; /**< tx buffer data */
+ uint16 control; /**< tx buffer control */
+#else
+ uint16 control; /**< tx buffer control */
+ uint16 data; /**< tx buffer data */
+#endif
+ } tx[128];
+ struct
+ {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ uint16 data; /**< rx buffer data */
+ uint16 flags; /**< rx buffer flags */
+#else
+ uint16 flags; /**< rx buffer flags */
+ uint16 data; /**< rx buffer data */
+#endif
+ } rx[128];
+} mibspiRAM_t;
+
+
+/** @def mibspiRAM1
+* @brief MIBSPI1 Buffer RAM Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM1 ((mibspiRAM_t *)0xFF0E0000U)
+
+/** @def mibspiRAM3
+* @brief MIBSPI3 Buffer RAM Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM3 ((mibspiRAM_t *)0xFF0C0000U)
+
+/** @def mibspiRAM5
+* @brief MIBSPI5 Buffer RAM Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiRAM5 ((mibspiRAM_t *)0xFF0A0000U)
+
+/** @def mibspiPARRAM1
+* @brief MIBSPI1 Buffer RAM PARITY Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM1 (*(volatile uint32 *)(0xFF0E0000U + 0x00000400U))
+
+/** @def mibspiPARRAM3
+* @brief MIBSPI3 Buffer RAM PARITY Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM3 (*(volatile uint32 *)(0xFF0C0000U + 0x00000400U))
+
+
+/** @def mibspiPARRAM5
+* @brief MIBSPI5 Buffer RAM PARITY Pointer
+*
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.
+*/
+#define mibspiPARRAM5 (*(volatile uint32 *)(0xFF0A0000U + 0x00000400U))
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_pbist.h
===================================================================
diff -u
--- firmware/include/reg_pbist.h (revision 0)
+++ firmware/include/reg_pbist.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,98 @@
+/** @file reg_pbist.h
+* @brief PBIST Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_PBIST_H__
+#define __REG_PBIST_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* PBIST Register Frame Definition */
+/** @struct pbistBase
+* @brief PBIST Base Register Definition
+*
+* This structure is used to access the PBIST module registers.
+*/
+/** @typedef pbistBASE_t
+* @brief PBIST Register Frame Type Definition
+*
+* This type is used to access the PBIST Registers.
+*/
+typedef volatile struct pbistBase
+{
+ uint32 RAMT; /* 0x0160: RAM Configuration Register */
+ uint32 DLR; /* 0x0164: Datalogger Register */
+ uint32 rsvd1[6U]; /* 0x0168 */
+ uint32 PACT; /* 0x0180: PBIST Activate Register */
+ uint32 PBISTID; /* 0x0184: PBIST ID Register */
+ uint32 OVER; /* 0x0188: Override Register */
+ uint32 rsvd2; /* 0x018C */
+ uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */
+ uint32 rsvd5; /* 0x0194 */
+ uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */
+ uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */
+ uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */
+ uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */
+ uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */
+ uint32 rsvd3; /* 0x01AC */
+ uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */
+ uint32 rsvd4[3U]; /* 0x01B4 */
+ uint32 ROM; /* 0x01C0: ROM Mask Register */
+ uint32 ALGO; /* 0x01C4: Algorithm Mask Register */
+ uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */
+ uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */
+} pbistBASE_t;
+
+#define pbistREG ((pbistBASE_t *)0xFFFFE560U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_pcr.h
===================================================================
diff -u
--- firmware/include/reg_pcr.h (revision 0)
+++ firmware/include/reg_pcr.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,113 @@
+/** @file reg_pcr.h
+* @brief PCR Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_PCR_H__
+#define __REG_PCR_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pcr Register Frame Definition */
+/** @struct pcrBase
+* @brief Pcr Register Frame Definition
+*
+* This type is used to access the Pcr Registers.
+*/
+/** @typedef pcrBASE_t
+* @brief PCR Register Frame Type Definition
+*
+* This type is used to access the PCR Registers.
+*/
+typedef volatile struct pcrBase
+{
+ uint32 PMPROTSET0; /* 0x0000 */
+ uint32 PMPROTSET1; /* 0x0004 */
+ uint32 rsvd1[2U]; /* 0x0008 */
+ uint32 PMPROTCLR0; /* 0x0010 */
+ uint32 PMPROTCLR1; /* 0x0014 */
+ uint32 rsvd2[2U]; /* 0x0018 */
+ uint32 PPROTSET0; /* 0x0020 */
+ uint32 PPROTSET1; /* 0x0024 */
+ uint32 PPROTSET2; /* 0x0028 */
+ uint32 PPROTSET3; /* 0x002C */
+ uint32 rsvd3[4U]; /* 0x0030 */
+ uint32 PPROTCLR0; /* 0x0040 */
+ uint32 PPROTCLR1; /* 0x0044 */
+ uint32 PPROTCLR2; /* 0x0048 */
+ uint32 PPROTCLR3; /* 0x004C */
+ uint32 rsvd4[4U]; /* 0x0050 */
+ uint32 PCSPWRDWNSET0; /* 0x0060 */
+ uint32 PCSPWRDWNSET1; /* 0x0064 */
+ uint32 rsvd5[2U]; /* 0x0068 */
+ uint32 PCSPWRDWNCLR0; /* 0x0070 */
+ uint32 PCSPWRDWNCLR1; /* 0x0074 */
+ uint32 rsvd6[2U]; /* 0x0078 */
+ uint32 PSPWRDWNSET0; /* 0x0080 */
+ uint32 PSPWRDWNSET1; /* 0x0084 */
+ uint32 PSPWRDWNSET2; /* 0x0088 */
+ uint32 PSPWRDWNSET3; /* 0x008C */
+ uint32 rsvd7[4U]; /* 0x0090 */
+ uint32 PSPWRDWNCLR0; /* 0x00A0 */
+ uint32 PSPWRDWNCLR1; /* 0x00A4 */
+ uint32 PSPWRDWNCLR2; /* 0x00A8 */
+ uint32 PSPWRDWNCLR3; /* 0x00AC */
+} pcrBASE_t;
+
+/** @def pcrREG
+* @brief Pcr Register Frame Pointer
+*
+* This pointer is used by the system driver to access the Pcr registers.
+*/
+#define pcrREG ((pcrBASE_t *)0xFFFFE000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_pinmux.h
===================================================================
diff -u
--- firmware/include/reg_pinmux.h (revision 0)
+++ firmware/include/reg_pinmux.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,180 @@
+/** @file reg_pinmux.h
+* @brief PINMUX Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the PINMUX driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_PINMUX_H__
+#define __REG_PINMUX_H__
+
+#include "sys_common.h"
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* IOMM Revision and Boot Register */
+#define REVISION_REG (*(volatile uint32 *)0xFFFFEA00U)
+#define ENDIAN_REG (*(volatile uint32 *)0xFFFFEA20U)
+
+/* IOMM Error and Fault Registers */
+/** @struct iommErrFault
+* @brief IOMM Error and Fault Register Definition
+*
+* This structure is used to access the IOMM Error and Fault registers.
+*/
+typedef volatile struct iommErrFault
+{
+ uint32 ERR_RAW_STATUS_REG; /* Error Raw Status / Set Register */
+ uint32 ERR_ENABLED_STATUS_REG; /* Error Enabled Status / Clear Register */
+ uint32 ERR_ENABLE_REG; /* Error Signaling Enable Register */
+ uint32 ERR_ENABLE_CLR_REG; /* Error Signaling Enable Clear Register */
+ uint32 rsvd; /* Reserved */
+ uint32 FAULT_ADDRESS_REG; /* Fault Address Register */
+ uint32 FAULT_STATUS_REG; /* Fault Status Register */
+ uint32 FAULT_CLEAR_REG; /* Fault Clear Register */
+} iommErrFault_t;
+
+/* Pinmux Register Frame Definition */
+/** @struct pinMuxKicker
+* @brief Pin Muxing Kicker Register Definition
+*
+* This structure is used to access the Pin Muxing Kicker registers.
+*/
+typedef volatile struct pinMuxKicker
+{
+ uint32 KICKER0; /* kicker 0 register */
+ uint32 KICKER1; /* kicker 1 register */
+} pinMuxKICKER_t;
+
+/** @struct pinMuxBase
+* @brief PINMUX Register Definition
+*
+* This structure is used to access the PINMUX module egisters.
+*/
+/** @typedef pinMuxBASE_t
+* @brief PINMUX Register Frame Type Definition
+*
+* This type is used to access the PINMUX Registers.
+*/
+typedef volatile struct pinMuxBase
+{
+ uint32 PINMMR0; /**< 0xEB10 Pin Mux 0 register*/
+ uint32 PINMMR1; /**< 0xEB14 Pin Mux 1 register*/
+ uint32 PINMMR2; /**< 0xEB18 Pin Mux 2 register*/
+ uint32 PINMMR3; /**< 0xEB1C Pin Mux 3 register*/
+ uint32 PINMMR4; /**< 0xEB20 Pin Mux 4 register*/
+ uint32 PINMMR5; /**< 0xEB24 Pin Mux 5 register*/
+ uint32 PINMMR6; /**< 0xEB28 Pin Mux 6 register*/
+ uint32 PINMMR7; /**< 0xEB2C Pin Mux 7 register*/
+ uint32 PINMMR8; /**< 0xEB30 Pin Mux 8 register*/
+ uint32 PINMMR9; /**< 0xEB34 Pin Mux 9 register*/
+ uint32 PINMMR10; /**< 0xEB38 Pin Mux 10 register*/
+ uint32 PINMMR11; /**< 0xEB3C Pin Mux 11 register*/
+ uint32 PINMMR12; /**< 0xEB40 Pin Mux 12 register*/
+ uint32 PINMMR13; /**< 0xEB44 Pin Mux 13 register*/
+ uint32 PINMMR14; /**< 0xEB48 Pin Mux 14 register*/
+ uint32 PINMMR15; /**< 0xEB4C Pin Mux 15 register*/
+ uint32 PINMMR16; /**< 0xEB50 Pin Mux 16 register*/
+ uint32 PINMMR17; /**< 0xEB54 Pin Mux 17 register*/
+ uint32 PINMMR18; /**< 0xEB58 Pin Mux 18 register*/
+ uint32 PINMMR19; /**< 0xEB5C Pin Mux 19 register*/
+ uint32 PINMMR20; /**< 0xEB60 Pin Mux 20 register*/
+ uint32 PINMMR21; /**< 0xEB64 Pin Mux 21 register*/
+ uint32 PINMMR22; /**< 0xEB68 Pin Mux 22 register*/
+ uint32 PINMMR23; /**< 0xEB6C Pin Mux 23 register*/
+ uint32 PINMMR24; /**< 0xEB70 Pin Mux 24 register*/
+ uint32 PINMMR25; /**< 0xEB74 Pin Mux 25 register*/
+ uint32 PINMMR26; /**< 0xEB78 Pin Mux 26 register*/
+ uint32 PINMMR27; /**< 0xEB7C Pin Mux 27 register*/
+ uint32 PINMMR28; /**< 0xEB80 Pin Mux 28 register*/
+ uint32 PINMMR29; /**< 0xEB84 Pin Mux 29 register*/
+ uint32 PINMMR30; /**< 0xEB88 Pin Mux 30 register*/
+ uint32 PINMMR31; /**< 0xEB8C Pin Mux 31 register*/
+ uint32 PINMMR32; /**< 0xEB90 Pin Mux 32 register*/
+ uint32 PINMMR33; /**< 0xEB94 Pin Mux 33 register*/
+ uint32 PINMMR34; /**< 0xEB98 Pin Mux 34 register*/
+ uint32 PINMMR35; /**< 0xEB9C Pin Mux 35 register*/
+ uint32 PINMMR36; /**< 0xEBA0 Pin Mux 36 register*/
+ uint32 PINMMR37; /**< 0xEBA4 Pin Mux 37 register*/
+ uint32 PINMMR38; /**< 0xEBA8 Pin Mux 38 register*/
+ uint32 PINMMR39; /**< 0xEBAC Pin Mux 39 register*/
+ uint32 PINMMR40; /**< 0xEBB0 Pin Mux 40 register*/
+ uint32 PINMMR41; /**< 0xEBB4 Pin Mux 41 register*/
+ uint32 PINMMR42; /**< 0xEBB8 Pin Mux 42 register*/
+ uint32 PINMMR43; /**< 0xEBBC Pin Mux 43 register*/
+ uint32 PINMMR44; /**< 0xEBC0 Pin Mux 44 register*/
+ uint32 PINMMR45; /**< 0xEBC4 Pin Mux 45 register*/
+ uint32 PINMMR46; /**< 0xEBC8 Pin Mux 46 register*/
+ uint32 PINMMR47; /**< 0xEBCC Pin Mux 47 register*/
+}pinMuxBASE_t;
+
+
+/** @def iommErrFaultReg
+* @brief IOMM Error Fault Register Frame Pointer
+*
+* This pointer is used to control IOMM Error and Fault across the device.
+*/
+#define iommErrFaultReg ((iommErrFault_t *) 0xFFFFEAE0U)
+
+/** @def kickerReg
+* @brief Pin Muxing Kicker Register Frame Pointer
+*
+* This pointer is used to enable and disable muxing accross the device.
+*/
+#define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38U)
+
+/** @def pinMuxReg
+* @brief Pin Muxing Control Register Frame Pointer
+*
+* This pointer is used to set the muxing registers accross the device.
+*/
+#define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_pmm.h
===================================================================
diff -u
--- firmware/include/reg_pmm.h (revision 0)
+++ firmware/include/reg_pmm.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,111 @@
+/** @file reg_pmm.h
+* @brief PMM Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the PMM driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_PMM_H__
+#define __REG_PMM_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pmm Register Frame Definition */
+/** @struct pmmBase
+* @brief Pmm Register Frame Definition
+*
+* This type is used to access the Pmm Registers.
+*/
+/** @typedef pmmBase_t
+* @brief Pmm Register Frame Type Definition
+*
+* This type is used to access the Pmm Registers.
+*/
+typedef volatile struct pmmBase
+{
+ uint32 LOGICPDPWRCTRL0; /**< 0x0000: Logic Power Domain Control Register 0 */
+ uint32 rsvd1[3U]; /**< 0x0004: Reserved*/
+ uint32 MEMPDPWRCTRL0; /**< 0x0010: Memory Power Domain Control Register 0 */
+ uint32 rsvd2[3U]; /**< 0x0014: Reserved*/
+ uint32 PDCLKDISREG; /**< 0x0020: Power Domain Clock Disable Register */
+ uint32 PDCLKDISSETREG; /**< 0x0024: Power Domain Clock Disable Set Register */
+ uint32 PDCLKDISCLRREG; /**< 0x0028: Power Domain Clock Disable Clear Register */
+ uint32 rsvd3[5U]; /**< 0x002C: Reserved */
+ uint32 LOGICPDPWRSTAT[4U]; /**< 0x0040, 0x0044, 0x0048, 0x004C: Logic Power Domain Power Status Register
+ - 0: PD2
+ - 1: PD3
+ - 2: PD4
+ - 3: PD5 */
+ uint32 rsvd4[12U]; /**< 0x0050: Reserved*/
+ uint32 MEMPDPWRSTAT[3U]; /**< 0x0080, 0x0084, 0x0088: Memory Power Domain Power Status Register
+ - 0: RAM_PD1
+ - 1: RAM_PD2
+ - 2: RAM_PD3 */
+ uint32 rsvd5[5U]; /**< 0x008C: Reserved */
+ uint32 GLOBALCTRL1; /**< 0x00A0: Global Control Register 1 */
+ uint32 rsvd6; /**< 0x00A4: Reserved */
+ uint32 GLOBALSTAT; /**< 0x00A8: Global Status Register */
+ uint32 PRCKEYREG; /**< 0x00AC: PSCON Diagnostic Compare Key Register */
+ uint32 LPDDCSTAT1; /**< 0x00B0: LogicPD PSCON Diagnostic Compare Status Register 1 */
+ uint32 LPDDCSTAT2; /**< 0x00B4: LogicPD PSCON Diagnostic Compare Status Register 2 */
+ uint32 MPDDCSTAT1; /**< 0x00B8: Memory PD PSCON Diagnostic Compare Status Register 1 */
+ uint32 MPDDCSTAT2; /**< 0x00BC: Memory PD PSCON Diagnostic Compare Status Register 2 */
+ uint32 ISODIAGSTAT; /**< 0x00C0: Isolation Diagnostic Status Register */
+}pmmBase_t;
+
+
+/** @def pmmREG
+* @brief Pmm Register Frame Pointer
+*
+* This pointer is used by the Pmm driver to access the Pmm registers.
+*/
+#define pmmREG ((pmmBase_t *)0xFFFF0000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_pom.h
===================================================================
diff -u
--- firmware/include/reg_pom.h (revision 0)
+++ firmware/include/reg_pom.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,127 @@
+/** @file reg_pom.h
+* @brief POM Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the POM driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_POM_H__
+#define __REG_POM_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Pom Register Frame Definition */
+/** @struct POMBase
+* @brief POM Register Frame Definition
+*
+* This structure is used to access the POM module registers(POM Register Map).
+*/
+typedef struct
+{
+ uint32 POMGLBCTRL; /* 0x00 */
+ uint32 POMREV; /* 0x04 */
+ uint32 POMCLKCTRL; /* 0x08 */
+ uint32 POMFLG; /* 0x0C */
+ struct
+ {
+ uint32 rsdv1;
+ }RESERVED_REG[124U];
+ struct /* 0x200 ... */
+ {
+ uint32 POMPROGSTART;
+ uint32 POMOVLSTART;
+ uint32 POMREGSIZE;
+ uint32 rsdv2;
+ }POMRGNCONF_ST[32U];
+}pomBASE_t;
+
+
+/** @struct POM_CORESIGHT_ST
+* @brief POM_CORESIGHT_ST Register Definition
+*
+* This structure is used to access the POM module registers(POM CoreSight Registers ).
+*/
+typedef struct
+{
+ uint32 POMITCTRL; /* 0xF00 */
+ struct /* 0xF04 to 0xF9C */
+ {
+ uint32 Reserved_Reg;
+ }Reserved1_ST[39U];
+ uint32 POMCLAIMSET; /* 0xFA0 */
+ uint32 POMCLAIMCLR; /* 0xFA4 */
+ uint32 rsvd1[2U]; /* 0xFA8 */
+ uint32 POMLOCKACCESS; /* 0xFB0 */
+ uint32 POMLOCKSTATUS; /* 0xFB4 */
+ uint32 POMAUTHSTATUS; /* 0xFB8 */
+ uint32 rsvd2[3U]; /* 0xFBC */
+ uint32 POMDEVID; /* 0xFC8 */
+ uint32 POMDEVTYPE; /* 0xFCC */
+ uint32 POMPERIPHERALID4; /* 0xFD0 */
+ uint32 POMPERIPHERALID5; /* 0xFD4 */
+ uint32 POMPERIPHERALID6; /* 0xFD8 */
+ uint32 POMPERIPHERALID7; /* 0xFDC */
+ uint32 POMPERIPHERALID0; /* 0xFE0 */
+ uint32 POMPERIPHERALID1; /* 0xFE4 */
+ uint32 POMPERIPHERALID2; /* 0xFE8 */
+ uint32 POMPERIPHERALID3; /* 0xFEC */
+ uint32 POMCOMPONENTID0; /* 0xFF0 */
+ uint32 POMCOMPONENTID1; /* 0xFF4 */
+ uint32 POMCOMPONENTID2; /* 0xFF8 */
+ uint32 POMCOMPONENTID3; /* 0xFFC */
+}POM_CORESIGHT_ST;
+
+
+#define pomREG ((pomBASE_t *)0xFFA04000U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_rti.h
===================================================================
diff -u
--- firmware/include/reg_rti.h (revision 0)
+++ firmware/include/reg_rti.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,129 @@
+/** @file reg_rti.h
+* @brief RTI Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the RTI driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_RTI_H__
+#define __REG_RTI_H__
+
+#include "sys_common.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Rti Register Frame Definition */
+/** @struct rtiBase
+* @brief RTI Register Frame Definition
+*
+* This type is used to access the RTI Registers.
+*/
+/** @typedef rtiBASE_t
+* @brief RTI Register Frame Type Definition
+*
+* This type is used to access the RTI Registers.
+*/
+typedef volatile struct rtiBase
+{
+ uint32 GCTRL; /**< 0x0000: Global Control Register */
+ uint32 TBCTRL; /**< 0x0004: Timebase Control Register */
+ uint32 CAPCTRL; /**< 0x0008: Capture Control Register */
+ uint32 COMPCTRL; /**< 0x000C: Compare Control Register */
+ struct
+ {
+ uint32 FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */
+ uint32 UCx; /**< 0x0014,0x0034: Up Counter x Register */
+ uint32 CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */
+ uint32 rsvd1; /**< 0x001C,0x003C: Reserved */
+ uint32 CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */
+ uint32 CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */
+ uint32 rsvd2[2U]; /**< 0x0028,0x0048: Reserved */
+ } CNT[2U]; /**< Counter x selection:
+ - 0: Counter 0
+ - 1: Counter 1 */
+ struct
+ {
+ uint32 COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */
+ uint32 UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */
+ } CMP[4U]; /**< Compare x selection:
+ - 0: Compare 0
+ - 1: Compare 1
+ - 2: Compare 2
+ - 3: Compare 3 */
+ uint32 TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */
+ uint32 TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */
+ uint32 rsvd3[2U]; /**< 0x0078: Reserved */
+ uint32 SETINTENA; /**< 0x0080: Set/Status Interrupt Register */
+ uint32 CLEARINTENA; /**< 0x0084: Clear/Status Interrupt Register */
+ uint32 INTFLAG; /**< 0x0088: Interrupt Flag Register */
+ uint32 rsvd4; /**< 0x008C: Reserved */
+ uint32 DWDCTRL; /**< 0x0090: Digital Watchdog Control Register */
+ uint32 DWDPRLD; /**< 0x0094: Digital Watchdog Preload Register */
+ uint32 WDSTATUS; /**< 0x0098: Watchdog Status Register */
+ uint32 WDKEY; /**< 0x009C: Watchdog Key Register */
+ uint32 DWDCNTR; /**< 0x00A0: Digital Watchdog Down Counter */
+ uint32 WWDRXNCTRL; /**< 0x00A4: Digital Windowed Watchdog Reaction Control */
+ uint32 WWDSIZECTRL; /**< 0x00A8: Digital Windowed Watchdog Window Size Control */
+ uint32 INTCLRENABLE; /**< 0x00AC: RTI Compare Interrupt Clear Enable Register */
+ uint32 COMP0CLR; /**< 0x00B0: RTI Compare 0 Clear Register */
+ uint32 COMP1CLR; /**< 0x00B4: RTI Compare 1 Clear Register */
+ uint32 COMP2CLR; /**< 0x00B8: RTI Compare 2 Clear Register */
+ uint32 COMP3CLR; /**< 0x00BC: RTI Compare 3 Clear Register */
+} rtiBASE_t;
+
+/** @def rtiREG1
+* @brief RTI1 Register Frame Pointer
+*
+* This pointer is used by the RTI driver to access the RTI1 registers.
+*/
+#define rtiREG1 ((rtiBASE_t *)0xFFFFFC00U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_sci.h
===================================================================
diff -u
--- firmware/include/reg_sci.h (revision 0)
+++ firmware/include/reg_sci.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,139 @@
+/** @file reg_sci.h
+* @brief SCI Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the SCI driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_SCI_H__
+#define __REG_SCI_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Sci Register Frame Definition */
+/** @struct sciBase
+* @brief SCI Base Register Definition
+*
+* This structure is used to access the SCI module registers.
+*/
+/** @typedef sciBASE_t
+* @brief SCI Register Frame Type Definition
+*
+* This type is used to access the SCI Registers.
+*/
+typedef volatile struct sciBase
+{
+ uint32 GCR0; /**< 0x0000 Global Control Register 0 */
+ uint32 GCR1; /**< 0x0004 Global Control Register 1 */
+ uint32 GCR2; /**< 0x0008 Global Control Register 2. Note: Applicable only to LIN � SCI Compatibility Mode,Reserved for standalone SCI*/
+ uint32 SETINT; /**< 0x000C Set Interrupt Enable Register */
+ uint32 CLEARINT; /**< 0x0010 Clear Interrupt Enable Register */
+ uint32 SETINTLVL; /**< 0x0014 Set Interrupt Level Register */
+ uint32 CLEARINTLVL; /**< 0x0018 Set Interrupt Level Register */
+ uint32 FLR; /**< 0x001C Interrupt Flag Register */
+ uint32 INTVECT0; /**< 0x0020 Interrupt Vector Offset 0 */
+ uint32 INTVECT1; /**< 0x0024 Interrupt Vector Offset 1 */
+ uint32 FORMAT; /**< 0x0028 Format Control Register */
+ uint32 BRS; /**< 0x002C Baud Rate Selection Register */
+ uint32 ED; /**< 0x0030 Emulation Register */
+ uint32 RD; /**< 0x0034 Receive Data Buffer */
+ uint32 TD; /**< 0x0038 Transmit Data Buffer */
+ uint32 PIO0; /**< 0x003C Pin Function Register */
+ uint32 PIO1; /**< 0x0040 Pin Direction Register */
+ uint32 PIO2; /**< 0x0044 Pin Data In Register */
+ uint32 PIO3; /**< 0x0048 Pin Data Out Register */
+ uint32 PIO4; /**< 0x004C Pin Data Set Register */
+ uint32 PIO5; /**< 0x0050 Pin Data Clr Register */
+ uint32 PIO6; /**< 0x0054: Pin Open Drain Output Enable Register */
+ uint32 PIO7; /**< 0x0058: Pin Pullup/Pulldown Disable Register */
+ uint32 PIO8; /**< 0x005C: Pin Pullup/Pulldown Selection Register */
+ uint32 rsdv2[12U]; /**< 0x0060: Reserved */
+ uint32 IODFTCTRL; /**< 0x0090: I/O Error Enable Register */
+} sciBASE_t;
+
+
+/** @def sciREG
+* @brief Register Frame Pointer
+*
+* This pointer is used by the SCI driver to access the sci module registers.
+*/
+#define sciREG ((sciBASE_t *)0xFFF7E500U)
+
+
+/** @def sciPORT
+* @brief SCI GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of SCI
+* (use the GIO drivers to access the port pins).
+*/
+#define sciPORT ((gioPORT_t *)0xFFF7E540U)
+
+
+/** @def scilinREG
+* @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer
+*
+* This pointer is used by the SCI driver to access the sci module registers.
+*/
+#define scilinREG ((sciBASE_t *)0xFFF7E400U)
+
+
+/** @def scilinPORT
+* @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of LIN
+* (use the GIO drivers to access the port pins).
+*/
+#define scilinPORT ((gioPORT_t *)0xFFF7E440U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_spi.h
===================================================================
diff -u
--- firmware/include/reg_spi.h (revision 0)
+++ firmware/include/reg_spi.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,187 @@
+/** @file reg_spi.h
+* @brief SPI Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the SPI driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_SPI_H__
+#define __REG_SPI_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Spi Register Frame Definition */
+/** @struct spiBase
+* @brief SPI Register Definition
+*
+* This structure is used to access the SPI module registers.
+*/
+/** @typedef spiBASE_t
+* @brief SPI Register Frame Type Definition
+*
+* This type is used to access the SPI Registers.
+*/
+typedef volatile struct spiBase
+{
+ uint32 GCR0; /**< 0x0000: Global Control 0 */
+ uint32 GCR1; /**< 0x0004: Global Control 1 */
+ uint32 INT0; /**< 0x0008: Interrupt Register */
+ uint32 LVL; /**< 0x000C: Interrupt Level */
+ uint32 FLG; /**< 0x0010: Interrupt flags */
+ uint32 PC0; /**< 0x0014: Function Pin Enable */
+ uint32 PC1; /**< 0x0018: Pin Direction */
+ uint32 PC2; /**< 0x001C: Pin Input Latch */
+ uint32 PC3; /**< 0x0020: Pin Output Latch */
+ uint32 PC4; /**< 0x0024: Output Pin Set */
+ uint32 PC5; /**< 0x0028: Output Pin Clr */
+ uint32 PC6; /**< 0x002C: Open Drain Output Enable */
+ uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */
+ uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */
+ uint32 DAT0; /**< 0x0038: Transmit Data */
+ uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
+ uint32 BUF; /**< 0x0040: Receive Buffer */
+ uint32 EMU; /**< 0x0044: Emulation Receive Buffer */
+ uint32 DELAY; /**< 0x0048: Delays */
+ uint32 DEF; /**< 0x004C: Default Chip Select */
+ uint32 FMT0; /**< 0x0050: Data Format 0 */
+ uint32 FMT1; /**< 0x0054: Data Format 1 */
+ uint32 FMT2; /**< 0x0058: Data Format 2 */
+ uint32 FMT3; /**< 0x005C: Data Format 3 */
+ uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */
+ uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */
+ uint32 RESERVED[51U]; /**< 0x0068 to 0x0130: Reserved */
+ uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
+} spiBASE_t;
+
+/** @def spiREG1
+* @brief SPI1 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+* This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG1 ((spiBASE_t *)0xFFF7F400U)
+
+
+/** @def spiPORT1
+* @brief SPI1 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of SPI1
+* (use the GIO drivers to access the port pins).
+*/
+#define spiPORT1 ((gioPORT_t *)0xFFF7F418U)
+
+/** @def spiREG2
+* @brief SPI2 Register Frame Pointer
+*
+* This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG2 ((spiBASE_t *)0xFFF7F600U)
+
+
+/** @def spiPORT2
+* @brief SPI2 GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of SPI2
+* (use the GIO drivers to access the port pins).
+*/
+#define spiPORT2 ((gioPORT_t *)0xFFF7F618U)
+
+/** @def spiREG3
+* @brief SPI3 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+* This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG3 ((spiBASE_t *)0xFFF7F800U)
+
+
+/** @def spiPORT3
+* @brief SPI3 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of SPI3
+* (use the GIO drivers to access the port pins).
+*/
+#define spiPORT3 ((gioPORT_t *)0xFFF7F818U)
+
+/** @def spiREG4
+* @brief SPI4 Register Frame Pointer
+*
+* This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG4 ((spiBASE_t *)0xFFF7FA00U)
+
+
+/** @def spiPORT4
+* @brief SPI4 GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of SPI4
+* (use the GIO drivers to access the port pins).
+*/
+#define spiPORT4 ((gioPORT_t *)0xFFF7FA18U)
+
+/** @def spiREG5
+* @brief SPI5 (MIBSPI - Compatibility Mode) Register Frame Pointer
+*
+* This pointer is used by the SPI driver to access the spi module registers.
+*/
+#define spiREG5 ((spiBASE_t *)0xFFF7FC00U)
+
+
+/** @def spiPORT5
+* @brief SPI5 (MIBSPI - Compatibility Mode) GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of SPI5
+* (use the GIO drivers to access the port pins).
+*/
+#define spiPORT5 ((gioPORT_t *)0xFFF7FC18U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_stc.h
===================================================================
diff -u
--- firmware/include/reg_stc.h (revision 0)
+++ firmware/include/reg_stc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,93 @@
+/** @file reg_stc.h
+* @brief STC Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_STC_H__
+#define __REG_STC_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Stc Register Frame Definition */
+/** @struct stcBase
+* @brief STC Base Register Definition
+*
+* This structure is used to access the STC module registers.
+*/
+/** @typedef stcBASE_t
+* @brief STC Register Frame Type Definition
+*
+* This type is used to access the STC Registers.
+*/
+typedef volatile struct stcBase
+{
+ uint32 STCGCR0; /**< 0x0000: STC Control Register 0 */
+ uint32 STCGCR1; /**< 0x0004: STC Control Register 1 */
+ uint32 STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */
+ uint32 STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */
+ uint32 STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */
+ uint32 STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */
+ uint32 STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */
+ uint32 CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */
+ uint32 CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */
+ uint32 CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */
+ uint32 CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */
+ uint32 CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */
+ uint32 CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */
+ uint32 CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */
+ uint32 CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */
+ uint32 STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */
+} stcBASE_t;
+
+#define stcREG ((stcBASE_t *)0xFFFFE600U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/reg_system.h
===================================================================
diff -u
--- firmware/include/reg_system.h (revision 0)
+++ firmware/include/reg_system.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,191 @@
+/** @file reg_system.h
+* @brief System Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_SYSTEM_H__
+#define __REG_SYSTEM_H__
+
+#include "sys_common.h"
+#include "reg_gio.h"
+
+
+/* System Register Frame 1 Definition */
+/** @struct systemBase1
+* @brief System Register Frame 1 Definition
+*
+* This type is used to access the System 1 Registers.
+*/
+/** @typedef systemBASE1_t
+* @brief System Register Frame 1 Type Definition
+*
+* This type is used to access the System 1 Registers.
+*/
+typedef volatile struct systemBase1
+{
+ uint32 SYSPC1; /* 0x0000 */
+ uint32 SYSPC2; /* 0x0004 */
+ uint32 SYSPC3; /* 0x0008 */
+ uint32 SYSPC4; /* 0x000C */
+ uint32 SYSPC5; /* 0x0010 */
+ uint32 SYSPC6; /* 0x0014 */
+ uint32 SYSPC7; /* 0x0018 */
+ uint32 SYSPC8; /* 0x001C */
+ uint32 SYSPC9; /* 0x0020 */
+ uint32 SSWPLL1; /* 0x0024 */
+ uint32 SSWPLL2; /* 0x0028 */
+ uint32 SSWPLL3; /* 0x002C */
+ uint32 CSDIS; /* 0x0030 */
+ uint32 CSDISSET; /* 0x0034 */
+ uint32 CSDISCLR; /* 0x0038 */
+ uint32 CDDIS; /* 0x003C */
+ uint32 CDDISSET; /* 0x0040 */
+ uint32 CDDISCLR; /* 0x0044 */
+ uint32 GHVSRC; /* 0x0048 */
+ uint32 VCLKASRC; /* 0x004C */
+ uint32 RCLKSRC; /* 0x0050 */
+ uint32 CSVSTAT; /* 0x0054 */
+ uint32 MSTGCR; /* 0x0058 */
+ uint32 MINITGCR; /* 0x005C */
+ uint32 MSINENA; /* 0x0060 */
+ uint32 MSTFAIL; /* 0x0064 */
+ uint32 MSTCGSTAT; /* 0x0068 */
+ uint32 MINISTAT; /* 0x006C */
+ uint32 PLLCTL1; /* 0x0070 */
+ uint32 PLLCTL2; /* 0x0074 */
+ uint32 SYSPC10; /* 0x0078 */
+ uint32 DIEIDL; /* 0x007C */
+ uint32 DIEIDH; /* 0x0080 */
+ uint32 VRCTL; /* 0x0084 */
+ uint32 LPOMONCTL; /* 0x0088 */
+ uint32 CLKTEST; /* 0x008C */
+ uint32 DFTCTRLREG1; /* 0x0090 */
+ uint32 DFTCTRLREG2; /* 0x0094 */
+ uint32 rsvd1; /* 0x0098 */
+ uint32 rsvd2; /* 0x009C */
+ uint32 GPREG1; /* 0x00A0 */
+ uint32 BTRMSEL; /* 0x00A4 */
+ uint32 IMPFASTS; /* 0x00A8 */
+ uint32 IMPFTADD; /* 0x00AC */
+ uint32 SSISR1; /* 0x00B0 */
+ uint32 SSISR2; /* 0x00B4 */
+ uint32 SSISR3; /* 0x00B8 */
+ uint32 SSISR4; /* 0x00BC */
+ uint32 RAMGCR; /* 0x00C0 */
+ uint32 BMMCR1; /* 0x00C4 */
+ uint32 BMMCR2; /* 0x00C8 */
+ uint32 CPURSTCR; /* 0x00CC */
+ uint32 CLKCNTL; /* 0x00D0 */
+ uint32 ECPCNTL; /* 0x00D4 */
+ uint32 DSPGCR; /* 0x00D8 */
+ uint32 DEVCR1; /* 0x00DC */
+ uint32 SYSECR; /* 0x00E0 */
+ uint32 SYSESR; /* 0x00E4 */
+ uint32 SYSTASR; /* 0x00E8 */
+ uint32 GBLSTAT; /* 0x00EC */
+ uint32 DEV; /* 0x00F0 */
+ uint32 SSIVEC; /* 0x00F4 */
+ uint32 SSIF; /* 0x00F8 */
+} systemBASE1_t;
+
+
+/** @def systemREG1
+* @brief System Register Frame 1 Pointer
+*
+* This pointer is used by the system driver to access the system frame 1 registers.
+*/
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
+
+/** @def systemPORT
+* @brief ECLK GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of System/Eclk
+* (use the GIO drivers to access the port pins).
+*/
+#define systemPORT ((gioPORT_t *)0xFFFFFF04U)
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* System Register Frame 2 Definition */
+/** @struct systemBase2
+* @brief System Register Frame 2 Definition
+*
+* This type is used to access the System 2 Registers.
+*/
+/** @typedef systemBASE2_t
+* @brief System Register Frame 2 Type Definition
+*
+* This type is used to access the System 2 Registers.
+*/
+typedef volatile struct systemBase2
+{
+ uint32 PLLCTL3; /* 0x0000 */
+ uint32 rsvd1; /* 0x0004 */
+ uint32 STCCLKDIV; /* 0x0008 */
+ uint32 rsvd2[6U]; /* 0x000C */
+ uint32 ECPCNTRL0; /* 0x0024 */
+ uint32 rsvd3[5U]; /* 0x0028 */
+ uint32 CLK2CNTL; /* 0x003C */
+ uint32 VCLKACON1; /* 0x0040 */
+ uint32 rsvd4[11U]; /* 0x0044 */
+ uint32 CLKSLIP; /* 0x0070 */
+ uint32 rsvd5[30U]; /* 0x0074 */
+ uint32 EFC_CTLEN; /* 0x00EC */
+ uint32 DIEIDL_REG0; /* 0x00F0 */
+ uint32 DIEIDH_REG1; /* 0x00F4 */
+ uint32 DIEIDL_REG2; /* 0x00F8 */
+ uint32 DIEIDH_REG3; /* 0x00FC */
+} systemBASE2_t;
+
+/** @def systemREG2
+* @brief System Register Frame 2 Pointer
+*
+* This pointer is used by the system driver to access the system frame 2 registers.
+*/
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
+
+
+#endif
Index: firmware/include/reg_tcram.h
===================================================================
diff -u
--- firmware/include/reg_tcram.h (revision 0)
+++ firmware/include/reg_tcram.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,94 @@
+/** @file reg_tcram.h
+* @brief TCRAM Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_TCRAM_H__
+#define __REG_TCRAM_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* Tcram Register Frame Definition */
+/** @struct tcramBase
+* @brief TCRAM Wrapper Register Frame Definition
+*
+* This type is used to access the TCRAM Wrapper Registers.
+*/
+/** @typedef tcramBASE_t
+* @brief TCRAM Wrapper Register Frame Type Definition
+*
+* This type is used to access the TCRAM Wrapper Registers.
+*/
+
+typedef volatile struct tcramBase
+{
+ uint32 RAMCTRL; /* 0x0000 */
+ uint32 RAMTHRESHOLD; /* 0x0004 */
+ uint32 RAMOCCUR; /* 0x0008 */
+ uint32 RAMINTCTRL; /* 0x000C */
+ uint32 RAMERRSTATUS; /* 0x0010 */
+ uint32 RAMSERRADDR; /* 0x0014 */
+ uint32 rsvd1; /* 0x0018 */
+ uint32 RAMUERRADDR; /* 0x001C */
+ uint32 rsvd2[4U]; /* 0x0020 */
+ uint32 RAMTEST; /* 0x0030 */
+ uint32 rsvd3; /* 0x0034 */
+ uint32 RAMADDRDECVECT; /* 0x0038 */
+ uint32 RAMPERADDR; /* 0x003C */
+} tcramBASE_t;
+
+#define tcram1REG ((tcramBASE_t *)(0xFFFFF800U))
+#define tcram2REG ((tcramBASE_t *)(0xFFFFF900U))
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#endif
Index: firmware/include/reg_vim.h
===================================================================
diff -u
--- firmware/include/reg_vim.h (revision 0)
+++ firmware/include/reg_vim.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,110 @@
+/** @file reg_vim.h
+* @brief VIM Register Layer Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __REG_VIM_H__
+#define __REG_VIM_H__
+
+#include "sys_common.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Vim Register Frame Definition */
+/** @struct vimBase
+* @brief Vim Register Frame Definition
+*
+* This type is used to access the Vim Registers.
+*/
+/** @typedef vimBASE_t
+* @brief VIM Register Frame Type Definition
+*
+* This type is used to access the VIM Registers.
+*/
+typedef volatile struct vimBase
+{
+ uint32 IRQINDEX; /* 0x0000 */
+ uint32 FIQINDEX; /* 0x0004 */
+ uint32 rsvd1; /* 0x0008 */
+ uint32 rsvd2; /* 0x000C */
+ uint32 FIRQPR0; /* 0x0010 */
+ uint32 FIRQPR1; /* 0x0014 */
+ uint32 FIRQPR2; /* 0x0018 */
+ uint32 FIRQPR3; /* 0x001C */
+ uint32 INTREQ0; /* 0x0020 */
+ uint32 INTREQ1; /* 0x0024 */
+ uint32 INTREQ2; /* 0x0028 */
+ uint32 INTREQ3; /* 0x002C */
+ uint32 REQMASKSET0; /* 0x0030 */
+ uint32 REQMASKSET1; /* 0x0034 */
+ uint32 REQMASKSET2; /* 0x0038 */
+ uint32 REQMASKSET3; /* 0x003C */
+ uint32 REQMASKCLR0; /* 0x0040 */
+ uint32 REQMASKCLR1; /* 0x0044 */
+ uint32 REQMASKCLR2; /* 0x0048 */
+ uint32 REQMASKCLR3; /* 0x004C */
+ uint32 WAKEMASKSET0; /* 0x0050 */
+ uint32 WAKEMASKSET1; /* 0x0054 */
+ uint32 WAKEMASKSET2; /* 0x0058 */
+ uint32 WAKEMASKSET3; /* 0x005C */
+ uint32 WAKEMASKCLR0; /* 0x0060 */
+ uint32 WAKEMASKCLR1; /* 0x0064 */
+ uint32 WAKEMASKCLR2; /* 0x0068 */
+ uint32 WAKEMASKCLR3; /* 0x006C */
+ uint32 IRQVECREG; /* 0x0070 */
+ uint32 FIQVECREG; /* 0x0074 */
+ uint32 CAPEVT; /* 0x0078 */
+ uint32 rsvd3; /* 0x007C */
+ uint32 CHANCTRL[32U]; /* 0x0080-0x0FC */
+} vimBASE_t;
+
+#define vimREG ((vimBASE_t *)0xFFFFFE00U)
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+#endif
Index: firmware/include/rti.h
===================================================================
diff -u
--- firmware/include/rti.h (revision 0)
+++ firmware/include/rti.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,326 @@
+/** @file rti.h
+* @brief RTI Driver Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* - Interface Prototypes
+* .
+* which are relevant for the RTI driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __RTI_H__
+#define __RTI_H__
+
+#include "reg_rti.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* RTI General Definitions */
+
+/** @def rtiCOUNTER_BLOCK0
+* @brief Alias name for RTI counter block 0
+*
+* This is an alias name for the RTI counter block 0.
+*
+* @note This value should be used for API argument @a counter
+*/
+#define rtiCOUNTER_BLOCK0 0U
+
+/** @def rtiCOUNTER_BLOCK1
+* @brief Alias name for RTI counter block 1
+*
+* This is an alias name for the RTI counter block 1.
+*
+* @note This value should be used for API argument @a counter
+*/
+#define rtiCOUNTER_BLOCK1 1U
+
+/** @def rtiCOMPARE0
+* @brief Alias name for RTI compare 0
+*
+* This is an alias name for the RTI compare 0.
+*
+* @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE0 0U
+
+/** @def rtiCOMPARE1
+* @brief Alias name for RTI compare 1
+*
+* This is an alias name for the RTI compare 1.
+*
+* @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE1 1U
+
+/** @def rtiCOMPARE2
+* @brief Alias name for RTI compare 2
+*
+* This is an alias name for the RTI compare 2.
+*
+* @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE2 2U
+
+/** @def rtiCOMPARE3
+* @brief Alias name for RTI compare 3
+*
+* This is an alias name for the RTI compare 3.
+*
+* @note This value should be used for API argument @a compare
+*/
+#define rtiCOMPARE3 3U
+
+/** @def rtiNOTIFICATION_COMPARE0
+* @brief Alias name for RTI compare 0 notification
+*
+* This is an alias name for the RTI compare 0 notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE0 1U
+
+/** @def rtiNOTIFICATION_COMPARE1
+* @brief Alias name for RTI compare 1 notification
+*
+* This is an alias name for the RTI compare 1 notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE1 2U
+
+/** @def rtiNOTIFICATION_COMPARE2
+* @brief Alias name for RTI compare 2 notification
+*
+* This is an alias name for the RTI compare 2 notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE2 4U
+
+/** @def rtiNOTIFICATION_COMPARE3
+* @brief Alias name for RTI compare 3 notification
+*
+* This is an alias name for the RTI compare 3 notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COMPARE3 8U
+
+/** @def rtiNOTIFICATION_TIMEBASE
+* @brief Alias name for RTI timebase notification
+*
+* This is an alias name for the RTI timebase notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_TIMEBASE 0x10000U
+
+/** @def rtiNOTIFICATION_COUNTER0
+* @brief Alias name for RTI counter block 0 overflow notification
+*
+* This is an alias name for the RTI counter block 0 overflow notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COUNTER0 0x20000U
+
+/** @def rtiNOTIFICATION_COUNTER1
+* @brief Alias name for RTI counter block 1 overflow notification
+*
+* This is an alias name for the RTI counter block 1 overflow notification.
+*
+* @note This value should be used for API argument @a notification
+*/
+#define rtiNOTIFICATION_COUNTER1 0x40000U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @enum dwdViolationTag
+* @brief DWD Violations
+*/
+typedef enum dwdViolationTag
+{
+ NoTime_Violation = 0U,
+ Time_Window_Violation = 1U,
+ EndTime_Window_Violation = 2U,
+ StartTime_Window_Violation = 3U,
+ Key_Seq_Violation = 4U
+}dwdViolation_t;
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @enum dwdResetStatusTag
+* @brief DWD Reset status
+*/
+typedef enum dwdResetStatusTag
+{
+ No_Reset_Generated = 0U,
+ Reset_Generated = 1U
+}dwdResetStatus_t;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/** @enum dwwdReactionTag
+* @brief DWWD Reaction on vioaltion
+*/
+typedef enum dwwdReactionTag
+{
+ Generate_Reset = 0x00000005U,
+ Generate_NMI = 0x0000000AU
+}dwwdReaction_t;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @enum dwwdWindowSizeTag
+* @brief DWWD Window size
+*/
+typedef enum dwwdWindowSizeTag
+{
+ Size_100_Percent = 0x00000005U,
+ Size_50_Percent = 0x00000050U,
+ Size_25_Percent = 0x00000500U,
+ Size_12_5_Percent = 0x00005000U,
+ Size_6_25_Percent = 0x00050000U,
+ Size_3_125_Percent = 0x00500000U
+}dwwdWindowSize_t;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+/* Configuration registers */
+typedef struct rti_config_reg
+{
+ uint32 CONFIG_GCTRL;
+ uint32 CONFIG_TBCTRL;
+ uint32 CONFIG_CAPCTRL;
+ uint32 CONFIG_COMPCTRL;
+ uint32 CONFIG_UDCP0;
+ uint32 CONFIG_UDCP1;
+ uint32 CONFIG_UDCP2;
+ uint32 CONFIG_UDCP3;
+} rti_config_reg_t;
+
+
+/* Configuration registers initial value */
+#define RTI_GCTRL_CONFIGVALUE ((uint32)((uint32)0x0U << 16U) | 0x00000000U)
+#define RTI_TBCTRL_CONFIGVALUE 0x00000000U
+#define RTI_CAPCTRL_CONFIGVALUE (0U | 0U)
+#define RTI_COMPCTRL_CONFIGVALUE (0x00000000U | 0x00000100U | 0x00000000U | 0x00000000U)
+#define RTI_UDCP0_CONFIGVALUE 10400U
+#define RTI_UDCP1_CONFIGVALUE 104000U
+#define RTI_UDCP2_CONFIGVALUE 83200U
+#define RTI_UDCP3_CONFIGVALUE 520000U
+
+
+/**
+ * @defgroup RTI RTI
+ * @brief Real Time Interrupt Module.
+ *
+ * The real-time interrupt (RTI) module provides timer functionality for operating systems and for
+ * benchmarking code. The RTI module can incorporate several counters that define the timebases needed
+ * for scheduling in the operating system.
+ *
+ * Related Files
+ * - reg_rti.h
+ * - rti.h
+ * - rti.c
+ * @addtogroup RTI
+ * @{
+ */
+
+/* RTI Interface Functions */
+
+void rtiInit(void);
+void rtiStartCounter(uint32 counter);
+void rtiStopCounter(uint32 counter);
+uint32 rtiResetCounter(uint32 counter);
+void rtiSetPeriod(uint32 compare, uint32 period);
+uint32 rtiGetPeriod(uint32 compare);
+uint32 rtiGetCurrentTick(uint32 compare);
+void rtiEnableNotification(uint32 notification);
+void rtiDisableNotification(uint32 notification);
+void dwdInit(uint16 dwdPreload);
+void dwwdInit(dwwdReaction_t Reaction, uint16 dwdPreload, dwwdWindowSize_t Window_Size);
+uint32 dwwdGetCurrentDownCounter(void);
+void dwdCounterEnable(void);
+void dwdSetPreload(uint16 dwdPreload);
+void dwdReset(void);
+void dwdGenerateSysReset(void);
+boolean IsdwdKeySequenceCorrect(void);
+dwdResetStatus_t dwdGetStatus(void);
+dwdViolation_t dwdGetViolationStatus(void);
+void dwdClearFlag(void);
+void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void rtiNotification(uint32 notification)
+* @brief Notification of RTI module
+* @param[in] notification Select notification of RTI module:
+* - rtiNOTIFICATION_COMPARE0: RTI compare 0 notification
+* - rtiNOTIFICATION_COMPARE1: RTI compare 1 notification
+* - rtiNOTIFICATION_COMPARE2: RTI compare 2 notification
+* - rtiNOTIFICATION_COMPARE3: RTI compare 3 notification
+* - rtiNOTIFICATION_TIMEBASE: RTI Timebase notification
+* - rtiNOTIFICATION_COUNTER0: RTI counter 0 overflow notification
+* - rtiNOTIFICATION_COUNTER1: RTI counter 1 overflow notification
+*
+* @note This function has to be provide by the user.
+*/
+void rtiNotification(uint32 notification);
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
Index: firmware/include/sci.h
===================================================================
diff -u
--- firmware/include/sci.h (revision 0)
+++ firmware/include/sci.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,238 @@
+/** @file sci.h
+* @brief SCI Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef __SCI_H__
+#define __SCI_H__
+
+#include "reg_sci.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @enum sciIntFlags
+* @brief Interrupt Flag Definitions
+*
+* Used with sciEnableNotification, sciDisableNotification
+*/
+enum sciIntFlags
+{
+ SCI_FE_INT = 0x04000000U, /* framing error */
+ SCI_OE_INT = 0x02000000U, /* overrun error */
+ SCI_PE_INT = 0x01000000U, /* parity error */
+ SCI_RX_INT = 0x00000200U, /* receive buffer ready */
+ SCI_TX_INT = 0x00000100U, /* transmit buffer ready */
+ SCI_WAKE_INT = 0x00000002U, /* wakeup */
+ SCI_BREAK_INT = 0x00000001U /* break detect */
+};
+
+/** @def SCI_IDLE
+* @brief Alias name for the SCI IDLE Flag
+*
+* This is an alias name for the SCI IDLE Flag.
+*
+*/
+#define SCI_IDLE 0x00000004U
+
+/** @struct sciBase
+* @brief SCI Register Definition
+*
+* This structure is used to access the SCI module registers.
+*/
+/** @typedef sciBASE_t
+* @brief SCI Register Frame Type Definition
+*
+* This type is used to access the SCI Registers.
+*/
+
+enum sciPinSelect
+{
+ PIN_SCI_TX = 4U,
+ PIN_SCI_RX = 2U
+};
+
+
+/* Configuration registers */
+typedef struct sci_config_reg
+{
+ uint32 CONFIG_GCR0;
+ uint32 CONFIG_GCR1;
+ uint32 CONFIG_SETINT;
+ uint32 CONFIG_SETINTLVL;
+ uint32 CONFIG_FORMAT;
+ uint32 CONFIG_BRS;
+ uint32 CONFIG_PIO0;
+ uint32 CONFIG_PIO1;
+ uint32 CONFIG_PIO6;
+ uint32 CONFIG_PIO7;
+ uint32 CONFIG_PIO8;
+} sci_config_reg_t;
+
+
+/* Configuration registers initial value for SCI*/
+#define SCI_GCR0_CONFIGVALUE 0x00000001U
+#define SCI_GCR1_CONFIGVALUE ((uint32)((uint32)1U << 5U) \
+ |(uint32)((uint32)(1U-1U) << 4U) \
+ |(uint32)((uint32)0U << 3U) \
+ |(uint32)((uint32)0U << 2U) \
+ |(uint32)((uint32)1U << 1U) \
+ |(uint32)((uint32)0U << 2U) \
+ |(uint32)(0x03000080U))
+
+#define SCI_SETINTLVL_CONFIGVALUE ((uint32)((uint32)0U << 26U) \
+ |(uint32)((uint32)0U << 25U) \
+ |(uint32)((uint32)0U << 24U) \
+ |(uint32)((uint32)0U << 9U) \
+ |(uint32)((uint32)0U << 8U) \
+ |(uint32)((uint32)0U << 1U) \
+ |(uint32)((uint32)0U << 0U))
+
+#define SCI_SETINT_CONFIGVALUE ((uint32)((uint32)1U << 26U) \
+ |(uint32)((uint32)1U << 25U) \
+ |(uint32)((uint32)0U << 24U) \
+ |(uint32)((uint32)0U << 9U) \
+ |(uint32)((uint32)0U << 1U) \
+ |(uint32)((uint32)0U << 0U))
+
+#define SCI_FORMAT_CONFIGVALUE (8U - 1U)
+#define SCI_BRS_CONFIGVALUE (55U)
+#define SCI_PIO0_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)1U << 1U))
+#define SCI_PIO1_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)0U << 1U))
+#define SCI_PIO6_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)0U << 1U))
+#define SCI_PIO7_CONFIGVALUE ((uint32)((uint32)0U << 2U ) | (uint32)((uint32)0U << 1U))
+#define SCI_PIO8_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)1U << 1U))
+
+
+
+/* Configuration registers initial value for SCI*/
+#define SCILIN_GCR0_CONFIGVALUE 0x00000001U
+#define SCILIN_GCR1_CONFIGVALUE ((uint32)((uint32)1U << 5U) \
+ |(uint32)((uint32)(1U-1U) << 4U) \
+ |(uint32)((uint32)0U << 3U) \
+ |(uint32)((uint32)0U << 2U) \
+ |(uint32)((uint32)1U << 1U) \
+ |(uint32)((uint32)0U << 2U) \
+ |(uint32)(0x03000080U))
+
+#define SCILIN_SETINTLVL_CONFIGVALUE ((uint32)((uint32)0U << 26U) \
+ |(uint32)((uint32)0U << 25U) \
+ |(uint32)((uint32)0U << 24U) \
+ |(uint32)((uint32)0U << 9U) \
+ |(uint32)((uint32)0U << 8U) \
+ |(uint32)((uint32)0U << 1U) \
+ |(uint32)((uint32)0U))
+
+#define SCILIN_SETINT_CONFIGVALUE ((uint32)((uint32)1U << 26U) \
+ |(uint32)((uint32)1U << 25U) \
+ |(uint32)((uint32)0U << 24U) \
+ |(uint32)((uint32)0U << 9U) \
+ |(uint32)((uint32)0U << 1U) \
+ |(uint32)((uint32)0U << 0U))
+
+#define SCILIN_FORMAT_CONFIGVALUE (8U - 1U)
+#define SCILIN_BRS_CONFIGVALUE (6U)
+#define SCILIN_PIO0_CONFIGVALUE ((uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U))
+#define SCILIN_PIO1_CONFIGVALUE ((uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 1U))
+#define SCILIN_PIO6_CONFIGVALUE ((uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 1U))
+#define SCILIN_PIO7_CONFIGVALUE ((uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U))
+#define SCILIN_PIO8_CONFIGVALUE ((uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U))
+
+
+
+/**
+ * @defgroup SCI SCI
+ * @brief Serial Communication Interface Module.
+ *
+ * The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
+ * to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-line.
+ *
+ * Related Files
+ * - reg_sci.h
+ * - sci.h
+ * - sci.c
+ * @addtogroup SCI
+ * @{
+ */
+
+/* SCI Interface Functions */
+void sciInit(void);
+void sciSetFunctional(sciBASE_t *sci, uint32 port);
+void sciSetBaudrate(sciBASE_t *sci, uint32 baud);
+uint32 sciIsTxReady(sciBASE_t *sci);
+void sciSendByte(sciBASE_t *sci, uint8 byte);
+void sciSend(sciBASE_t *sci, uint32 length, uint8 * data);
+uint32 sciIsRxReady(sciBASE_t *sci);
+uint32 sciIsIdleDetected(sciBASE_t *sci);
+uint32 sciRxError(sciBASE_t *sci);
+uint32 sciReceiveByte(sciBASE_t *sci);
+void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data);
+void sciEnableNotification(sciBASE_t *sci, uint32 flags);
+void sciDisableNotification(sciBASE_t *sci, uint32 flags);
+void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype);
+void sciDisableLoopback(sciBASE_t *sci);
+void sciEnterResetState(sciBASE_t *sci);
+void sciExitResetState(sciBASE_t *sci);
+void sciGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type);
+void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type);
+/** @fn void sciNotification(sciBASE_t *sci, uint32 flags)
+* @brief Interrupt callback
+* @param[in] sci - sci module base address
+* @param[in] flags - copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt. The parameter passed to the callback is a copy of the
+* interrupt flag register.
+*/
+void sciNotification(sciBASE_t *sci, uint32 flags);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/spi.h
===================================================================
diff -u
--- firmware/include/spi.h (revision 0)
+++ firmware/include/spi.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,222 @@
+/** @file spi.h
+* @brief SPI Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#include "reg_spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @enum chipSelect
+* @brief Transfer Group Chip Select
+*/
+enum spiChipSelect
+{
+ SPI_CS_NONE = 0xFFU,
+ SPI_CS_0 = 0xFEU,
+ SPI_CS_1 = 0xFDU,
+ SPI_CS_2 = 0xFBU,
+ SPI_CS_3 = 0xF7U,
+ SPI_CS_4 = 0xEFU,
+ SPI_CS_5 = 0xDFU,
+ SPI_CS_6 = 0xBFU,
+ SPI_CS_7 = 0x7FU
+};
+
+/** @enum spiPinSelect
+* @brief spi Pin Select
+*/
+enum spiPinSelect
+{
+ SPI_PIN_CS0 = 0U,
+ SPI_PIN_CS1 = 1U,
+ SPI_PIN_CS2 = 2U,
+ SPI_PIN_CS3 = 3U,
+ SPI_PIN_CS4 = 4U,
+ SPI_PIN_CS5 = 5U,
+ SPI_PIN_CS6 = 6U,
+ SPI_PIN_CS7 = 7U,
+ SPI_PIN_ENA = 8U,
+ SPI_PIN_CLK = 9U,
+ SPI_PIN_SIMO = 10U,
+ SPI_PIN_SOMI = 11U,
+ SPI_PIN_SIMO_1 = 17U,
+ SPI_PIN_SIMO_2 = 18U,
+ SPI_PIN_SIMO_3 = 19U,
+ SPI_PIN_SIMO_4 = 20U,
+ SPI_PIN_SIMO_5 = 21U,
+ SPI_PIN_SIMO_6 = 22U,
+ SPI_PIN_SIMO_7 = 23U,
+ SPI_PIN_SOMI_1 = 25U,
+ SPI_PIN_SOMI_2 = 26U,
+ SPI_PIN_SOMI_3 = 27U,
+ SPI_PIN_SOMI_4 = 28U,
+ SPI_PIN_SOMI_5 = 29U,
+ SPI_PIN_SOMI_6 = 30U,
+ SPI_PIN_SOMI_7 = 31U
+};
+
+/** @enum dataformat
+* @brief SPI dataformat register select
+*/
+typedef enum dataformat
+{
+ SPI_FMT_0 = 0U,
+ SPI_FMT_1 = 1U,
+ SPI_FMT_2 = 2U,
+ SPI_FMT_3 = 3U
+}SPIDATAFMT_t;
+
+/** @struct spiDAT1RegConfig
+* @brief SPI data register configuration
+*/
+typedef struct spiDAT1RegConfig
+{
+ boolean CS_HOLD;
+ boolean WDEL;
+ SPIDATAFMT_t DFSEL;
+ uint8 CSNR;
+}spiDAT1_t;
+
+/** @enum SpiTxRxDataStatus
+* @brief SPI Data Status
+*/
+typedef enum SpiTxRxDataStatus
+{
+ SPI_READY = 0U,
+ SPI_PENDING = 1U,
+ SPI_COMPLETED = 2U
+}SpiDataStatus_t;
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+typedef struct spi_config_reg
+{
+ uint32 CONFIG_GCR1;
+ uint32 CONFIG_INT0;
+ uint32 CONFIG_LVL;
+ uint32 CONFIG_PC0;
+ uint32 CONFIG_PC1;
+ uint32 CONFIG_PC6;
+ uint32 CONFIG_PC7;
+ uint32 CONFIG_PC8;
+ uint32 CONFIG_DELAY;
+ uint32 CONFIG_FMT0;
+ uint32 CONFIG_FMT1;
+ uint32 CONFIG_FMT2;
+ uint32 CONFIG_FMT3;
+}spi_config_reg_t;
+
+
+
+
+
+
+
+
+
+
+/**
+ * @defgroup SPI SPI
+ * @brief Serial Peripheral Interface Module.
+ *
+ * SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
+ * programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
+ *
+ * Related Files
+ * - reg_spi.h
+ * - spi.h
+ * - spi.c
+ * @addtogroup SPI
+ * @{
+ */
+
+/* SPI Interface Functions */
+void spiInit(void);
+void spiSetFunctional(spiBASE_t *spi, uint32 port);
+void spiEnableNotification(spiBASE_t *spi, uint32 flags);
+void spiDisableNotification(spiBASE_t *spi, uint32 flags);
+uint32 spiTransmitData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff);
+void spiSendData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff);
+uint32 spiReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * destbuff);
+void spiGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * destbuff);
+uint32 spiTransmitAndReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff, uint16 * destbuff);
+void spiSendAndGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32 blocksize, uint16 * srcbuff, uint16 * destbuff);
+void spiEnableLoopback(spiBASE_t *spi, loopBackType_t Loopbacktype);
+void spiDisableLoopback(spiBASE_t *spi);
+SpiDataStatus_t SpiTxStatus(spiBASE_t *spi);
+SpiDataStatus_t SpiRxStatus(spiBASE_t *spi);
+
+/** @fn void spiNotification(spiBASE_t *spi, uint32 flags)
+* @brief Interrupt callback
+* @param[in] spi - Spi module base address
+* @param[in] flags - Copy of error interrupt flags
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt. The parameter passed to the callback is a copy of the
+* interrupt flag register.
+*/
+void spiNotification(spiBASE_t *spi, uint32 flags);
+
+/** @fn void spiEndNotification(spiBASE_t *spi)
+* @brief Interrupt callback for End of TX or RX data length.
+* @param[in] spi - Spi module base address
+*
+* This is a callback that is provided by the application and is called upon
+* an interrupt at the End of TX or RX data length.
+*/
+void spiEndNotification(spiBASE_t *spi);
+
+/**@}*/
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
Index: firmware/include/std_nhet.h
===================================================================
diff -u
--- firmware/include/std_nhet.h (revision 0)
+++ firmware/include/std_nhet.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,2499 @@
+/** @file std_nhet.h
+* @brief NHET Instruction Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef __STD_NHET_H__
+#define __STD_NHET_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifndef HET_v2
+# define HET_v2 0
+#endif
+
+#if ((__little_endian__ == 0) || (__LITTLE_ENDIAN__ == 0) || defined(_TMS470_BIG) || defined(__big_endian__))
+
+#ifndef HETBYTE
+# define HETBYTE uint8
+#endif
+
+typedef struct memory_format
+{
+ uint32 program_word ;
+ uint32 control_word ;
+ uint32 data_word ;
+ uint32 reserved_word ;
+} HET_MEMORY ;
+
+/*---------------------------------------------*/
+/* ACMP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct acmp_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 9 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 coutprv : 1 ;
+ uint32 : 2 ;
+ uint32 en_pin_action : 1 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 ext_reg : 1 ;
+ uint32 : 2 ;
+ uint32 pin_action : 1 ;
+ uint32 : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} ACMP_FIELDS;
+
+typedef union
+{
+ ACMP_FIELDS acmp ;
+ HET_MEMORY memory ;
+} ACMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECMP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct ecmp_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 hr_lr : 1 ;
+ uint32 angle_compare : 1 ;
+ uint32 : 7 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 3 ;
+ uint32 en_pin_action : 1 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 sub_opcode : 2 ;
+ uint32 pin_action : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} ECMP_FIELDS;
+
+typedef union
+{
+ ECMP_FIELDS ecmp ;
+ HET_MEMORY memory ;
+} ECMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCMP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct scmp_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 2 ;
+ uint32 : 2 ;
+ uint32 : 5 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 coutprv : 1 ;
+ uint32 : 2 ;
+ uint32 en_pin_action : 1 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 compare_mode : 2 ;
+ uint32 pin_action : 1 ;
+ uint32 : 2 ;
+ uint32 restart_en : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} SCMP_FIELDS ;
+
+typedef union
+{
+ SCMP_FIELDS scmp ;
+ HET_MEMORY memory ;
+} SCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MCMP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct mcmp_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 hr_lr : 1 ;
+ uint32 angle_compare : 1 ;
+ uint32 : 1 ;
+ uint32 save_subtract : 1 ;
+ uint32 : 5 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 3 ;
+ uint32 en_pin_action : 1 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 sub_opcode : 1 ;
+ uint32 order : 1 ;
+ uint32 pin_action : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} MCMP_FIELDS ;
+
+typedef union
+{
+ MCMP_FIELDS mcmp ;
+ HET_MEMORY memory ;
+} MCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV64 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct mov64_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 3 ;
+ uint32 en_pin_action : 1 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 compare_mode : 2 ;
+ uint32 pin_action : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} MOV64_FIELDS ;
+
+typedef union
+{
+ MOV64_FIELDS mov64 ;
+ HET_MEMORY memory ;
+} MOV64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DADM64 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct dadm64_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 3 ;
+ uint32 en_pin_action : 1 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 compare_mode : 2 ;
+ uint32 pin_action : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} DADM64_FIELDS ;
+
+typedef union
+{
+ DADM64_FIELDS dadm64 ;
+ HET_MEMORY memory ;
+} DADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* RADM64 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct RADM64_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 3 ;
+ uint32 en_pin_action : 1 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 compare_mode : 2 ;
+ uint32 pin_action : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} RADM64_FIELDS ;
+
+
+typedef union
+{
+ RADM64_FIELDS radm64 ;
+ HET_MEMORY memory ;
+} RADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV32 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct MOV32_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 3 ;
+ uint32 z_flag : 1 ;
+ uint32 : 15 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode : 1 ;
+ uint32 move_type : 2 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} MOV32_FIELDS ;
+
+
+typedef union
+{
+ MOV32_FIELDS mov32 ;
+ HET_MEMORY memory ;
+} MOV32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADM32 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct ADM32_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 19 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode : 1 ;
+ uint32 move_type : 2 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} ADM32_FIELDS ;
+
+
+typedef union
+{
+ ADM32_FIELDS adm32 ;
+ HET_MEMORY memory ;
+} ADM32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADCNST INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct ADCNST_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 control : 1 ; /* pk */
+ uint32 : 1 ;
+ uint32 constant : 25 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} ADCNST_FIELDS ;
+
+
+typedef union
+{
+ ADCNST_FIELDS adcnst ;
+ HET_MEMORY memory ;
+} ADCNST_INSTRUCTION;
+
+
+/*----------------------------------------------*/
+/* ADD INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct ADD_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 control : 1;
+ uint32 sub_opcode3 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 src_2 : 3 ;
+ uint32 shft_mode : 3 ;
+ uint32 shft_cnt : 5 ;
+ uint32 reg_ext : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 rem_dest : 2 ;
+ uint32 reg : 2 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} ADD_FIELDS ;
+
+
+typedef union
+{
+ ADD_FIELDS add ;
+ HET_MEMORY memory ;
+} ADD_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* ADC INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct ADC_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 control : 1;
+ uint32 sub_opcode3 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 src_2 : 3 ;
+ uint32 shft_mode : 3 ;
+ uint32 shft_cnt : 5 ;
+ uint32 reg_ext : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 rem_dest : 2 ;
+ uint32 reg : 2 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} ADC_FIELDS ;
+
+
+typedef union
+{
+ ADC_FIELDS adc ;
+ HET_MEMORY memory ;
+} ADC_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* SUB INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct SUB_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 control : 1;
+ uint32 sub_opcode3 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 src_2 : 3 ;
+ uint32 shft_mode : 3 ;
+ uint32 shft_cnt : 5 ;
+ uint32 reg_ext : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 rem_dest : 2 ;
+ uint32 reg : 2 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} SUB_FIELDS ;
+
+
+typedef union
+{
+ SUB_FIELDS sub ;
+ HET_MEMORY memory ;
+} SUB_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* SBB INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct SBB_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 control : 1;
+ uint32 sub_opcode3 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 src_2 : 3 ;
+ uint32 shft_mode : 3 ;
+ uint32 shft_cnt : 5 ;
+ uint32 reg_ext : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 rem_dest : 2 ;
+ uint32 reg : 2 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} SBB_FIELDS ;
+
+
+typedef union
+{
+ SBB_FIELDS sbb ;
+ HET_MEMORY memory ;
+} SBB_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* AND INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct AND_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 control : 1;
+ uint32 sub_opcode3 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 src_2 : 3 ;
+ uint32 shft_mode : 3 ;
+ uint32 shft_cnt : 5 ;
+ uint32 reg_ext : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 rem_dest : 2 ;
+ uint32 reg : 2 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} AND_FIELDS ;
+
+
+typedef union
+{
+#ifdef __cplusplus
+ AND_FIELDS and_cpp ;
+#else
+ AND_FIELDS and ;
+#endif
+ HET_MEMORY memory ;
+} AND_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* OR INSTRUCTION */
+/*----------------------------------------------*/
+
+
+typedef struct OR_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 control : 1;
+ uint32 sub_opcode3 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 src_2 : 3 ;
+ uint32 shft_mode : 3 ;
+ uint32 shft_cnt : 5 ;
+ uint32 reg_ext : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 rem_dest : 2 ;
+ uint32 reg : 2 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} OR_FIELDS ;
+
+
+typedef union
+{
+#ifdef __cplusplus
+ OR_FIELDS or_cpp ;
+#else
+ OR_FIELDS or ;
+#endif
+ HET_MEMORY memory ;
+} OR_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* XOR INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct XOR_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 remote_address : 9 ;
+
+ uint32 : 5 ;
+ uint32 control : 1;
+ uint32 sub_opcode3 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 src_2 : 3 ;
+ uint32 shft_mode : 3 ;
+ uint32 shft_cnt : 5 ;
+ uint32 reg_ext : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 rem_dest : 2 ;
+ uint32 reg : 2 ;
+ uint32 : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} XOR_FIELDS ;
+
+
+typedef union
+{
+#ifdef __cplusplus
+ XOR_FIELDS xor_cpp ;
+#else
+ XOR_FIELDS xor ;
+#endif
+ HET_MEMORY memory ;
+} XOR_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* CNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct CNT_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 angle_cnt : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 : 4 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 1 ;
+ uint32 max : 25 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} CNT_FIELDS ;
+
+typedef union
+{
+ CNT_FIELDS cnt ;
+ HET_MEMORY memory ;
+} CNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* APCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct apcnt_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 interrupt_enable : 1 ;
+ uint32 edge_select : 2 ;
+ uint32 : 6 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 previous_bit : 1 ;
+ uint32 count : 25 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} APCNT_FIELDS ;
+
+typedef union
+{
+ APCNT_FIELDS apcnt ;
+ HET_MEMORY memory ;
+} APCNT_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* PCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct pcnt_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 interrupt_enable : 1 ;
+ uint32 period_pulse_select : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 previous_bit : 1 ;
+ uint32 count : 25 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} PCNT_FIELDS ;
+
+typedef union
+{
+ PCNT_FIELDS pcnt ;
+ HET_MEMORY memory ;
+} PCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct scnt_format
+{
+ uint32 : 9 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 1 ;
+ uint32 count_mode : 2 ;
+ uint32 step_width : 2 ;
+ uint32 : 4 ;
+
+ uint32 : 5 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 1 ;
+ uint32 gap_start : 25 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} SCNT_FIELDS ;
+
+typedef union
+{
+ SCNT_FIELDS scnt ;
+ HET_MEMORY memory ;
+} SCNT_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* ACNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct acnt_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 edge_select : 1 ;
+ uint32 : 7 ;
+ uint32 interrupt_enable : 1 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 previous_bit : 1 ;
+ uint32 gap_end : 25 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} ACNT_FIELDS ;
+
+typedef union
+{
+ ACNT_FIELDS acnt ;
+ HET_MEMORY memory ;
+} ACNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct ecnt_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 1 ;
+ uint32 count_mode : 2 ;
+ uint32 : 6 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 previous_bit : 1 ;
+ uint32 : 3 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 count_cond : 3 ;
+ uint32 : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} ECNT_FIELDS ;
+
+typedef union
+{
+ ECNT_FIELDS ecnt ;
+ HET_MEMORY memory ;
+} ECNT_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* RCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct rcnt_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 1 ;
+ uint32 count_mode : 2 ;
+ uint32 : 5 ;
+ uint32 count_mode1 : 1 ;
+
+ uint32 : 3 ;
+ uint32 : 2 ;
+ uint32 control : 1 ;
+ uint32 : 1 ;
+ uint32 divisor : 25 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} RCNT_FIELDS ;
+
+typedef union
+{
+ RCNT_FIELDS rcnt ;
+ HET_MEMORY memory ;
+} RCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJNZ INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct djnz_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 1 ;
+ uint32 sub_opcode : 2 ;
+ uint32 : 6 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 4 ;
+ uint32 cond_addr : 9 ;
+ uint32 : 10 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} DJNZ_FIELDS ;
+
+typedef union
+{
+ DJNZ_FIELDS djnz ;
+ HET_MEMORY memory ;
+} DJNZ_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJZ INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct djz_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 1 ;
+ uint32 sub_opcode : 2 ;
+ uint32 : 6 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 4 ;
+ uint32 cond_addr : 9 ;
+ uint32 : 10 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} DJZ_FIELDS ;
+
+typedef union
+{
+ DJZ_FIELDS djz ;
+ HET_MEMORY memory ;
+} DJZ_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* PWCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct pwcnt_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 hr_lr : 1 ;
+ uint32 count_mode : 2 ;
+ uint32 : 6 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 3 ;
+ uint32 en_pin_action : 1 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 3 ;
+ uint32 pin_action : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} PWCNT_FIELDS ;
+
+typedef union
+{
+ PWCNT_FIELDS pwcnt ;
+ HET_MEMORY memory ;
+} PWCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* WCAP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct wcap_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 hr_lr : 1 ;
+ uint32 : 8 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 previous_bit : 1 ;
+ uint32 : 3 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 capture_condition : 2 ;
+ uint32 : 2 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} WCAP_FIELDS ;
+
+typedef union
+{
+ WCAP_FIELDS wcap ;
+ HET_MEMORY memory ;
+} WCAP_INSTRUCTION;
+
+/*----------------------------------------------*/
+/* WCAPE INSTRUCTION */
+/*----------------------------------------------*/
+typedef struct wcape_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 9 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 previous_bit : 1 ;
+ uint32 : 3 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 capture_condition : 2 ;
+ uint32 : 2 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 ts_data : 25 ;
+ uint32 ec_data : 7 ;
+
+} WCAPE_FIELDS ;
+
+typedef union
+{
+ WCAPE_FIELDS wcape ;
+ HET_MEMORY memory ;
+} WCAPE_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* BR INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct br_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 9 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 previous_bit : 1 ;
+ uint32 : 3 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+
+#if HET_v2
+ uint32 branch_condition : 5 ;
+#else
+ uint32 branch_condition : 3 ;
+ uint32 : 1 ;
+ uint32 : 1 ;
+#endif
+
+ uint32 : 2 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 hr_data : 7 ;
+
+} BR_FIELDS ;
+
+typedef union
+{
+ BR_FIELDS br ;
+ HET_MEMORY memory ;
+} BR_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SHFT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct shft_format
+{
+ uint32 : 6 ;
+ uint32 reqnum : 3 ;
+ uint32 brk : 1 ;
+ uint32 next_program_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 : 5 ;
+ uint32 shift_mode : 4 ;
+
+ uint32 : 3 ;
+ uint32 request : 2 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 previous_bit : 1 ;
+ uint32 : 3 ;
+ uint32 cond_addr : 9 ;
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 shift_condition : 2 ;
+ uint32 : 2 ;
+ uint32 t_register_select : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 interrupt_enable : 1 ;
+
+
+ uint32 data : 25 ;
+ uint32 : 7 ;
+
+} SHFT_FIELDS ;
+
+typedef union
+{
+ SHFT_FIELDS shft ;
+ HET_MEMORY memory ;
+} SHFT_INSTRUCTION;
+
+/* ---------------------------------------------------------------------------------------------------- */
+
+#else
+
+#ifndef HETBYTE
+# define HETBYTE uint8
+#endif
+
+typedef struct memory_format
+{
+ uint32 program_word ;
+ uint32 control_word ;
+ uint32 data_word ;
+ uint32 reserved_word ;
+} HET_MEMORY ;
+
+/*---------------------------------------------*/
+/* ACMP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct acmp_format
+{
+ uint32 : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 : 1 ;
+ uint32 pin_action : 1 ;
+ uint32 : 3 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 en_pin_action : 1 ;
+ uint32 : 2 ;
+ uint32 coutprv : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} ACMP_FIELDS;
+
+typedef union
+{
+ ACMP_FIELDS acmp ;
+ HET_MEMORY memory ;
+} ACMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECMP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct ecmp_format
+{
+ uint32 : 7 ;
+ uint32 angle_compare : 1 ;
+ uint32 hr_lr : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 pin_action : 1 ;
+ uint32 sub_opcode : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 en_pin_action : 1 ;
+ uint32 : 3 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} ECMP_FIELDS;
+
+typedef union
+{
+ ECMP_FIELDS ecmp ;
+ HET_MEMORY memory ;
+} ECMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCMP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct scmp_format
+{
+ uint32 : 5 ;
+ uint32 : 2 ;
+ uint32 : 2 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 restart_en : 1 ;
+ uint32 : 2 ;
+ uint32 pin_action : 1 ;
+ uint32 compare_mode : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 en_pin_action : 1 ;
+ uint32 : 2 ;
+ uint32 coutprv : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} SCMP_FIELDS ;
+
+typedef union
+{
+ SCMP_FIELDS scmp ;
+ HET_MEMORY memory ;
+} SCMP_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MCMP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct mcmp_format
+{
+ uint32 : 5 ;
+ uint32 save_subtract : 1 ;
+ uint32 : 1 ;
+ uint32 angle_compare : 1 ;
+ uint32 hr_lr : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 pin_action : 1 ;
+ uint32 order : 1 ;
+ uint32 sub_opcode : 1 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 en_pin_action : 1 ;
+ uint32 : 3 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} MCMP_FIELDS ;
+
+typedef union
+{
+ MCMP_FIELDS mcmp ;
+ HET_MEMORY memory ;
+} MCMP_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* MOV64 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct mov64_format
+{
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 pin_action : 1 ;
+ uint32 compare_mode : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 en_pin_action : 1 ;
+ uint32 : 3 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} MOV64_FIELDS ;
+
+typedef union
+{
+ MOV64_FIELDS mov64 ;
+ HET_MEMORY memory ;
+} MOV64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DADM64 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct dadm64_format
+{
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 pin_action : 1 ;
+ uint32 compare_mode : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 en_pin_action : 1 ;
+ uint32 : 3 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} DADM64_FIELDS ;
+
+typedef union
+{
+ DADM64_FIELDS dadm64 ;
+ HET_MEMORY memory ;
+} DADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* RADM64 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct RADM64_format
+{
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 pin_action : 1 ;
+ uint32 compare_mode : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 en_pin_action : 1 ;
+ uint32 : 3 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} RADM64_FIELDS ;
+
+
+typedef union
+{
+ RADM64_FIELDS radm64 ;
+ HET_MEMORY memory ;
+} RADM64_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* MOV32 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct MOV32_format
+{
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 move_type : 2 ;
+ uint32 sub_opcode : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 : 15 ;
+ uint32 z_flag : 1 ;
+ uint32 : 3 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} MOV32_FIELDS ;
+
+
+typedef union
+{
+ MOV32_FIELDS mov32 ;
+ HET_MEMORY memory ;
+} MOV32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADM32 INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct ADM32_format
+{
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 move_type : 2 ;
+ uint32 sub_opcode : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 : 19 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} ADM32_FIELDS ;
+
+
+typedef union
+{
+ ADM32_FIELDS adm32 ;
+ HET_MEMORY memory ;
+} ADM32_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ADCNST INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct ADCNST_format
+{
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 constant : 25 ;
+ uint32 : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} ADCNST_FIELDS ;
+
+
+typedef union
+{
+ ADCNST_FIELDS adcnst ;
+ HET_MEMORY memory ;
+} ADCNST_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* ADD INSTRUCTION */
+/*----------------------------------------------*/
+typedef struct ADD_format
+{
+
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 reg : 2 ;
+ uint32 rem_dest : 2 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 reg_ext : 1 ;
+ uint32 shft_cnt : 5 ;
+ uint32 shft_mode : 3 ;
+ uint32 src_2 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 sub_opcode3 : 3 ;
+ uint32 control : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+
+} ADD_FIELDS ;
+
+
+typedef union
+{
+ ADD_FIELDS add ;
+ HET_MEMORY memory ;
+} ADD_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* ADC INSTRUCTION */
+/*----------------------------------------------*/
+
+
+typedef struct ADC_format
+{
+
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 reg : 2 ;
+ uint32 rem_dest : 2 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 reg_ext : 1 ;
+ uint32 shft_cnt : 5 ;
+ uint32 shft_mode : 3 ;
+ uint32 src_2 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 sub_opcode3 : 3 ;
+ uint32 control : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+
+} ADC_FIELDS ;
+
+
+typedef union
+{
+ ADC_FIELDS adc ;
+ HET_MEMORY memory ;
+} ADC_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* SUB INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct SUB_format
+{
+
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 reg : 2 ;
+ uint32 rem_dest : 2 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 reg_ext : 1 ;
+ uint32 shft_cnt : 5 ;
+ uint32 shft_mode : 3 ;
+ uint32 src_2 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 sub_opcode3 : 3 ;
+ uint32 control : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+
+} SUB_FIELDS ;
+
+
+typedef union
+{
+ SUB_FIELDS sub ;
+ HET_MEMORY memory ;
+} SUB_INSTRUCTION;
+
+
+
+
+
+/*----------------------------------------------*/
+/* SBB INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct SBB_format
+{
+
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 reg : 2 ;
+ uint32 rem_dest : 2 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 reg_ext : 1 ;
+ uint32 shft_cnt : 5 ;
+ uint32 shft_mode : 3 ;
+ uint32 src_2 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 sub_opcode3 : 3 ;
+ uint32 control : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+
+} SBB_FIELDS ;
+
+
+typedef union
+{
+ SBB_FIELDS sbb ;
+ HET_MEMORY memory ;
+} SBB_INSTRUCTION;
+
+
+
+
+/*----------------------------------------------*/
+/* AND INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct AND_format
+{
+
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 reg : 2 ;
+ uint32 rem_dest : 2 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 reg_ext : 1 ;
+ uint32 shft_cnt : 5 ;
+ uint32 shft_mode : 3 ;
+ uint32 src_2 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 sub_opcode3 : 3 ;
+ uint32 control : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+
+} AND_FIELDS ;
+
+
+typedef union
+{
+#ifdef __cplusplus
+ AND_FIELDS and_cpp ;
+#else
+ AND_FIELDS and ;
+#endif
+ HET_MEMORY memory ;
+} AND_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* OR INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct OR_format
+{
+
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 reg : 2 ;
+ uint32 rem_dest : 2 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 reg_ext : 1 ;
+ uint32 shft_cnt : 5 ;
+ uint32 shft_mode : 3 ;
+ uint32 src_2 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 sub_opcode3 : 3 ;
+ uint32 control : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+
+} OR_FIELDS ;
+
+
+typedef union
+{
+#ifdef __cplusplus
+ OR_FIELDS or_cpp ;
+#else
+ OR_FIELDS or ;
+#endif
+ HET_MEMORY memory ;
+} OR_INSTRUCTION;
+
+
+
+/*----------------------------------------------*/
+/* XOR INSTRUCTION */
+/*----------------------------------------------*/
+
+typedef struct XOR_format
+{
+
+ uint32 remote_address : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 : 1 ;
+ uint32 reg : 2 ;
+ uint32 rem_dest : 2 ;
+ uint32 sub_opcode1 : 1 ;
+ uint32 init_flag : 1 ;
+ uint32 reg_ext : 1 ;
+ uint32 shft_cnt : 5 ;
+ uint32 shft_mode : 3 ;
+ uint32 src_2 : 3 ;
+ uint32 src_1 : 4 ;
+ uint32 sub_opcode3 : 3 ;
+ uint32 control : 1 ;
+ uint32 : 5 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+
+} XOR_FIELDS ;
+
+
+typedef union
+{
+#ifdef __cplusplus
+ XOR_FIELDS xor_cpp ;
+#else
+ XOR_FIELDS xor ;
+#endif
+ HET_MEMORY memory ;
+} XOR_INSTRUCTION;
+
+
+
+
+/*---------------------------------------------*/
+/* CNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct CNT_format
+{
+ uint32 interrupt_enable : 1 ;
+ uint32 : 4 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 angle_cnt : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 max : 25 ;
+ uint32 : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} CNT_FIELDS ;
+
+typedef union
+{
+ CNT_FIELDS cnt ;
+ HET_MEMORY memory ;
+} CNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* APCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct apcnt_format
+{
+ uint32 : 6 ;
+ uint32 edge_select : 2 ;
+ uint32 interrupt_enable : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 count : 25 ;
+ uint32 previous_bit : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} APCNT_FIELDS ;
+
+typedef union
+{
+ APCNT_FIELDS apcnt ;
+ HET_MEMORY memory ;
+} APCNT_INSTRUCTION;
+
+
+
+/*---------------------------------------------*/
+/* PCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct pcnt_format
+{
+ uint32 pin_select : 5 ;
+ uint32 : 1 ;
+ uint32 period_pulse_select : 2 ;
+ uint32 interrupt_enable : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 count : 25 ;
+ uint32 previous_bit : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} PCNT_FIELDS ;
+
+typedef union
+{
+ PCNT_FIELDS pcnt ;
+ HET_MEMORY memory ;
+} PCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct scnt_format
+{
+ uint32 : 4 ;
+ uint32 step_width : 2 ;
+ uint32 count_mode : 2 ;
+ uint32 : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 : 9 ;
+
+ uint32 gap_start : 25 ;
+ uint32 : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 : 5 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} SCNT_FIELDS ;
+
+typedef union
+{
+ SCNT_FIELDS scnt ;
+ HET_MEMORY memory ;
+} SCNT_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* ACNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct acnt_format
+{
+ uint32 interrupt_enable : 1 ;
+ uint32 : 7 ;
+ uint32 edge_select : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 gap_end : 25 ;
+ uint32 previous_bit : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} ACNT_FIELDS ;
+
+typedef union
+{
+ ACNT_FIELDS acnt ;
+ HET_MEMORY memory ;
+} ACNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* ECNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct ecnt_format
+{
+ uint32 : 6 ;
+ uint32 count_mode : 2 ;
+ uint32 : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 : 1 ;
+ uint32 count_cond : 3 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 : 3 ;
+ uint32 previous_bit : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+
+} ECNT_FIELDS ;
+
+typedef union
+{
+ ECNT_FIELDS ecnt ;
+ HET_MEMORY memory ;
+} ECNT_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* RCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct rcnt_format
+{
+
+ uint32 count_mode1 : 1 ;
+ uint32 : 5 ;
+ uint32 count_mode : 2 ;
+ uint32 : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+
+ uint32 divisor : 25 ;
+ uint32 : 1 ;
+ uint32 control : 1 ;
+ uint32 : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+
+} RCNT_FIELDS ;
+
+typedef union
+{
+ RCNT_FIELDS rcnt ;
+ HET_MEMORY memory ;
+} RCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJNZ INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct djnz_format
+{
+ uint32 : 6 ;
+ uint32 sub_opcode : 2 ;
+ uint32 : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 : 10 ;
+ uint32 cond_addr : 9 ;
+ uint32 : 4 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} DJNZ_FIELDS ;
+
+typedef union
+{
+ DJNZ_FIELDS djnz ;
+ HET_MEMORY memory ;
+} DJNZ_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* DJZ INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct djz_format
+{
+ uint32 : 6 ;
+ uint32 sub_opcode : 2 ;
+ uint32 : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 : 10 ;
+ uint32 cond_addr : 9 ;
+ uint32 : 4 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} DJZ_FIELDS ;
+
+typedef union
+{
+ DJZ_FIELDS djz ;
+ HET_MEMORY memory ;
+} DJZ_INSTRUCTION;
+
+/*---------------------------------------------*/
+/* PWCNT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct pwcnt_format
+{
+ uint32 : 6 ;
+ uint32 count_mode : 2 ;
+ uint32 hr_lr : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 opposite_action : 1 ;
+ uint32 pin_action : 1 ;
+ uint32 : 3 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 en_pin_action : 1 ;
+ uint32 : 3 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} PWCNT_FIELDS ;
+
+typedef union
+{
+ PWCNT_FIELDS pwcnt ;
+ HET_MEMORY memory ;
+} PWCNT_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* WCAP INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct wcap_format
+{
+ uint32 : 8 ;
+ uint32 hr_lr : 1 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 : 2 ;
+ uint32 capture_condition : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 : 3 ;
+ uint32 previous_bit : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} WCAP_FIELDS ;
+
+typedef union
+{
+ WCAP_FIELDS wcap ;
+ HET_MEMORY memory ;
+} WCAP_INSTRUCTION;
+
+/*----------------------------------------------*/
+/* WCAPE INSTRUCTION */
+/*----------------------------------------------*/
+typedef struct wcape_format
+{
+ uint32 : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 : 2 ;
+ uint32 capture_condition : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 previous_bit : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 ec_data : 7 ;
+ uint32 ts_data : 25 ;
+
+} WCAPE_FIELDS ;
+
+typedef union
+{
+ WCAPE_FIELDS wcape ;
+ HET_MEMORY memory ;
+} WCAPE_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* BR INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct br_format
+{
+ uint32 : 9 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 : 2 ;
+ uint32 : 1 ;
+ uint32 : 1 ;
+ uint32 branch_condition : 3 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 : 3 ;
+ uint32 previous_bit : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 hr_data : 7 ;
+ uint32 data : 25 ;
+
+} BR_FIELDS ;
+
+typedef union
+{
+ BR_FIELDS br ;
+ HET_MEMORY memory ;
+} BR_INSTRUCTION;
+
+
+/*---------------------------------------------*/
+/* SHFT INSTRUCTION */
+/*---------------------------------------------*/
+typedef struct shft_format
+{
+ uint32 shift_mode : 4 ;
+ uint32 : 5 ;
+ uint32 op_code : 4 ;
+ uint32 next_program_address : 9 ;
+ uint32 brk : 1 ;
+ uint32 reqnum : 3 ;
+ uint32 : 6 ;
+
+ uint32 interrupt_enable : 1 ;
+ uint32 ab_register_select : 1 ;
+ uint32 t_register_select : 1 ;
+ uint32 : 2 ;
+ uint32 shift_condition : 2 ;
+ uint32 : 1 ;
+ uint32 pin_select : 5 ;
+ uint32 cond_addr : 9 ;
+ uint32 : 3 ;
+ uint32 previous_bit : 1 ;
+ uint32 auto_read_clear : 1 ;
+ uint32 request : 2 ;
+ uint32 : 3 ;
+
+ uint32 : 7 ;
+ uint32 data : 25 ;
+
+} SHFT_FIELDS ;
+
+typedef union
+{
+ SHFT_FIELDS shft ;
+ HET_MEMORY memory ;
+} SHFT_INSTRUCTION;
+
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
+/*--------------------------- End Of File ----------------------------------*/
Index: firmware/include/sys_common.h
===================================================================
diff -u
--- firmware/include/sys_common.h (revision 0)
+++ firmware/include/sys_common.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,130 @@
+/** @file sys_common.h
+* @brief Common Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - General Definitions
+* .
+* which are relevant for all drivers.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_COMMON_H__
+#define __SYS_COMMON_H__
+
+#include "hal_stdtypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/************************************************************/
+/* Type Definitions */
+/************************************************************/
+
+#ifndef _TBOOLEAN_DECLARED
+typedef boolean tBoolean;
+#define _TBOOLEAN_DECLARED
+#endif
+
+/** @enum loopBackType
+* @brief Loopback type definition
+*/
+/** @typedef loopBackType_t
+* @brief Loopback type Type Definition
+*
+* This type is used to select the module Loopback type Digital or Analog loopback.
+*/
+typedef enum loopBackType
+{
+ Digital_Lbk = 0U,
+ Analog_Lbk = 1U
+}loopBackType_t;
+
+/** @enum config_value_type
+* @brief config type definition
+*/
+/** @typedef config_value_type_t
+* @brief config type Type Definition
+*
+* This type is used to specify the Initial and Current value.
+*/
+typedef enum config_value_type
+{
+ InitialValue,
+ CurrentValue
+}config_value_type_t;
+
+#ifndef __little_endian__
+#define __little_endian__ 1
+#endif
+#ifndef __LITTLE_ENDIAN__
+#define __LITTLE_ENDIAN__ 1
+#endif
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/********************************************************************************/
+/* The ASSERT macro, which does the actual assertion checking. Typically, this */
+/* will be for procedure arguments. */
+/********************************************************************************/
+#ifdef DEBUG
+#define ASSERT(expr) { \
+ if(!(expr)) \
+ { \
+ __error__(__FILE__, __LINE__); \
+ } \
+ }
+#else
+#define ASSERT(expr)
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
Index: firmware/include/sys_core.h
===================================================================
diff -u
--- firmware/include/sys_core.h (revision 0)
+++ firmware/include/sys_core.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,358 @@
+/** @file sys_core.h
+* @brief System Core Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Core Interface Functions
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_CORE_H__
+#define __SYS_CORE_H__
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def USER_STACK_LENGTH
+* @brief USER Mode Stack length (in bytes)
+*
+* Alias for USER Mode Stack length (in bytes)
+*
+* @note: Use this macro for USER Mode Stack length (in bytes)
+*/
+#define USER_STACK_LENGTH 0x00002000U
+
+/** @def SVC_STACK_LENGTH
+* @brief SVC Mode Stack length (in bytes)
+*
+* Alias for SVC Mode Stack length (in bytes)
+*
+* @note: Use this macro for SVC Mode Stack length (in bytes)
+*/
+#define SVC_STACK_LENGTH 0x00000400U
+
+/** @def FIQ_STACK_LENGTH
+* @brief FIQ Mode Stack length (in bytes)
+*
+* Alias for FIQ Mode Stack length (in bytes)
+*
+* @note: Use this macro for FIQ Mode Stack length (in bytes)
+*/
+#define FIQ_STACK_LENGTH 0x00000400U
+
+/** @def IRQ_STACK_LENGTH
+* @brief IRQ Mode Stack length (in bytes)
+*
+* Alias for IRQ Mode Stack length (in bytes)
+*
+* @note: Use this macro for IRQ Mode Stack length (in bytes)
+*/
+#define IRQ_STACK_LENGTH 0x00000400U
+
+/** @def ABORT_STACK_LENGTH
+* @brief ABORT Mode Stack length (in bytes)
+*
+* Alias for ABORT Mode Stack length (in bytes)
+*
+* @note: Use this macro for ABORT Mode Stack length (in bytes)
+*/
+#define ABORT_STACK_LENGTH 0x00000400U
+
+/** @def UNDEF_STACK_LENGTH
+* @brief UNDEF Mode Stack length (in bytes)
+*
+* Alias for UNDEF Mode Stack length (in bytes)
+*
+* @note: Use this macro for UNDEF Mode Stack length (in bytes)
+*/
+#define UNDEF_STACK_LENGTH 0x00000400U
+
+/* System Core Interface Functions */
+
+/** @fn void _coreInitRegisters_(void)
+* @brief Initialize Core register
+*/
+void _coreInitRegisters_(void);
+
+/** @fn void _coreInitStackPointer_(void)
+* @brief Initialize Core stack pointer
+*/
+void _coreInitStackPointer_(void);
+
+/** @fn void _getCPSRValue_(void)
+* @brief Get CPSR Value
+*/
+uint32 _getCPSRValue_(void);
+
+/** @fn void _gotoCPUIdle_(void)
+* @brief Take CPU to Idle state
+*/
+void _gotoCPUIdle_(void);
+
+/** @fn void _coreEnableIrqVicOffset_(void)
+* @brief Enable Irq offset propagation via Vic controller
+*/
+void _coreEnableIrqVicOffset_(void);
+
+/** @fn void _coreEnableVfp_(void)
+* @brief Enable vector floating point unit
+*/
+void _coreEnableVfp_(void);
+
+/** @fn void _coreEnableEventBusExport_(void)
+* @brief Enable event bus export for external monitoring modules
+* @note It is required to enable event bus export to process ecc issues.
+*
+* This function enables event bus exports to external monitoring modules
+* like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
+*/
+void _coreEnableEventBusExport_(void);
+
+/** @fn void _coreDisableEventBusExport_(void)
+* @brief Disable event bus export for external monitoring modules
+*
+* This function disables event bus exports to external monitoring modules
+* like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
+*/
+void _coreDisableEventBusExport_(void);
+
+/** @fn void _coreEnableRamEcc_(void)
+* @brief Enable external ecc error for RAM odd and even bank
+* @note It is required to enable event bus export to process ecc issues.
+*/
+void _coreEnableRamEcc_(void);
+
+/** @fn void _coreDisableRamEcc_(void)
+* @brief Disable external ecc error for RAM odd and even bank
+*/
+void _coreDisableRamEcc_(void);
+
+/** @fn void _coreEnableFlashEcc_(void)
+* @brief Enable external ecc error for the Flash
+* @note It is required to enable event bus export to process ecc issues.
+*/
+void _coreEnableFlashEcc_(void);
+
+/** @fn void _coreDisableFlashEcc_(void)
+* @brief Disable external ecc error for the Flash
+*/
+void _coreDisableFlashEcc_(void);
+
+/** @fn uint32 _coreGetDataFault_(void)
+* @brief Get core data fault status register
+* @return The function will return the data fault status register value:
+* - bit [10,3..0]:
+* - 0b00001: Alignment -> address is valid
+* - 0b00000: Background -> address is valid
+* - 0b01101: Permission -> address is valid
+* - 0b01000: Precise External Abort -> address is valid
+* - 0b10110: Imprecise External Abort -> address is unpredictable
+* - 0b11001: Precise ECC Error -> address is valid
+* - 0b11000: Imprecise ECC Error -> address is unpredictable
+* - 0b00010: Debug -> address is unchanged
+* - bit [11]:
+* - 0: Read
+* - 1: Write
+* - bit [12]:
+* - 0: AXI Decode Error (DECERR)
+* - 1: AXI Slave Error (SLVERR)
+*/
+uint32 _coreGetDataFault_(void);
+
+/** @fn void _coreClearDataFault_(void)
+* @brief Clear core data fault status register
+*/
+void _coreClearDataFault_(void);
+
+/** @fn uint32 _coreGetInstructionFault_(void)
+* @brief Get core instruction fault status register
+* @return The function will return the instruction fault status register value:
+* - bit [10,3..0]:
+* - 0b00001: Alignment -> address is valid
+* - 0b00000: Background -> address is valid
+* - 0b01101: Permission -> address is valid
+* - 0b01000: Precise External Abort -> address is valid
+* - 0b10110: Imprecise External Abort -> address is unpredictable
+* - 0b11001: Precise ECC Error -> address is valid
+* - 0b11000: Imprecise ECC Error -> address is unpredictable
+* - 0b00010: Debug -> address is unchanged
+* - bit [12]:
+* - 0: AXI Decode Error (DECERR)
+* - 1: AXI Slave Error (SLVERR)
+*/
+uint32 _coreGetInstructionFault_(void);
+
+/** @fn void _coreClearInstructionFault_(void)
+* @brief Clear core instruction fault status register
+*/
+void _coreClearInstructionFault_(void);
+
+/** @fn uint32 _coreGetDataFaultAddress_(void)
+* @brief Get core data fault address register
+* @return The function will return the data fault address:
+*/
+uint32 _coreGetDataFaultAddress_(void);
+
+/** @fn void _coreClearDataFaultAddress_(void)
+* @brief Clear core data fault address register
+*/
+void _coreClearDataFaultAddress_(void);
+
+/** @fn uint32 _coreGetInstructionFaultAddress_(void)
+* @brief Get core instruction fault address register
+* @return The function will return the instruction fault address:
+*/
+uint32 _coreGetInstructionFaultAddress_(void);
+
+/** @fn void _coreClearInstructionFaultAddress_(void)
+* @brief Clear core instruction fault address register
+*/
+void _coreClearInstructionFaultAddress_(void);
+
+/** @fn uint32 _coreGetAuxiliaryDataFault_(void)
+* @brief Get core auxiliary data fault status register
+* @return The function will return the auxiliary data fault status register value:
+* - bit [13..5]:
+* - Index value for access giving error
+* - bit [21]:
+* - 0: Unrecoverable error
+* - 1: Recoverable error
+* - bit [23..22]:
+* - 0: Side cache
+* - 1: Side ATCM (Flash)
+* - 2: Side BTCM (RAM)
+* - 3: Reserved
+* - bit [27..24]:
+* - Cache way or way in which error occurred
+*/
+uint32 _coreGetAuxiliaryDataFault_(void);
+
+/** @fn void _coreClearAuxiliaryDataFault_(void)
+* @brief Clear core auxiliary data fault status register
+*/
+void _coreClearAuxiliaryDataFault_(void);
+
+/** @fn uint32 _coreGetAuxiliaryInstructionFault_(void)
+* @brief Get core auxiliary instruction fault status register
+* @return The function will return the auxiliary instruction fault status register value:
+* - bit [13..5]:
+* - Index value for access giving error
+* - bit [21]:
+* - 0: Unrecoverable error
+* - 1: Recoverable error
+* - bit [23..22]:
+* - 0: Side cache
+* - 1: Side ATCM (Flash)
+* - 2: Side BTCM (RAM)
+* - 3: Reserved
+* - bit [27..24]:
+* - Cache way or way in which error occurred
+*/
+uint32 _coreGetAuxiliaryInstructionFault_(void);
+
+/** @fn void _coreClearAuxiliaryInstructionFault_(void)
+* @brief Clear core auxiliary instruction fault status register
+*/
+void _coreClearAuxiliaryInstructionFault_(void);
+
+/** @fn void _disable_interrupt_(void)
+* @brief Disable IRQ and FIQ Interrupt mode in CPSR register
+*
+* This function disables IRQ and FIQ Interrupt mode in CPSR register.
+*/
+void _disable_interrupt_(void);
+
+/** @fn void _disable_IRQ_interrupt_(void)
+* @brief Disable IRQ Interrupt mode in CPSR register
+*
+* This function disables IRQ Interrupt mode in CPSR register.
+*/
+void _disable_IRQ_interrupt_(void);
+
+/** @fn void _disable_FIQ_interrupt_(void)
+* @brief Disable FIQ Interrupt mode in CPSR register
+*
+* This function disables IRQ Interrupt mode in CPSR register.
+*/
+void _disable_FIQ_interrupt_(void);
+
+/** @fn void _enable_interrupt_(void)
+* @brief Enable IRQ and FIQ Interrupt mode in CPSR register
+*
+* This function Enables IRQ and FIQ Interrupt mode in CPSR register.
+* User must call this function to enable Interrupts in non-OS environments.
+*/
+void _enable_interrupt_(void);
+
+/** @fn void _esmCcmErrorsClear_(void)
+* @brief Clears ESM Error caused due to CCM Errata in RevA Silicon
+*
+* This function Clears ESM Error caused due to CCM Errata
+* in RevA Silicon immediately after powerup.
+*/
+void _esmCcmErrorsClear_(void);
+
+/** @fn void _errata_CORTEXR4_66_(void)
+* @brief Work Around for Errata CORTEX-R4#66
+*
+* This function Disable out-of-order completion for divide
+* instructions in Auxiliary Control register.
+*/
+void _errata_CORTEXR4_66_(void);
+
+/** @fn void _errata_CORTEXR4_57_(void)
+* @brief Work Around for Errata CORTEX-R4#57
+*
+* Disable out-of-order single-precision floating point
+* multiply-accumulate instruction completion.
+*/
+void _errata_CORTEXR4_57_(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/sys_dma.h
===================================================================
diff -u
--- firmware/include/sys_dma.h (revision 0)
+++ firmware/include/sys_dma.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,367 @@
+/** @file dma.h
+* @brief DMA Driver Definition File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "reg_dma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @def BLOCK_TRANSFER
+* @brief Alias name for DMA Block transfer
+* @note This value should be used while setting the DMA control packet
+*/
+#define BLOCK_TRANSFER 1U
+
+/** @def FRAME_TRANSFER
+* @brief Alias name for DMA Frame transfer
+* @note This value should be used while setting the DMA control packet
+*/
+#define FRAME_TRANSFER 0U
+
+/** @def AUTOINIT_ON
+* @brief Alias name for Auto Initialization ON
+* @note This value should be used while setting the DMA control packet
+*/
+#define AUTOINIT_ON 1U
+
+/** @def AUTOINIT_OFF
+* @brief Alias name for Auto Initialization OFF
+* @note This value should be used while setting the DMA control packet
+*/
+#define AUTOINIT_OFF 0U
+
+/** @def ADDR_FIXED
+* @brief Alias name for Fixed Addressing mode
+* @note This value should be used while setting the DMA control packet
+*/
+#define ADDR_FIXED 0U
+
+/** @def ADDR_INC1
+* @brief Alias name for Post-increment Addressing mode
+* @note This value should be used while setting the DMA control packet
+*/
+#define ADDR_INC1 1U
+
+/** @def ADDR_OFFSET
+* @brief Alias name for Offset Addressing mode
+* @note This value should be used while setting the DMA control packet
+*/
+#define ADDR_OFFSET 3U
+
+/** @def INTERRUPT_ENABLE
+* @brief Alias name for Interrupt enable
+* @note @note This value should be used for API argument @a intenable
+*/
+#define INTERRUPT_ENABLE 1U
+
+/** @def INTERRUPT_DISABLE
+* @brief Alias name for Interrupt disable
+* @note @note This value should be used for API argument @a intenable
+*/
+#define INTERRUPT_DISABLE 0U
+
+
+/** @def DMA_GCTRL_BUSBUSY
+* @brief Bit mask for BUS BUSY in GCTRL Register
+* @note @note This value should be used for API argument @a intenable
+*/
+#define DMA_GCTRL_BUSBUSY (0x00004000U)
+
+/** @enum dmaREQTYPE
+* @brief DMA TRANSFER Type definitions
+*
+* Used to define DMA transfer type
+*/
+enum dmaREQTYPE
+{
+ DMA_HW = 0x0U, /**< Hardware trigger */
+ DMA_SW = 0x1U /**< Software trigger */
+};
+
+
+/** @enum dmaCHANNEL
+* @brief DMA CHANNEL definitions
+*
+* Used to define DMA Channel Number
+*/
+enum dmaCHANNEL
+{
+ DMA_CH0 = 0x00U,
+ DMA_CH1 = 0x01U,
+ DMA_CH2 = 0x02U,
+ DMA_CH3 = 0x03U,
+ DMA_CH4 = 0x04U,
+ DMA_CH5 = 0x05U,
+ DMA_CH6 = 0x06U,
+ DMA_CH7 = 0x07U,
+ DMA_CH8 = 0x08U,
+ DMA_CH9 = 0x09U,
+ DMA_CH10 = 0x0AU,
+ DMA_CH11 = 0x0BU,
+ DMA_CH12 = 0x0CU,
+ DMA_CH13 = 0x0DU,
+ DMA_CH14 = 0x0EU,
+ DMA_CH15 = 0x0FU,
+ DMA_CH16 = 0x10U,
+ DMA_CH17 = 0x11U,
+ DMA_CH18 = 0x12U,
+ DMA_CH19 = 0x13U,
+ DMA_CH20 = 0x14U,
+ DMA_CH21 = 0x15U,
+ DMA_CH22 = 0x16U,
+ DMA_CH23 = 0x17U,
+ DMA_CH24 = 0x18U,
+ DMA_CH25 = 0x19U,
+ DMA_CH26 = 0x1AU,
+ DMA_CH27 = 0x1BU,
+ DMA_CH28 = 0x1CU,
+ DMA_CH29 = 0x1DU,
+ DMA_CH30 = 0x1EU,
+ DMA_CH31 = 0x1FU
+};
+
+/** @enum dmaACCESS
+* @brief DMA ACESS WIDTH definitions
+*
+* Used to define DMA access width
+*/
+typedef enum dmaACCESS
+{
+ ACCESS_8_BIT = 0U,
+ ACCESS_16_BIT = 1U,
+ ACCESS_32_BIT = 2U,
+ ACCESS_64_BIT = 3U
+}dmaACCESS_t;
+
+
+/** @enum dmaPRIORITY
+* @brief DMA Channel Priority
+*
+* Used to define to which priority queue a DMA channel is assigned to
+*/
+typedef enum dmaPRIORITY
+{
+ LOWPRIORITY = 0U,
+ HIGHPRIORITY = 1U
+}dmaPRIORITY_t;
+
+
+/** @enum dmaREGION
+* @brief DMA Memory Protection Region
+*
+* Used to define DMA Memory Protection Region
+*/
+typedef enum dmaREGION
+{
+ DMA_REGION0 = 0U,
+ DMA_REGION1 = 1U,
+ DMA_REGION2 = 2U,
+ DMA_REGION3 = 3U
+}dmaREGION_t;
+
+
+/** @enum dmaRegionAccess
+* @brief DMA Memory Protection Region Access
+*
+* Used to define access permission of DMA memory protection regions
+*/
+typedef enum dmaRegionAccess
+{
+ FULLACCESS = 0U,
+ READONLY = 1U,
+ WRITEONLY = 2U,
+ NOACCESS = 3U
+}dmaRegionAccess_t;
+
+
+/** @enum dmaInterrupt
+* @brief DMA Interrupt
+*
+* Used to define DMA interrupts
+*/
+typedef enum dmaInterrupt
+{
+ FTC = 1U, /**< Frame transfer complete Interrupt */
+ LFS = 2U, /**< Last frame transfer started Interrupt */
+ HBC = 3U, /**< First half of block complete Interrupt */
+ BTC = 4U /**< Block transfer complete Interrupt */
+}dmaInterrupt_t;
+
+/** @struct g_dmaCTRL
+* @brief Interrupt mode globals
+*
+*/
+typedef struct dmaCTRLPKT
+{
+ uint32 SADD; /* initial source address */
+ uint32 DADD; /* initial destination address */
+ uint32 CHCTRL; /* next ctrl packet to be trigger + 1 */
+ uint32 FRCNT; /* frame count */
+ uint32 ELCNT; /* element count */
+ uint32 ELDOFFSET; /* element destination offset */
+ uint32 ELSOFFSET; /* element source offset */
+ uint32 FRDOFFSET; /* frame detination offset */
+ uint32 FRSOFFSET; /* frame source offset */
+ uint32 PORTASGN; /* dma port */
+ uint32 RDSIZE; /* read element size */
+ uint32 WRSIZE; /* write element size */
+ uint32 TTYPE; /* trigger type - frame/block */
+ uint32 ADDMODERD; /* addresssing mode for source */
+ uint32 ADDMODEWR; /* addresssing mode for destination */
+ uint32 AUTOINIT; /* auto-init mode */
+ uint32 COMBO; /* next ctrl packet trigger(Not used) */
+} g_dmaCTRL;
+
+typedef volatile struct
+{
+
+ struct /* 0x000-0x400 */
+ {
+ uint32 ISADDR;
+ uint32 IDADDR;
+ uint32 ITCOUNT;
+ uint32 rsvd1;
+ uint32 CHCTRL;
+ uint32 EIOFF;
+ uint32 FIOFF;
+ uint32 rsvd2;
+ }PCP[32U];
+
+ struct /* 0x400-0x800 */
+ {
+ uint32 res[256U];
+ } RESERVED;
+
+ struct /* 0x800-0xA00 */
+ {
+ uint32 CSADDR;
+ uint32 CDADDR;
+ uint32 CTCOUNT;
+ uint32 rsvd3;
+ }WCP[32U];
+
+} dmaRAMBASE_t;
+
+#define dmaRAMREG ((dmaRAMBASE_t *)0xFFF80000U)
+
+typedef struct dma_config_reg
+{
+ uint32 CONFIG_CHPRIOS;
+ uint32 CONFIG_GCHIENAS;
+ uint32 CONFIG_DREQASI[8U];
+ uint32 CONFIG_FTCINTENAS;
+ uint32 CONFIG_LFSINTENAS;
+ uint32 CONFIG_HBCINTENAS;
+ uint32 CONFIG_BTCINTENAS;
+ uint32 CONFIG_DMAPCR;
+ uint32 CONFIG_DMAMPCTRL;
+} dma_config_reg_t;
+
+
+/**
+ * @defgroup DMA DMA
+ * @brief Direct Memory Access Controller
+ *
+ * The DMA controller is used to transfer data between two locations in the memory map in the background
+ * of CPU operations. Typically, the DMA is used to:
+ * - Transfer blocks of data between external and internal data memories
+ * - Restructure portions of internal data memory
+ * - Continually service a peripheral
+ * - Page program sections to internal program memory
+ *
+ * Related files:
+ * - reg_dma.h
+ * - sys_dma.h
+ * - sys_dma.c
+ *
+ * @addtogroup DMA
+ * @{
+ */
+/* DMA Interface Functions */
+void dmaEnable(void);
+void dmaDisable(void);
+void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT);
+void dmaSetChEnable(uint32 channel,uint32 type);
+void dmaReqAssign(uint32 channel,uint32 reqline);
+uint32 dmaGetReq(uint32 channel);
+void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority);
+void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype);
+void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype);
+void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add);
+void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable);
+void dmaDisableRegion(dmaREGION_t region);
+void dmaEnableParityCheck(void);
+void dmaDisableParityCheck(void);
+void dmaGetConfigValue(dma_config_reg_t *config_reg, config_value_type_t type);
+
+/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
+* @brief Interrupt callback
+* @param[in] inttype Interrupt type
+* - FTC
+* - LFS
+* - HBC
+* - BTC
+* @param[in] channel channel number 0..15
+* This is a callback that is provided by the application and is called apon
+* an interrupt. The parameter passed to the callback is a copy of the
+* interrupt flag register.
+*/
+void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel);
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/sys_mpu.h
===================================================================
diff -u
--- firmware/include/sys_mpu.h (revision 0)
+++ firmware/include/sys_mpu.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,517 @@
+/** @file sys_mpu.h
+* @brief System Mpu Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Mpu Interface Functions
+* .
+* which are relevant for the memory protection unit driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_MPU_H__
+#define __SYS_MPU_H__
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def mpuREGION1
+* @brief Mpu region 1
+*
+* Alias for Mpu region 1
+*/
+#define mpuREGION1 0U
+
+/** @def mpuREGION2
+* @brief Mpu region 2
+*
+* Alias for Mpu region 1
+*/
+#define mpuREGION2 1U
+
+/** @def mpuREGION3
+* @brief Mpu region 3
+*
+* Alias for Mpu region 3
+*/
+#define mpuREGION3 2U
+
+/** @def mpuREGION4
+* @brief Mpu region 4
+*
+* Alias for Mpu region 4
+*/
+#define mpuREGION4 3U
+
+/** @def mpuREGION5
+* @brief Mpu region 5
+*
+* Alias for Mpu region 5
+*/
+#define mpuREGION5 4U
+
+/** @def mpuREGION6
+* @brief Mpu region 6
+*
+* Alias for Mpu region 6
+*/
+#define mpuREGION6 5U
+
+/** @def mpuREGION7
+* @brief Mpu region 7
+*
+* Alias for Mpu region 7
+*/
+#define mpuREGION7 6U
+
+/** @def mpuREGION8
+* @brief Mpu region 8
+*
+* Alias for Mpu region 8
+*/
+#define mpuREGION8 7U
+
+/** @def mpuREGION9
+* @brief Mpu region 9
+*
+* Alias for Mpu region 9
+*/
+#define mpuREGION9 8U
+
+/** @def mpuREGION10
+* @brief Mpu region 10
+*
+* Alias for Mpu region 10
+*/
+#define mpuREGION10 9U
+
+/** @def mpuREGION11
+* @brief Mpu region 11
+*
+* Alias for Mpu region 11
+*/
+#define mpuREGION11 10U
+
+/** @def mpuREGION12
+* @brief Mpu region 12
+*
+* Alias for Mpu region 12
+*/
+#define mpuREGION12 11U
+
+/** @def mpuREGION_ENABLE
+* @brief Enable MPU Region
+*
+* Alias for MPU region enable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuREGION_ENABLE 1U
+
+/** @def mpuREGION_DISABLE
+* @brief Disable MPU Region
+*
+* Alias for MPU region disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuREGION_DISABLE 0U
+
+/** @def mpuSUBREGION0_DISABLE
+* @brief Disable MPU Sub Region0
+*
+* Alias for MPU subregion0 disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION0_DISABLE 0x100U
+
+/** @def mpuSUBREGION1_DISABLE
+* @brief Disable MPU Sub Region1
+*
+* Alias for MPU subregion1 disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION1_DISABLE 0x200U
+
+/** @def mpuSUBREGION2_DISABLE
+* @brief Disable MPU Sub Region2
+*
+* Alias for MPU subregion2 disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION2_DISABLE 0x400U
+
+/** @def mpuSUBREGION3_DISABLE
+* @brief Disable MPU Sub Region3
+*
+* Alias for MPU subregion3 disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION3_DISABLE 0x800U
+
+/** @def mpuSUBREGION4_DISABLE
+* @brief Disable MPU Sub Region4
+*
+* Alias for MPU subregion4 disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION4_DISABLE 0x1000U
+
+/** @def mpuSUBREGION5_DISABLE
+* @brief Disable MPU Sub Region5
+*
+* Alias for MPU subregion5 disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION5_DISABLE 0x2000U
+
+/** @def mpuSUBREGION6_DISABLE
+* @brief Disable MPU Sub Region6
+*
+* Alias for MPU subregion6 disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION6_DISABLE 0x4000U
+
+/** @def mpuSUBREGION7_DISABLE
+* @brief Disable MPU Sub Region7
+*
+* Alias for MPU subregion7 disable.
+*
+* @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_
+*/
+#define mpuSUBREGION7_DISABLE 0x8000U
+
+
+
+/** @enum mpuRegionAccessPermission
+* @brief Alias names for mpu region access permissions
+*
+* This enumeration is used to provide alias names for the mpu region access permission:
+* - MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and execute
+* - MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode and execute
+* - MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode and execute
+* - MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode and execute
+* - MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and execute
+* - MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and execute
+* - MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode and no execution
+* - MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode and no execution
+* - MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode and no execution
+* - MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode and no execution
+* - MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode and no execution
+* - MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode and no execution
+*
+*/
+enum mpuRegionAccessPermission
+{
+ MPU_PRIV_NA_USER_NA_EXEC = 0x0000U, /**< Alias no access in privileged mode, no access in user mode and execute */
+ MPU_PRIV_RW_USER_NA_EXEC = 0x0100U, /**< Alias no read/write in privileged mode, no access in user mode and execute */
+ MPU_PRIV_RW_USER_RO_EXEC = 0x0200U, /**< Alias no read/write in privileged mode, read only in user mode and execute */
+ MPU_PRIV_RW_USER_RW_EXEC = 0x0300U, /**< Alias no read/write in privileged mode, read/write in user mode and execute */
+ MPU_PRIV_RO_USER_NA_EXEC = 0x0500U, /**< Alias no read only in privileged mode, no access in user mode and execute */
+ MPU_PRIV_RO_USER_RO_EXEC = 0x0600U, /**< Alias no read only in privileged mode, read only in user mode and execute */
+ MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no access in user mode and no execution */
+ MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias no read/write in privileged mode, no access in user mode and no execution */
+ MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias no read/write in privileged mode, read only in user mode and no execution */
+ MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias no read/write in privileged mode, read/write in user mode and no execution */
+ MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias no read only in privileged mode, no access in user mode and no execution */
+ MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U /**< Alias no read only in privileged mode, read only in user mode and no execution */
+};
+
+/** @enum mpuRegionType
+* @brief Alias names for mpu region type
+*
+* This enumeration is used to provide alias names for the mpu region type:
+* - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable
+* - MPU_DEVICE_SHAREABLE Memory type device and sharable
+* - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, no write allocate and non shared
+* - MPU_NORMAL_OIWTNOWA_SHARED Memory type normal outer and inner write-through, no write allocate and shared
+* - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no write allocate and non shared
+* - MPU_NORMAL_OIWBNOWA_SHARED Memory type normal outer and inner write-back, no write allocate and shared
+* - MPU_NORMAL_OINC_NONSHARED Memory type normal outer and inner non-cachable and non shared
+* - MPU_NORMAL_OINC_SHARED Memory type normal outer and inner non-cachable and shared
+* - MPU_NORMAL_OIWBWA_NONSHARED Memory type normal outer and inner write-back, write allocate and non shared
+* - MPU_NORMAL_OIWBWA_SHARED Memory type normal outer and inner write-back, write allocate and shared
+* - MPU_DEVICE_NONSHAREABLE Memory type device and non sharable
+*/
+enum mpuRegionType
+{
+ MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and sharable */
+ MPU_DEVICE_SHAREABLE = 0x0001U, /**< Memory type device and sharable */
+ MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner write-through, no write allocate and non shared */
+ MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner write-back, no write allocate and non shared */
+ MPU_NORMAL_OIWTNOWA_SHARED = 0x0006U, /**< Memory type normal outer and inner write-through, no write allocate and shared */
+ MPU_NORMAL_OIWBNOWA_SHARED = 0x0007U, /**< Memory type normal outer and inner write-back, no write allocate and shared */
+ MPU_NORMAL_OINC_NONSHARED = 0x0008U, /**< Memory type normal outer and inner non-cachable and non shared */
+ MPU_NORMAL_OIWBWA_NONSHARED = 0x000BU, /**< Memory type normal outer and inner write-back, write allocate and non shared */
+ MPU_NORMAL_OINC_SHARED = 0x000CU, /**< Memory type normal outer and inner non-cachable and shared */
+ MPU_NORMAL_OIWBWA_SHARED = 0x000FU, /**< Memory type normal outer and inner write-back, write allocate and shared */
+ MPU_DEVICE_NONSHAREABLE = 0x0010U /**< Memory type device and non sharable */
+};
+
+/** @enum mpuRegionSize
+* @brief Alias names for mpu region type
+*
+* This enumeration is used to provide alias names for the mpu region type:
+* - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable
+* - MPU_32_BYTES Memory size in bytes
+* - MPU_64_BYTES Memory size in bytes
+* - MPU_128_BYTES Memory size in bytes
+* - MPU_256_BYTES Memory size in bytes
+* - MPU_512_BYTES Memory size in bytes
+* - MPU_1_KB Memory size in kB
+* - MPU_2_KB Memory size in kB
+* - MPU_4_KB Memory size in kB
+* - MPU_8_KB Memory size in kB
+* - MPU_16_KB Memory size in kB
+* - MPU_32_KB Memory size in kB
+* - MPU_64_KB Memory size in kB
+* - MPU_128_KB Memory size in kB
+* - MPU_256_KB Memory size in kB
+* - MPU_512_KB Memory size in kB
+* - MPU_1_MB Memory size in MB
+* - MPU_2_MB Memory size in MB
+* - MPU_4_MB Memory size in MB
+* - MPU_8_MBv Memory size in MB
+* - MPU_16_MB Memory size in MB
+* - MPU_32_MB Memory size in MB
+* - MPU_64_MB Memory size in MB
+* - MPU_128_MB Memory size in MB
+* - MPU_256_MB Memory size in MB
+* - MPU_512_MB Memory size in MB
+* - MPU_1_GB Memory size in GB
+* - MPU_2_GB Memory size in GB
+* - MPU_4_GB Memory size in GB
+*/
+enum mpuRegionSize
+{
+ MPU_32_BYTES = 0x04U << 1U, /**< Memory size in bytes */
+ MPU_64_BYTES = 0x05U << 1U, /**< Memory size in bytes */
+ MPU_128_BYTES = 0x06U << 1U, /**< Memory size in bytes */
+ MPU_256_BYTES = 0x07U << 1U, /**< Memory size in bytes */
+ MPU_512_BYTES = 0x08U << 1U, /**< Memory size in bytes */
+ MPU_1_KB = 0x09U << 1U, /**< Memory size in kB */
+ MPU_2_KB = 0x0AU << 1U, /**< Memory size in kB */
+ MPU_4_KB = 0x0BU << 1U, /**< Memory size in kB */
+ MPU_8_KB = 0x0CU << 1U, /**< Memory size in kB */
+ MPU_16_KB = 0x0DU << 1U, /**< Memory size in kB */
+ MPU_32_KB = 0x0EU << 1U, /**< Memory size in kB */
+ MPU_64_KB = 0x0FU << 1U, /**< Memory size in kB */
+ MPU_128_KB = 0x10U << 1U, /**< Memory size in kB */
+ MPU_256_KB = 0x11U << 1U, /**< Memory size in kB */
+ MPU_512_KB = 0x12U << 1U, /**< Memory size in kB */
+ MPU_1_MB = 0x13U << 1U, /**< Memory size in MB */
+ MPU_2_MB = 0x14U << 1U, /**< Memory size in MB */
+ MPU_4_MB = 0x15U << 1U, /**< Memory size in MB */
+ MPU_8_MB = 0x16U << 1U, /**< Memory size in MB */
+ MPU_16_MB = 0x17U << 1U, /**< Memory size in MB */
+ MPU_32_MB = 0x18U << 1U, /**< Memory size in MB */
+ MPU_64_MB = 0x19U << 1U, /**< Memory size in MB */
+ MPU_128_MB = 0x1AU << 1U, /**< Memory size in MB */
+ MPU_256_MB = 0x1BU << 1U, /**< Memory size in MB */
+ MPU_512_MB = 0x1CU << 1U, /**< Memory size in MB */
+ MPU_1_GB = 0x1DU << 1U, /**< Memory size in GB */
+ MPU_2_GB = 0x1EU << 1U, /**< Memory size in GB */
+ MPU_4_GB = 0x1FU << 1U /**< Memory size in GB */
+};
+
+/** @fn void _mpuInit_(void)
+* @brief Initialize Mpu
+*
+* This function initializes memory protection unit.
+*/
+void _mpuInit_(void);
+
+/** @fn void _mpuEnable_(void)
+* @brief Enable Mpu
+*
+* This function enables memory protection unit.
+*/
+void _mpuEnable_(void);
+
+/** @fn void _mpuDisable_(void)
+* @brief Disable Mpu
+*
+* This function disables memory protection unit.
+*/
+void _mpuDisable_(void);
+
+/** @fn void _mpuEnableBackgroundRegion_(void)
+* @brief Enable Mpu background region
+*
+* This function enables background region of the memory protection unit.
+*/
+void _mpuEnableBackgroundRegion_(void);
+
+/** @fn void _mpuDisableBackgroundRegion_(void)
+* @brief Disable Mpu background region
+*
+* This function disables background region of the memory protection unit.
+*/
+void _mpuDisableBackgroundRegion_(void);
+
+/** @fn uint32 _mpuGetNumberOfRegions_(void)
+* @brief Returns number of implemented Mpu regions
+* @return Number of implemented mpu regions
+*
+* This function returns the number of implemented mpu regions.
+*/
+uint32 _mpuGetNumberOfRegions_(void);
+
+/** @fn uint32 _mpuAreRegionsSeparate_(void)
+* @brief Returns the type of the implemented mpu regions
+* @return Mpu type of regions
+*
+* This function returns 0 when mpu regions are of type unified otherwise regions are of type separate.
+*/
+uint32 _mpuAreRegionsSeparate_(void);
+
+/** @fn void _mpuSetRegion_(uint32 region)
+* @brief Set mpu region number
+* @param[in] region Region number: mpuREGION1..mpuREGION12
+*
+* This function selects one of the implemented mpu regions.
+*/
+void _mpuSetRegion_(uint32 region);
+
+/** @fn uint32 _mpuGetRegion_(void)
+* @brief Returns the currently selected mpu region
+* @return Mpu region number
+*
+* This function returns currently selected mpu region number.
+*/
+uint32 _mpuGetRegion_(void);
+
+/** @fn void _mpuSetRegionBaseAddress_(uint32 address)
+* @brief Set base address of currently selected mpu region
+* @param[in] address Base address of the MPU region
+* @note The base address must always aligned with region size
+*
+* This function sets the base address of currently selected mpu region.
+*/
+void _mpuSetRegionBaseAddress_(uint32 address);
+
+/** @fn uint32 _mpuGetRegionBaseAddress_(void)
+* @brief Returns base address of currently selected mpu region
+* @return Current base address of selected mpu region
+*
+* This function returns the base address of currently selected mpu region.
+*/
+uint32 _mpuGetRegionBaseAddress_(void);
+
+/** @fn void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission)
+* @brief Set type of currently selected mpu region
+* @param[in] type Region Type
+* - MPU_STRONGLYORDERED_SHAREABLE : Memory type strongly ordered and sharable
+* - MPU_DEVICE_SHAREABLE : Memory type device and sharable
+* - MPU_NORMAL_OIWTNOWA_NONSHARED : Memory type normal outer and inner write-through, no write allocate and non shared
+* - MPU_NORMAL_OIWBNOWA_NONSHARED : Memory type normal outer and inner write-back, no write allocate and non shared
+* - MPU_NORMAL_OIWTNOWA_SHARED : Memory type normal outer and inner write-through, no write allocate and shared
+* - MPU_NORMAL_OIWBNOWA_SHARED : Memory type normal outer and inner write-back, no write allocate and shared
+* - MPU_NORMAL_OINC_NONSHARED : Memory type normal outer and inner non-cachable and non shared
+* - MPU_NORMAL_OIWBWA_NONSHARED : Memory type normal outer and inner write-back, write allocate and non shared
+* - MPU_NORMAL_OINC_SHARED : Memory type normal outer and inner non-cachable and shared
+* - MPU_NORMAL_OIWBWA_SHARED : Memory type normal outer and inner write-back, write allocate and shared
+* - MPU_DEVICE_NONSHAREABLE : Memory type device and non sharable
+*
+* @param[in] permission Region Access permission
+* - MPU_PRIV_NA_USER_NA_EXEC : Alias no access in privileged mode, no access in user mode and execute
+* - MPU_PRIV_RW_USER_NA_EXEC : Alias no read/write in privileged mode, no access in user mode and execute
+* - MPU_PRIV_RW_USER_RO_EXEC : Alias no read/write in privileged mode, read only in user mode and execute
+* - MPU_PRIV_RW_USER_RW_EXEC : Alias no read/write in privileged mode, read/write in user mode and execute
+* - MPU_PRIV_RO_USER_NA_EXEC : Alias no read only in privileged mode, no access in user mode and execute
+* - MPU_PRIV_RO_USER_RO_EXEC : Alias no read only in privileged mode, read only in user mode and execute
+* - MPU_PRIV_NA_USER_NA_NOEXEC : Alias no access in privileged mode, no access in user mode and no execution
+* - MPU_PRIV_RW_USER_NA_NOEXEC : Alias no read/write in privileged mode, no access in user mode and no execution
+* - MPU_PRIV_RW_USER_RO_NOEXEC : Alias no read/write in privileged mode, read only in user mode and no execution
+* - MPU_PRIV_RW_USER_RW_NOEXEC : Alias no read/write in privileged mode, read/write in user mode and no execution
+* - MPU_PRIV_RO_USER_NA_NOEXEC : Alias no read only in privileged mode, no access in user mode and no execution
+* - MPU_PRIV_RO_USER_RO_NOEXEC : Alias no read only in privileged mode, read only in user mode and no execution
+*
+* This function sets the type of currently selected mpu region.
+*/
+void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission);
+
+/** @fn uint32 _mpuGetRegionType_(void)
+* @brief Returns the type of currently selected mpu region
+* @return Current type of selected mpu region
+*
+* This function returns the type of currently selected mpu region.
+*/
+uint32 _mpuGetRegionType_(void);
+
+/** @fn uint32 _mpuGetRegionPermission_(void)
+* @brief Returns permission of currently selected mpu region
+* @return Current type of selected mpu region
+*
+* This function returns permission of currently selected mpu region.
+*/
+uint32 _mpuGetRegionPermission_(void);
+
+/** @fn void _mpuSetRegionSizeRegister_(uint32 value)
+* @brief Set mpu region size register value
+* @param[in] value Value to be written in the MPU Region Size and Enable register
+*
+* This function sets mpu region size register value.
+*
+* Sample usuage:
+* _mpuSetRegion_(mpuREGION5);
+* _mpuSetRegionSizeRegister_(mpuREGION_ENABLE | MPU_16_KB | mpuSUBREGION3_DISABLE | mpuSUBREGION4_DISABLE);
+*/
+void _mpuSetRegionSizeRegister_(uint32 value);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/sys_pcr.h
===================================================================
diff -u
--- firmware/include/sys_pcr.h (revision 0)
+++ firmware/include/sys_pcr.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,297 @@
+/** @file sys_pcr.h
+* @brief PCR Driver Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_PCR_H__
+#define __SYS_PCR_H__
+
+#include "reg_pcr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* PCR General Definitions */
+
+typedef uint32 peripheralFrame_CS_t;
+
+#define PeripheralFrame_CS0 0U
+#define PeripheralFrame_CS1 1U
+#define PeripheralFrame_CS2 2U
+#define PeripheralFrame_CS3 3U
+#define PeripheralFrame_CS4 4U
+#define PeripheralFrame_CS5 5U
+#define PeripheralFrame_CS6 6U
+#define PeripheralFrame_CS7 7U
+#define PeripheralFrame_CS8 8U
+#define PeripheralFrame_CS9 9U
+#define PeripheralFrame_CS10 10U
+#define PeripheralFrame_CS11 11U
+#define PeripheralFrame_CS12 12U
+#define PeripheralFrame_CS13 13U
+#define PeripheralFrame_CS14 14U
+#define PeripheralFrame_CS15 15U
+#define PeripheralFrame_CS16 16U
+#define PeripheralFrame_CS17 17U
+#define PeripheralFrame_CS18 18U
+#define PeripheralFrame_CS19 19U
+#define PeripheralFrame_CS20 20U
+#define PeripheralFrame_CS21 21U
+#define PeripheralFrame_CS22 22U
+#define PeripheralFrame_CS23 23U
+#define PeripheralFrame_CS24 24U
+#define PeripheralFrame_CS25 25U
+#define PeripheralFrame_CS26 26U
+#define PeripheralFrame_CS27 27U
+#define PeripheralFrame_CS28 28U
+#define PeripheralFrame_CS29 29U
+#define PeripheralFrame_CS30 30U
+#define PeripheralFrame_CS31 31U
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+typedef uint32 quadrant_Select_t;
+#define Quadrant0 1U
+#define Quadrant1 2U
+#define Quadrant2 4U
+#define Quadrant3 8U
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @typedef peripheral_Frame_Select_t
+* @brief PCR Peripheral Frame Type Definition
+*
+* This type is used to access the PCR peripheral Frame configuration register.
+*/
+typedef struct peripheral_Frame_Select
+{
+ peripheralFrame_CS_t Peripheral_CS;
+ quadrant_Select_t Peripheral_Quadrant;
+}peripheral_Frame_Select_t;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+/** @typedef peripheral_Quad_ChipSelect_t
+* @brief PCR Peripheral Frame registers Type Definition
+*
+* This type is used to access all the PCR peripheral Frame configuration registers.
+*/
+typedef struct peripheral_Quad_ChipSelect
+{
+ uint32 Peripheral_Quad0_3_CS0_7;
+ uint32 Peripheral_Quad4_7_CS8_15;
+ uint32 Peripheral_Quad8_11_CS16_23;
+ uint32 Peripheral_Quad12_15_CS24_31;
+}peripheral_Quad_ChipSelect_t;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+/** @typedef peripheral_Memory_ChipSelect_t
+* @brief PCR Peripheral Memory Frame registers Type Definition
+*
+* This type is used to access all the PCR peripheral Memory Frame configuration registers.
+*/
+typedef struct peripheral_Memory_ChipSelect
+{
+ uint32 Peripheral_Mem_CS0_31;
+ uint32 Peripheral_Mem_CS32_63;
+}peripheral_Memory_ChipSelect_t;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+typedef uint32 peripheral_MemoryFrame_CS_t;
+
+#define PeripheralMemoryFrame_CS0 0U
+#define PeripheralMemoryFrame_CS1 1U
+#define PeripheralMemoryFrame_CS2 2U
+#define PeripheralMemoryFrame_CS3 3U
+#define PeripheralMemoryFrame_CS4 4U
+#define PeripheralMemoryFrame_CS5 5U
+#define PeripheralMemoryFrame_CS6 6U
+#define PeripheralMemoryFrame_CS7 7U
+#define PeripheralMemoryFrame_CS8 8U
+#define PeripheralMemoryFrame_CS9 9U
+#define PeripheralMemoryFrame_CS10 10U
+#define PeripheralMemoryFrame_CS11 11U
+#define PeripheralMemoryFrame_CS12 12U
+#define PeripheralMemoryFrame_CS13 13U
+#define PeripheralMemoryFrame_CS14 14U
+#define PeripheralMemoryFrame_CS15 15U
+#define PeripheralMemoryFrame_CS16 16U
+#define PeripheralMemoryFrame_CS17 17U
+#define PeripheralMemoryFrame_CS18 18U
+#define PeripheralMemoryFrame_CS19 19U
+#define PeripheralMemoryFrame_CS20 20U
+#define PeripheralMemoryFrame_CS21 21U
+#define PeripheralMemoryFrame_CS22 22U
+#define PeripheralMemoryFrame_CS23 23U
+#define PeripheralMemoryFrame_CS24 24U
+#define PeripheralMemoryFrame_CS25 25U
+#define PeripheralMemoryFrame_CS26 26U
+#define PeripheralMemoryFrame_CS27 27U
+#define PeripheralMemoryFrame_CS28 28U
+#define PeripheralMemoryFrame_CS29 29U
+#define PeripheralMemoryFrame_CS30 30U
+#define PeripheralMemoryFrame_CS31 31U
+#define PeripheralMemoryFrame_CS32 32U
+#define PeripheralMemoryFrame_CS33 33U
+#define PeripheralMemoryFrame_CS34 34U
+#define PeripheralMemoryFrame_CS35 35U
+#define PeripheralMemoryFrame_CS36 36U
+#define PeripheralMemoryFrame_CS37 37U
+#define PeripheralMemoryFrame_CS38 38U
+#define PeripheralMemoryFrame_CS39 39U
+#define PeripheralMemoryFrame_CS40 40U
+#define PeripheralMemoryFrame_CS41 41U
+#define PeripheralMemoryFrame_CS42 42U
+#define PeripheralMemoryFrame_CS43 43U
+#define PeripheralMemoryFrame_CS44 44U
+#define PeripheralMemoryFrame_CS45 45U
+#define PeripheralMemoryFrame_CS46 46U
+#define PeripheralMemoryFrame_CS47 47U
+#define PeripheralMemoryFrame_CS48 48U
+#define PeripheralMemoryFrame_CS49 49U
+#define PeripheralMemoryFrame_CS50 50U
+#define PeripheralMemoryFrame_CS51 51U
+#define PeripheralMemoryFrame_CS52 52U
+#define PeripheralMemoryFrame_CS53 53U
+#define PeripheralMemoryFrame_CS54 54U
+#define PeripheralMemoryFrame_CS55 55U
+#define PeripheralMemoryFrame_CS56 56U
+#define PeripheralMemoryFrame_CS57 57U
+#define PeripheralMemoryFrame_CS58 58U
+#define PeripheralMemoryFrame_CS59 59U
+#define PeripheralMemoryFrame_CS60 60U
+#define PeripheralMemoryFrame_CS61 61U
+#define PeripheralMemoryFrame_CS62 62U
+#define PeripheralMemoryFrame_CS63 63U
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+typedef struct pcr_config_reg
+{
+ uint32 CONFIG_PMPROTSET0;
+ uint32 CONFIG_PMPROTSET1;
+ uint32 CONFIG_PPROTSET0;
+ uint32 CONFIG_PPROTSET1;
+ uint32 CONFIG_PPROTSET2;
+ uint32 CONFIG_PPROTSET3;
+ uint32 CONFIG_PCSPWRDWNSET0;
+ uint32 CONFIG_PCSPWRDWNSET1;
+ uint32 CONFIG_PSPWRDWNSET0;
+ uint32 CONFIG_PSPWRDWNSET1;
+ uint32 CONFIG_PSPWRDWNSET2;
+ uint32 CONFIG_PSPWRDWNSET3;
+} pcr_config_reg_t;
+
+/**
+ * @defgroup PCR PCR
+ * @brief Peripheral Central Resource Controller
+ *
+ * The PCR manages the accesses to the peripheral registers and peripheral
+ * memories. It provides a global reset for all the peripherals. It also supports the
+ * capability to selectively enable or disable the clock for each peripheral
+ * individually. The PCR also manages the accesses to the system module
+ * registers required to configure the device�s clocks, interrupts, and so on. The
+ * system module registers also include status flags for indicating exception
+ * conditions � resets, aborts, errors, interrupts.
+ *
+ * Related files:
+ * - reg_pcr.h
+ * - sys_pcr.h
+ * - sys_pcr.c
+ *
+ * @addtogroup PCR
+ * @{
+ */
+
+/* PCR Interface Functions */
+
+void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame);
+void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame);
+
+void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Protection_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS);
+void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS);
+void peripheral_Powerdown_Status(peripheral_Quad_ChipSelect_t* peripheral_Quad_CS);
+
+void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Protection_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS);
+void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS);
+void peripheral_Memory_Powerdown_Status(peripheral_Memory_ChipSelect_t* peripheral_Memory_CS);
+
+void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS);
+
+void pcrGetConfigValue(pcr_config_reg_t *config_reg, config_value_type_t type);
+
+/**@}*/
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: firmware/include/sys_pmm.h
===================================================================
diff -u
--- firmware/include/sys_pmm.h (revision 0)
+++ firmware/include/sys_pmm.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,182 @@
+/** @file sys_pmm.h
+* @brief PMM Driver Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_PMM_H__
+#define __SYS_PMM_H__
+
+#include "reg_pmm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Bit Masks */
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON0 0x0F000000U /*PD2*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON1 0x000F0000U /*PD3*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON2 0x00000F00U /*PD4*/
+#define PMM_LOGICPDPWRCTRL0_LOGICPDON3 0x0000000FU /*PD5*/
+
+#define PMM_MEMPDPWRCTRL0_MEMPDON0 0x0F000000U /*RAM_PD1*/
+#define PMM_MEMPDPWRCTRL0_MEMPDON1 0x000F0000U /*RAM_PD2*/
+#define PMM_MEMPDPWRCTRL0_MEMPDON2 0x00000F00U /*RAM_PD3*/
+
+#define PMM_LOGICPDPWRSTAT_DOMAINON 0x00000100U
+#define PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT 0x00000003U
+#define PMM_MEMPDPWRSTAT_DOMAINON 0x00000100U
+#define PMM_MEMPDPWRSTAT_MEMPDPWRSTAT 0x00000003U
+#define PMM_GLOBALCTRL1_AUTOCLKWAKEENA 0x00000001U
+
+/* Configuration registers initial value */
+#define PMM_LOGICPDPWRCTRL0_CONFIGVALUE ( (uint32)((uint32)0x5U << 24U) \
+ | (uint32)((uint32)0x5U << 16U) \
+ | (uint32)((uint32)0xAU << 8U) \
+ | (uint32)((uint32)0x5U << 0U) )
+#define PMM_MEMPDPWRCTRL0_CONFIGVALUE ( (uint32)((uint32)0x5U << 24U) \
+ | (uint32)((uint32)0x5U << 16U) \
+ )
+
+#define PMM_PDCLKDISREG_CONFIGVALUE ( (uint32)((uint32)(1U-1U) << 0U) \
+ | (uint32)((uint32)(1U-1U) << 1U) \
+ | (uint32)((uint32)(1U-0U) << 2U) \
+ | (uint32)((uint32)(1U-1U) << 3U) )
+
+#define PMM_GLOBALCTRL1_CONFIGVALUE ( (uint32)((uint32)0U << 8U) \
+ | (uint32)((uint32)0U << 0U))
+
+
+/** @enum pmmLogicPDTag
+* @brief PMM Logic Power Domain
+*
+* Used to define PMM Logic Power Domain
+*/
+typedef enum pmmLogicPDTag
+{
+ PMM_LOGICPD1 = 4U, /*-- NOT USED*/
+ PMM_LOGICPD2 = 0U,
+ PMM_LOGICPD3 = 1U,
+ PMM_LOGICPD4 = 2U,
+ PMM_LOGICPD5 = 3U
+}pmm_LogicPD_t;
+
+
+/** @enum pmmMemPDTag
+* @brief PMM Memory-Only Power Domain
+*
+* Used to define PMM Memory-Only Power Domain
+*/
+typedef enum pmmMemPDTag
+{
+ PMM_MEMPD1 = 0U,
+ PMM_MEMPD2 = 1U,
+ PMM_MEMPD3 = 2U
+}pmm_MemPD_t;
+
+
+/** @enum pmmModeTag
+* @brief PSCON operating mode
+*
+* Used to define the operating mode of PSCON Compare Block
+*/
+typedef enum pmmModeTag
+{
+ LockStep = 0x0U,
+ SelfTest = 0x6U,
+ ErrorForcing = 0x9U,
+ SelfTestErrorForcing = 0xFU
+}pmm_Mode_t;
+
+
+typedef struct pmm_config_reg
+{
+ uint32 CONFIG_LOGICPDPWRCTRL0;
+ uint32 CONFIG_MEMPDPWRCTRL0;
+ uint32 CONFIG_PDCLKDISREG;
+ uint32 CONFIG_GLOBALCTRL1;
+}pmm_config_reg_t;
+
+/**
+ * @defgroup PMM PMM
+ * @brief Power Management Module
+ *
+ * The PMM provides memory-mapped registers that control the states of the supported power domains.
+ * The PMM includes interfaces to the Power Mode Controller (PMC) and the Power State Controller (PSCON).
+ * The PMC and PSCON control the power up/down sequence of each power domain.
+ *
+ * Related files:
+ * - reg_pmm.h
+ * - sys_pmm.h
+ * - sys_pmm.c
+ *
+ * @addtogroup PMM
+ * @{
+ */
+
+/* Pmm Interface Functions */
+void pmmInit(void);
+void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD);
+void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD);
+void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD);
+void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD);
+boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD);
+boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD);
+void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type);
+void pmmSetMode(pmm_Mode_t mode);
+boolean pmmPerformSelfTest(void);
+
+/**@}*/
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+
+#endif
+
Index: firmware/include/sys_pmu.h
===================================================================
diff -u
--- firmware/include/sys_pmu.h (revision 0)
+++ firmware/include/sys_pmu.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,241 @@
+/** @file sys_pmu.h
+* @brief System Pmu Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Pmu Interface Functions
+* .
+* which are relevant for the performance monitor unit driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __SYS_PMU_H__
+#define __SYS_PMU_H__
+
+#include "sys_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/** @def pmuCOUNTER0
+* @brief pmu event counter 0 mask
+*
+* Alias for pmu event counter 0 mask
+*
+* @note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and _pmuStopCounters_
+*/
+#define pmuCOUNTER0 0x00000001U
+
+/** @def pmuCOUNTER1
+* @brief pmu event counter 1 mask
+*
+* Alias for pmu event counter 1 mask
+*
+* @note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and _pmuStopCounters_
+*/
+#define pmuCOUNTER1 0x00000002U
+
+/** @def pmuCOUNTER2
+* @brief pmu event counter 2 mask
+*
+* Alias for pmu event counter 2 mask
+*
+* @note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and _pmuStopCounters_
+*/
+#define pmuCOUNTER2 0x00000004U
+
+/** @def pmuCYCLE_COUNTER
+* @brief pmu cycle counter mask
+*
+* Alias for pmu event counter mask
+*
+* @note: Use this macro as a parameter 'counters' in APIs _pmuStartCounters_ and _pmuStopCounters_
+*/
+#define pmuCYCLE_COUNTER 0x80000000U
+
+/** @enum pmuEvent
+* @brief pmu event
+*
+* Alias for pmu event counter increment source
+*/
+enum pmuEvent
+{
+ PMU_INST_CACHE_MISS = 0x01U,
+ PMU_DATA_CACHE_MISS = 0x03U,
+ PMU_DATA_CACHE_ACCESS = 0x04U,
+ PMU_DATA_READ_ARCH_EXECUTED = 0x06U,
+ PMU_DATA_WRITE_ARCH_EXECUTED = 0x07U,
+ PMU_INST_ARCH_EXECUTED = 0x08U,
+ PMU_EXCEPTION_TAKEN = 0x09U,
+ PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0AU,
+ PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0BU,
+ PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0CU,
+ PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0DU,
+ PMU_PROC_RETURN_ARCH_EXECUTED = 0x0EU,
+ PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0FU,
+ PMU_BRANCH_MISSPREDICTED = 0x10U,
+ PMU_CYCLE_COUNT = 0x11U,
+ PMU_PREDICTABLE_BRANCHES = 0x12U,
+ PMU_INST_BUFFER_STALL = 0x40U,
+ PMU_DATA_DEPENDENCY_INST_STALL = 0x41U,
+ PMU_DATA_CACHE_WRITE_BACK = 0x42U,
+ PMU_EXT_MEMORY_REQUEST = 0x43U,
+ PMU_LSU_BUSY_STALL = 0x44U,
+ PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45U,
+ PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46U,
+ PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47U,
+ PMU_ETMEXTOUT_0 = 0x48U,
+ PMU_ETMEXTOUT_1 = 0x49U,
+ PMU_INST_CACHE_TAG_ECC_ERROR = 0x4AU,
+ PMU_INST_CACHE_DATA_ECC_ERROR = 0x4BU,
+ PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4CU,
+ PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4DU,
+ PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4EU,
+ PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4FU,
+ PMU_STORE_BUFFER_MERGE = 0x50U,
+ PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51U,
+ PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52U,
+ PMU_INTEGER_DIV_EXECUTED = 0x53U,
+ PMU_STALL_INTEGER_DIV = 0x54U,
+ PMU_PLD_INST_LINE_FILL = 0x55U,
+ PMU_PLD_INST_NO_LINE_FILL = 0x56U,
+ PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57U,
+ PMU_INST_CACHE_ACCESS = 0x58U,
+ PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59U,
+ PMU_DUAL_ISSUE_CASE_A = 0x5AU,
+ PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5BU,
+ PMU_DUAL_ISSUE_OTHER = 0x5CU,
+ PMU_DP_FLOAT_INST_EXCECUTED = 0x5DU,
+ PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU,
+ PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60U,
+ PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61U,
+ PMU_PROCESSOR_LIVE_LOCK = 0x62U,
+ PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64U,
+ PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65U,
+ PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66U,
+ PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67U,
+ PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68U,
+ PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69U,
+ PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6AU,
+ PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6BU,
+ PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6CU,
+ PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6DU
+};
+
+/** @fn void _pmuInit_(void)
+* @brief Initialize Performance Monitor Unit
+*/
+void _pmuInit_(void);
+
+/** @fn void _pmuEnableCountersGlobal_(void)
+* @brief Enable and reset cycle counter and all 3 event counters
+*/
+void _pmuEnableCountersGlobal_(void);
+
+/** @fn void _pmuDisableCountersGlobal_(void)
+* @brief Disable cycle counter and all 3 event counters
+*/
+void _pmuDisableCountersGlobal_(void);
+
+/** @fn void _pmuResetCycleCounter_(void)
+* @brief Reset cycle counter
+*/
+void _pmuResetCycleCounter_(void);
+
+/** @fn void _pmuResetEventCounters_(void)
+* @brief Reset event counters 0-2
+*/
+void _pmuResetEventCounters_(void);
+
+/** @fn void _pmuResetCounters_(void)
+* @brief Reset cycle counter and event counters 0-2
+*/
+void _pmuResetCounters_(void);
+
+/** @fn void _pmuStartCounters_(uint32 counters)
+* @brief Starts selected counters
+* @param[in] counters - Counter mask
+*/
+void _pmuStartCounters_(uint32 counters);
+
+/** @fn void _pmuStopCounters_(uint32 counters)
+* @brief Stops selected counters
+* @param[in] counters - Counter mask
+*/
+void _pmuStopCounters_(uint32 counters);
+
+/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event)
+* @brief Set event counter count event
+* @param[in] counter - Counter select 0..2
+* @param[in] event - Count event
+*/
+void _pmuSetCountEvent_(uint32 counter, uint32 event);
+
+/** @fn uint32 _pmuGetCycleCount_(void)
+* @brief Returns current cycle counter value
+*
+* @return cycle count.
+*/
+uint32 _pmuGetCycleCount_(void);
+
+/** @fn uint32 _pmuGetEventCount_(uint32 counter)
+* @brief Returns current event counter value
+* @param[in] counter - Counter select 0..2
+*
+* @return event counter count.
+*/
+uint32 _pmuGetEventCount_(uint32 counter);
+
+/** @fn uint32 _pmuGetOverflow_(void)
+* @brief Returns current overflow register and clear flags
+*
+* @return overflow flags.
+*/
+uint32 _pmuGetOverflow_(void);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+#endif
Index: firmware/include/sys_selftest.h
===================================================================
diff -u
--- firmware/include/sys_selftest.h (revision 0)
+++ firmware/include/sys_selftest.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,471 @@
+/** @file sys_selftest.h
+* @brief System Memory Header File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - Efuse Self Test Functions
+* .
+* which are relevant for the System driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __sys_selftest_H__
+#define __sys_selftest_H__
+
+#include "reg_pbist.h"
+#include "reg_stc.h"
+#include "reg_efc.h"
+#include "sys_core.h"
+#include "system.h"
+#include "sys_vim.h"
+#include "adc.h"
+#include "can.h"
+#include "mibspi.h"
+#include "het.h"
+#include "htu.h"
+#include "esm.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#define flash1bitError (*(volatile uint32 *)(0xF00803F0U))
+#define flash2bitError (*(volatile uint32 *)(0xF00803F8U))
+
+#define tcramA1bitError (*(volatile uint32 *)(0x08400000U))
+#define tcramA2bitError (*(volatile uint32 *)(0x08400010U))
+
+#define tcramB1bitError (*(volatile uint32 *)(0x08400008U))
+#define tcramB2bitError (*(volatile uint32 *)(0x08400018U))
+
+#define tcramA1bit (*(volatile uint64 *)(0x08000000U))
+#define tcramA2bit (*(volatile uint64 *)(0x08000010U))
+
+#define tcramB1bit (*(volatile uint64 *)(0x08000008U))
+#define tcramB2bit (*(volatile uint64 *)(0x08000018U))
+
+#define flashBadECC1 (*(volatile uint32 *)(0x20000000U))
+#define flashBadECC2 (*(volatile uint32 *)(0x20000010U))
+
+#define CCMSR (*(volatile uint32 *)(0xFFFFF600U))
+#define CCMKEYR (*(volatile uint32 *)(0xFFFFF604U))
+
+#define DMA_PARCR (*(volatile uint32 *)(0xFFFFF1A8U))
+#define DMA_PARADDR (*(volatile uint32 *)(0xFFFFF1ACU))
+#define DMARAMLOC (*(volatile uint32 *)(0xFFF80000U))
+#define DMARAMPARLOC (*(volatile uint32 *)(0xFFF80A00U))
+
+#define MIBSPI1RAMLOC (*(volatile uint32 *)(0xFF0E0000U))
+#define MIBSPI3RAMLOC (*(volatile uint32 *)(0xFF0C0000U))
+#define MIBSPI5RAMLOC (*(volatile uint32 *)(0xFF0A0000U))
+
+
+#ifndef __PBIST_H__
+#define __PBIST_H__
+
+/** @enum pbistPort
+* @brief Alias names for pbist Port number
+*
+* This enumeration is used to provide alias names for the pbist Port number
+* - PBIST_PORT0
+* - PBIST_PORT1
+*
+* @note Check the datasheet for the port avaiability
+*/
+enum pbistPort
+{
+ PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */
+ PBIST_PORT1 = 1U /**< Alias for PBIST Port 1 < Check datasheet for Port 1 availability > */
+};
+/** @enum pbistAlgo
+* @brief Alias names for pbist Algorithm
+*
+* This enumeration is used to provide alias names for the pbist Algorithm
+*/
+enum pbistAlgo
+{
+ PBIST_TripleReadSlow = 0x00000001U, /**>16U)
+#define SYS_EXCEPTION (*(volatile uint32 *)0xFFFFFFE4U)
+
+#define POWERON_RESET 0x8000U
+#define OSC_FAILURE_RESET 0x4000U
+#define WATCHDOG_RESET 0x2000U
+#define ICEPICK_RESET 0x2000U
+#define CPU_RESET 0x0020U
+#define SW_RESET 0x0010U
+
+#define WATCHDOG_STATUS (*(volatile uint32 *)0xFFFFFC98U)
+#define DEVICE_ID_REV (*(volatile uint32 *)0xFFFFFFF0U)
+
+/** @def OSC_FREQ
+* @brief Oscillator clock source exported from HALCoGen GUI
+*
+* Oscillator clock source exported from HALCoGen GUI
+*/
+#define OSC_FREQ 16.0F
+
+/** @def PLL1_FREQ
+* @brief PLL 1 clock source exported from HALCoGen GUI
+*
+* PLL 1 clock source exported from HALCoGen GUI
+*/
+#define PLL1_FREQ 208.00F
+
+/** @def LPO_LF_FREQ
+* @brief LPO Low Freq Oscillator source exported from HALCoGen GUI
+*
+* LPO Low Freq Oscillator source exported from HALCoGen GUI
+*/
+#define LPO_LF_FREQ 0.080F
+
+/** @def LPO_HF_FREQ
+* @brief LPO High Freq Oscillator source exported from HALCoGen GUI
+*
+* LPO High Freq Oscillator source exported from HALCoGen GUI
+*/
+#define LPO_HF_FREQ 10.000F
+
+/** @def PLL1_FREQ
+* @brief PLL 2 clock source exported from HALCoGen GUI
+*
+* PLL 2 clock source exported from HALCoGen GUI
+*/
+#define PLL2_FREQ 220.00F
+
+/** @def GCLK_FREQ
+* @brief GCLK domain frequency exported from HALCoGen GUI
+*
+* GCLK domain frequency exported from HALCoGen GUI
+*/
+#define GCLK_FREQ 208.000F
+
+/** @def HCLK_FREQ
+* @brief HCLK domain frequency exported from HALCoGen GUI
+*
+* HCLK domain frequency exported from HALCoGen GUI
+*/
+#define HCLK_FREQ 208.000F
+
+/** @def RTI_FREQ
+* @brief RTI Clock frequency exported from HALCoGen GUI
+*
+* RTI Clock frequency exported from HALCoGen GUI
+*/
+#define RTI_FREQ 104.000F
+
+/** @def AVCLK1_FREQ
+* @brief AVCLK1 Domain frequency exported from HALCoGen GUI
+*
+* AVCLK Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK1_FREQ 104.000F
+
+/** @def AVCLK2_FREQ
+* @brief AVCLK2 Domain frequency exported from HALCoGen GUI
+*
+* AVCLK2 Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK2_FREQ 0.000F
+
+/** @def AVCLK3_FREQ
+* @brief AVCLK3 Domain frequency exported from HALCoGen GUI
+*
+* AVCLK3 Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK3_FREQ 104.000F
+
+/** @def AVCLK4_FREQ
+* @brief AVCLK4 Domain frequency exported from HALCoGen GUI
+*
+* AVCLK4 Domain frequency exported from HALCoGen GUI
+*/
+#define AVCLK4_FREQ 104.000F
+
+/** @def VCLK1_FREQ
+* @brief VCLK1 Domain frequency exported from HALCoGen GUI
+*
+* VCLK1 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK1_FREQ 104.000F
+
+/** @def VCLK2_FREQ
+* @brief VCLK2 Domain frequency exported from HALCoGen GUI
+*
+* VCLK2 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK2_FREQ 104.000F
+
+/** @def VCLK3_FREQ
+* @brief VCLK3 Domain frequency exported from HALCoGen GUI
+*
+* VCLK3 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK3_FREQ 104.000F
+
+/** @def VCLK4_FREQ
+* @brief VCLK4 Domain frequency exported from HALCoGen GUI
+*
+* VCLK4 Domain frequency exported from HALCoGen GUI
+*/
+#define VCLK4_FREQ 104.000F
+
+
+/** @def SYS_PRE1
+* @brief Alias name for RTI1CLK PRE clock source
+*
+* This is an alias name for the RTI1CLK pre clock source.
+* This can be either:
+* - Oscillator
+* - Pll
+* - 32 kHz Oscillator
+* - External
+* - Low Power Oscillator Low
+* - Low Power Oscillator High
+* - Flexray Pll
+*/
+/*SAFETYMCUSW 79 S MR:19.4 " Value comes from GUI drop down option " */
+#define SYS_PRE1 (SYS_PLL1)
+
+/** @def SYS_PRE2
+* @brief Alias name for RTI2CLK pre clock source
+*
+* This is an alias name for the RTI2CLK pre clock source.
+* This can be either:
+* - Oscillator
+* - Pll
+* - 32 kHz Oscillator
+* - External
+* - Low Power Oscillator Low
+* - Low Power Oscillator High
+* - Flexray Pll
+*/
+/*SAFETYMCUSW 79 S MR:19.4 " Value comes from GUI drop down option " */
+#define SYS_PRE2 (SYS_PLL1)
+
+/* Configuration registers */
+typedef struct system_config_reg
+{
+ uint32 CONFIG_SYSPC1;
+ uint32 CONFIG_SYSPC2;
+ uint32 CONFIG_SYSPC7;
+ uint32 CONFIG_SYSPC8;
+ uint32 CONFIG_SYSPC9;
+ uint32 CONFIG_CSDIS;
+ uint32 CONFIG_CDDIS;
+ uint32 CONFIG_GHVSRC;
+ uint32 CONFIG_VCLKASRC;
+ uint32 CONFIG_RCLKSRC;
+ uint32 CONFIG_MSTGCR;
+ uint32 CONFIG_MINITGCR;
+ uint32 CONFIG_MSINENA;
+ uint32 CONFIG_PLLCTL1;
+ uint32 CONFIG_PLLCTL2;
+ uint32 CONFIG_UERFLAG;
+ uint32 CONFIG_LPOMONCTL;
+ uint32 CONFIG_CLKTEST;
+ uint32 CONFIG_DFTCTRLREG1;
+ uint32 CONFIG_DFTCTRLREG2;
+ uint32 CONFIG_GPREG1;
+ uint32 CONFIG_RAMGCR;
+ uint32 CONFIG_BMMCR1;
+ uint32 CONFIG_MMUGCR;
+ uint32 CONFIG_CLKCNTL;
+ uint32 CONFIG_ECPCNTL;
+ uint32 CONFIG_DEVCR1;
+ uint32 CONFIG_SYSECR;
+ uint32 CONFIG_PLLCTL3;
+ uint32 CONFIG_STCCLKDIV;
+ uint32 CONFIG_CLK2CNTL;
+ uint32 CONFIG_VCLKACON1;
+ uint32 CONFIG_CLKSLIP;
+ uint32 CONFIG_EFC_CTLEN;
+} system_config_reg_t;
+
+/* Configuration registers initial value */
+#define SYS_SYSPC1_CONFIGVALUE 0U
+
+#define SYS_SYSPC2_CONFIGVALUE 1U
+
+#define SYS_SYSPC7_CONFIGVALUE 0U
+
+#define SYS_SYSPC8_CONFIGVALUE 0U
+
+#define SYS_SYSPC9_CONFIGVALUE 1U
+
+#define SYS_CSDIS_CONFIGVALUE ( 0x00000000U\
+ | 0x00000000U \
+ | 0x00000008U \
+ | 0x00000080U \
+ | 0x00000000U \
+ | 0x00000000U \
+ | 0x00000000U\
+ | 0x4U )
+
+#define SYS_CDDIS_CONFIGVALUE ( (uint32)((uint32)0U << 4U )\
+ | (uint32)((uint32)1U << 5U )\
+ | (uint32)((uint32)0U << 8U )\
+ | (uint32)((uint32)0U << 9U )\
+ | (uint32)((uint32)0U << 10U)\
+ | (uint32)((uint32)0U << 11U) )
+
+#define SYS_GHVSRC_CONFIGVALUE ( (uint32)((uint32)SYS_OSC << 24U) \
+ | (uint32)((uint32)SYS_OSC << 16U) \
+ | (uint32)((uint32)SYS_PLL1 << 0U) )
+
+#define SYS_VCLKASRC_CONFIGVALUE ( (uint32)((uint32)SYS_VCLK << 8U)\
+ | (uint32)((uint32)SYS_VCLK << 0U) )
+
+#define SYS_RCLKSRC_CONFIGVALUE ( (uint32)((uint32)1U << 24U)\
+ | (uint32)((uint32)SYS_VCLK << 16U)\
+ | (uint32)((uint32)1U << 8U)\
+ | (uint32)((uint32)SYS_VCLK << 0U) )
+
+#define SYS_MSTGCR_CONFIGVALUE 0x00000105U
+
+#define SYS_MINITGCR_CONFIGVALUE 0x5U
+
+#define SYS_MSINENA_CONFIGVALUE 0U
+
+#define SYS_PLLCTL1_CONFIGVALUE_1 ( (uint32)0x00000000U \
+ | (uint32)0x20000000U \
+ | (uint32)((uint32)0x1FU << 24U) \
+ | (uint32)0x00000000U \
+ | (uint32)((uint32)(6U - 1U)<< 16U)\
+ | (uint32)(0x9B00U))
+
+#define SYS_PLLCTL1_CONFIGVALUE_2 (((SYS_PLLCTL1_CONFIGVALUE_1) & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U))
+
+#define SYS_PLLCTL2_CONFIGVALUE ( (uint32)0x00000000U\
+ | (uint32)((uint32)255U << 22U)\
+ | (uint32)((uint32)7U << 12U)\
+ | (uint32)((uint32)(2U - 1U)<< 9U)\
+ | (uint32)61U)
+
+#define SYS_UERFLAG_CONFIGVALUE 0U
+
+#define SYS_LPOMONCTL_CONFIGVALUE_1 ((uint32)((uint32)1U << 24U) | LPO_TRIM_VALUE)
+#define SYS_LPOMONCTL_CONFIGVALUE_2 ((uint32)((uint32)1U << 24U) | (uint32)((uint32)16U << 8U) | 16U)
+
+#define SYS_CLKTEST_CONFIGVALUE 0x000A0000U
+
+#define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U
+
+#define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U
+
+#define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU
+
+#define SYS_RAMGCR_CONFIGVALUE 0x00050000U
+
+#define SYS_BMMCR1_CONFIGVALUE 0xAU
+
+#define SYS_MMUGCR_CONFIGVALUE 0U
+
+#define SYS_CLKCNTL_CONFIGVALUE ( 0x00000100U \
+ | (uint32)((uint32)1U << 16U) \
+ | (uint32)((uint32)1U << 24U) )
+
+#define SYS_ECPCNTL_CONFIGVALUE ( (uint32)((uint32)0U << 24U)\
+ | (uint32)((uint32)0U << 23U)\
+ | (uint32)((uint32)(8U - 1U) & 0xFFFFU) )
+
+#define SYS_DEVCR1_CONFIGVALUE 0xAU
+
+#define SYS_SYSECR_CONFIGVALUE 0x00004000U
+#define SYS2_PLLCTL3_CONFIGVALUE_1 ( (uint32)((uint32)(2U - 1U) << 29U)\
+ | (uint32)((uint32)0x1FU << 24U) \
+ | (uint32)((uint32)(6U - 1U)<< 16U) \
+ | (uint32)(0xA400U))
+
+#define SYS2_PLLCTL3_CONFIGVALUE_2 (((SYS2_PLLCTL3_CONFIGVALUE_1) & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U))
+#define SYS2_STCCLKDIV_CONFIGVALUE 0U
+#define SYS2_CLK2CNTL_CONFIGVALUE (1U | 0x00000100U)
+#define SYS2_VCLKACON1_CONFIGVALUE ( (uint32)((uint32)1U << 24U) \
+ | (uint32)((uint32)1U << 20U) \
+ | (uint32)((uint32)SYS_VCLK << 16U)\
+ | (uint32)((uint32)1U << 8U)\
+ | (uint32)((uint32)1U << 4U) \
+ | (uint32)((uint32)SYS_VCLK << 0U) )
+#define SYS2_CLKSLIP_CONFIGVALUE 0x5U
+#define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U
+
+void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/* FlashW General Definitions */
+
+
+/** @enum flashWPowerModes
+* @brief Alias names for flash bank power modes
+*
+* This enumeration is used to provide alias names for the flash bank power modes:
+* - sleep
+* - standby
+* - active
+*/
+enum flashWPowerModes
+{
+ SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */
+ SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
+ SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */
+};
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+#define FSM_WR_ENA_HL (*(volatile uint32 *)0xFFF87288U)
+#define EEPROM_CONFIG_HL (*(volatile uint32 *)0xFFF872B8U)
+
+/* Configuration registers */
+typedef struct tcmflash_config_reg
+{
+ uint32 CONFIG_FRDCNTL;
+ uint32 CONFIG_FEDACCTRL1;
+ uint32 CONFIG_FEDACCTRL2;
+ uint32 CONFIG_FEDACSDIS;
+ uint32 CONFIG_FBPROT;
+ uint32 CONFIG_FBSE;
+ uint32 CONFIG_FBAC;
+ uint32 CONFIG_FBFALLBACK;
+ uint32 CONFIG_FPAC1;
+ uint32 CONFIG_FPAC2;
+ uint32 CONFIG_FMAC;
+ uint32 CONFIG_FLOCK;
+ uint32 CONFIG_FDIAGCTRL;
+ uint32 CONFIG_FEDACSDIS2;
+} tcmflash_config_reg_t;
+
+/* Configuration registers initial value */
+#define TCMFLASH_FRDCNTL_CONFIGVALUE (0x00000000U | (uint32)((uint32)3U << 8U) | (uint32)((uint32)1U << 4U) | 1U)
+#define TCMFLASH_FEDACCTRL1_CONFIGVALUE 0x000A0005U
+#define TCMFLASH_FEDACCTRL2_CONFIGVALUE 0U
+#define TCMFLASH_FEDACSDIS_CONFIGVALUE 0U
+#define TCMFLASH_FBPROT_CONFIGVALUE 0U
+#define TCMFLASH_FBSE_CONFIGVALUE 0U
+#define TCMFLASH_FBAC_CONFIGVALUE 0xFU
+#define TCMFLASH_FBFALLBACK_CONFIGVALUE ( (uint32)((uint32)SYS_ACTIVE << 14U) \
+ | (uint32)((uint32)3U << 12U) \
+ | (uint32)((uint32)3U << 10U) \
+ | (uint32)((uint32)3U << 8U) \
+ | (uint32)((uint32)3U << 6U) \
+ | (uint32)((uint32)3U << 4U) \
+ | (uint32)((uint32)SYS_ACTIVE << 2U) \
+ | (uint32)((uint32)SYS_ACTIVE << 0U) )
+
+#define TCMFLASH_FPAC1_CONFIGVALUE 0x00C80001U
+#define TCMFLASH_FPAC2_CONFIGVALUE 0U
+#define TCMFLASH_FMAC_CONFIGVALUE 0U
+#define TCMFLASH_FLOCK_CONFIGVALUE 0x55AAU
+#define TCMFLASH_FDIAGCTRL_CONFIGVALUE 0x000A0000U
+#define TCMFLASH_FEDACSDIS2_CONFIGVALUE 0U
+
+void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type);
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+
+/* System Interface Functions */
+void setupPLL(void);
+void trimLPO(void);
+void customTrimLPO(void);
+void setupFlash(void);
+void periphInit(void);
+void mapClocks(void);
+void systemInit(void);
+void systemPowerDown(uint32 mode);
+
+/*Configuration registers
+* index 0: Even RAM
+* index 1: Odd RAM
+*/
+typedef struct sram_config_reg
+{
+ uint32 CONFIG_RAMCTRL[2U];
+ uint32 CONFIG_RAMTHRESHOLD[2U];
+ uint32 CONFIG_RAMINTCTRL[2U];
+ uint32 CONFIG_RAMTEST[2U];
+ uint32 CONFIG_RAMADDRDECVECT[2U];
+} sram_config_reg_t;
+
+/* Configuration registers initial value */
+#define SRAM_RAMCTRL_CONFIGVALUE 0x0005000AU
+#define SRAM_RAMTHRESHOLD_CONFIGVALUE 1U
+#define SRAM_RAMINTCTRL_CONFIGVALUE 1U
+#define SRAM_RAMTEST_CONFIGVALUE 0x5U
+#define SRAM_RAMADDRDECVECT_CONFIGVALUE 0U
+
+void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type);
+#ifdef __cplusplus
+}
+#endif /*extern "C" */
+#endif
Index: firmware/include/ti_fee.h
===================================================================
diff -u
--- firmware/include/ti_fee.h (revision 0)
+++ firmware/include/ti_fee.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,504 @@
+/**********************************************************************************************************************
+ * FILE DESCRIPTION
+ * -------------------------------------------------------------------------------------------------------------------
+ * File: ti_fee.h
+ * Project: Tms570_TIFEEDriver
+ * Module: TIFEEDriver
+ * Generator: None
+ *
+ * Description: This file implements the TI FEE Api.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author: Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version Date Author Change ID Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version
+ * 00.01.01 29Oct2012 Vishwanath Reddy 0000000000000 Changes for implementing Error Recovery
+ * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory segmentation changes.
+ * 00.01.03 14Jan2013 Vishwanath Reddy SDOCM00098510 Changes as requested by Vector.
+ * 00.01.04 12Feb2012 Vishwanath Reddy SDOCM00099152 Integration issues fix.
+ * 00.01.05 04Mar2013 Vishwanath Reddy SDOCM00099152 Added Deleting a block feature, bug fixes.
+ * 00.01.06 11Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : copying of unconfigured blocks.
+ * 00.01.07 15Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : Number of 8 bytes writes, fixed
+ issue with copy blocks.
+ * 00.01.08 05Apr2013 Vishwanath Reddy SDOCM00099152 Added feature : CRC check for unconfigured blocks,
+ Main function modified to complete writes as fast
+ as possible, Added Non polling mode support.
+ * 00.01.09 19Apr2013 Vishwanath Reddy SDOCM00099152 Warning removal, Added feature comparision of data
+ during write.
+ * 00.01.10 11Jun2013 Vishwanath Reddy SDOCM00101845 Updated version information.
+ * 00.01.11 05Jul2013 Vishwanath Reddy SDOCM00101643 Updated version information.
+ * 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 Traceability tags added.
+ * MISRA C fixes. Version info corrected.
+ * 01.13.00 30Dec2013 Vishwanath Reddy 0000000000000 Undated version info for SDOCM00107976
+ * and SDOCM00105795.
+ * 01.13.01 19May2014 Vishwanath Reddy 0000000000000 Updated version info for SDOCM00107913
+ * and SDOCM00107622.
+ * 01.13.02 12Jun2014 Vishwanath Reddy 0000000000000 Updated version info for SDOCM00108238
+ * 01.14.00 26Mar2014 Vishwanath Reddy Update version info for SDOCM00107161.
+ * 01.15.00 06Jun2014 Vishwanath Reddy Support for Conqueror.
+ * 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove MISRA warnings.
+ * 01.16.01 12Sep2014 Vishwanath Reddy SDOCM00112930 Prototype for TI_Fee_SuspendResumeErase added.
+ * TI_Fee_EraseCommandType enum added.
+ * extern added for TI_Fee_bEraseSuspended.
+ * 01.17.00 15Oct2014 Vishwanath Reddy SDOCM00113379 RAM Optimization changes.
+ * 01.17.01 30Oct2014 Vishwanath Reddy SDOCM00113536 Support for TMS570LS07xx,TMS570LS09xx,
+ * TMS570LS05xx, RM44Lx.
+ * 01.17.02 26Dec2014 Vishwanath Reddy SDOCM00114102 FLEE Errata Fix.
+ * SDOCM00114104 Change ALL 1's OK check condition.
+ * Updated version info. Added new macros.
+ * SDOCM00114423 Add new enum TI_Fee_DeviceType.
+ * Add new variable TI_Fee_MaxSectors and
+ * prototype TI_FeeInternal_PopulateStructures.
+ * 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version history.
+ * Update ti_fee_util.c file for the
+ * bugfix "If morethan one data set is config-
+ * ured, then a valid block may get invalidated if
+ * multiple valid blocks are present in FEE memory.
+ * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version history.
+ * In TI_FeeInternal_FeeManager, do not change the
+ * state to IDLE,after completing the copy operation.
+ * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version history.
+ * Add a call of TI_FeeInternal_PollFlashStatus()
+ * before reading data from FEE bank in
+ * TI_FeeInternal_UpdateBlockOffsetArray(),
+ * TI_Fee_WriteAsync(),TI_Fee_WriteSync(),
+ * TI_Fee_ReadSync(), TI_Fee_Read()
+ * 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update patch version TI_FEE_SW_PATCH_VERSION.
+ * TI_FEE_FLASH_CRC_ENABLE is renamed to
+ * TI_FEE_FLASH_CHECKSUM_ENABLE.
+ * SDOCM00122429 In ti_fee_types.h, add error when endianess
+ * is not defined.
+ * 01.19.00 08Augu2016 Vishwanath Reddy SDOCM00122592 Update patch version TI_FEE_MINOR_VERSION.
+ * Code for using partially ersed sector is now
+ * removed.
+ * Bugfix for FEE reading from unimplemented memory
+ * space.
+ * 01.19.01 12Augu2016 Vishwanath Reddy SDOCM00122543 Update patch version TI_FEE_MINOR_VERSION.
+ * Synchronous write API modified to avoid copy of
+ * already copied block.
+ * 01.19.02 25Janu2017 Vishwanath Reddy SDOCM00122832 Update patch version TI_FEE_MINOR_VERSION.
+ * Format API modified to erase all configured VS.
+ * SDOCM00122833 In API TI_Fee_ErrorRecovery, added polling for
+ * flash status before calling TI_Fee_Init.
+ * 01.19.03 15May2017 Prathap Srinivasan SDOCM00122917 Added TI_Fee_bIsMainFunctionCalled Global Variable.
+ * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version history.
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef TI_FEE_H
+#define TI_FEE_H
+
+/**********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+#include "hal_stdtypes.h"
+#include "fee_interface.h"
+#include "ti_fee_types.h"
+#include "ti_fee_cfg.h"
+/**********************************************************************************************************************
+ * GLOBAL CONSTANT MACROS
+ *********************************************************************************************************************/
+/* Fee Published Information */
+#define TI_FEE_MAJOR_VERSION 3U
+#define TI_FEE_MINOR_VERSION 0U
+#define TI_FEE_PATCH_VERSION 2U
+#define TI_FEE_SW_MAJOR_VERSION 1U
+#define TI_FEE_SW_MINOR_VERSION 19U
+#define TI_FEE_SW_PATCH_VERSION 4U
+
+#define TI_FEE_VIRTUAL_SECTOR_VERSION 1U
+
+/* Virtual sector states */
+#define ActiveVSHi 0x0000FFFFU
+#define ActiveVSLo 0x00000000U
+#define CopyVSHi 0xFFFFFFFFU
+#define CopyVSLo 0x00000000U
+#define EmptyVSHi 0xFFFFFFFFU
+#define EmptyVSLo 0x0000FFFFU
+#define InvalidVSHi 0xFFFFFFFFU
+#define InvalidVSLo 0xFFFFFFFFU
+#define ReadyforEraseVSHi 0x00000000U
+#define ReadyforEraseVSLo 0x00000000U
+
+/* Data Block states*/
+#define EmptyBlockHi 0xFFFFFFFFU
+#define EmptyBlockLo 0xFFFFFFFFU
+#define StartProgramBlockHi 0xFFFF0000U
+#define StartProgramBlockLo 0xFFFFFFFFU
+#define ValidBlockHi 0x00000000U
+#define ValidBlockLo 0xFFFFFFFFU
+#define InvalidBlockHi 0x00000000U
+#define InvalidBlockLo 0xFFFF0000U
+#define CorruptBlockHi 0x00000000U
+#define CorruptBlockLo 0x00000000U
+
+#define FEE_BANK 0U
+
+/* Enable/Disable FEE sectors */
+#define FEE_DISABLE_SECTORS_31_00 0x00000000U
+#define FEE_DISABLE_SECTORS_63_32 0x00000000U
+#define FEE_ENABLE_SECTORS_31_00 0xFFFFFFFFU
+#define FEE_ENABLE_SECTORS_63_32 0xFFFFFFFFU
+
+/**********************************************************************************************************************
+ * GLOBAL DATA TYPES AND STRUCTURES
+ *********************************************************************************************************************/
+/* Structures used */
+/* Enum to describe the Fee Status types */
+typedef enum
+{
+ TI_FEE_OK = 0U, /* Function returned no error */
+ TI_FEE_ERROR = 1U /* Function returned an error */
+} TI_Fee_StatusType;
+
+/* Enum to describe the Virtual Sector State */
+typedef enum
+{
+ VsState_Invalid=1U,
+ VsState_Empty=2U,
+ VsState_Copy=3U,
+ VsState_Active=4U,
+ VsState_ReadyForErase=5U
+}VirtualSectorStatesType;
+
+/* Enum to describe the Block State */
+typedef enum
+{
+ Block_StartProg=1U,
+ Block_Valid=2U,
+ Block_Invalid=3U
+}BlockStatesType;
+
+/* Enum for error trpes */
+typedef enum
+{
+ Error_Nil=0U,
+ Error_TwoActiveVS=1U,
+ Error_TwoCopyVS=2U,
+ Error_SetupStateMachine=3U,
+ Error_CopyButNoActiveVS=4U,
+ Error_NoActiveVS=5U,
+ Error_BlockInvalid=6U,
+ Error_NullDataPtr=7U,
+ Error_NoFreeVS=8U,
+ Error_InvalidVirtualSectorParameter=9U,
+ Error_ExceedSectorOnBank=10U,
+ Error_EraseVS=11U,
+ Error_BlockOffsetGtBlockSize=12U,
+ Error_LengthParam=13U,
+ Error_FeeUninit=14U,
+ Error_Suspend=15U,
+ Error_InvalidBlockIndex=16U,
+ Error_NoErase=17U,
+ Error_CurrentAddress=18U,
+ Error_Exceed_No_Of_DataSets=19U
+}TI_Fee_ErrorCodeType;
+
+typedef enum
+{
+ Suspend_Erase=0U,
+ Resume_Erase
+}TI_Fee_EraseCommandType;
+
+/* Enum to describe the Device types */
+typedef enum
+{
+ CHAMPION = 0U, /* Function returned no error */
+ ARCHER = 1U /* Function returned an error */
+} TI_Fee_DeviceType;
+
+typedef uint32 TI_Fee_AddressType; /* Used for defining variables to indicate number of
+ bytes for address offset */
+typedef uint32 TI_Fee_LengthType; /* Used for defining variables to indicate number of
+ bytes per read/write/erase */
+typedef TI_Fee_ErrorCodeType Fee_ErrorCodeType;
+
+/* Structure used when defining virtual sectors */
+/* The following error checks need to be performed: */
+/* Virtual Sector definitions are not allowed to overlap */
+/* Virtual Sector definition is at least twice the size in bytes of the total size of all defined blocks */
+/* We will need to define a formula to indicate if the number of write cycles indicated in the block definitions */
+/* is possible in the defined Virtual Sector. */
+/* Ending sector cannot be less than Starting sector */
+typedef struct
+{
+ uint16 FeeVirtualSectorNumber; /* Virtual Sector's Number - 0 and 0xFFFF values are not allowed*/
+ /* Minimum 1, Maximum 4 */
+ uint16 FeeFlashBank; /* Flash Bank to use for virtual sector. */
+ /* As we do not allow Flash EEPROM Emulation in Bank 0,
+ 0 is not a valid option */
+ /* Defaultvalue 1, Minimum 1, Maxiumum 7 */
+ Fapi_FlashSectorType FeeStartSector; /* Defines the Starting Sector inthe Bank for this VirtualSector*/
+ Fapi_FlashSectorType FeeEndSector; /* Defines the Ending Sector inthe Bank for this Virtual Sector */
+ /* Start and End sectors can be the same, which indicates only
+ one sector */
+ /* is the entire virtual sector. */
+ /* Values are based on the FLASH_SECT enum */
+ /* Defaultvalue and Min is the same sector defined as the starting
+ sector */
+ /* Max values are based onthe device definition file being used.*/
+} Fee_VirtualSectorConfigType;
+
+/* Structure used when defining blocks */
+typedef struct
+{
+ uint16 FeeBlockNumber; /* Block's Number - 0 and 0xFFFF values are not allowed */
+ /* Start 1, Next: Number of Blocks + 1, Min 1, Max 0xFFFE */
+ uint16 FeeBlockSize; /* Block's Size - Actual number of bits used is reduced */
+ /* by number of bits used for dataset. */
+ /* Default 8, Min 1, Max (2^(16-# of Dataset Bits))-1 */
+ boolean FeeImmediateData; /* Indicates if the block is used for immediate data */
+ /* Default: False */
+ uint32 FeeNumberOfWriteCycles; /* Number of write cycles this block requires */
+ /* Default: 0, but this will not be a valid number.
+ Force customer to select a value */
+ /* Min 1, Max (2^32)-1 */
+ uint8 FeeDeviceIndex; /* Device Index - This will always be 0 */
+ /* Fixed value: 0 */
+ uint8 FeeNumberOfDataSets; /* Number of DataSets for the Block */
+ /* Default value: 1 */
+ uint8 FeeEEPNumber;
+} Fee_BlockConfigType;
+
+
+/* Structure used for Global variables */
+typedef struct
+{
+ TI_Fee_AddressType Fee_oFlashNextAddress; /* The next Flash Address to write to */
+ TI_Fee_AddressType Fee_oCopyCurrentAddress; /* Indicates the Address within the Active VS
+ which will be copied to Copy VS */
+ TI_Fee_AddressType Fee_oCopyNextAddress; /* Indicates the Address within the Copy VS to
+ which the data from Active VS will be copied to */
+ TI_Fee_AddressType Fee_u32nextwriteaddress; /* Indicates the next free Address within the curent
+ VS to which the data will be written */
+ TI_Fee_AddressType Fee_oVirtualSectorStartAddress; /* Start Address of the current Virtual Sector */
+ TI_Fee_AddressType Fee_oVirtualSectorEndAddress; /* End Address of the current Virtual Sector */
+ TI_Fee_AddressType Fee_oCopyVirtualSectorAddress; /* Start Address of the Copy Virtual Address */
+ TI_Fee_AddressType Fee_oCurrentStartAddress; /* Start Address of the Previous Block */
+ TI_Fee_AddressType Fee_oCurrentBlockHeader; /* Start Address of the Block which is being currently
+ written*/
+ TI_Fee_AddressType Fee_oWriteAddress; /* Address within the VS where data is to be written */
+ TI_Fee_AddressType Fee_oCopyWriteAddress; /* Address within the VS where data is to be copied */
+ TI_Fee_AddressType Fee_oActiveVirtualSectorAddress; /* Start Address of the Active VS */
+ TI_Fee_AddressType Fee_oBlankFailAddress; /* Address of first non-blank location */
+ TI_Fee_AddressType Fee_oActiveVirtualSectorStartAddress;/* Start Address of the active VS */
+ TI_Fee_AddressType Fee_oActiveVirtualSectorEndAddress; /* End Address of the active VS */
+ TI_Fee_AddressType Fee_oCopyVirtualSectorStartAddress; /* Start Address of the Copy VS */
+ TI_Fee_AddressType Fee_oCopyVirtualSectorEndAddress; /* End Address of the Copy VS */
+ TI_Fee_AddressType Fee_u32nextActiveVSwriteaddress; /* Next write address in Active VS */
+ TI_Fee_AddressType Fee_u32nextCopyVSwriteaddress; /* Next write address in Copy VS */
+ uint16 Fee_u16CopyBlockSize; /* Indicates the size of current block in bytes which is
+ been copied from Active to Copy VS */
+ uint8 Fee_u8VirtualSectorStart; /* Index of the Start Sector of the VS */
+ uint8 Fee_u8VirtualSectorEnd; /* Index of the End Sector of the VS */
+ uint32 Fee_au32VirtualSectorStateValue[TI_FEE_VIRTUAL_SECTOR_OVERHEAD >> 2U]; /* Array to store the Virtual
+ Sector Header and
+ Information record */
+ uint8 Fee_au8VirtualSectorState[TI_FEE_NUMBER_OF_VIRTUAL_SECTORS]; /* Stores the state of each
+ Virtual sector */
+ uint32 Fee_au32VirtualSectorEraseCount[TI_FEE_NUMBER_OF_VIRTUAL_SECTORS]; /* Array to store the erase
+ count of each Virtual
+ Sector*/
+ uint16 Fee_au16BlockOffset[TI_FEE_TOTAL_BLOCKS_DATASETS]; /* Array to store within the VS */
+ uint32 Fee_au32BlockHeader[TI_FEE_BLOCK_OVERHEAD >> 2U]; /* Array to store the Block Header value */
+ uint8 Fee_au8BlockCopyStatus[TI_FEE_TOTAL_BLOCKS_DATASETS]; /* Array to storeblock copy status */
+ uint8 Fee_u8InternalVirtualSectorStart; /* Indicates internal VS start index */
+ uint8 Fee_u8InternalVirtualSectorEnd; /* Indicates internal VS end index */
+ TI_FeeModuleStatusType Fee_ModuleState; /* Indicates the state of the FEE module */
+ TI_FeeJobResultType Fee_u16JobResult; /* Stores the Job Result of the current command */
+ TI_Fee_StatusType Fee_oStatus; /* Indicates the status of FEE */
+ TI_Fee_ErrorCodeType Fee_Error; /* Indicates the Error code */
+ uint16 Fee_u16CopyBlockNumber; /* Block number which is currently being copied */
+ uint16 Fee_u16BlockIndex; /* Index of the Current Block */
+ uint16 Fee_u16BlockCopyIndex; /* Index of the Block being copied from Copy to Active VS */
+ uint16 Fee_u16DataSetIndex; /* Index of the Current DataSet */
+ uint16 Fee_u16ArrayIndex; /* Index of the Current DataSet */
+ uint16 Fee_u16BlockSize; /* Size of the current block in bytes */
+ uint16 Fee_u16BlockSizeinBlockHeader; /* Size of the current block. Used to write into Block Header */
+ uint16 Fee_u16BlockNumberinBlockHeader; /* Number of the current block. Used to write into Block Header */
+ uint8 Fee_u8ActiveVirtualSector; /* Indicates the FeeVirtualSectorNumber for the Active VS */
+ uint8 Fee_u8CopyVirtualSector; /* Indicates the FeeVirtualSectorNumber for the Copy VS */
+ uint32 Fee_u32InternalEraseQueue; /* Indicates which VS can be erased when the FEE is in
+ BusyInternal State*/
+ uint8 Fee_u8WriteCopyVSHeader; /* Indicates the number of bytes of the Copy VS Header being
+ written */
+ uint8 Fee_u8WriteCount; /* Indicates the number of bytes of the Block Header being
+ written */
+ uint8 * Fee_pu8ReadDataBuffer; /* Pointer to read data */
+ uint8 * Fee_pu8ReadAddress; /* Pointer to read address */
+ uint8 * Fee_pu8Data; /* Pointer to the next data to be written to the VS */
+ uint8 * Fee_pu8CopyData; /* Pointer to the next data to be copied to the VS */
+ uint8 * Fee_pu8DataStart; /* Pointer to the first data to be written to the VS */
+ boolean Fee_bInvalidWriteBit; /* Indicates whether the block is written/invalidated/erased
+ for the first time */
+ boolean Fee_bWriteData; /* Indicates that there is data which is pending to be written
+ to the Block */
+ boolean Fee_bWriteBlockHeader; /* Indicates whether the Block Header has been written or not */
+ boolean bWriteFirstTime; /* Indicates if the block is being written first time */
+ boolean Fee_bFindNextVirtualSector; /* Indicates if there is aneed to find next free VS */
+ boolean Fee_bWriteVSHeader; /* Indicates if block header needs to be written */
+ boolean Fee_bWriteStartProgram; /* Indicates if start program block header needs to be written */
+ boolean Fee_bWritePartialBlockHeader; /* Indicates if start program block header needs to be written */
+ #if (TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U)
+ uint16 Fee_au16UnConfiguredBlockAddress[TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY]; /* Indicates
+ number of unconfigured blocks to copy */
+ uint8 Fee_au8UnConfiguredBlockCopyStatus[TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY]; /* Array to store block
+ copy status */
+ #endif
+}TI_Fee_GlobalVarsType;
+
+/**********************************************************************************************************************
+ * EXTERN Declarations
+ *********************************************************************************************************************/
+/* Fee Global Variables */
+extern const Fee_BlockConfigType Fee_BlockConfiguration[TI_FEE_NUMBER_OF_BLOCKS];
+#if (TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_OFF)
+extern const Fee_VirtualSectorConfigType Fee_VirtualSectorConfiguration[TI_FEE_NUMBER_OF_VIRTUAL_SECTORS];
+extern const Device_FlashType Device_FlashDevice;
+#endif
+#if (TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON)
+extern Fee_VirtualSectorConfigType Fee_VirtualSectorConfiguration[TI_FEE_NUMBER_OF_VIRTUAL_SECTORS];
+extern Device_FlashType Device_FlashDevice;
+extern uint8 TI_Fee_MaxSectors;
+#endif
+extern TI_Fee_GlobalVarsType TI_Fee_GlobalVariables[TI_FEE_NUMBER_OF_EEPS];
+extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord[TI_FEE_NUMBER_OF_EEPS];
+#if(TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON)
+extern uint32 TI_Fee_u32FletcherChecksum;
+#endif
+extern uint32 TI_Fee_u32BlockEraseCount;
+extern uint8 TI_Fee_u8DataSets;
+extern uint8 TI_Fee_u8DeviceIndex;
+extern uint32 TI_Fee_u32ActCpyVS;
+extern uint8 TI_Fee_u8ErrEraseVS;
+#if (TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U)
+extern uint16 TI_Fee_u16NumberOfUnconfiguredBlocks[TI_FEE_NUMBER_OF_EEPS];
+#endif
+#if(TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix)
+extern boolean Fee_bDoubleBitError;
+extern boolean Fee_bSingleBitError;
+#endif
+#if(TI_FEE_NUMBER_OF_EEPS==2U)
+extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord_Global;
+#endif
+extern boolean TI_Fee_FapiInitCalled;
+extern boolean TI_Fee_bEraseSuspended;
+extern boolean TI_Fee_bIsMainFunctionCalled;
+
+
+/**********************************************************************************************************************
+ * GLOBAL FUNCTION PROTOTYPES
+ *********************************************************************************************************************/
+/* Interface Functions */
+extern void TI_Fee_Cancel(uint8 u8EEPIndex);
+extern Std_ReturnType TI_Fee_EraseImmediateBlock(uint16 BlockNumber);
+extern TI_FeeModuleStatusType TI_Fee_GetStatus(uint8 u8EEPIndex);
+extern void TI_Fee_GetVersionInfo(Std_VersionInfoType* VersionInfoPtr);
+extern void TI_Fee_Init(void);
+extern Std_ReturnType TI_Fee_InvalidateBlock(uint16 BlockNumber);
+extern Std_ReturnType TI_Fee_Read(uint16 BlockNumber,
+ uint16 BlockOffset,
+ uint8* DataBufferPtr,
+ uint16 Length);
+extern Std_ReturnType TI_Fee_WriteAsync(uint16 BlockNumber, uint8* DataBufferPtr);
+extern void TI_Fee_MainFunction(void);
+extern TI_Fee_ErrorCodeType TI_FeeErrorCode(uint8 u8EEPIndex);
+extern void TI_Fee_ErrorRecovery(TI_Fee_ErrorCodeType ErrorCode, uint8 u8VirtualSector);
+extern TI_FeeJobResultType TI_Fee_GetJobResult(uint8 u8EEPIndex);
+extern void TI_Fee_SuspendResumeErase(TI_Fee_EraseCommandType Command);
+
+#if(TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix)
+extern void TI_Fee_ErrorHookSingleBitError(void);
+extern void TI_Fee_ErrorHookDoubleBitError(void);
+#endif
+
+#if(TI_FEE_DRIVER == 1U)
+extern Std_ReturnType TI_Fee_WriteSync(uint16 BlockNumber, uint8* DataBufferPtr);
+extern Std_ReturnType TI_Fee_Shutdown(void);
+extern boolean TI_Fee_Format(uint32 u32FormatKey);
+extern Std_ReturnType TI_Fee_ReadSync(uint16 BlockNumber,uint16 BlockOffset,uint8* DataBufferPtr,uint16 Length);
+#endif
+
+/* TI Fee Internal Functions */
+TI_Fee_AddressType TI_FeeInternal_GetNextFlashAddress(uint8 u8EEPIndex);
+TI_Fee_AddressType TI_FeeInternal_AlignAddressForECC(TI_Fee_AddressType oAddress);
+TI_Fee_AddressType TI_FeeInternal_GetCurrentBlockAddress(uint16 BlockNumber,uint16 DataSetNumber, uint8 u8EEPIndex);
+/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - TI_FeeInternal_GetVirtualSectorParameter name is required here."*/
+uint32 TI_FeeInternal_GetVirtualSectorParameter(Fapi_FlashSectorType oSector, uint16 u16Bank, boolean VirtualSectorInfo,
+ uint8 u8EEPIndex);
+uint32 TI_FeeInternal_PollFlashStatus(void);
+uint16 TI_FeeInternal_GetBlockSize(uint16 BlockIndex);
+uint16 TI_FeeInternal_GetBlockIndex(uint16 BlockNumber);
+uint16 TI_FeeInternal_GetDataSetIndex(uint16 BlockNumber);
+uint16 TI_FeeInternal_GetBlockNumber(uint16 BlockNumber);
+uint8 TI_FeeInternal_FindNextVirtualSector(uint8 u8EEPIndex);
+uint8 TI_FeeInternal_WriteDataF021(boolean bCopy,uint16 u16WriteSize, uint8 u8EEPIndex);
+boolean TI_FeeInternal_BlankCheck(uint32 u32StartAddress, uint32 u32EndAddress, uint16 u16Bank, uint8 u8EEPIndex);
+Std_ReturnType TI_FeeInternal_CheckReadParameters(uint32 u32BlockSize,uint16 BlockOffset, const uint8* DataBufferPtr,
+ uint16 Length, uint8 u8EEPIndex);
+Std_ReturnType TI_FeeInternal_CheckModuleState(uint8 u8EEPIndex);
+Std_ReturnType TI_FeeInternal_InvalidateErase(uint16 BlockNumber);
+TI_Fee_StatusType TI_FeeInternal_FeeManager(uint8 u8EEPIndex);
+void TI_FeeInternal_WriteVirtualSectorHeader(uint8 FeeVirtualSectorNumber, VirtualSectorStatesType VsState,
+ uint8 u8EEPIndex) ;
+/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - TI_FeeInternal_GetVirtualSectorIndex name is required here."*/
+void TI_FeeInternal_GetVirtualSectorIndex(Fapi_FlashSectorType oSectorStart, Fapi_FlashSectorType oSectorEnd,
+ uint16 u16Bank, boolean bOperation, uint8 u8EEPIndex);
+void TI_FeeInternal_WritePreviousBlockHeader(boolean bWrite, uint8 u8EEPIndex);
+void TI_FeeInternal_WriteBlockHeader(boolean bWrite, uint8 u8EEPIndex,uint16 Fee_BlockSize_u16,uint16 u16BlockNumber);
+void TI_FeeInternal_SetClearCopyBlockState(uint8 u8EEPIndex, boolean bSetClear);
+void TI_FeeInternal_SanityCheck(uint16 BlockSize, uint8 u8EEPIndex);
+void TI_FeeInternal_StartProgramBlock(uint8 u8EEPIndex);
+void TI_FeeInternal_UpdateBlockOffsetArray(uint8 u8EEPIndex, boolean bActCpyVS,uint8 u8VirtualSector);
+void TI_FeeInternal_WriteInitialize(TI_Fee_AddressType oFlashNextAddress, uint8* DataBufferPtr, uint8 u8EEPIndex);
+void TI_FeeInternal_CheckForError(uint8 u8EEPIndex);
+void TI_FeeInternal_EnableRequiredFlashSector(uint32 u32VirtualSectorStartAddress);
+uint16 TI_FeeInternal_GetArrayIndex(uint16 BlockNumber, uint16 DataSetNumber, uint8 u8EEPIndex, boolean bCallContext);
+#if(TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON)
+uint32 TI_FeeInternal_Fletcher16( uint8 const *pu8data, uint16 u16Length);
+#endif
+#if (TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON)
+void TI_FeeInternal_PopulateStructures(TI_Fee_DeviceType DeviceType);
+#endif
+#endif /* TI_FEE_H */
+/**********************************************************************************************************************
+ * END OF FILE: ti_fee.h
+ *********************************************************************************************************************/
+
+
Index: firmware/include/ti_fee_cfg.h
===================================================================
diff -u
--- firmware/include/ti_fee_cfg.h (revision 0)
+++ firmware/include/ti_fee_cfg.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,55 @@
+/**********************************************************************************************************************
+ * FILE DESCRIPTION
+ * -------------------------------------------------------------------------------------------------------------------
+ * File: ti_fee_cfg.h
+ * Project: Tms570_TIFEEDriver
+ * Module: TIFEEDriver
+ * Generator: HALCoGen
+ *
+ * Description: This file implements the TI FEE Api.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author: Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version Date Author Change ID Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 00.00.01 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version
+ * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version history.
+ *
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
Index: firmware/include/ti_fee_types.h
===================================================================
diff -u
--- firmware/include/ti_fee_types.h (revision 0)
+++ firmware/include/ti_fee_types.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,203 @@
+/**********************************************************************************************************************
+ * FILE DESCRIPTION
+ * -------------------------------------------------------------------------------------------------------------------
+ * File: ti_fee_types.h
+ * Project: Tms570_TIFEEDriver
+ * Module: TIFEEDriver
+ * Generator: None
+ *
+ * Description: This file implements the TI FEE Api.
+ *---------------------------------------------------------------------------------------------------------------------
+ * Author: Vishwanath Reddy
+ *---------------------------------------------------------------------------------------------------------------------
+ * Revision History
+ *---------------------------------------------------------------------------------------------------------------------
+ * Version Date Author Change ID Description
+ *---------------------------------------------------------------------------------------------------------------------
+ * 03.00.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version
+ * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version
+ * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory segmentation changes.
+ * 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 MISRA C fixes.
+ * 01.15.00 06Jun2014 Vishwanath Reddy Support for LC Varients.
+ * 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove MISRA warnings.
+ * 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version history.
+ * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version history.
+ * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version history.
+ * 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update version history.
+ * SDOCM00122429 Added error when endianess is not defined.
+ * 01.19.00 08Augu2016 Vishwanath Reddy SDOCM00122592 Update version history.
+ * 01.19.01 12Augu2016 Vishwanath Reddy SDOCM00122543 Update version history.
+ * 01.19.03 15May2017 Prathap Srinivasan SDOCM00122917 Update version history.
+ * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version history.
+ *********************************************************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef TI_FEE_TYPES_H
+#define TI_FEE_TYPES_H
+
+/**********************************************************************************************************************
+ * INCLUDES
+ *********************************************************************************************************************/
+#include "Device_header.h"
+
+#ifndef TI_Fee_None
+#define TI_Fee_None 0x00U /*Take no action on single bit errors, (respond with corrected data), */
+ /*return error for uncorrectable error reads (multibit errors for ECC or parity failures)*/
+ /*For devices with no ECC (they may have parity or not) the only valid option is none. */
+#endif
+
+#ifndef TI_Fee_Fix
+#define TI_Fee_Fix 0x01U /* single bit error will be fixed by reprogramming */
+ /* return previous valid data for uncorrectable error reads (multi bit errors for ECC
+ or parity failures). */
+#endif
+
+#if !defined(_LITTLE_ENDIAN) && !defined(_BIG_ENDIAN)
+#error "Target Endianess is not defined. Include F021 header files and library."
+#endif
+
+/*SAFETYMCUSW 74 S MR:18.4 "Reason - union declaration is necessary here."*/
+typedef union
+{
+ uint16 Fee_u16StatusWord;
+ #ifdef _BIG_ENDIAN
+ struct
+ {
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Reserved: 5U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Erase:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 ReadSync:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 ProgramFailed:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Read:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 WriteSync:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 WriteAsync:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 EraseImmediate:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 InvalidateBlock:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Copy:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Initialized:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 SingleBitError:1U;
+ }Fee_StatusWordType_ST;
+ #endif
+ #ifdef _LITTLE_ENDIAN
+ struct
+ {
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 SingleBitError:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Initialized:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Copy:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 InvalidateBlock:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 EraseImmediate:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 WriteAsync:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 WriteSync:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Read:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 ProgramFailed:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 ReadSync:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Erase:1U;
+ /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary here."*/
+ /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as unsigned."*/
+ uint16 Reserved: 5U;
+ }Fee_StatusWordType_ST;
+ #endif
+}TI_Fee_StatusWordType_UN;
+
+typedef enum
+{
+ UNINIT,
+ IDLE,
+ /*SAFETYMCUSW 91 S MR:5.2,5.6,5.7 "Reason - BUSY in F021 is a member of structure."*/
+ BUSY,
+ BUSY_INTERNAL
+}TI_FeeModuleStatusType;
+
+typedef enum
+{
+ JOB_OK,
+ JOB_FAILED,
+ JOB_PENDING,
+ JOB_CANCELLED,
+ BLOCK_INCONSISTENT,
+ BLOCK_INVALID
+}TI_FeeJobResultType;
+
+#endif /* TI_FEE_TYPES_H */
+
+/**********************************************************************************************************************
+ * END OF FILE: ti_fee_types.h
+ *********************************************************************************************************************/
Index: firmware/include/usb-ids.h
===================================================================
diff -u
--- firmware/include/usb-ids.h (revision 0)
+++ firmware/include/usb-ids.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,71 @@
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ * @file usb-ids.h
+ *
+ * @brief Definitions of VIDs and PIDs used by Stellaris USB examples.
+ *
+ */
+
+#ifndef __USBIDS_H__
+#define __USBIDS_H__
+
+/** ***************************************************************************
+ *
+ * TI Vendor ID.
+ *
+ *****************************************************************************/
+#define USB_VID_TI 0x0000
+
+/** ***************************************************************************
+ *
+ * Product IDs.
+ *
+ *****************************************************************************/
+#define USB_PID_MOUSE 0x0000
+#define USB_PID_KEYBOARD 0x0001
+#define USB_PID_SERIAL 0x0000
+#define USB_PID_BULK 0x0003
+#define USB_PID_SCOPE 0x0004
+#define USB_PID_MSC 0x0005
+#define USB_PID_AUDIO 0x0006
+#define USB_PID_COMP_SERIAL 0x0007
+#define USB_PID_COMP_AUDIO_HID 0x0008
+#define USB_PID_COMP_HID_SER 0x0009
+#define USB_PID_DFU 0x00FF
+
+
+#endif /* __USBIDS_H__ */
Index: firmware/include/usb.h
===================================================================
diff -u
--- firmware/include/usb.h (revision 0)
+++ firmware/include/usb.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,694 @@
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef USB_H_
+#define USB_H_
+
+/******************************************************************************
+ *
+ * These macros allow conversion between 0-based endpoint indices and the
+ * USB_EP_x values required when calling various USB APIs.
+ *
+ *****************************************************************************/
+#define INDEX_TO_USB_EP(x) ((x) << 4u)
+#define USB_EP_TO_INDEX(x) ((x) >> 4u)
+
+/******************************************************************************
+ *
+ * The following are values that can be passed to USBFIFOConfigSet() as the
+ * uFIFOSize parameter.
+ *
+ *****************************************************************************/
+#define USB_FIFO_SZ_8 0x00U /* 8 byte FIFO */
+#define USB_FIFO_SZ_16 0x01U /* 16 byte FIFO */
+#define USB_FIFO_SZ_32 0x02U /* 32 byte FIFO */
+#define USB_FIFO_SZ_64 0x03U /* 64 byte FIFO */
+#define USB_FIFO_SZ_128 0x04U /* 128 byte FIFO */
+#define USB_FIFO_SZ_256 0x05U /* 256 byte FIFO */
+#define USB_FIFO_SZ_512 0x06U /* 512 byte FIFO */
+#define USB_FIFO_SZ_1024 0x07U /* 1024 byte FIFO */
+
+
+/******************************************************************************
+ *
+ * This macro allow conversion from a FIFO size label as defined above to
+ * a number of bytes
+ *
+ *****************************************************************************/
+#define USB_FIFO_SIZE_DB_FLAG 0x10U
+#define USB_FIFO_SZ_TO_BYTES(x) (uint16_t)((uint8_t)8U << (((uint8_t)(x) & (uint8_t)(~(uint8_t)USB_FIFO_SIZE_DB_FLAG)) + \
+ (uint8_t)(((uint8_t)(x) & (uint8_t)USB_FIFO_SIZE_DB_FLAG) >> 4U)))
+
+
+/******************************************************************************
+ *
+ * The maximum number of independent interfaces that any single device
+ * implementation can support. Independent interfaces means interface
+ * descriptors with different bInterfaceNumber values - several interface
+ * descriptors offering different alternative settings but the same interface
+ * number count as a single interface.
+ *
+ *****************************************************************************/
+#define USB_MAX_INTERFACES_PER_DEVICE 8u
+
+
+/******************************************************************************
+ *
+ * Following macro directives can be used for the configuring the USB device.
+ * Note that these directives map directly to the hardware bit definitions and
+ * cannot be modified to any other value.
+ *
+ *****************************************************************************/
+#define USBD_PWR_BUS_PWR (0x0000u) /* Device is bus powered */
+#define USBD_PWR_SELF_PWR (0x0004u) /* Device is self powered */
+#define USBD_DATA_ENDIAN_LITTLE (0x0000u) /* Little Endian Data (RM48x) */
+#define USBD_DATA_ENDIAN_BIG (0x0080u) /* Bit Endian Data */
+#define USBD_DMA_ENDIAN_LITTLE (0x0000u) /* DMA is Little Endian */
+#define USBD_DMA_ENDIAN_BIG (0x0040u) /* DMA is Big Endian */
+
+/******************************************************************************
+ *
+ * Following macro directives can be used for the configuring the Endpoints
+ * Note that these directives map directly to the hardware bit definitions and
+ * cannot be modified to any other value.
+ *
+ *****************************************************************************/
+
+#define USBD_EP_DIR_IN (0x0010u) /* IN Endpoint */
+#define USBD_EP_DIR_OUT (0x0000u) /* OUT Endpoint */
+#define USB_EP_DEV_IN (USBD_EP_DIR_IN) /* IN Endpoint */
+#define USB_EP_DEV_OUT (USBD_EP_DIR_OUT)/* OUT Endpoint */
+#define USB_TRANS_IN (USBD_EP_DIR_IN) /* IN Endpoint */
+#define USB_TRANS_OUT (USBD_EP_DIR_OUT)/* OUT Endpoint */
+#define USB_EP_DIR_IN (USBD_EP_DIR_IN)
+#define USB_EP_DIR_OUT (USBD_EP_DIR_OUT)
+#define USB_TRANS_IN_LAST 0u /* Used to indicate the last transaction
+ (NOT USED in this port of USB) */
+
+#define USBD_TXRX_EP_VALID_VALID (0x8000u) /* EP is valid & configured */
+#define USBD_TXRX_EP_VALID_NOTVALID (0x0000u) /* EP is not valid & not configured */
+#define USBD_TXRX_EP_ISO_ISO (0x0800u) /* EP is of ISO type */
+#define USBD_TXRX_EP_ISO_NONISO (0x0000u) /* EP is either Bulk/Interrup/Control */
+#define USBD_TXRX_EP_DB_ENABLED (0x4000u) /* EP has double buffering enabled */
+ /* For IN EPs DB should be enabled only in DMA mode */
+#define USBD_TXRX_EP_DB_DISABLED (0x0000u) /* EP has double buffering disabled */
+
+/******************************************************************************
+ *
+ * Following macro directives are to be used for enabling/disabling interrupts
+ * Note that these directives map directly to the hardware bit definitions and
+ * cannot be modified to any other value.
+ *
+ *****************************************************************************/
+#define USBD_INT_EN_SOF_IE (0x0080u) /* Start-of-Frame Interrupt */
+#define USBD_INT_EN_EPN_RX_IE (0x0020u) /* Non-EP0 RX Interrupt */
+#define USBD_INT_EN_EPN_TX_IE (0x0010u) /* Non-EP0 TX Interrupt */
+#define USBD_INT_EN_DS_CHG_IE (0x0008u) /* Device State change interrupt */
+#define USBD_INT_EN_EP0_IE (0x0001u) /* EP0 Interrupt */
+#define USBD_INT_EN_ALL (USBD_IRQ_EN_SOF_IE | \
+ USBD_IRQ_EN_EPN_RX_IE | \
+ USBD_IRQ_EN_EPN_TX_IE | \
+ USBD_IRQ_EN_DS_CHG_IE | \
+ USBD_IRQ_EN_EP0_IE)
+
+
+/******************************************************************************
+ *
+ * Following macro directives are to be used for decoding the interrupt source
+ * Note that these directives map directly to the hardware bit definitions and
+ * cannot be modified to any other value.
+ *
+ *****************************************************************************/
+#define USBD_INT_SRC_TXN_DONE (0x0400u) /* non-EP0 TX done interrupt */
+#define USBD_INT_SRC_RXN_CNT (0x0200u) /* non-EP0 RX Count */
+#define USBD_INT_SRC_RXN_EOT (0x0100u) /* non-EP0 RX end of transfer */
+#define USBD_INT_SRC_SOF (0x0080u) /* Start-of-frame interrupt */
+#define USBD_INT_SRC_EPN_RX (0x0020u) /* non-EP0 RX interrupt */
+#define USBD_INT_SRC_EPN_TX (0x0010u) /* non-EP0 TX interrupt */
+#define USBD_INT_SRC_DS_CHG (0x0008u) /* Device State change interrupt */
+#define USBD_INT_SRC_SETUP (0x0004u) /* Setup interrupt */
+#define USBD_INT_SRC_EP0_RX (0x0002u) /* EP0 RX Interrupt */
+#define USBD_INT_SRC_EP0_TX (0x0001u) /* EP0 TX Interrupt */
+
+
+/******************************************************************************
+ *
+ * These values are used to indicate which endpoint to access.
+ *
+ *****************************************************************************/
+#define USB_EP_0 0x00000000u /* Endpoint 0 */
+#define USB_EP_1 0x00000010u /* Endpoint 1 */
+#define USB_EP_2 0x00000020u /* Endpoint 2 */
+#define USB_EP_3 0x00000030u /* Endpoint 3 */
+#define USB_EP_4 0x00000040u /* Endpoint 4 */
+#define USB_EP_5 0x00000050u /* Endpoint 5 */
+#define USB_EP_6 0x00000060u /* Endpoint 6 */
+#define USB_EP_7 0x00000070u /* Endpoint 7 */
+#define USB_EP_8 0x00000080u /* Endpoint 8 */
+#define USB_EP_9 0x00000090u /* Endpoint 9 */
+#define USB_EP_10 0x000000A0u /* Endpoint 10 */
+#define USB_EP_11 0x000000B0u /* Endpoint 11 */
+#define USB_EP_12 0x000000C0u /* Endpoint 12 */
+#define USB_EP_13 0x000000D0u /* Endpoint 13 */
+#define USB_EP_14 0x000000E0u /* Endpoint 14 */
+#define USB_EP_15 0x000000F0u /* Endpoint 15 */
+#define NUM_USB_EP 16u /* Number of supported endpoints */
+
+
+/******************************************************************************
+ *
+ * The following are values that can be passed to USBHostEndpointConfig() and
+ * USBDevEndpointConfigSet() as the ulFlags parameter.
+ *
+ *****************************************************************************/
+#define USB_EP_AUTO_SET 0x00000001u /* Auto set feature enabled */
+#define USB_EP_AUTO_REQUEST 0x00000002u /* Auto request feature enabled */
+#define USB_EP_AUTO_CLEAR 0x00000004u /* Auto clear feature enabled */
+#define USB_EP_DMA_MODE_0 0x00000008u /* Enable DMA access using mode 0 */
+#define USB_EP_DMA_MODE_1 0x00000010u /* Enable DMA access using mode 1 */
+#define USB_EP_MODE_ISOC 0x00000000u /* Isochronous endpoint */
+#define USB_EP_MODE_BULK 0x00000100u /* Bulk endpoint */
+#define USB_EP_MODE_INT 0x00000200u /* Interrupt endpoint */
+#define USB_EP_MODE_CTRL 0x00000300u /* Control endpoint */
+#define USB_EP_MODE_MASK 0x00000300u /* Mode Mask */
+#define USB_EP_SPEED_LOW 0x00000000u /* Low Speed */
+#define USB_EP_SPEED_FULL 0x00001000u /* Full Speed */
+
+
+/******************************************************************************
+ *
+ * The following are values that are returned from USBEndpointStatus(). The
+ * USB_HOST_* values are used when the USB controller is in host mode and the
+ * USB_DEV_* values are used when the USB controller is in device mode.
+ *
+ *****************************************************************************/
+#define USB_DEV_EP0_OUT_PKTRDY 0x00000001u /* Receive data packet ready */
+#define USB_DEV_RX_PKT_RDY 0x00010000u /* Data packet ready */
+#define USB_DEV_TX_TXPKTRDY 0x00000001u
+#define USB_DEV_TX_FIFO_NE 0x00000002u
+
+
+/******************************************************************************
+ *
+ * This value specifies the maximum size of transfers on endpoint 0 as 64
+ * bytes. This value is fixed in hardware as the FIFO size for endpoint 0.
+ *
+ *****************************************************************************/
+#define MAX_PACKET_SIZE_EP0 64u
+
+
+/******************************************************************************
+ *
+ * Macros for hardware access, both direct and via the bit-band region.
+ *
+ *****************************************************************************/
+#define HWREG(x) (*((volatile uint32_t *)(x)))
+
+
+
+
+/******************************************************************************
+ *
+ * Initialize the USB Device
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usFlags specifies the bus/self powered and endianness for data & dma.
+ * Should be a combination of the following flags
+ * USBD_PWR_BUS_PWR or USBD_PWR_SELF_PWR
+ * USBD_DATA_ENDIAN_LITTLE or USBD_DATA_ENDIAN_BIG
+ * USBD_DMA_ENDIAN_LITTLE or USBD_DMA_ENDIAN_BIG
+ * \param usFifoPtr specifies the start of the EP0 FIFO.
+ *
+ * This function will initialize the USB Device controller specified by the
+ * \e ulBase parameter.
+ *
+ * \return None
+ *
+ * Note This function does not intiate a device connect (pull ups are
+ * not enabled). Also the EP0 is intialized with FIFO size of 64Bytes.
+ *
+ *
+ *****************************************************************************/
+void USBDevInit(uint32 ulBase, uint16 usFlags, uint16 usFifoPtr);
+
+
+/******************************************************************************
+ *
+ * Initialize the USB Device's EP0
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usSize FIFO size. Supported values are USB_FIFO_SZ_8/USB_FIFO_SZ_16/
+ * USB_FIFO_SZ_32/USB_FIFO_SZ_64.
+ * \param usFifoPtr specifies the start of the EP0 FIFO.
+ *
+ * This function will initialize the USB Device controller specified by the
+ * \e ulBase parameter. The \e uFlags parameter is not used by this
+ * implementation.
+ *
+ * \return None
+ *
+ *
+ *****************************************************************************/
+void USBDevEp0Config(uint32 ulBase, uint16 usSize, uint16 usFifoPtr);
+
+
+/******************************************************************************
+ *
+ * Disable control interrupts on a given USB device controller.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usFlags specifies which control interrupts to disable.
+ *
+ * This function will disable the interrupts for the USB device controller
+ * specified by the \e ulBase parameter. The \e usFlags parameter specifies
+ * which control interrupts to disable. The flags passed in the \e usFlags
+ * parameters should be the definitions that start with \b USBD_INT_EN_*
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBIntDisable(uint32 ulBase, uint16 usFlags);
+
+
+/******************************************************************************
+ *
+ * Enable control interrupts on a given USB device controller.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usFlags specifies which control interrupts to enable.
+ *
+ * This function will enable the control interrupts for the USB device controller
+ * specified by the \e ulBase parameter. The \e usFlags parameter specifies
+ * which control interrupts to enable. The flags passed in the \e usFlags
+ * parameters should be the definitions that start with \b USBD_INT_EN_* and
+ * not any other \b USB_INT flags.
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBIntEnable(uint32 ulBase, uint16 usFlags);
+
+
+/******************************************************************************
+ *
+ * Returns the control interrupt status on a given USB device controller.
+ *
+ * \param ulBase specifies the USB module base address.
+ *
+ * This function will read interrupt status for a USB device controller.
+ * The bit values returned should be compared against the \b USBD_INT_SRC_*
+ * values.
+ *
+ * \return Returns the status of the control interrupts for a USB device controller.
+ *
+ *****************************************************************************/
+uint16 USBIntStatus(uint32 ulBase);
+
+
+/******************************************************************************
+ *
+ * Stalls the specified endpoint in device mode.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint specifies the endpoint to stall.
+ * \param usFlags specifies whether to stall the IN or OUT endpoint.
+ *
+ * This function will cause to endpoint number passed in to go into a stall
+ * condition. If the \e usFlags parameter is \b USB_EP_DEV_IN then the stall
+ * will be issued on the IN portion of this endpoint. If the \e usFlags
+ * parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT
+ * portion of this endpoint.
+ *
+ * \note This function should only be called in device mode.
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointStall(uint32 ulBase, uint16 usEndpoint, uint16 usFlags);
+
+
+/******************************************************************************
+ *
+ * Clears the stall condition on the specified endpoint in device mode.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint specifies which endpoint to remove the stall condition.
+ * \param usFlags specifies whether to remove the stall condition from the IN
+ * or the OUT portion of this endpoint.
+ *
+ * This function will cause the endpoint number passed in to exit the stall
+ * condition. If the \e usFlags parameter is \b USB_EP_DEV_IN then the stall
+ * will be cleared on the IN portion of this endpoint. If the \e usFlags
+ * parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT
+ * portion of this endpoint.
+ *
+ * \note This function should only be called in device mode.
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointStallClear(uint32 ulBase, uint16 usEndpoint, uint16 usFlags);
+
+
+/******************************************************************************
+ *
+ * Connects the USB device controller to the bus in device mode.
+ *
+ * \param ulBase specifies the USB module base address.
+ *
+ * This function will cause the soft connect feature of the USB device controller to
+ * be enabled. Call USBDisconnect() to remove the USB device from the bus.
+ *
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevConnect(uint32 ulBase);
+
+
+/******************************************************************************
+ *
+ * Removes the USB device controller from the bus in device mode.
+ *
+ * \param ulBase specifies the USB module base address.
+ *
+ * This function will cause the soft disconnect feature of the USB device controller to
+ * remove the device from the USB bus. A call to USBDevConnect() is needed to
+ * reconnect to the bus.
+ *
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevDisconnect(uint32 ulBase);
+
+
+/******************************************************************************
+ *
+ * Sets the address in device mode.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param ulAddress is the address to use for a device.
+ *
+ * This function will set the device address on the USB bus. This address was
+ * likely received via a SET ADDRESS command from the host controller.
+ *
+ * \note This function is not available on this controller. This is maintained
+ * for compatibility.
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevAddrSet(uint32 ulBase, uint32 ulAddress);
+
+
+/******************************************************************************
+ *
+ * Determine the number of bytes of data available in a given endpoint's FIFO.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint is the endpoint to access.
+ *
+ * This function will return the number of bytes of data currently available
+ * in the FIFO for the given receive (OUT) endpoint. It may be used prior to
+ * calling USBEndpointDataGet() to determine the size of buffer required to
+ * hold the newly-received packet.
+ *
+ * \return This call will return the number of bytes available in a given
+ * endpoint FIFO.
+ *
+ *****************************************************************************/
+uint16 USBEndpointDataAvail(uint32 ulBase, uint16 usEndpoint);
+
+
+/******************************************************************************
+ *
+ * Retrieves data from the given endpoint's FIFO.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint is the endpoint to access.
+ * \param pucData is a pointer to the data area used to return the data from
+ * the FIFO.
+ * \param pulSize is initially the size of the buffer passed into this call
+ * via the \e pucData parameter. It will be set to the amount of data
+ * returned in the buffer.
+ *
+ * This function will return the data from the FIFO for the given endpoint.
+ * The \e pulSize parameter should indicate the size of the buffer passed in
+ * the \e pulData parameter. The data in the \e pulSize parameter will be
+ * changed to match the amount of data returned in the \e pucData parameter.
+ * If a zero byte packet was received this call will not return a error but
+ * will instead just return a zero in the \e pulSize parameter. The only
+ * error case occurs when there is no data packet available.
+ *
+ * \return This call will return 0, or -1 if no packet was received.
+ *
+ *****************************************************************************/
+sint32 USBEndpointDataGet(
+ uint32 ulBase,
+ uint16 usEndpoint,
+ uint8 * pucData,
+ uint32 * pulSize);
+
+
+/******************************************************************************
+ *
+ * Retrieves the setup packet from EP0 Setup FIFO
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param sPkt Pointer to the data area for storing the setup packet.
+ * Atleast 8 bytes should be available.
+ * \param pusPktSize On return this contains the size of the setup packet (8Bytes)
+ *
+ * This function will retrieves the 8Byte long setup packet from the EP0 setup
+ * FIFO.
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevGetSetupPacket (uint32 ulBase, uint8 * sPkt, uint16 * pusPktSize);
+
+
+/******************************************************************************
+ *
+ * Acknowledge that data was read from the given endpoint's FIFO in device
+ * mode.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint is the endpoint to access.
+ * \param bIsLastPacket This parameter is not used.
+ *
+ * This function acknowledges that the data was read from the endpoint's FIFO.
+ * The \e bIsLastPacket parameter is set to a \b true value if this is the
+ * last in a series of data packets on endpoint zero. The \e bIsLastPacket
+ * parameter is not used for endpoints other than endpoint zero. This call
+ * can be used if processing is required between reading the data and
+ * acknowledging that the data has been read.
+ *
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointDataAck(uint32 ulBase, uint16 usEndpoint, tBoolean bIsLastPacket);
+
+
+/******************************************************************************
+ *
+ * Puts data into the given endpoint's FIFO.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint is the endpoint to access.
+ * \param pucData is a pointer to the data area used as the source for the
+ * data to put into the FIFO.
+ * \param ulSize is the amount of data to put into the FIFO.
+ *
+ * This function will put the data from the \e pucData parameter into the FIFO
+ * for this endpoint. If a packet is already pending for transmission then
+ * this call will not put any of the data into the FIFO and will return -1.
+ * Care should be taken to not write more data than can fit into the FIFO
+ * allocated by the call to USBFIFOConfig().
+ *
+ * \return This call will return 0 on success, or -1 to indicate that the FIFO
+ * is in use and cannot be written.
+ *
+ *****************************************************************************/
+uint32 USBEndpointDataPut(
+ uint32 ulBase,
+ uint16 usEndpoint,
+ uint8 * pucData,
+ uint32 ulSize);
+
+/******************************************************************************
+ *
+ * Starts the transfer of data from an endpoint's FIFO.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint is the endpoint to access.
+ * \param ulTransType Not used.
+ *
+ * This function will start the transfer of data from the FIFO for a given
+ * endpoint.
+ *
+ * \return This call will return 0 on success, or -1 if a transmission is
+ * already in progress.
+ *
+ *****************************************************************************/
+uint32 USBEndpointDataSend(uint32 ulBase, uint16 usEndpoint, uint32 ulTransType);
+
+
+/******************************************************************************
+ *
+ * Resets the USB Device Controller
+ *
+ * \param void
+ *
+ * \return None.
+ *
+ * \note Since the USB Device reset is handled by the host, this is a dummy
+ * function & maintained for compatibility purpose.
+ *
+ *****************************************************************************/
+void USBReset(void);
+
+
+/******************************************************************************
+ *
+ * Sets the FIFO configuration for an endpoint.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint is the endpoint to access.
+ * \param uFIFOAddress is the starting address for the FIFO.
+ * \param uFIFOSize is the size of the FIFO in bytes.
+ * \param uFlags specifies what information to set in the FIFO configuration.
+ *
+ * This function will set the starting FIFO RAM address and size of the FIFO
+ * for a given endpoint. Endpoint zero does not have a dynamically
+ * configurable FIFO so this function should not be called for endpoint zero.
+ * The \e uFIFOSize parameter should be one of the values in the
+ * \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering
+ * it should use the values with the \b _DB at the end of the value. For
+ * example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16
+ * byte double buffered FIFO. If a double buffered FIFO is used, then the
+ * actual size of the FIFO will be twice the size indicated by the
+ * \e uFIFOSize parameter. This means that the \b USB_FIFO_SZ_16_DB value
+ * will use 32 bytes of the USB controller's FIFO memory.
+ *
+ * The \e uFIFOAddress value should be a multiple of 8 bytes and directly
+ * indicates the starting address in the USB controller's FIFO RAM. For
+ * example, a value of 64 indicates that the FIFO should start 64 bytes into
+ * the USB controller's FIFO memory. The \e uFlags value specifies whether
+ * the endpoint's OUT or IN FIFO should be configured. If in host mode, use
+ * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use
+ * \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN.
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBFIFOConfigSet(uint32 ulBase, uint32 usEndpoint, uint32 uFIFOAddress, uint32 uFIFOSize, uint16 uFlags);
+
+
+/******************************************************************************
+ *
+ * Gets the current configuration for an endpoint.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint is the endpoint to access.
+ * \param pulMaxPacketSize is a pointer which will be written with the
+ * maximum packet size for this endpoint.
+ * \param puFlags is a pointer which will be written with the current
+ * endpoint settings. On entry to the function, this pointer must contain
+ * either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or
+ * OUT endpoint is to be queried.
+ *
+ * This function will return the basic configuration for an endpoint in device
+ * mode. The values returned in \e *pulMaxPacketSize and \e *puFlags are
+ * equivalent to the \e ulMaxPacketSize and \e uFlags previously passed to
+ * USBDevEndpointConfigSet() for this endpoint.
+ *
+ * \note This function should only be called in device mode.
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointConfigGet(
+ uint32 ulBase,
+ uint16 usEndpoint,
+ uint32 * pulMaxPacketSize,
+ uint32 * puFlags);
+
+
+/******************************************************************************
+ *
+ * Sets the configuration for an endpoint.
+ *
+ * \param ulBase specifies the USB module base address.
+ * \param usEndpoint is the endpoint to access.
+ * \param ulMaxPacketSize is the maximum packet size for this endpoint.
+ * \param uFlags are used to configure other endpoint settings.
+ *
+ * This function will set the basic configuration for an endpoint in device
+ * mode. Endpoint zero does not have a dynamic configuration, so this
+ * function should not be called for endpoint zero. The \e uFlags parameter
+ * determines some of the configuration while the other parameters provide the
+ * rest.
+ *
+ * The \b USB_EP_MODE_ flags define what the type is for the given endpoint.
+ *
+ * - \b USB_EP_MODE_CTRL is a control endpoint.
+ * - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+ * - \b USB_EP_MODE_BULK is a bulk endpoint.
+ * - \b USB_EP_MODE_INT is an interrupt endpoint.
+ *
+ *
+ * \note This function should only be called in device mode.
+ *
+ * \return None.
+ *
+ *****************************************************************************/
+void USBDevEndpointConfigSet(uint32 ulBase, uint16 usEndpoint, uint32 ulMaxPacketSize, uint32 uFlags);
+
+void USBDevSetDevCfg(uint32 ulBase);
+void USBDevClearDevCfg(uint32 ulBase);
+uint16 USBDevGetEPnStat(uint32 ulBase);
+void USBDevPullEnableDisable(uint32 ulBase, uint32 ulSet);
+void USBIntStatusClear (uint16 uFlag);
+uint16 USBDevGetDevStat(uint32 ulBase);
+void USBDevCfgUnlock(uint32 ulBase);
+void USBDevCfgLock(uint32 ulBase);
+
+#endif /*USB_H_*/
+
+
+
+
Index: firmware/include/usb_serial_structs.h
===================================================================
diff -u
--- firmware/include/usb_serial_structs.h (revision 0)
+++ firmware/include/usb_serial_structs.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,74 @@
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ * @file usb_serial_structs.h
+ *
+ * @brief Data structures defining this USB CDC device.
+ *
+ */
+
+#ifndef _USB_SERIAL_STRUCTS_H_
+#define _USB_SERIAL_STRUCTS_H_
+
+/******************************************************************************
+ *
+ * The size of the transmit and receive buffers used for the redirected UART.
+ * This number should be a power of 2 for best performance. 256 is chosen
+ * pretty much at random though the buffer should be at least twice the size of
+ * a maxmum-sized USB packet.
+ *
+ *****************************************************************************/
+#define UART_BUFFER_SIZE 0x0001
+
+/** ***************************************************************************
+ *
+ * CDC device callback function prototypes.
+ *
+ *****************************************************************************/
+uint32 RxHandler(void *pvCBData, uint32 ulEvent,
+ uint32 ulMsgValue, void *pvMsgData);
+uint32 TxHandler(void *pvCBData, uint32 ulEvent,
+ uint32 ulMsgValue, void *pvMsgData);
+uint32 ControlHandler(void *pvCBData, uint32 ulEvent,
+ uint32 ulMsgValue, void *pvMsgData);
+
+extern const tUSBBuffer g_sTxBuffer;
+extern const tUSBBuffer g_sRxBuffer;
+extern const tUSBDCDCDevice g_sCDCDevice;
+extern uint8 g_pucUSBTxBuffer[];
+extern uint8 g_pucUSBRxBuffer[];
+
+#endif
Index: firmware/include/usbcdc.h
===================================================================
diff -u
--- firmware/include/usbcdc.h (revision 0)
+++ firmware/include/usbcdc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,742 @@
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/******************************************************************************
+ *
+ * Note: This header contains definitions related to the USB Communication
+ * Device Class specification. The header is complete for ACM model
+ * devices but request and notification definitions specific to other
+ * modem types, ISDN, ATM and Ethernet are currently incomplete or
+ * omitted.
+ *
+ *****************************************************************************/
+
+#ifndef __USBCDC_H__
+#define __USBCDC_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/******************************************************************************
+ *
+ * \ingroup cdc_device_class_api
+ * @{
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Generic macros to read a byte, word or long from a character pointer.
+ *
+ *****************************************************************************/
+/* #define BYTE(pucData) (*(uint8 *)(pucData))
+#define SHORT(pucData) (*(uint16 *)(pucData))
+#define LONG(pucData) (*(uint32 *)(pucData)) */
+
+/******************************************************************************
+ *
+ * USB CDC subclass codes. Used in interface descriptor, bInterfaceClass
+ *
+ *****************************************************************************/
+#define USB_CDC_SUBCLASS_DIRECT_LINE_MODEL 0x01
+#define USB_CDC_SUBCLASS_ABSTRACT_MODEL 0x02
+#define USB_CDC_SUBCLASS_TELEPHONE_MODEL 0x03
+#define USB_CDC_SUBCLASS_MULTI_CHANNEL_MODEL 0x04
+#define USB_CDC_SUBCLASS_CAPI_MODEL 0x05
+#define USB_CDC_SUBCLASS_ETHERNET_MODEL 0x06
+#define USB_CDC_SUBCLASS_ATM_MODEL 0x07
+
+/******************************************************************************
+ *
+ * USB CDC control interface protocols. Used in control interface descriptor,
+ * bInterfaceProtocol
+ *
+ *****************************************************************************/
+#define USB_CDC_PROTOCOL_NONE 0x00
+#define USB_CDC_PROTOCOL_V25TER 0x01
+#define USB_CDC_PROTOCOL_VENDOR 0xFF
+
+/******************************************************************************
+ *
+ * USB CDC data interface protocols. Used in data interface descriptor,
+ * bInterfaceProtocol
+ *
+ *****************************************************************************/
+/* USB_CDC_PROTOCOL_NONE 0x00 */
+#define USB_CDC_PROTOCOL_I420 0x30
+#define USB_CDC_PROTOCOL_TRANSPARENT 0x32
+#define USB_CDC_PROTOCOL_Q921M 0x50
+#define USB_CDC_PROTOCOL_Q921 0x51
+#define USB_CDC_PROTOCOL_Q921TM 0x52
+#define USB_CDC_PROTOCOL_V42BIS 0x90
+#define USB_CDC_PROTOCOL_Q921EURO 0x91
+#define USB_CDC_PROTOCOL_V120 0x92
+#define USB_CDC_PROTOCOL_CAPI20 0x93
+#define USB_CDC_PROTOCOL_HOST_DRIVER 0xFD
+#define USB_CDC_PROTOCOL_CDC_SPEC 0xFE
+/* USB_CDC_PROTOCOL_VENDOR 0xFF */
+
+/******************************************************************************
+ *
+ * Functional descriptor definitions
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Functional descriptor types
+ *
+ *****************************************************************************/
+#define USB_CDC_CS_INTERFACE 0x24
+#define USB_CDC_CS_ENDPOINT 0x25
+
+/******************************************************************************
+ *
+ * Functional descriptor subtypes
+ *
+ *****************************************************************************/
+#define USB_CDC_FD_SUBTYPE_HEADER 0x00
+#define USB_CDC_FD_SUBTYPE_CALL_MGMT 0x01
+#define USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT 0x02
+#define USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT 0x03
+#define USB_CDC_FD_SUBTYPE_TELEPHONE_RINGER 0x04
+#define USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS 0x05
+#define USB_CDC_FD_SUBTYPE_UNION 0x06
+#define USB_CDC_FD_SUBTYPE_COUNTRY 0x07
+#define USB_CDC_FD_SUBTYPE_TELEPHONE_MODES 0x08
+#define USB_CDC_FD_SUBTYPE_USB_TERMINAL 0x09
+#define USB_CDC_FD_SUBTYPE_NETWORK_TERMINAL 0x0A
+#define USB_CDC_FD_SUBTYPE_PROTOCOL_UNIT 0x0B
+#define USB_CDC_FD_SUBTYPE_EXTENSION_UNIT 0x0C
+#define USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT 0x0D
+#define USB_CDC_FD_SUBTYPE_CAPI_MGMT 0x0E
+#define USB_CDC_FD_SUBTYPE_ETHERNET 0x0F
+#define USB_CDC_FD_SUBTYPE_ATM 0x10
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_CALL_MGMT, Header functional descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_CALL_MGMT_VIA_DATA 0x02
+#define USB_CDC_CALL_MGMT_HANDLED 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT, Abstract Control Management functional
+ * descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_ACM_SUPPORTS_NETWORK_CONNECTION 0x08
+#define USB_CDC_ACM_SUPPORTS_SEND_BREAK 0x04
+#define USB_CDC_ACM_SUPPORTS_LINE_PARAMS 0x02
+#define USB_CDC_ACM_SUPPORTS_COMM_FEATURE 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT, Direct Line Management functional
+ * descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_DLM_NEEDS_EXTRA_PULSE_SETUP 0x04
+#define USB_CDC_DLM_SUPPORTS_AUX 0x02
+#define USB_CDC_DLM_SUPPORTS_PULSE 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_TELEPHONE_MODES, Telephone Operational Modes functional
+ * descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_TELEPHONE_SUPPORTS_COMPUTER 0x04
+#define USB_CDC_TELEPHONE_SUPPORTS_STANDALONE 0x02
+#define USB_CDC_TELEPHONE_SUPPORTS_SIMPLE 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS, Telephone Call and Line State Reporting
+ * Capabilities descriptor
+ *
+ *****************************************************************************/
+#define USB_CDC_LINE_STATE_CHANGES_NOTIFIED 0x20
+#define USB_CDC_LINE_STATE_REPORTS_DTMF 0x10
+#define USB_CDC_LINE_STATE_REPORTS_DIST_RING 0x08
+#define USB_CDC_LINE_STATE_REPORTS_CALLERID 0x04
+#define USB_CDC_LINE_STATE_REPORTS_BUSY 0x02
+#define USB_CDC_LINE_STATE_REPORTS_INT_DIALTONE 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_USB_TERMINAL, USB Terminal functional descriptor,
+ * bmOptions
+ *
+ *****************************************************************************/
+#define USB_CDC_TERMINAL_NO_WRAPPER_USED 0x00
+#define USB_CDC_TERMINAL_WRAPPER_USED 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT, Multi-Channel Management functional
+ * descriptor, bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_MCM_SUPPORTS_SET_UNIT_PARAM 0x04
+#define USB_CDC_MCM_SUPPORTS_CLEAR_UNIT_PARAM 0x02
+#define USB_CDC_MCM_UNIT_PARAMS_NON_VOLATILE 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_CAPI_MGMT, CAPI Control Management functional descriptor,
+ * bmCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_CAPI_INTELLIGENT 0x01
+#define USB_CDC_CAPI_SIMPLE 0x00
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_ETHERNET, Ethernet Networking functional descriptor,
+ * bmEthernetStatistics
+ *
+ *****************************************************************************/
+#define USB_CDC_ENET_XMIT_OK 0x01000000U
+#define USB_CDC_ENET_RCV_OK 0x02000000U
+#define USB_CDC_ENET_XMIT_ERROR 0x04000000U
+#define USB_CDC_ENET_RCV_ERROR 0x08000000U
+#define USB_CDC_ENET_RCV_NO_BUFFER 0x10000000U
+#define USB_CDC_ENET_DIRECTED_BYTES_XMIT 0x20000000U
+#define USB_CDC_ENET_DIRECTED_FRAMES_XMIT 0x40000000U
+#define USB_CDC_ENET_MULTICAST_BYTES_XMIT 0x80000000U
+#define USB_CDC_ENET_MULTICAST_FRAMES_XMIT 0x00010000U
+#define USB_CDC_ENET_BROADCAST_BYTES_XMIT 0x00020000U
+#define USB_CDC_ENET_BROADCAST_FRAMES_XMIT 0x00040000U
+#define USB_CDC_ENET_DIRECTED_BYTES_RCV 0x00080000U
+#define USB_CDC_ENET_DIRECTED_FRAMES_RCV 0x00100000U
+#define USB_CDC_ENET_MULTICAST_BYTES_RCV 0x00200000U
+#define USB_CDC_ENET_MULTICAST_FRAMES_RCV 0x00400000U
+#define USB_CDC_ENET_BROADCAST_BYTES_RCV 0x00800000U
+#define USB_CDC_ENET_BROADCAST_FRAMES_RCV 0x00000100U
+#define USB_CDC_ENET_RCV_CRC_ERROR 0x00000200U
+#define USB_CDC_ENET_TRANSMIT_QUEUE_LENGTH 0x00000400U
+#define USB_CDC_ENET_RCV_ERROR_ALIGNMENT 0x00000800U
+#define USB_CDC_ENET_XMIT_ONE_COLLISION 0x00001000U
+#define USB_CDC_ENET_XMIT_MORE_COLLISIONS 0x00002000U
+#define USB_CDC_ENET_XMIT_DEFERRED 0x00004000U
+#define USB_CDC_ENET_XMIT_MAX_COLLISIONS 0x00008000U
+#define USB_CDC_ENET_RCV_OVERRUN 0x00000001U
+#define USB_CDC_ENET_XMIT_UNDERRUN 0x00000002U
+#define USB_CDC_ENET_XMIT_HEARTBEAT_FAILURE 0x00000004U
+#define USB_CDC_ENET_XMIT_TIMES_CRS_LOST 0x00000008U
+#define USB_CDC_ENET_XMIT_LATE_COLLISIONS 0x00000010U
+
+/******************************************************************************
+ *
+ * USB_CDC_FD_SUBTYPE_ATM, ATM Networking functional descriptor,
+ * bmDataCapabilities
+ *
+ *****************************************************************************/
+#define USB_CDC_ATM_TYPE_3 0x08
+#define USB_CDC_ATM_TYPE_2 0x04
+#define USB_CDC_ATM_TYPE_1 0x02
+
+/******************************************************************************
+ *
+ * bmATMDeviceStatistics
+ *
+ *****************************************************************************/
+#define USB_CDC_ATM_VC_US_CELLS_SENT 0x10
+#define USB_CDC_ATM_VC_US_CELLS_RECEIVED 0x08
+#define USB_CDC_ATM_DS_CELLS_HEC_ERR_CORRECTED 0x04
+#define USB_CDC_ATM_US_CELLS_SENT 0x02
+#define USB_CDC_ATM_US_CELLS_RECEIVED 0x01
+
+/******************************************************************************
+ *
+ * Management Element Requests (provided in tUSBRequest.ucRequest)
+ *
+ *****************************************************************************/
+#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00u
+#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01u
+#define USB_CDC_SET_COMM_FEATURE 0x02u
+#define USB_CDC_GET_COMM_FEATURE 0x03u
+#define USB_CDC_CLEAR_COMM_FEATURE 0x04u
+#define USB_CDC_SET_AUX_LINE_STATE 0x10u
+#define USB_CDC_SET_HOOK_STATE 0x11u
+#define USB_CDC_PULSE_SETUP 0x12u
+#define USB_CDC_SEND_PULSE 0x13u
+#define USB_CDC_SET_PULSE_TIME 0x14u
+#define USB_CDC_RING_AUX_JACK 0x15u
+#define USB_CDC_SET_LINE_CODING 0x20u
+#define USB_CDC_GET_LINE_CODING 0x21u
+#define USB_CDC_SET_CONTROL_LINE_STATE 0x22u
+#define USB_CDC_SEND_BREAK 0x23u
+#define USB_CDC_SET_RINGER_PARMS 0x30u
+#define USB_CDC_GET_RINGER_PARMS 0x31u
+#define USB_CDC_SET_OPERATION_PARMS 0x32u
+#define USB_CDC_GET_OPERATION_PARMS 0x33u
+#define USB_CDC_SET_LINE_PARMS 0x34u
+#define USB_CDC_GET_LINE_PARMS 0x35u
+#define USB_CDC_DIAL_DIGITS 0x36u
+#define USB_CDC_SET_UNIT_PARAMETER 0x37u
+#define USB_CDC_GET_UNIT_PARAMETER 0x38u
+#define USB_CDC_CLEAR_UNIT_PARAMETER 0x39u
+#define USB_CDC_GET_PROFILE 0x3Au
+#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40u
+#define USB_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 0x41u
+#define USB_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 0x42u
+#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43u
+#define USB_CDC_GET_ETHERNET_STATISTIC 0x44u
+#define USB_CDC_SET_ATM_DATA_FORMAT 0x50u
+#define USB_CDC_GET_ATM_DEVICE_STATISTICS 0x51u
+#define USB_CDC_SET_ATM_DEFAULT_VC 0x52u
+#define USB_CDC_GET_ATM_VC_STATISTICS 0x53u
+
+/******************************************************************************
+ *
+ * In cases where a request defined above results in the return of a fixed size
+ * data block, the following group of labels define the size of that block. In
+ * each of these cases, an access macro is also provided to write the response
+ * data into an appropriately-sized array of uint8acters.
+ *
+ *****************************************************************************/
+#define USB_CDC_SIZE_COMM_FEATURE 2
+#define USB_CDC_SIZE_LINE_CODING 7
+#define USB_CDC_SIZE_RINGER_PARMS 4
+#define USB_CDC_SIZE_OPERATION_PARMS 2
+#define USB_CDC_SIZE_UNIT_PARAMETER 2
+#define USB_CDC_SIZE_PROFILE 64
+#define USB_CDC_SIZE_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 2
+#define USB_CDC_SIZE_ETHERNET_STATISTIC 4
+#define USB_CDC_SIZE_ATM_DEVICE_STATISTICS 4
+#define USB_CDC_SIZE_ATM_VC_STATISTICS 4
+#define USB_CDC_SIZE_LINE_PARMS 10
+
+/******************************************************************************
+ *
+ * NB: USB_CDC_SIZE_LINE_PARAMS assumes only a single call. For multiple
+ * calls, add 4 bytes per additional call.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * USB_CDC_GET_COMM_FEATURE & USB_CDC_SET_COMM_FEATURE
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * wValue (Feature Selector)
+ *
+ *****************************************************************************/
+#define USB_CDC_ABSTRACT_STATE 0x0001
+#define USB_CDC_COUNTRY_SETTING 0x0002
+
+/******************************************************************************
+ *
+ * Data when feature selector is USB_DCD_ABSTRACT_STATE
+ *
+ *****************************************************************************/
+#define USB_CDC_ABSTRACT_CALL_DATA_MULTIPLEXED 0x0002
+#define USB_CDC_ABSTRACT_ENDPOINTS_IDLE 0x0001
+
+/******************************************************************************
+ *
+ * Macros to populate the response data buffer (whose size in bytes is defined
+ * by USB_CDC_SIZE_COMM_FEATURE).
+ *
+ *****************************************************************************/
+/*
+ * Add code for macro SetResponseCommFeature.
+ */
+/******************************************************************************
+ *
+ * USB_CDC_SET_AUX_LINE_STATE, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_AUX_DISCONNECT 0x0000
+#define USB_CDC_AUX_CONNECT 0x0001
+
+/******************************************************************************
+ *
+ * USB_CDC_SET_HOOK_STATE, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_ON_HOOK 0x0000
+#define USB_CDC_OFF_HOOK 0x0001
+#define USB_CDC_SNOOPING 0x0002
+
+/******************************************************************************
+ *
+ * USB_CDC_GET_LINE_CODING
+ *
+ *****************************************************************************/
+#define USB_CDC_STOP_BITS_1 0x00
+#define USB_CDC_STOP_BITS_1_5 0x01
+#define USB_CDC_STOP_BITS_2 0x02
+
+#define USB_CDC_PARITY_NONE 0x00
+#define USB_CDC_PARITY_ODD 0x01
+#define USB_CDC_PARITY_EVEN 0x02
+#define USB_CDC_PARITY_MARK 0x03
+#define USB_CDC_PARITY_SPACE 0x04
+
+/******************************************************************************
+ *
+ * Macro to populate the response data buffer (whose size in bytes is defined
+ * by USB_CDC_SIZE_LINE_CODING).
+ *
+ *****************************************************************************/
+/*
+ * Add code for macro SetResponseLineCoding.
+ */
+/******************************************************************************
+ *
+ * USB_CDC_SET_CONTROL_LINE_STATE, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_DEACTIVATE_CARRIER 0x00
+#define USB_CDC_ACTIVATE_CARRIER 0x02
+#define USB_CDC_DTE_NOT_PRESENT 0x00
+#define USB_CDC_DTE_PRESENT 0x01
+
+/******************************************************************************
+ *
+ * USB_CDC_SET_RINGER_PARMS, USB_CDC_GET_RINGER_PARMS and
+ * USB_CDC_GET_LINE_PARMS (ulRingerBmp)
+ *
+ *****************************************************************************/
+#define USB_CDC_RINGER_EXISTS 0x80000000U
+#define USB_CDC_RINGER_DOES_NOT_EXIST 0x00000000
+
+/******************************************************************************
+ *
+ * Macro to populate the response data buffer to USB_CDC_GET_RINGER_PARMS.
+ * Parameter buf points to a buffer of size USB_CDC_SIZE_RINGER_PARMS bytes.
+ *
+ *****************************************************************************/
+/*
+ * Add code for macro SetResponseRingerParms.
+ */
+/******************************************************************************
+ *
+ * Macros to extract fields from the USB_CDC_SET_RINGER_PARMS data
+ *
+ *****************************************************************************/
+/* #define GetRingerVolume(pcData) (BYTE((pcData)+1)) */
+/* #define GetRingerPattern(pcData) (BYTE(pcData)) */
+/* #define GetRingerExists(pcData) ((LONG(pcData)) & USB_CDC_RINGER_EXISTS) */
+
+/******************************************************************************
+ *
+ * USB_CDC_SET_OPERATION_PARMS, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_SIMPLE_MODE 0x0000
+#define USB_CDC_STANDALONE_MODE 0x0001
+#define USB_CDC_HOST_CENTRIC_MODE 0x0002
+
+/******************************************************************************
+ *
+ * Macro to populate the response data buffer to USB_CDC_GET_OPERATION_PARMS.
+ * Parameter buf points to a buffer of size USB_CDC_SIZE_OPERATION_PARMS
+ * bytes.
+ *
+ *****************************************************************************/
+/*
+ * Add code for macro SetResponseOperationParms.
+ */
+/******************************************************************************
+ *
+ * USB_CDC_SET_LINE_PARMS, wParam - Line State Change
+ *
+ *****************************************************************************/
+#define USB_CDC_DROP_ACTIVE_CALL 0x0000
+#define USB_CDC_START_NEW_CALL 0x0001
+#define USB_CDC_APPLY_RINGING 0x0002
+#define USB_CDC_REMOVE_RINGING 0x0003
+#define USB_CDC_SWITCH_CALL 0x0004
+
+/******************************************************************************
+ *
+ * Line state bitmap in USB_CDC_GET_LINE_PARMS response
+ *
+ *****************************************************************************/
+#define USB_CDC_LINE_IS_ACTIVE 0x80000000U
+#define USB_CDC_LINE_IS_IDLE 0x00000000U
+#define USB_CDC_LINE_NO_ACTIVE_CALL 0x000000FFU
+
+#define USB_CDC_CALL_ACTIVE 0x80000000U
+
+/******************************************************************************
+ *
+ * Call state value definitions
+ *
+ *****************************************************************************/
+#define USB_CDC_CALL_IDLE 0x00000000
+#define USB_CDC_CALL_TYPICAL_DIALTONE 0x00000001
+#define USB_CDC_CALL_INTERRUPTED_DIALTONE 0x00000002
+#define USB_CDC_CALL_DIALING 0x00000003
+#define USB_CDC_CALL_RINGBACK 0x00000004
+#define USB_CDC_CALL_CONNECTED 0x00000005
+#define USB_CDC_CALL_INCOMING 0x00000006
+
+/******************************************************************************
+ *
+ * Call state change value definitions
+ *
+ *****************************************************************************/
+#define USB_CDC_CALL_STATE_IDLE 0x01
+#define USB_CDC_CALL_STATE_DIALING 0x02
+#define USB_CDC_CALL_STATE_RINGBACK 0x03
+#define USB_CDC_CALL_STATE_CONNECTED 0x04
+#define USB_CDC_CALL_STATE_INCOMING 0x05
+
+/******************************************************************************
+ *
+ * Extra byte of data describing the connection type for
+ * USB_CDC_CALL_STATE_CONNECTED.
+ *
+ *****************************************************************************/
+#define USB_CDC_VOICE 0x00
+#define USB_CDC_ANSWERING_MACHINE 0x01
+#define USB_CDC_FAX 0x02
+#define USB_CDC_MODEM 0x03
+#define USB_CDC_UNKNOWN 0xFF
+
+/******************************************************************************
+ *
+ * Macro to extract call index from request in cases where wParam is
+ * USB_CDC_SWITCH_CALL.
+ *
+ *****************************************************************************/
+/* #define GetCallIndex(pcData) (BYTE(pcData)) */
+
+/******************************************************************************
+ *
+ * Macro to populate the CallState entries in response to request
+ * USB_CDC_GET_LINE_PARMS. The ucIndex parameter is a zero based index
+ * indicating which call entry in the pcBuf response buffer to fill in. Note
+ * that pcBuf points to the first byte of the buffer (the wLength field).
+ *
+ *****************************************************************************/
+/*
+ * Add code for macro SetResponseCallState.
+ */
+/******************************************************************************
+ *
+ * Macro to populate the response data buffer (whose size in bytes is defined
+ * by USB_CDC_SIZE_LINE_PARMS). Note that this macro only populates fields for
+ * a single call. If multiple calls are being managed, additional 4 byte
+ * fields must be appended to provide call state for each call after the first.
+ * This may be done using the SetResponseCallState macro with the appropriate
+ * call index supplied.
+ *
+ *****************************************************************************/
+/*
+ * Add code for macro SetResponseLineParms.
+ */
+/******************************************************************************
+ *
+ * Notification Element definitions
+ *
+ *****************************************************************************/
+#define USB_CDC_NOTIFY_NETWORK_CONNECTION 0x00
+#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE 0x01
+#define USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE 0x08
+#define USB_CDC_NOTIFY_RING_DETECT 0x09
+#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
+#define USB_CDC_NOTIFY_CALL_STATE_CHANGE 0x28
+#define USB_CDC_NOTIFY_LINE_STATE_CHANGE 0x29
+#define USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE 0x2A
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_NETWORK_CONNECTION, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_NETWORK_DISCONNECTED 0x0000
+#define USB_CDC_NETWORK_CONNECTED 0x0001
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE, wValue
+ *
+ *****************************************************************************/
+#define USB_CDC_AUX_JACK_ON_HOOK 0x0000
+#define USB_CDC_AUX_JACK_OFF_HOOK 0x0001
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_SERIAL_STATE, Data
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Number of bytes of data returned alongside this notification.
+ *
+ *****************************************************************************/
+#define USB_CDC_NOTIFY_SERIAL_STATE_SIZE 2u
+
+#define USB_CDC_SERIAL_STATE_OVERRUN 0x0040U
+#define USB_CDC_SERIAL_STATE_PARITY 0x0020U
+#define USB_CDC_SERIAL_STATE_FRAMING 0x0010U
+#define USB_CDC_SERIAL_STATE_RING_SIGNAL 0x0008U
+#define USB_CDC_SERIAL_STATE_BREAK 0x0004U
+#define USB_CDC_SERIAL_STATE_TXCARRIER 0x0002U
+#define USB_CDC_SERIAL_STATE_RXCARRIER 0x0001U
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_CALL_STATE_CHANGE, wValue
+ *
+ * Call state values are defined above in the group beginning
+ * USB_CDC_CALL_STATE_IDLE. Note that the data returned alongside this
+ * notification are heavily dependent upon the call state being reported so no
+ * specific lengths or access macros are provided here.
+ *
+ * Macro to construct the correct wValue for this notification given a state
+ * and call index.
+ *
+ *****************************************************************************/
+/*
+ * Add code for macro SetNotifyCallStatewValue.
+ */
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_LINE_STATE_CHANGE, wValue
+ *
+ * Note that the data returned alongside this notification are heavily
+ * dependent upon the call state being reported so no specific lengths or
+ * access macros are provided here.
+ *
+ *****************************************************************************/
+#define USB_CDC_LINE_STATE_IDLE 0x0000
+#define USB_CDC_LINE_STATE_HOLD 0x0001
+#define USB_CDC_LINE_STATE_OFF_HOOK 0x0002
+#define USB_CDC_LINE_STATE_ON_HOOK 0x0003
+
+/******************************************************************************
+ *
+ * USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE, Data
+ *
+ * Macro to populate the 8 byte data structure returned alongside this
+ * notification.
+ *
+ *****************************************************************************/
+/*
+ * Add code for macro SetNotifyConnectionSpeedChange.
+ */
+/******************************************************************************
+ *
+ * Packed structure definitions for request/response data blocks
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * All structures defined in this section of the header require byte packing of
+ * fields. This is usually accomplished using the PACKED macro but, for IAR
+ * Embedded Workbench, this requires a pragma.
+ *
+ *****************************************************************************/
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack(1)
+#endif
+
+/**
+ * @brief USB_CDC_GET/SET_LINE_CODING request-specific data.
+ */
+typedef struct
+{
+ /**
+ * @brief The data terminal rate in bits per second.
+ */
+ uint32 ulRate;
+
+ /**
+ * @brief The number of stop bits. Valid values are USB_CDC_STOP_BITS_1,
+ * USB_CDC_STOP_BITS_1_5 or USB_CDC_STOP_BITS_2
+ */
+ uint8 ucStop;
+
+ /**
+ * @brief The parity setting. Valid values are USB_CDC_PARITY_NONE,
+ * USB_CDC_PARITY_ODD, USB_CDC_PARITY_EVEN, USB_CDC_PARITY_MARK
+ * and USB_CDC_PARITY_SPACE.
+ */
+ uint8 ucParity;
+
+ /**
+ * @brief The number of data bits per character. Valid values are
+ * 5, 6, 7 and 8 in this implementation.
+ */
+ uint8 ucDatabits;
+}
+PACKED tLineCoding;
+
+/******************************************************************************
+ *
+ * Return to default packing when using the IAR Embedded Workbench compiler.
+ *
+ *****************************************************************************/
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack()
+#endif
+
+/**
+ * Close the Doxygen group.
+ * @}
+ */
+
+/******************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBCDC_H__ */
Index: firmware/include/usbdcdc.h
===================================================================
diff -u
--- firmware/include/usbdcdc.h (revision 0)
+++ firmware/include/usbdcdc.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,383 @@
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ * @file usbdcdc.h
+ *
+ * @brief USBLib support for generic CDC ACM (serial) device.
+ *
+ */
+
+#ifndef __USBDCDC_H__
+#define __USBDCDC_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** ***************************************************************************
+ *
+ * \ingroup cdc_device_class_api
+ * @{
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * PRIVATE
+ *
+ * The first few sections of this header are private defines that are used by
+ * the USB CDC Serial code and are here only to help with the application
+ * allocating the correct amount of memory for the CDC Serial device code.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * PRIVATE
+ *
+ * This enumeration holds the various states that the device can be in during
+ * normal operation.
+ *
+ *****************************************************************************/
+typedef enum
+{
+ /**
+ * @brief Unconfigured.
+ */
+ CDC_STATE_UNCONFIGURED,
+
+ /**
+ * @brief No outstanding transaction remains to be completed.
+ */
+ CDC_STATE_IDLE,
+
+ /**
+ * @brief Waiting on completion of a send or receive transaction.
+ */
+ CDC_STATE_WAIT_DATA,
+
+ /**
+ * @brief Waiting for client to process data.
+ */
+ CDC_STATE_WAIT_CLIENT
+}
+tCDCState;
+
+/******************************************************************************
+ *
+ * PRIVATE
+ *
+ * This structure defines the private instance data and state variables for the
+ * CDC Serial device. The memory for this structure is pointed to by the
+ * psPrivateCDCSerData field in the tUSBDCDCDevice structure passed on
+ * USBDCDCInit().
+ *
+ *****************************************************************************/
+typedef struct
+{
+ uint32 ulUSBBase;
+ tDeviceInfo *psDevInfo;
+ tConfigDescriptor *psConfDescriptor;
+ volatile tCDCState eCDCRxState;
+ volatile tCDCState eCDCTxState;
+ volatile tCDCState eCDCRequestState;
+ volatile tCDCState eCDCInterruptState;
+ volatile uint8 ucPendingRequest;
+ uint16 usBreakDuration;
+ uint16 usControlLineState;
+ uint16 usSerialState;
+ volatile uint32 usDeferredOpFlags;
+ uint16 usLastTxSize;
+ tLineCoding sLineCoding;
+ volatile tBoolean bRxBlocked;
+ volatile tBoolean bControlBlocked;
+ volatile tBoolean bConnected;
+ uint8 ucControlEndpoint;
+ uint8 ucBulkINEndpoint;
+ uint8 ucBulkOUTEndpoint;
+ uint8 ucInterfaceControl;
+ uint8 ucInterfaceData;
+}
+tCDCSerInstance;
+
+
+#ifndef DEPRECATED
+/** ***************************************************************************
+ *
+ * @brief The number of bytes of workspace required by the CDC device class
+ * driver. The client must provide a block of RAM of at least this
+ * size in the psPrivateCDCSerData field of the tUSBCDCDevice
+ * structure passed on USBDCDCInit().
+ *
+ * This value is deprecated and should not be used, any new code
+ * should just pass in a tUSBCDCDevice structure in the
+ * psPrivateCDCSerData field.
+ *
+ *****************************************************************************/
+#define USB_CDCSER_WORKSPACE_SIZE (sizeof(tCDCSerInstance))
+#endif
+
+/** ***************************************************************************
+ *
+ * The following defines are used when working with composite devices.
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief The size of the memory that should be allocated to create a
+ * configuration descriptor for a single instance of the USB Serial
+ * CDC Device. This does not include the configuration descriptor
+ * which is automatically ignored by the composite device class.
+ *
+ * For reference this is sizeof(g_pIADSerDescriptor) +
+ * sizeof(g_pCDCSerCommInterface) + sizeof(g_pCDCSerDataInterface)
+ *
+ *****************************************************************************/
+#define COMPOSITE_DCDC_SIZE (8u + 35u + 23u)
+
+/** ***************************************************************************
+ *
+ * CDC-specific events These events are provided to the application in the
+ * \e ulMsg parameter of the tUSBCallback function.
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief The host requests that the device send a BREAK condition on its
+ * serial communication channel. The BREAK should remain active until
+ * a USBD_CDC_EVENT_CLEAR_BREAK event is received.
+ */
+#define USBD_CDC_EVENT_SEND_BREAK (USBD_CDC_EVENT_BASE + 0u)
+
+/** ***************************************************************************
+ *
+ * @brief The host requests that the device stop sending a BREAK condition on
+ * its serial communication channel.
+ */
+#define USBD_CDC_EVENT_CLEAR_BREAK (USBD_CDC_EVENT_BASE + 1u)
+
+/** ***************************************************************************
+ *
+ * @brief The host requests that the device set the RS232 signaling lines to
+ * a particular state. The ulMsgValue parameter contains the RTS and
+ * DTR control line states as defined in table 51 of the USB CDC class
+ * definition and is a combination of the following values:
+ *
+ * (RTS) USB_CDC_DEACTIVATE_CARRIER or USB_CDC_ACTIVATE_CARRIER
+ * (DTR) USB_CDC_DTE_NOT_PRESENT or USB_CDC_DTE_PRESENT
+ */
+#define USBD_CDC_EVENT_SET_CONTROL_LINE_STATE (USBD_CDC_EVENT_BASE + 2u)
+
+/** ***************************************************************************
+ *
+ * @brief The host requests that the device set the RS232 communication
+ * parameters. The pvMsgData parameter points to a tLineCoding
+ * structure defining the required number of bits per character,
+ * parity mode, number of stop bits and the baud rate.
+ */
+#define USBD_CDC_EVENT_SET_LINE_CODING (USBD_CDC_EVENT_BASE + 3u)
+
+/** ***************************************************************************
+ *
+ * @brief The host is querying the current RS232 communication parameters.
+ * The pvMsgData parameter points to a tLineCoding structure that the
+ * application must fill with the current settings prior to returning
+ * from the callback.
+ */
+#define USBD_CDC_EVENT_GET_LINE_CODING (USBD_CDC_EVENT_BASE + 4u)
+
+/** ***************************************************************************
+ *
+ * @brief The structure used by the application to define operating
+ * parameters for the CDC device.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The vendor ID that this device is to present in the device
+ * descriptor.
+ */
+ uint16 usVID;
+
+ /**
+ * @brief The product ID that this device is to present in the device
+ * descriptor.
+ */
+ uint16 usPID;
+
+ /**
+ * @brief The maximum power consumption of the device, expressed in
+ * milliamps.
+ */
+ uint16 usMaxPowermA;
+
+ /**
+ * @brief Indicates whether the device is self- or bus-powered and
+ * whether or not it supports remote wakeup. Valid values are
+ * USB_CONF_ATTR_SELF_PWR or USB_CONF_ATTR_BUS_PWR, optionally
+ * ORed with USB_CONF_ATTR_RWAKE.
+ */
+ uint8 ucPwrAttributes;
+
+ /**
+ * @brief A pointer to the callback function which will be called to
+ * notify the application of all asynchronous control events
+ * related to the operation of the device.
+ */
+ tUSBCallback pfnControlCallback;
+
+ /**
+ * @brief A client-supplied pointer which will be sent as the first
+ * parameter in all calls made to the control channel callback,
+ * pfnControlCallback.
+ */
+ void *pvControlCBData;
+
+ /**
+ * @brief A pointer to the callback function which will be called to
+ * notify the application of events related to the device's data
+ * receive channel.
+ */
+ tUSBCallback pfnRxCallback;
+
+ /**
+ * @brief A client-supplied pointer which will be sent as the first
+ * parameter in all calls made to the receive channel callback,
+ * pfnRxCallback.
+ */
+ void *pvRxCBData;
+
+ /**
+ * @brief A pointer to the callback function which will be called to
+ * notify the application of events related to the device's data
+ * transmit channel.
+ */
+ tUSBCallback pfnTxCallback;
+
+ /**
+ * @brief A client-supplied pointer which will be sent as the first
+ * parameter in all calls made to the transmit channel callback,
+ * pfnTxCallback.
+ */
+ void *pvTxCBData;
+
+ /**
+ * @brief A pointer to the string descriptor array for this device. This
+ * array must contain the following string descriptor pointers in
+ * this order. Language descriptor, Manufacturer name string
+ * (language 1), Product name string (language 1), Serial number
+ * Control interface description string (language 1),
+ * Configuration description string (language 1).
+ *
+ * If supporting more than 1 language, the strings for indices
+ * 1 through 5 must be repeated for each of the other languages
+ * defined in the language descriptor.
+ */
+ const uint8 * const *ppStringDescriptors;
+
+ /**
+ * @brief The number of descriptors provided in the ppStringDescriptors
+ * array. This must be 1 + (5 * number of supported languages).
+ */
+ uint32 ulNumStringDescriptors;
+
+ /**
+ * @brief A pointer to the private instance data for this device. This
+ * memory must remain accessible for as long as the CDC device is
+ * in use and must not be modified by any code outside the CDC
+ * class driver.
+ */
+ tCDCSerInstance *psPrivateCDCSerData;
+}
+tUSBDCDCDevice;
+
+extern tDeviceInfo g_sCDCSerDeviceInfo;
+
+/** ***************************************************************************
+ *
+ * API Function Prototypes
+ *
+ *****************************************************************************/
+extern void * USBDCDCCompositeInit(uint32 ulIndex,
+ const tUSBDCDCDevice *psCDCDevice);
+extern void *USBDCDCInit(uint32 ulIndex,
+ const tUSBDCDCDevice *psCDCDevice);
+extern void USBDCDCTerm(void *pvInstance);
+extern void *USBDCDCSetControlCBData(tUSBDCDCDevice *pvInstance, void *pvCBData);
+extern void *USBDCDCSetRxCBData(void *pvInstance, void *pvCBData);
+extern void *USBDCDCSetTxCBData(void *pvInstance, void *pvCBData);
+extern uint32 USBDCDCPacketWrite(void *pvInstance,
+ uint8 *pcData,
+ uint32 ulLength,
+ tBoolean bLast);
+extern uint32 USBDCDCPacketRead(void *pvInstance,
+ uint8 *pcData,
+ uint32 ulLength,
+ tBoolean bLast);
+extern uint32 USBDCDCTxPacketAvailable(void *pvInstance);
+extern uint32 USBDCDCRxPacketAvailable(void *pvInstance);
+extern void USBDCDCSerialStateChange(void *pvInstance,
+ uint16 usState);
+extern void USBDCDCPowerStatusSet(void *pvInstance, uint8 ucPower);
+extern tBoolean USBDCDCRemoteWakeupRequest(void *pvInstance);
+
+/** ***************************************************************************
+ *
+ * Close the Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBDCDC_H__ */
Index: firmware/include/usbdevice.h
===================================================================
diff -u
--- firmware/include/usbdevice.h (revision 0)
+++ firmware/include/usbdevice.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,153 @@
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ * @file usbdevice.h
+ *
+ * @brief Types and definitions used during USB enumeration.
+ *
+ */
+
+#ifndef __USBDEVICE_H__
+#define __USBDEVICE_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** ***************************************************************************
+ *
+ * \ingroup device_api
+ * @{
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief The maximum number of independent interfaces that any single device
+ * implementation can support. Independent interfaces means interface
+ * descriptors with different bInterfaceNumber values - several
+ * interface descriptors offering different alternative settings but
+ * the same interface number count as a single interface.
+ *
+ *****************************************************************************/
+/*#define USB_MAX_INTERFACES_PER_DEVICE 8u*/
+
+/** ***************************************************************************
+ *
+ * Close the Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief The default USB endpoint FIFO configuration structure. This
+ * structure contains definitions to set all USB FIFOs into single
+ * buffered mode with no DMA use. Each endpoint's FIFO is sized to
+ * hold the largest maximum packet size for any interface alternate
+ * setting in the current config descriptor. A pointer to this
+ * structure may be passed in the psFIFOConfig field of the
+ * tDeviceInfo structure passed to USBCDCInit if the application does
+ * not require any special handling of the USB controller FIFO.
+ *
+ *****************************************************************************/
+extern const tFIFOConfig g_sUSBDefaultFIFOConfig;
+
+/** ***************************************************************************
+ *
+ * Public APIs offered by the USB library device control driver.
+ *
+ *****************************************************************************/
+extern void USBDCDInit(uint32 ulIndex, tDeviceInfo *psDevice);
+extern void USBDCDTerm(uint32 ulIndex);
+extern void USBDCDStallEP0(uint32 ulIndex);
+extern void USBDCDRequestDataEP0(uint32 ulIndex, uint8 *pucData,
+ uint32 ulSize);
+extern void USBDCDSendDataEP0(uint32 ulIndex, uint8 *pucData,
+ uint32 ulSize);
+extern void USBDCDSetDefaultConfiguration(uint32 ulIndex,
+ uint32 ulDefaultConfig);
+extern uint32 USBDCDConfigDescGetSize(const tConfigHeader *psConfig);
+extern uint32 USBDCDConfigDescGetNum(const tConfigHeader *psConfig,
+ uint32 ulType);
+extern tDescriptorHeader *USBDCDConfigDescGet(const tConfigHeader *psConfig,
+ uint32 ulType,
+ uint32 ulIndex,
+ uint32 *pulSection);
+extern uint32
+ USBDCDConfigGetNumAlternateInterfaces(const tConfigHeader *psConfig,
+ uint8 ucInterfaceNumber);
+extern tInterfaceDescriptor *
+ USBDCDConfigGetInterface(const tConfigHeader *psConfig,
+ uint32 ulIndex, uint32 ulAltCfg,
+ uint32 *pulSection);
+extern tEndpointDescriptor *
+ USBDCDConfigGetInterfaceEndpoint(const tConfigHeader *psConfig,
+ uint32 ulInterfaceNumber,
+ uint32 ulAltCfg,
+ uint32 ulIndex);
+extern void USBDCDPowerStatusSet(uint32 ulIndex, uint8 ucPower);
+extern tBoolean USBDCDRemoteWakeupRequest(uint32 ulIndex);
+
+/** ***************************************************************************
+ *
+ * Early releases of the USB library had the following function named
+ * incorrectly. This macro ensures that any code which used the previous name
+ * will still operate as expected.
+ *
+ *****************************************************************************/
+#ifndef DEPRECATED
+#define USBCDCConfigGetInterfaceEndpoint(a, b, c, d) \
+ USBDCDConfigGetInterfaceEndpoint((a), (b), (c), (d))
+#endif
+
+/** ***************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBENUM_H__ */
Index: firmware/include/usbdevicepriv.h
===================================================================
diff -u
--- firmware/include/usbdevicepriv.h (revision 0)
+++ firmware/include/usbdevicepriv.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,90 @@
+/******************************************************************************
+ * FILE DESCRIPTION
+ * ---------------------------------------------------------------------------
+ * File: usbdevicepriv.h
+ * Component:
+ * Module: usb
+ * Generator: -
+ *
+ * Description: Private header file used to share internal variables and
+ * function prototypes between the various device-related
+ * modules in the USB library. This header MUST NOT be
+ * used by application code.
+ *
+ *****************************************************************************/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __USBDEVICEPRIV_H__
+#define __USBDEVICEPRIV_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/******************************************************************************
+ *
+ * Device enumeration functions provided by device/usbenum.c and called from
+ * the interrupt handler in device/usbhandler.c
+ *
+ *****************************************************************************/
+extern tBoolean USBDeviceConfig(uint32 ulIndex,
+ const tConfigHeader *psConfig,
+ const tFIFOConfig *psFIFOConfig);
+extern tBoolean USBDeviceConfigAlternate(uint32 ulIndex,
+ const tConfigHeader *psConfig,
+ uint8 ucInterfaceNum,
+ uint8 ucAlternateSetting);
+extern void USBDeviceResumeTickHandler(uint32 ulIndex);
+
+/******************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBDEVICEPRIV_H__ */
Index: firmware/include/usblib.h
===================================================================
diff -u
--- firmware/include/usblib.h (revision 0)
+++ firmware/include/usblib.h (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1899 @@
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/**
+ * @file usblib.h
+ *
+ * @brief Main header file for the USB Library.
+ *
+ */
+
+#ifndef __USBLIB_H__
+#define __USBLIB_H__
+
+/******************************************************************************
+ *
+ * If building with a C++ compiler, make all of the definitions in this header
+ * have a C binding.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+/* standard device requests -- USB_SetupDataPacket::bRequest */
+#define USB_REQUEST_GETSTATUS (0u)
+#define USB_REQUEST_CLEARFEATURE (1u)
+#define USB_REQUEST_SETFEATURE (3u)
+#define USB_REQUEST_SETADDRESS (5u)
+#define USB_REQUEST_GETDESCRIPTOR (6u)
+#define USB_REQUEST_SETDESCRIPTOR (7u)
+#define USB_REQUEST_GETCONFIGURATION (8u)
+#define USB_REQUEST_SETCONFIGURATION (9u)
+#define USB_REQUEST_GETINTERFACE (10u)
+#define USB_REQUEST_SETINTERFACE (11u)
+#define USB_REQUEST_SYNCHFRAME (12u)
+
+
+/** ***************************************************************************
+ *
+ * This is the maximum number of endpoints supported by the usblib.
+ *
+ *****************************************************************************/
+#define USBLIB_NUM_EP 16u /* Number of supported endpoints. */
+
+/******************************************************************************
+ *
+ * The following macro allows compiler-independent syntax to be used to
+ * define packed structures. A typical structure definition using these
+ * macros will look similar to the following example:
+ *
+ * #ifdef ewarm
+ * #pragma pack(1)
+ * #endif
+ *
+ * typedef struct _PackedStructName
+ * {
+ * uint32 ulFirstField;
+ * char cCharMember;
+ * uint16 usShort;
+ * }
+ * PACKED tPackedStructName;
+ *
+ * #ifdef ewarm
+ * #pragma pack()
+ * #endif
+ *
+ * The conditional blocks related to ewarm include the #pragma pack() lines
+ * only if the IAR Embedded Workbench compiler is being used. Unfortunately,
+ * it is not possible to emit a #pragma from within a macro definition so this
+ * must be done explicitly.
+ *
+ *****************************************************************************/
+#if defined(ccs) || \
+ defined(codered) || \
+ defined(gcc) || \
+ defined(rvmdk) || \
+ defined(__ARMCC_VERSION) || \
+ defined(sourcerygxx)
+#define PACKED __attribute__ ((packed))
+#elif defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#define PACKED
+#elif (__TMS470__)
+#define PACKED __attribute__ ((packed))
+#else
+#error Unrecognized COMPILER!
+#endif
+
+/******************************************************************************
+ *
+ * Assorted language IDs from the document "USB_LANGIDs.pdf" provided by the
+ * USB Implementers' Forum (Version 1.0).
+ *
+ *****************************************************************************/
+#define USB_LANG_CHINESE_PRC 0x0804u /**< Chinese (PRC) */
+#define USB_LANG_CHINESE_TAIWAN 0x0404u /**< Chinese (Taiwan) */
+#define USB_LANG_EN_US 0x0409u /**< English (United States) */
+#define USB_LANG_EN_UK 0x0809u /**< English (United Kingdom) */
+#define USB_LANG_EN_AUS 0x0C09u /**< English (Australia) */
+#define USB_LANG_EN_CA 0x1009u /**< English (Canada) */
+#define USB_LANG_EN_NZ 0x1409u /**< English (New Zealand) */
+#define USB_LANG_FRENCH 0x040Cu /**< French (Standard) */
+#define USB_LANG_GERMAN 0x0407u /**< German (Standard) */
+#define USB_LANG_HINDI 0x0439u /**< Hindi */
+#define USB_LANG_ITALIAN 0x0410u /**< Italian (Standard) */
+#define USB_LANG_JAPANESE 0x0411u /**< Japanese */
+#define USB_LANG_KOREAN 0x0412u /**< Korean */
+#define USB_LANG_ES_TRAD 0x040Au /**< Spanish (Traditional) */
+#define USB_LANG_ES_MODERN 0x0C0Au /**< Spanish (Modern) */
+#define USB_LANG_SWAHILI 0x0441u /**< Swahili (Kenya) */
+#define USB_LANG_URDU_IN 0x0820u /**< Urdu (India) */
+#define USB_LANG_URDU_PK 0x0420u /**< Urdu (Pakistan) */
+/** ***************************************************************************
+ *
+ * @ingroup usbchap9_src
+ * @{
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Note:
+ *
+ * Structure definitions which are derived directly from the USB specification
+ * use field names from the specification. Since a somewhat different version
+ * of Hungarian prefix notation is used from the Stellaris standard, beware of
+ * making assumptions about field sizes based on the field prefix when using
+ * these structures. Of particular note is the difference in the meaning of
+ * the 'i' prefix. In USB structures, this indicates a single byte index
+ * whereas in Stellaris code, this is a 32 bit integer.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * All structures defined in this section of the header require byte packing of
+ * fields. This is usually accomplished using the PACKED macro but, for IAR
+ * Embedded Workbench, this requires a pragma.
+ *
+ *****************************************************************************/
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack(1)
+#endif
+
+/******************************************************************************
+ *
+ * Definitions related to standard USB device requests (sections 9.3 & 9.4)
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief The standard USB request header as defined in section 9.3 of the
+ * USB 2.0 specification.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief Determines the type and direction of the request.
+ */
+ uint8 bmRequestType;
+
+ /**
+ * @brief Identifies the specific request being made.
+ */
+ uint8 bRequest;
+
+ /**
+ * @brief Word-sized field that varies according to the request.
+ */
+ uint16 wValue;
+
+ /**
+ * @brief Word-sized field that varies according to the request; typically used
+ * to pass an index or offset.
+ */
+ uint16 wIndex;
+
+ /**
+ * @brief The number of bytes to transfer if there is a data stage to the
+ * request.
+ */
+ uint16 wLength;
+
+}
+PACKED tUSBRequest;
+
+/******************************************************************************
+ *
+ * The following defines are used with the bmRequestType member of tUSBRequest.
+ *
+ * Request types have 3 bit fields:
+ * 4:0 - Is the recipient type.
+ * 6:5 - Is the request type.
+ * 7 - Is the direction of the request.
+ *
+ *****************************************************************************/
+#define USB_RTYPE_DIR_IN 0x80u
+#define USB_RTYPE_DIR_OUT 0x00u
+
+#define USB_RTYPE_TYPE_M 0x60u
+#define USB_RTYPE_VENDOR 0x40u
+#define USB_RTYPE_CLASS 0x20u
+#define USB_RTYPE_STANDARD 0x00u
+
+#define USB_RTYPE_RECIPIENT_M 0x1fu
+#define USB_RTYPE_OTHER 0x03u
+#define USB_RTYPE_ENDPOINT 0x02u
+#define USB_RTYPE_INTERFACE 0x01u
+#define USB_RTYPE_DEVICE 0x00u
+
+/******************************************************************************
+ *
+ * Standard USB requests IDs used in the bRequest field of tUSBRequest.
+ *
+ *****************************************************************************/
+#define USBREQ_GET_STATUS 0x00u
+#define USBREQ_CLEAR_FEATURE 0x01u
+#define USBREQ_SET_FEATURE 0x03u
+#define USBREQ_SET_ADDRESS 0x05u
+#define USBREQ_GET_DESCRIPTOR 0x06u
+#define USBREQ_SET_DESCRIPTOR 0x07u
+#define USBREQ_GET_CONFIG 0x08u
+#define USBREQ_SET_CONFIG 0x09u
+#define USBREQ_GET_INTERFACE 0x0au
+#define USBREQ_SET_INTERFACE 0x0bu
+#define USBREQ_SYNC_FRAME 0x0cu
+
+#define USBREQ_COUNT (USBREQ_SYNC_FRAME + 1u)
+
+/******************************************************************************
+ *
+ * Data returned from a USBREQ_GET_STATUS request to a device.
+ *
+ *****************************************************************************/
+#define USB_STATUS_SELF_PWR 0x0001u /**< Currently self powered. */
+#define USB_STATUS_BUS_PWR 0x0000u /**< Currently bus-powered. */
+#define USB_STATUS_PWR_M 0x0001u /**< Mask for power mode. */
+#define USB_STATUS_REMOTE_WAKE 0x0002u /**< Remote wake-up is currently
+ enabled. */
+
+/******************************************************************************
+ *
+ * Feature Selectors (tUSBRequest.wValue) passed on USBREQ_CLEAR_FEATURE and
+ * USBREQ_SET_FEATURE.
+ *
+ *****************************************************************************/
+#define USB_FEATURE_EP_HALT 0x0000u /**< Endpoint halt feature. */
+#define USB_FEATURE_REMOTE_WAKE 0x0001u /**< Remote wake feature, device only. */
+#define USB_FEATURE_TEST_MODE 0x0002u /**< Test mode */
+
+/******************************************************************************
+ *
+ * Endpoint Selectors (tUSBRequest.wIndex) passed on USBREQ_CLEAR_FEATURE,
+ * USBREQ_SET_FEATURE and USBREQ_GET_STATUS.
+ *
+ *****************************************************************************/
+#define USB_REQ_EP_NUM_M 0x007Fu
+#define USB_REQ_EP_DIR_M 0x0080u
+#define USB_REQ_EP_DIR_IN 0x0080u
+#define USB_REQ_EP_DIR_OUT 0x0000u
+
+/******************************************************************************
+ *
+ * Standard USB descriptor types. These values are passed in the upper bytes
+ * of tUSBRequest.wValue on USBREQ_GET_DESCRIPTOR and also appear in the
+ * bDescriptorType field of standard USB descriptors.
+ *
+ *****************************************************************************/
+#define USB_DTYPE_DEVICE 1u
+#define USB_DTYPE_CONFIGURATION 2u
+#define USB_DTYPE_STRING 3u
+#define USB_DTYPE_INTERFACE 4u
+#define USB_DTYPE_ENDPOINT 5u
+#define USB_DTYPE_DEVICE_QUAL 6u
+#define USB_DTYPE_OSPEED_CONF 7u
+#define USB_DTYPE_INTERFACE_PWR 8u
+#define USB_DTYPE_OTG 9u
+#define USB_DTYPE_INTERFACE_ASC 11u
+#define USB_DTYPE_CS_INTERFACE 36u
+
+/******************************************************************************
+ *
+ * Definitions related to USB descriptors (sections 9.5 & 9.6)
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief This structure describes a generic descriptor header. These
+ * fields are to be found at the beginning of all valid USB
+ * descriptors.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The length of this descriptor (including this length byte) expressed
+ * in bytes.
+ */
+ uint8 bLength;
+
+ /**
+ * @brief The type identifier of the descriptor whose information follows.
+ * For standard descriptors, this field could contain, for example,
+ * USB_DTYPE_DEVICE to identify a device descriptor or
+ * USB_DTYPE_ENDPOINT to identify an endpoint descriptor.
+ */
+ uint8 bDescriptorType;
+}
+PACKED tDescriptorHeader;
+
+/** ***************************************************************************
+ *
+ * @brief This structure describes the USB device descriptor as defined in USB
+ * 2.0 specification section 9.6.1.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The length of this descriptor in bytes. All device descriptors
+ * are 18 bytes long.
+ */
+ uint8 bLength;
+
+ /**
+ * @brief The type of the descriptor. For a device descriptor, this will
+ * be USB_DTYPE_DEVICE (1).
+ */
+ uint8 bDescriptorType;
+
+ /**
+ * @brief The USB Specification Release Number in BCD format.
+ * For USB 2.0, this will be 0x0200.
+ */
+ uint16 bcdUSB;
+
+ /**
+ * @brief The device class code.
+ */
+ uint8 bDeviceClass;
+
+ /**
+ * @brief The device subclass code. This value qualifies the value
+ * found in the bDeviceClass field.
+ */
+ uint8 bDeviceSubClass;
+
+ /**
+ * @brief The device protocol code. This value is qualified by the
+ * values of bDeviceClass and bDeviceSubClass.
+ */
+ uint8 bDeviceProtocol;
+
+ /**
+ * @brief The maximum packet size for endpoint zero. Valid values
+ * are 8, 16, 32 and 64.
+ */
+ uint8 bMaxPacketSize0;
+
+ /**
+ * @brief The device Vendor ID (VID) as assigned by the USB-IF.
+ */
+ uint16 idVendor;
+
+ /**
+ * @brief The device Product ID (PID) as assigned by the manufacturer.
+ */
+ uint16 idProduct;
+
+ /**
+ * @brief The device release number in BCD format.
+ */
+ uint16 bcdDevice;
+
+ /**
+ * @brief The index of a string descriptor describing the manufacturer.
+ */
+ uint8 iManufacturer;
+
+ /**
+ * @brief The index of a string descriptor describing the product.
+ */
+ uint8 iProduct;
+
+ /**
+ * @brief The index of a string descriptor describing the device's serial
+ * number.
+ */
+ uint8 iSerialNumber;
+
+ /**
+ * @brief The number of possible configurations offered by the device.
+ * This field indicates the number of distinct configuration
+ * descriptors that the device offers.
+ */
+ uint8 bNumConfigurations;
+}
+PACKED tDeviceDescriptor;
+
+/******************************************************************************
+ *
+ * USB Device Class codes used in the tDeviceDescriptor.bDeviceClass field.
+ * Definitions for the bDeviceSubClass and bDeviceProtocol fields are device
+ * specific and can be found in the appropriate device class header files.
+ *
+ *****************************************************************************/
+#define USB_CLASS_DEVICE 0x00u
+#define USB_CLASS_AUDIO 0x01u
+#define USB_CLASS_CDC 0x02u
+#define USB_CLASS_HID 0x03u
+#define USB_CLASS_PHYSICAL 0x05u
+#define USB_CLASS_IMAGE 0x06u
+#define USB_CLASS_PRINTER 0x07u
+#define USB_CLASS_MASS_STORAGE 0x08u
+#define USB_CLASS_HUB 0x09u
+#define USB_CLASS_CDC_DATA 0x0au
+#define USB_CLASS_SMART_CARD 0x0bu
+#define USB_CLASS_SECURITY 0x0du
+#define USB_CLASS_VIDEO 0x0eu
+#define USB_CLASS_HEALTHCARE 0x0fu
+#define USB_CLASS_DIAG_DEVICE 0xdcu
+#define USB_CLASS_WIRELESS 0xe0u
+#define USB_CLASS_MISC 0xefu
+#define USB_CLASS_APP_SPECIFIC 0xfeu
+#define USB_CLASS_VEND_SPECIFIC 0xffu
+#define USB_CLASS_EVENTS 0xffffffffU
+
+/******************************************************************************
+ *
+ * Generic values for undefined subclass and protocol.
+ *
+ *****************************************************************************/
+#define USB_SUBCLASS_UNDEFINED 0x00u
+#define USB_PROTOCOL_UNDEFINED 0x00u
+
+/******************************************************************************
+ *
+ * The following are the miscellaneous subclass values.
+ *
+ *****************************************************************************/
+#define USB_MISC_SUBCLASS_SYNC 0x01u
+#define USB_MISC_SUBCLASS_COMMON 0x02u
+
+/******************************************************************************
+ *
+ * These following are miscellaneous protocol values.
+ *
+ *****************************************************************************/
+#define USB_MISC_PROTOCOL_IAD 0x01u
+
+/** ***************************************************************************
+ *
+ * @brief This structure describes the USB device qualifier descriptor as
+ * defined in the USB 2.0 specification, section 9.6.2.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The length of this descriptor in bytes. All device qualifier
+ * descriptors are 10 bytes long.
+ */
+ uint8 bLength;
+
+ /**
+ * @brief The type of the descriptor. For a device descriptor, this will
+ * be USB_DTYPE_DEVICE_QUAL (6).
+ */
+ uint8 bDescriptorType;
+
+ /**
+ * @brief The USB Specification Release Number in BCD format.
+ * For USB 2.0, this will be 0x0200.
+ */
+ uint16 bcdUSB;
+
+ /**
+ * @brief The device class code.
+ */
+ uint8 bDeviceClass;
+
+ /**
+ * @brief The device subclass code. This value qualifies the value
+ * found in the bDeviceClass field.
+ */
+ uint8 bDeviceSubClass;
+
+ /**
+ * @brief The device protocol code. This value is qualified by the
+ * values of bDeviceClass and bDeviceSubClass.
+ */
+ uint8 bDeviceProtocol;
+
+ /**
+ * @brief The maximum packet size for endpoint zero when operating at
+ * a speed other than high speed.
+ */
+ uint8 bMaxPacketSize0;
+
+ /**
+ * @brief The number of other-speed configurations supported.
+ */
+ uint8 bNumConfigurations;
+
+ /**
+ * @brief Reserved for future use. Must be set to zero.
+ */
+ uint8 bReserved;
+}
+PACKED tDeviceQualifierDescriptor;
+
+/** ***************************************************************************
+ *
+ * This structure describes the USB configuration descriptor as defined in
+ * USB 2.0 specification section 9.6.3. This structure also applies to the
+ * USB other speed configuration descriptor defined in section 9.6.4.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The length of this descriptor in bytes. All configuration
+ * descriptors are 9 bytes long.
+ */
+ uint8 bLength;
+
+ /**
+ * @brief The type of the descriptor. For a configuration descriptor,
+ * this will be USB_DTYPE_CONFIGURATION (2).
+ */
+ uint8 bDescriptorType;
+
+ /**
+ * @brief The total length of data returned for this configuration.
+ * This includes the combined length of all descriptors
+ * (configuration, interface, endpoint and class- or
+ * vendor-specific) returned for this configuration.
+ */
+ uint16 wTotalLength;
+
+ /**
+ * @brief The number of interface supported by this configuration.
+ */
+ uint8 bNumInterfaces;
+
+ /**
+ * @brief The value used as an argument to the SetConfiguration standard
+ * request to select this configuration.
+ */
+ uint8 bConfigurationValue;
+
+ /**
+ * @brief The index of a string descriptor describing this configuration.
+ */
+ uint8 iConfiguration;
+
+ /**
+ * @brief Attributes of this configuration.
+ */
+ uint8 bmAttributes;
+
+ /**
+ * @brief The maximum power consumption of the USB device from the bus
+ * in this configuration when the device is fully operational.
+ * This is expressed in units of 2mA so, for example,
+ * 100 represents 200mA.
+ */
+ uint8 bMaxPower;
+}
+PACKED tConfigDescriptor;
+
+/******************************************************************************
+ *
+ * Flags used in constructing the value assigned to the field
+ * tConfigDescriptor.bmAttributes. Note that bit 7 is reserved and must be set
+ * to 1.
+ *
+ *****************************************************************************/
+#define USB_CONF_ATTR_PWR_M 0xC0u
+
+#define USB_CONF_ATTR_SELF_PWR 0xC0u
+#define USB_CONF_ATTR_BUS_PWR 0x80u
+#define USB_CONF_ATTR_RWAKE 0xA0u
+
+/** ***************************************************************************
+ *
+ * This structure describes the USB interface descriptor as defined in USB
+ * 2.0 specification section 9.6.5.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The length of this descriptor in bytes. All interface
+ * descriptors are 9 bytes long.
+ */
+ uint8 bLength;
+
+ /**
+ * @brief The type of the descriptor. For an interface descriptor, this
+ * will be USB_DTYPE_INTERFACE (4).
+ */
+ uint8 bDescriptorType;
+
+ /**
+ * @brief The number of this interface. This is a zero based index into
+ * the array of concurrent interfaces supported by this
+ * configuration.
+ */
+ uint8 bInterfaceNumber;
+
+ /**
+ * @brief The value used to select this alternate setting for the
+ * interface defined in bInterfaceNumber.
+ */
+ uint8 bAlternateSetting;
+
+ /**
+ * @brief The number of endpoints used by this interface (excluding
+ * endpoint zero).
+ */
+ uint8 bNumEndpoints;
+
+ /**
+ * @brief The interface class code as assigned by the USB-IF.
+ */
+ uint8 bInterfaceClass;
+
+ /**
+ * @brief The interface subclass code as assigned by the USB-IF.
+ */
+ uint8 bInterfaceSubClass;
+
+ /**
+ * @brief The interface protocol code as assigned by the USB-IF.
+ */
+ uint8 bInterfaceProtocol;
+
+ /**
+ * @brief The index of a string descriptor describing this interface.
+ */
+ uint8 iInterface;
+}
+PACKED tInterfaceDescriptor;
+
+/** ***************************************************************************
+ *
+ * This structure describes the USB endpoint descriptor as defined in USB
+ * 2.0 specification section 9.6.6.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The length of this descriptor in bytes. All endpoint
+ * descriptors are 7 bytes long.
+ */
+ uint8 bLength;
+
+ /**
+ * @brief The type of the descriptor. For an endpoint descriptor, this
+ * will be USB_DTYPE_ENDPOINT (5).
+ */
+ uint8 bDescriptorType;
+
+ /**
+ * @brief The address of the endpoint. This field contains the endpoint
+ * number ORed with flag USB_EP_DESC_OUT or USB_EP_DESC_IN to
+ * indicate the endpoint direction.
+ */
+ uint8 bEndpointAddress;
+
+ /**
+ * @brief The endpoint transfer type, USB_EP_ATTR_CONTROL,
+ * USB_EP_ATTR_ISOC, USB_EP_ATTR_BULK or USB_EP_ATTR_INT and,
+ * if isochronous, additional flags indicating usage type and
+ * synchronization method.
+ */
+ uint8 bmAttributes;
+
+ /**
+ * @brief The maximum packet size this endpoint is capable of sending or
+ * receiving when this configuration is selected. For high speed
+ * isochronous or interrupt endpoints, bits 11 and 12 are used to
+ * pass additional information.
+ */
+ uint16 wMaxPacketSize;
+
+ /**
+ * @brief The polling interval for data transfers expressed in frames or
+ * micro frames depending upon the operating speed.
+ */
+ uint8 bInterval;
+}
+PACKED tEndpointDescriptor;
+
+/******************************************************************************
+ *
+ * Flags used in constructing the value assigned to the field
+ * tEndpointDescriptor.bEndpointAddress.
+ *
+ *****************************************************************************/
+#define USB_EP_DESC_OUT 0x00u
+#define USB_EP_DESC_IN 0x80u
+#define USB_EP_DESC_NUM_M 0x0fu
+
+/******************************************************************************
+ *
+ * Mask used to extract the maximum packet size (in bytes) from the
+ * wMaxPacketSize field of the endpoint descriptor.
+ *
+ *****************************************************************************/
+#define USB_EP_MAX_PACKET_COUNT_M 0x07FFu
+
+/******************************************************************************
+ *
+ * Endpoint attributes used in tEndpointDescriptor.bmAttributes.
+ *
+ *****************************************************************************/
+#define USB_EP_ATTR_CONTROL 0x00u
+#define USB_EP_ATTR_ISOC 0x01u
+#define USB_EP_ATTR_BULK 0x02u
+#define USB_EP_ATTR_INT 0x03u
+#define USB_EP_ATTR_TYPE_M 0x03u
+
+#define USB_EP_ATTR_ISOC_M 0x0cu
+#define USB_EP_ATTR_ISOC_NOSYNC 0x00u
+#define USB_EP_ATTR_ISOC_ASYNC 0x04u
+#define USB_EP_ATTR_ISOC_ADAPT 0x08u
+#define USB_EP_ATTR_ISOC_SYNC 0x0cu
+#define USB_EP_ATTR_USAGE_M 0x30u
+#define USB_EP_ATTR_USAGE_DATA 0x00u
+#define USB_EP_ATTR_USAGE_FEEDBACK 0x10u
+#define USB_EP_ATTR_USAGE_IMPFEEDBACK 0x20u
+
+/** ***************************************************************************
+ *
+ * @brief This structure describes the USB string descriptor for index 0 as
+ * defined in USB 2.0 specification section 9.6.7. Note that the
+ * number of language IDs is variable and can be determined by
+ * examining bLength. The number of language IDs present in the
+ * descriptor is given by ((bLength - 2) / 2).
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The length of this descriptor in bytes. This value will vary
+ * depending upon the number of language codes provided in the
+ * descriptor.
+ */
+ uint8 bLength;
+
+ /**
+ * @brief The type of the descriptor. For a string descriptor, this will
+ * be USB_DTYPE_STRING (3).
+ */
+ uint8 bDescriptorType;
+
+ /**
+ * @brief The language code (LANGID) for the first supported language.
+ * Note that this descriptor may support multiple languages, in
+ * which case, the number of elements in the wLANGID array will
+ * increase and bLength will be updated accordingly.
+ */
+ uint16 wLANGID[1];
+}
+PACKED tString0Descriptor;
+
+/** ***************************************************************************
+ *
+ * @brief This structure describes the USB string descriptor for all string
+ * indexes other than 0 as defined in USB 2.0 specification
+ * section 9.6.7.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The length of this descriptor in bytes. This value will be
+ * 2 greater than the number of bytes comprising the UNICODE
+ * string that the descriptor contains.
+ */
+ uint8 bLength;
+
+ /**
+ * @brief The type of the descriptor. For a string descriptor, this will
+ * be USB_DTYPE_STRING (3).
+ */
+ uint8 bDescriptorType;
+
+ /**
+ * @brief The first byte of the UNICODE string. This string is not NULL
+ * terminated. Its length (in bytes) can be computed by
+ * subtracting 2 from the value in the bLength field.
+ */
+ uint8 bString;
+}
+PACKED tStringDescriptor;
+
+/** ***************************************************************************
+ *
+ * Write a 2 byte uint16 value to a USB descriptor block.
+ *
+ * @param usValue is the two byte uint16 that is to be written to
+ * the descriptor.
+ *
+ * This helper macro is used in descriptor definitions to write two-byte
+ * values. Since the configuration descriptor contains all interface and
+ * endpoint descriptors in a contiguous block of memory, these descriptors are
+ * typically defined using an array of bytes rather than as packed structures.
+ *
+ * @return Not a function.
+ *
+ *****************************************************************************/
+#define USBShort(usValue) (uint8_t)((uint16_t)(usValue) & (uint16_t)0x00ffU), (uint8_t)((uint16_t)(usValue) >> 8U)
+
+/** ***************************************************************************
+ *
+ * Write a 3 byte uint32 value to a USB descriptor block.
+ *
+ * @param ulValue is the three byte unsigned value that is to be written to the
+ * descriptor.
+ *
+ * This helper macro is used in descriptor definitions to write three-byte
+ * values. Since the configuration descriptor contains all interface and
+ * endpoint descriptors in a contiguous block of memory, these descriptors are
+ * typically defined using an array of bytes rather than as packed structures.
+ *
+ * @return Not a function.
+ *
+ *****************************************************************************/
+#define USB3Byte(ulValue) (ulValue & 0xff), \
+ ((ulValue >> 8) & 0xff), \
+ ((ulValue >> 16) & 0xff)
+
+/** ***************************************************************************
+ *
+ * Write a 4 byte uint32 value to a USB descriptor block.
+ *
+ * @param ulValue is the four byte uint32 that is to be written to the
+ * descriptor.
+ *
+ * This helper macro is used in descriptor definitions to write four-byte
+ * values. Since the configuration descriptor contains all interface and
+ * endpoint descriptors in a contiguous block of memory, these descriptors are
+ * typically defined using an array of bytes rather than as packed structures.
+ *
+ * @return Not a function.
+ *
+ *****************************************************************************/
+#define USBLong(ulValue) (ulValue & 0xff), \
+ ((ulValue >> 8) & 0xff), \
+ ((ulValue >> 16) & 0xff), \
+ ((ulValue >> 24) & 0xff)
+
+/** ***************************************************************************
+ *
+ * Traverse to the next USB descriptor in a block.
+ *
+ * @param ptr points to the first byte of a descriptor in a block of
+ * USB descriptors.
+ *
+ * This macro aids in traversing lists of descriptors by returning a pointer
+ * to the next descriptor in the list given a pointer to the current one.
+ *
+ * @return Returns a pointer to the next descriptor in the block following
+ * @e ptr.
+ *
+ *****************************************************************************/
+#define NEXT_USB_DESCRIPTOR(ptr) \
+ (tDescriptorHeader *)(((uint8 *)(ptr)) + \
+ (ptr)->bLength)
+
+/******************************************************************************
+ *
+ * Return to default packing when using the IAR Embedded Workbench compiler.
+ *
+ *****************************************************************************/
+#if defined(ewarm) || defined(__IAR_SYSTEMS_ICC__)
+#pragma pack()
+#endif
+
+/** ***************************************************************************
+ *
+ * Close the usbchap9_src Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @ingroup device_api
+ * @{
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief Function prototype for any standard USB request.
+ *
+ *****************************************************************************/
+typedef void (* tStdRequest)(void * pvInstance, tUSBRequest * pUSBRequest);
+
+/** ***************************************************************************
+ *
+ * @brief Data callback for receiving data from an endpoint.
+ *
+ *****************************************************************************/
+typedef void (* tInfoCallback)(void * pvInstance, uint32 ulInfo);
+
+/** ***************************************************************************
+ *
+ * @brief Callback made to indicate that an interface alternate setting
+ * change has occurred.
+ *
+ *****************************************************************************/
+typedef void (* tInterfaceCallback)(void * pvInstance,
+ uint8 ucInterfaceNum,
+ uint8 ucAlternateSetting);
+
+/** ***************************************************************************
+ *
+ * @brief Generic interrupt handler callbacks.
+ *
+ *****************************************************************************/
+typedef void (* tUSBIntHandler)(void * pvInstance);
+
+/** ***************************************************************************
+ *
+ * @brief Interrupt handler callbacks that have status information.
+ *
+ *****************************************************************************/
+typedef void (* tUSBEPIntHandler)(void * pvInstance,
+ uint32 ulStatus);
+
+/** ***************************************************************************
+ *
+ * @brief Generic handler callbacks that are used when the callers needs to
+ * call into an instance of class.
+ *
+ *****************************************************************************/
+typedef void (* tUSBDeviceHandler)(void * pvInstance,
+ uint32 ulRequest,
+ void * pvRequestData);
+
+/** ***************************************************************************
+ *
+ * @brief USB event handler functions used during enumeration and operation
+ * of the device stack.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief This callback is made whenever the USB host requests a
+ * non-standard descriptor from the device.
+ */
+ tStdRequest pfnGetDescriptor;
+
+ /**
+ * @brief This callback is made whenever the USB host makes a
+ * non-standard request.
+ */
+ tStdRequest pfnRequestHandler;
+
+ /**
+ * @brief This callback is made in response to a SetInterface request
+ * from the host.
+ */
+ tInterfaceCallback pfnInterfaceChange;
+
+ /**
+ * @brief This callback is made in response to a SetConfiguration
+ * request from the host.
+ */
+ tInfoCallback pfnConfigChange;
+
+ /**
+ * @brief This callback is made when data has been received following
+ * to a call to USBDCDRequestDataEP0.
+ */
+ tInfoCallback pfnDataReceived;
+
+ /**
+ * @brief This callback is made when data has been transmitted following
+ * a call to USBDCDSendDataEP0.
+ */
+ tInfoCallback pfnDataSent;
+
+ /**
+ * @brief This callback is made when a USB reset is detected.
+ */
+ tUSBIntHandler pfnResetHandler;
+
+ /**
+ * @brief This callback is made when the bus has been inactive long
+ * enough to trigger a suspend condition.
+ */
+ tUSBIntHandler pfnSuspendHandler;
+
+ /**
+ * @brief This is called when resume signaling is detected.
+ */
+ tUSBIntHandler pfnResumeHandler;
+
+ /**
+ * @brief This callback is made when the device is disconnected from
+ * the USB bus.
+ */
+ tUSBIntHandler pfnDisconnectHandler;
+
+ /**
+ * @brief This callback is made to inform the device of activity on
+ * all endpoints other than endpoint zero.
+ */
+ tUSBEPIntHandler pfnEndpointHandler;
+
+ /**
+ * @brief This generic handler is provided to allow requests based on
+ * a given instance to be passed into a device. This is commonly
+ * used by a top level composite device that is using multiple
+ * instances of a class.
+ */
+ tUSBDeviceHandler pfnDeviceHandler;
+}
+tCustomHandlers;
+
+/** ***************************************************************************
+ *
+ * @brief This structure defines how a given endpoint's FIFO is configured in
+ * relation to the maximum packet size for the endpoint as specified
+ * in the endpoint descriptor.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The multiplier to apply to an endpoint's maximum packet size
+ * when configuring the FIFO for that endpoint. For example,
+ * setting this value to 2 will result in a 128 byte FIFO being
+ * configured if bDoubleBuffer is FALSE and the associated
+ * endpoint is set to use a 64 byte maximum packet size.
+ */
+ uint8 cMultiplier;
+
+ /**
+ * @brief This field indicates whether to configure an endpoint's FIFO
+ * to be double- or single-buffered. If TRUE, a double-buffered
+ * FIFO is created and the amount of required FIFO storage is
+ * multiplied by two.
+ */
+ tBoolean bDoubleBuffer;
+
+ /**
+ * @brief This field defines endpoint mode flags which cannot be deduced
+ * from the configuration descriptor, namely any in the set
+ * USB_EP_AUTO_xxx or USB_EP_DMA_MODE_x. USBDCDConfig adds these
+ * flags to the endpoint mode and direction determined from the
+ * config descriptor before it configures the endpoint using a
+ * call to USBDevEndpointConfigSet().
+ */
+ uint16 usEPFlags;
+}
+tFIFOEntry;
+
+/** ***************************************************************************
+ *
+ * @brief This structure defines endpoint and FIFO configuration information
+ * for all endpoints that the device wishes to use. This information
+ * cannot be determined by examining the USB configuration descriptor
+ * and is provided to USBDCDConfig by the application to allow the USB
+ * controller endpoints to be correctly configured.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief An array containing one FIFO entry for each of the IN
+ * endpoints. Note that endpoint 0 is configured and managed by
+ * the USB device stack so is excluded from this array. The
+ * index 0 entry of the array corresponds to endpoint 1,
+ * index 1 to endpoint 2, etc.
+ */
+ tFIFOEntry sIn[USBLIB_NUM_EP - 1];
+
+ /**
+ * @brief An array containing one FIFO entry for each of the OUT
+ * endpoints. Note that endpoint 0 is configured and managed by
+ * the USB device stack so is excluded from this array.
+ * The index 0 entry of the array corresponds to endpoint 1,
+ * index 1 to endpoint 2, etc.
+ */
+ tFIFOEntry sOut[USBLIB_NUM_EP - 1];
+}
+tFIFOConfig;
+
+/** ***************************************************************************
+ *
+ * @brief This structure defines a contiguous block of data which contains a
+ * group of descriptors that form part of a configuration descriptor
+ * for a device. It is assumed that a config section contains only
+ * whole descriptors. It is not valid to split a single descriptor
+ * across multiple sections.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The number of bytes of descriptor data pointed to by pucData.
+ */
+ uint8 ucSize;
+
+ /**
+ * @brief A pointer to a block of data containing an integral number of
+ * SB descriptors which form part of a larger configuration
+ * descriptor.
+ */
+ const uint8 * pucData;
+}
+tConfigSection;
+
+/** ***************************************************************************
+ *
+ * @brief This is the top level structure defining a USB device configuration
+ * descriptor. A configuration descriptor contains a collection of
+ * device-specific descriptors in addition to the basic config,
+ * interface and endpoint descriptors. To allow flexibility in
+ * constructing the configuration, the descriptor is described in
+ * terms of a list of data blocks. The first block must contain the
+ * configuration descriptor itself and the following blocks are
+ * appended to this in order to produce the full descriptor sent to
+ * the host in response to a GetDescriptor request for the
+ * configuration descriptor.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The number of sections comprising the full descriptor for this
+ * configuration.
+ */
+ uint8 ucNumSections;
+
+ /**
+ * @brief A pointer to an array of ucNumSections section pointers which
+ * must be concatenated to form the configuration descriptor.
+ */
+ const tConfigSection * const * psSections;
+}
+tConfigHeader;
+
+/** ***************************************************************************
+ *
+ * @brief This structure is passed to the USB library on a call to USBDCDInit
+ * and provides the library with information about the device that the
+ * application is implementing. It contains functions pointers for
+ * the various USB event handlers and pointers to each of the standard
+ * device descriptors.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief A pointer to a structure containing pointers to event handler
+ * functions provided by the client to support the operation of
+ * this device.
+ */
+ tCustomHandlers sCallbacks;
+
+ /**
+ * @brief A pointer to the device descriptor for this device.
+ */
+ const uint8 * pDeviceDescriptor;
+
+ /**
+ * @brief A pointer to an array of configuration descriptor pointers.
+ * Each entry in the array corresponds to one configuration that
+ * the device may be set to use by the USB host. The number of
+ * entries in the array must match the bNumConfigurations value
+ * in the device descriptor array, pDeviceDescriptor.
+ */
+ const tConfigHeader * const * ppConfigDescriptors;
+
+ /**
+ * @brief A pointer to the string descriptor array for this device.
+ * This array must be arranged as follows:
+ *
+ * - [0] - Standard descriptor containing supported language codes.
+ * - [1] - String 1 for the first language listed in descriptor 0.
+ * - [2] - String 2 for the first language listed in descriptor 0.
+ * - ...
+ * - [n] - String n for the first language listed in descriptor 0.
+ * - [n+1] - String 1 for the second language listed in descriptor 0.
+ * - ...
+ * - [2n] - String n for the second language listed in descriptor 0.
+ * - [2n+1]- String 1 for the third language listed in descriptor 0.
+ * - ...
+ * - [3n] - String n for the third language listed in descriptor 0.
+ *
+ * and so on.
+ */
+ const uint8 * const * ppStringDescriptors;
+
+ /**
+ * @brief The total number of descriptors provided in the ppStringDescriptors
+ * array.
+ */
+ uint32 ulNumStringDescriptors;
+
+ /**
+ * @brief A structure defining how the USB controller FIFO is to be
+ * partitioned between the various endpoints. This member can be
+ * set to point to g_sUSBDefaultFIFOConfig if the default FIFO
+ * configuration is acceptable. This configuration sets each
+ * endpoint FIFO to be single buffered and sized to hold the
+ * maximum packet size for the endpoint.
+ */
+ const tFIFOConfig * psFIFOConfig;
+
+ /**
+ * @brief This value will be passed back to all call back functions so
+ * that they have access to individual instance data based on the
+ * this pointer.
+ */
+ void * pvInstance;
+}
+tDeviceInfo;
+
+/** ***************************************************************************
+ *
+ * Close the Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @ingroup general_usblib_api
+ * @{
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * USB descriptor parsing functions found in usbdesc.c
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief The USB_DESC_ANY label is used as a wild card in several of the
+ * descriptor parsing APIs to determine whether or not particular
+ * search criteria should be ignored.
+ *
+ *****************************************************************************/
+#define USB_DESC_ANY 0xFFFFFFFFu
+
+extern uint32 USBDescGetNum(tDescriptorHeader * psDesc,
+ uint32 ulSize, uint32 ulType);
+extern tDescriptorHeader * USBDescGet(tDescriptorHeader * psDesc,
+ uint32 ulSize,
+ uint32 ulType,
+ uint32 ulIndex);
+extern uint32
+ USBDescGetNumAlternateInterfaces(tConfigDescriptor * psConfig,
+ uint8 ucInterfaceNumber);
+extern tInterfaceDescriptor * USBDescGetInterface(tConfigDescriptor * psConfig,
+ uint32 ulIndex,
+ uint32 ulAltCfg);
+extern tEndpointDescriptor *
+ USBDescGetInterfaceEndpoint(tInterfaceDescriptor * psInterface,
+ uint32 ulIndex,
+ uint32 ulSize);
+
+/** ***************************************************************************
+ *
+ * The operating mode required by the USB library client. This type is used
+ * by applications which wish to be able to switch between host and device
+ * modes by calling the USBStackModeSet() API.
+ *
+ *****************************************************************************/
+typedef enum
+{
+ /**
+ * @brief The application wishes to operate as a USB device.
+ */
+ USB_MODE_DEVICE = 0,
+
+ /**
+ * @brief The application wishes to operate as a USB host.
+ */
+ USB_MODE_HOST,
+
+ /**
+ * @brief The application wishes to operate as both a host and device
+ * using On-The-Go protocols to negotiate.
+ */
+ USB_MODE_OTG,
+
+ /**
+ * @brief A marker indicating that no USB mode has yet been set by the
+ * application.
+ */
+ USB_MODE_NONE
+} tUSBMode;
+
+/** ***************************************************************************
+ *
+ * A pointer to a USB mode callback function. This function is called by the
+ * USB library to indicate to the application which operating mode it should
+ * use, host or device.
+ *
+ *****************************************************************************/
+typedef void (* tUSBModeCallback)(uint32 ulIndex, tUSBMode eMode);
+
+/** ***************************************************************************
+ *
+ * Mode selection and dual mode interrupt steering functions.
+ *
+ *****************************************************************************/
+extern void USBStackModeSet(uint32 ulIndex, tUSBMode eUSBMode,
+ tUSBModeCallback pfnCallback);
+extern void USBDualModeInit(uint32 ulIndex);
+extern void USBDualModeTerm(uint32 ulIndex);
+extern void USBOTGMain(uint32 ulMsTicks);
+extern void USBOTGPollRate(uint32 ulIndex, uint32 ulPollRate);
+extern void USBOTGModeInit(uint32 ulIndex, uint32 ulPollRate,
+ void * pHostData, uint32 ulHostDataSize);
+extern void USBOTGModeTerm(uint32 ulIndex);
+extern void USB0OTGModeIntHandler(void);
+extern void USB0DualModeIntHandler(void);
+
+/** ***************************************************************************
+ *
+ * USB callback function.
+ *
+ * @param pvCBData is the callback pointer associated with the instance
+ * generating the callback. This is a value provided by the client during
+ * initialization of the instance making the callback.
+ * @param ulEvent is the identifier of the asynchronous event which is being
+ * notified to the client.
+ * @param ulMsgParam is an event-specific parameter.
+ * @param pvMsgData is an event-specific data pointer.
+ *
+ * A function pointer provided to the USB layer by the application
+ * which will be called to notify it of all asynchronous events relating to
+ * data transmission or reception. This callback is used by device class
+ * drivers and host pipe functions.
+ *
+ * @return Returns an event-dependent value.
+ *
+ *****************************************************************************/
+typedef uint32 (* tUSBCallback)(void * pvCBData, uint32 ulEvent,
+ uint32 ulMsgParam,
+ void * pvMsgData);
+
+/** ***************************************************************************
+ *
+ * Base identifiers for groups of USB events. These are used by both the
+ * device class drivers and host layer.
+ *
+ * USB_CLASS_EVENT_BASE is the lowest identifier that should be used for
+ * a class-specific event. Individual event bases are defined for each
+ * of the supported device class drivers. Events with IDs between
+ * USB_EVENT_BASE and USB_CLASS_EVENT_BASE are reserved for stack use.
+ *
+ *****************************************************************************/
+#define USB_EVENT_BASE 0x0000u
+#define USB_CLASS_EVENT_BASE 0x8000u
+
+/** ***************************************************************************
+ *
+ * Event base identifiers for the various device classes supported in host
+ * and device modes.
+ * The first 0x800 values of a range are reserved for the device specific
+ * messages and the second 0x800 values of a range are used for the host
+ * specific messages for a given class.
+ *
+ *****************************************************************************/
+#define USBD_CDC_EVENT_BASE (USB_CLASS_EVENT_BASE + 0u)
+#define USBD_HID_EVENT_BASE (USB_CLASS_EVENT_BASE + 0x1000u)
+#define USBD_HID_KEYB_EVENT_BASE (USBD_HID_EVENT_BASE + 0x100u)
+#define USBD_BULK_EVENT_BASE (USB_CLASS_EVENT_BASE + 0x2000u)
+#define USBD_MSC_EVENT_BASE (USB_CLASS_EVENT_BASE + 0x3000u)
+#define USBD_AUDIO_EVENT_BASE (USB_CLASS_EVENT_BASE + 0x4000u)
+
+#define USBH_CDC_EVENT_BASE (USBD_CDC_EVENT_BASE + 0x800u)
+#define USBH_HID_EVENT_BASE (USBD_HID_EVENT_BASE + 0x800u)
+#define USBH_BULK_EVENT_BASE (USBD_BULK_EVENT_BASE + 0x800u)
+#define USBH_MSC_EVENT_BASE (USBD_MSC_EVENT_BASE + 0x800u)
+#define USBH_AUDIO_EVENT_BASE (USBD_AUDIO_EVENT_BASE + 0x800u)
+
+/** ***************************************************************************
+ *
+ * General events supported by device classes and host pipes.
+ *
+ *****************************************************************************/
+
+/**
+ * @brief The device is now attached to a USB host and ready to begin sending
+ * and receiving data (used by device classes only).
+ */
+#define USB_EVENT_CONNECTED (USB_EVENT_BASE + 0u)
+
+/**
+ * @brief The device has been disconnected from the USB host (used by device
+ * classes only).
+ *
+ * Note: Due to a hardware erratum in revision A of LM3S3748, this
+ * event is not posted to self-powered USB devices when they are disconnected
+ * from the USB host.
+ */
+#define USB_EVENT_DISCONNECTED (USB_EVENT_BASE + 1u)
+
+/**
+ * @brief Data has been received and is in the buffer provided.
+ */
+#define USB_EVENT_RX_AVAILABLE (USB_EVENT_BASE + 2u)
+
+/**
+ * @brief This event is sent by a lower layer to inquire about the amount of
+ * unprocessed data buffered in the layers above. It is used in
+ * cases where a low level driver needs to ensure that all preceding
+ * data has been processed prior to performing some action or making
+ * some notification. Clients receiving this event should return the
+ * number of bytes of data that are unprocessed or 0 if no outstanding
+ * data remains.
+ */
+#define USB_EVENT_DATA_REMAINING (USB_EVENT_BASE + 3u)
+
+/**
+ * @brief This event is sent by a lower layer supporting DMA to request a
+ * buffer in which the next received packet may be stored.
+ * The \e ulMsgValue parameter indicates the maximum size of packet
+ * that can be received in this channel and \e pvMsgData points to
+ * storage which should be written with the returned buffer pointer.
+ * The return value from the callback should be the size of the buffer
+ * allocated (which may be less than the maximum size passed in
+ * \e ulMsgValue if the client knows that fewer bytes are expected
+ * to be received) or 0 if no buffer is being returned.
+ */
+#define USB_EVENT_REQUEST_BUFFER (USB_EVENT_BASE + 4u)
+
+/**
+ * @brief Data has been sent and acknowledged. If this event is received via
+ * the USB buffer callback, the \e ulMsgValue parameter indicates the
+ * number of bytes from the transmit buffer that have been successfully
+ * transmitted and acknowledged.
+ */
+#define USB_EVENT_TX_COMPLETE (USB_EVENT_BASE + 5u)
+
+/**
+ * @brief An error has been reported on the channel or pipe. The
+ * \e ulMsgValue parameter indicates the source(s) of the error and
+ * is the logical OR combination of "USBERR_" flags defined below.
+ */
+#define USB_EVENT_ERROR (USB_EVENT_BASE + 6u)
+
+/**
+ * @brief The bus has entered suspend state.
+ */
+#define USB_EVENT_SUSPEND (USB_EVENT_BASE + 7u)
+
+/**
+ * @brief The bus has left suspend state.
+ */
+#define USB_EVENT_RESUME (USB_EVENT_BASE + 8u)
+
+/**
+ * @brief A scheduler event has occurred.
+ */
+#define USB_EVENT_SCHEDULER (USB_EVENT_BASE + 9u)
+/**
+ * @brief A device or host has detected a stall condition.
+ */
+#define USB_EVENT_STALL (USB_EVENT_BASE + 10u)
+
+/**
+ * @brief The host detected a power fault condition.
+ */
+#define USB_EVENT_POWER_FAULT (USB_EVENT_BASE + 11u)
+
+/**
+ * @brief The controller has detected a A-Side cable and needs power applied.
+ * This is only generated on OTG parts if automatic power control is
+ * disabled.
+ */
+#define USB_EVENT_POWER_ENABLE (USB_EVENT_BASE + 12u)
+
+/**
+ * @brief The controller needs power removed, This is only generated on OTG
+ * parts if automatic power control is disabled.
+ */
+#define USB_EVENT_POWER_DISABLE (USB_EVENT_BASE + 13u)
+
+/**
+ * @brief Used with pfnDeviceHandler handler function is classes to indicate
+ * changes in the interface number by a class outside the class being
+ * accessed. Typically this is when composite device class is in use.
+ *
+ * The \e pvInstance value should point to an instance of the device being
+ * accessed.
+ *
+ * The \e ulRequest should be USB_EVENT_COMP_IFACE_CHANGE.
+ *
+ * The \e pvRequestData should point to a two byte array where the first value
+ * is the old interface number and the second is the new interface number.
+ */
+#define USB_EVENT_COMP_IFACE_CHANGE (USB_EVENT_BASE + 14u)
+
+/**
+ * @brief Used with pfnDeviceHandler handler function is classes to indicate
+ * changes in endpoint number by a class outside the class being
+ * accessed. Typically this is when composite device class is in use.
+ *
+ * The \e pvInstance value should point to an instance of the device being
+ * accessed.
+ *
+ * The \e ulRequest should be USB_EVENT_COMP_EP_CHANGE.
+ *
+ * The \e pvRequestData should point to a two byte array where the first value
+ * is the old endpoint number and the second is the new endpoint number. The
+ * endpoint numbers should be exactly as USB specification defines them and
+ * bit 7 set indicates an IN endpoint and bit 7 clear indicates an OUT
+ * endpoint.
+ */
+#define USB_EVENT_COMP_EP_CHANGE (USB_EVENT_BASE + 15u)
+
+/**
+ * @brief Used with pfnDeviceHandler handler function is classes to indicate
+ * changes in string index number by a class outside the class being
+ * accessed. Typically this is when composite device class is in use.
+ *
+ * The \e pvInstance value should point to an instance of the device being
+ * accessed.
+ *
+ * The \e ulRequest should be USB_EVENT_COMP_STR_CHANGE.
+ *
+ * The \e pvRequestData should point to a two byte array where the first value
+ * is the old string index and the second is the new string index.
+ */
+#define USB_EVENT_COMP_STR_CHANGE (USB_EVENT_BASE + 16u)
+
+/**
+ * @brief Used with pfnDeviceHandler handler function is classes to allow the
+ * device class to make final adjustments to the configuration
+ * descriptor. This is only used when a device class is used in a
+ * composite device class is in use.
+ *
+ * The \e pvInstance value should point to an instance of the device being
+ * accessed.
+ *
+ * The \e ulRequest should be USB_EVENT_COMP_CONFIG.
+ *
+ * The \e pvRequestData should point to the beginning of the configuration
+ * descriptor for the device instance.
+ */
+#define USB_EVENT_COMP_CONFIG (USB_EVENT_BASE + 17u)
+
+/** ***************************************************************************
+ *
+ * Error sources reported via USB_EVENT_ERROR.
+ *
+ *****************************************************************************/
+
+/**
+ * @brief The host received an invalid PID in a transaction.
+ */
+#define USBERR_HOST_IN_PID_ERROR 0x01000000u
+
+/**
+ * @brief The host did not receive a response from a device.
+ */
+#define USBERR_HOST_IN_NOT_COMP 0x00100000u
+
+/**
+ * @brief The host received a stall on an IN endpoint.
+ */
+#define USBERR_HOST_IN_STALL 0x00400000u
+
+/**
+ * @brief The host detected a CRC or bit-stuffing error (isochronous mode).
+ */
+#define USBERR_HOST_IN_DATA_ERROR 0x00080000u
+
+/**
+ * @brief The host received NAK on an IN endpoint for longer than the
+ * specified timeout period (interrupt, bulk and control modes).
+ */
+#define USBERR_HOST_IN_NAK_TO 0x00080000u
+
+/**
+ * @brief The host failed to communicate with a device via an IN endpoint.
+ */
+#define USBERR_HOST_IN_ERROR 0x00040000u
+
+/**
+ * @brief The host receive FIFO is full.
+ */
+#define USBERR_HOST_IN_FIFO_FULL 0x00020000u /* RX FIFO full */
+/**
+ * @brief The host received NAK on an OUT endpoint for longer than the
+ * specified timeout period (bulk, interrupt and control modes).
+ */
+#define USBERR_HOST_OUT_NAK_TO 0x00000080u
+
+/**
+ * @brief The host did not receive a response from a device (isochronous mode).
+ */
+#define USBERR_HOST_OUT_NOT_COMP 0x00000080u
+
+/**
+ * @brief The host received a stall on an OUT endpoint.
+ */
+#define USBERR_HOST_OUT_STALL 0x00000020u
+
+/**
+ * @brief The host failed to communicate with a device via an OUT endpoint.
+ */
+#define USBERR_HOST_OUT_ERROR 0x00000004u
+
+/**
+ * @brief The host received NAK on endpoint 0 for longer than the configured
+ * timeout.
+ */
+#define USBERR_HOST_EP0_NAK_TO 0x00000080u
+
+/**
+ * @brief The host failed to communicate with a device via an endpoint zero.
+ */
+#define USBERR_HOST_EP0_ERROR 0x00000010u
+
+/**
+ * @brief The device detected a CRC error in received data.
+ */
+#define USBERR_DEV_RX_DATA_ERROR 0x00080000u
+
+/**
+ * @brief The device was unable to receive a packet from the host since the
+ * receive FIFO is full.
+ */
+#define USBERR_DEV_RX_OVERRUN 0x00040000u
+
+/**
+ * @brief The device receive FIFO is full.
+ */
+#define USBERR_DEV_RX_FIFO_FULL 0x00020000u /* RX FIFO full */
+
+/** ***************************************************************************
+ *
+ * Close the general_usblib_api Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @ingroup usblib_buffer_api
+ * @{
+ *
+ *****************************************************************************/
+
+/** ***************************************************************************
+ *
+ * @brief A function pointer type which describes either a class driver
+ * packet read or packet write function (both have the same prototype)
+ * to the USB buffer object.
+ *
+ *****************************************************************************/
+typedef uint32 (* tUSBPacketTransfer)(void * pvHandle,
+ uint8 * pcData,
+ uint32 ulLength,
+ tBoolean bLast);
+
+/** ***************************************************************************
+ *
+ * @brief A function pointer type which describes either a class driver
+ * transmit or receive packet available function (both have the same
+ * prototype) to the USB buffer object.
+ *
+ *****************************************************************************/
+typedef uint32 (* tUSBPacketAvailable)(void * pvHandle);
+
+/** ***************************************************************************
+ *
+ * @brief The number of bytes of workspace that each USB buffer object
+ * requires. This workspace memory is provided to the buffer on
+ * USBBufferInit() in the \e pvWorkspace field of the \e tUSBBuffer
+ * structure.
+ *
+ *****************************************************************************/
+#define USB_BUFFER_WORKSPACE_SIZE 16
+
+/** ***************************************************************************
+ *
+ * @brief The structure used by the application to initialize a buffer object
+ * that will provide buffered access to either a transmit or receive
+ * channel.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief This field sets the mode of the buffer. If TRUE, the buffer
+ * operates as a transmit buffer and supports calls to
+ * USBBufferWrite by the client. If FALSE, the buffer operates
+ * as a receive buffer and supports calls to USBBufferRead.
+ */
+ tBoolean bTransmitBuffer;
+
+ /**
+ * @brief A pointer to the callback function which will be called to
+ * notify the application of all asynchronous events related to
+ * the operation of the buffer.
+ */
+ tUSBCallback pfnCBack;
+
+ /**
+ * @brief A pointer that the buffer will pass back to the client in the
+ * first parameter of all callbacks related to this instance.
+ */
+ void * pvCBData;
+
+ /**
+ * @brief The function which should be called to transmit a packet of
+ * data in transmit mode or receive a packet in receive mode.
+ */
+ tUSBPacketTransfer pfnTransfer;
+
+ /**
+ * @brief The function which should be called to determine if the
+ * endpoint is ready to accept a new packet for transmission in
+ * transmit mode or to determine the size of the buffer required
+ * to read a packet in receive mode.
+ */
+ tUSBPacketAvailable pfnAvailable;
+
+ /**
+ * @brief The handle to pass to the low level function pointers provided
+ * in the pfnTransfer and pfnAvailable members. For USB device
+ * use, this is the psDevice parameter required by the relevant
+ * device class driver APIs. For USB host use, this is the pipe
+ * identifier returned by USBHCDPipeAlloc.
+ */
+ void * pvHandle;
+
+ /**
+ * @brief A pointer to memory to be used as the ring buffer for this
+ * instance.
+ */
+ uint8 * pcBuffer;
+
+ /**
+ * @brief The size, in bytes, of the buffer pointed to by pcBuffer.
+ */
+ uint32 ulBufferSize;
+
+ /**
+ * @brief A pointer to USB_BUFFER_WORKSPACE_SIZE bytes of RAM that the
+ * buffer object can use for workspace.
+ */
+ void * pvWorkspace;
+}
+tUSBBuffer;
+
+/** ***************************************************************************
+ *
+ * @brief The structure used for encapsulating all the items associated with
+ * a ring buffer.
+ *
+ *****************************************************************************/
+typedef struct
+{
+ /**
+ * @brief The ring buffer size.
+ */
+ uint32 ulSize;
+
+ /**
+ * @brief The ring buffer write index.
+ */
+ volatile uint32 ulWriteIndex;
+
+ /**
+ * @brief The ring buffer read index.
+ */
+ volatile uint32 ulReadIndex;
+
+ /**
+ * @brief The ring buffer.
+ */
+ uint8 * pucBuf;
+}
+tUSBRingBufObject;
+
+/** ***************************************************************************
+ *
+ * USB buffer API function prototypes.
+ *
+ *****************************************************************************/
+extern const tUSBBuffer * USBBufferInit(const tUSBBuffer * psBuffer);
+extern void USBBufferInfoGet(const tUSBBuffer * psBuffer,
+ tUSBRingBufObject * psRingBuf);
+extern void * USBBufferCallbackDataSet(tUSBBuffer * psBuffer, void * pvCBData);
+extern uint32 USBBufferWrite(const tUSBBuffer * psBuffer,
+ const uint8 * pucData,
+ uint32 ulLength);
+extern void USBBufferDataWritten(const tUSBBuffer * psBuffer,
+ uint32 ulLength);
+extern void USBBufferDataRemoved(const tUSBBuffer * psBuffer,
+ uint32 ulLength);
+extern void USBBufferFlush(const tUSBBuffer * psBuffer);
+extern uint32 USBBufferRead(const tUSBBuffer * psBuffer,
+ uint8 * pucData,
+ uint32 ulLength);
+extern uint32 USBBufferDataAvailable(const tUSBBuffer * psBuffer);
+extern uint32 USBBufferSpaceAvailable(const tUSBBuffer * psBuffer);
+extern uint32 USBBufferEventCallback(void * pvCBData,
+ uint32 ulEvent,
+ uint32 ulMsgValue,
+ void * pvMsgData);
+extern tBoolean USBRingBufFull(tUSBRingBufObject * ptUSBRingBuf);
+extern tBoolean USBRingBufEmpty(tUSBRingBufObject * ptUSBRingBuf);
+extern void USBRingBufFlush(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufUsed(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufFree(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufContigUsed(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufContigFree(tUSBRingBufObject * ptUSBRingBuf);
+extern uint32 USBRingBufSize(tUSBRingBufObject * ptUSBRingBuf);
+extern uint8 USBRingBufReadOne(tUSBRingBufObject * ptUSBRingBuf);
+extern void USBRingBufRead(tUSBRingBufObject * ptUSBRingBuf,
+ uint8 * pucData, uint32 ulLength);
+extern void USBRingBufWriteOne(tUSBRingBufObject * ptUSBRingBuf,
+ uint8 ucData);
+extern void USBRingBufWrite(tUSBRingBufObject * ptUSBRingBuf,
+ const uint8 pucData[],
+ uint32 ulLength);
+extern void USBRingBufAdvanceWrite(tUSBRingBufObject * ptUSBRingBuf,
+ uint32 ulNumBytes);
+extern void USBRingBufAdvanceRead(tUSBRingBufObject * ptUSBRingBuf,
+ uint32 ulNumBytes);
+extern void USBRingBufInit(tUSBRingBufObject * ptUSBRingBuf,
+ uint8 * pucBuf, uint32 ulSize);
+
+/** ***************************************************************************
+ *
+ * Close the Doxygen group.
+ * @}
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Mark the end of the C bindings section for C++ compilers.
+ *
+ *****************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBLIB_H__ */
Index: firmware/source/adc.c
===================================================================
diff -u
--- firmware/source/adc.c (revision 0)
+++ firmware/source/adc.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1010 @@
+/** @file adc.c
+* @brief ADC Driver Source File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - API Functions
+* - Interrupt Handlers
+* .
+* which are relevant for the ADC driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "adc.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void adcInit(void)
+* @brief Initializes ADC Driver
+*
+* This function initializes the ADC driver.
+*
+*/
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+/* SourceId : ADC_SourceId_001 */
+/* DesignId : ADC_DesignId_001 */
+/* Requirements : HL_SR185 */
+void adcInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /** @b Initialize @b ADC1: */
+
+ /** - Reset ADC module */
+ adcREG1->RSTCR = 1U;
+ adcREG1->RSTCR = 0U;
+
+ /** - Enable 12-BIT ADC */
+ adcREG1->OPMODECR |= 0x80000000U;
+
+ /** - Setup prescaler */
+ adcREG1->CLOCKCR = 25U;
+
+ /** - Setup memory boundaries */
+ adcREG1->BNDCR = (uint32)((uint32)0U << 16U) | (0U + 10U);
+ adcREG1->BNDEND = (adcREG1->BNDEND & 0xFFFF0000U) | (2U);
+
+ /** - Setup event group conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG1->GxMODECR[0U] = (uint32)ADC_12_BIT
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U;
+
+ /** - Setup event group hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG1->EVSRC = (uint32)0x00000000U
+ | (uint32)ADC1_EVENT;
+
+ /** - Setup event group sample window */
+ adcREG1->EVSAMP = 0U;
+
+ /** - Setup event group sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG1->EVSAMPDISEN = (uint32)((uint32)0U << 8U)
+ | (uint32)0x00000000U;
+
+ /** - Setup group 1 conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG1->GxMODECR[1U] = (uint32)ADC_12_BIT
+ | (uint32)0x00000020U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U;
+
+ /** - Setup group 1 hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG1->G1SRC = (uint32)0x00000000U
+ | (uint32)ADC1_EVENT;
+
+ /** - Setup group 1 sample window */
+ adcREG1->G1SAMP = 0U;
+
+ /** - Setup group 1 sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG1->G1SAMPDISEN = (uint32)((uint32)0U << 8U)
+ | (uint32)0x00000000U;
+
+ /** - Setup group 2 conversion mode
+ * - Setup data format
+ * - Enable/Disable channel id in conversion result
+ * - Enable/Disable continuous conversion
+ */
+ adcREG1->GxMODECR[2U] = (uint32)ADC_12_BIT
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U;
+
+ /** - Setup group 2 hardware trigger
+ * - Setup hardware trigger edge
+ * - Setup hardware trigger source
+ */
+ adcREG1->G2SRC = (uint32)0x00000000U
+ | (uint32)ADC1_EVENT;
+
+ /** - Setup group 2 sample window */
+ adcREG1->G2SAMP = 0U;
+
+ /** - Setup group 2 sample discharge
+ * - Setup discharge prescaler
+ * - Enable/Disable discharge
+ */
+ adcREG1->G2SAMPDISEN = (uint32)((uint32)0U << 8U)
+ | (uint32)0x00000000U;
+
+ /** - ADC1 EVT pin output value */
+ adcREG1->EVTOUT = 0U;
+
+ /** - ADC1 EVT pin direction */
+ adcREG1->EVTDIR = 0U;
+
+ /** - ADC1 EVT pin open drain enable */
+ adcREG1->EVTPDR = 0U;
+
+ /** - ADC1 EVT pin pullup / pulldown selection */
+ adcREG1->EVTPSEL = 1U;
+
+ /** - ADC1 EVT pin pullup / pulldown enable*/
+ adcREG1->EVTDIS = 0U;
+
+ /** - Enable ADC module */
+ adcREG1->OPMODECR |= 0x80140001U;
+
+ /** - Wait for buffer initialization complete */
+ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */
+ while (((adcREG1->BNDEND & 0xFFFF0000U) >> 16U ) != 0U)
+ {
+ } /* Wait */
+
+ /** - Setup parity */
+ adcREG1->PARCR = 0x00000005U;
+
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+
+/** - s_adcSelect is used as constant table for channel selection */
+static const uint32 s_adcSelect[2U][3U] =
+{
+ {0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U,
+ 0x00000001U |
+ 0x00000002U |
+ 0x00000004U |
+ 0x00000008U |
+ 0x00000010U |
+ 0x00000020U |
+ 0x00000040U |
+ 0x00000080U |
+ 0x00000100U |
+ 0x00000000U |
+ 0x00000400U |
+ 0x00000800U |
+ 0x00001000U |
+ 0x00002000U |
+ 0x00004000U |
+ 0x00000000U |
+ 0x00010000U |
+ 0x00020000U |
+ 0x00040000U |
+ 0x00080000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00400000U |
+ 0x00800000U,
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U},
+ {0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U ,
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U,
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U |
+ 0x00000000U}
+};
+
+/** - s_adcFiFoSize is used as constant table for channel selection */
+static const uint32 s_adcFiFoSize[2U][3U] =
+{
+ {0U,
+ 20U,
+ 32U},
+ {16U,
+ 16U,
+ 16U}
+};
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group)
+* @brief Starts an ADC conversion
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function starts a conversion of the ADC hardware group.
+*
+*/
+/* SourceId : ADC_SourceId_002 */
+/* DesignId : ADC_DesignId_002 */
+/* Requirements : HL_SR186 */
+void adcStartConversion(adcBASE_t *adc, uint32 group)
+{
+ uint32 index = (adc == adcREG1) ? 0U : 1U;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ /** - Setup FiFo size */
+ adc->GxINTCR[group] = s_adcFiFoSize[index][group];
+
+ /** - Start Conversion */
+ adc->GxSEL[group] = s_adcSelect[index][group];
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+
+/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group)
+* @brief Stops an ADC conversion
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function stops a conversion of the ADC hardware group.
+*
+*/
+/* SourceId : ADC_SourceId_003 */
+/* DesignId : ADC_DesignId_003 */
+/* Requirements : HL_SR187 */
+void adcStopConversion(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ /** - Stop Conversion */
+ adc->GxSEL[group] = 0U;
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+
+/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group)
+* @brief Resets FiFo read and write pointer.
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function resets the FiFo read and write pointers.
+*
+*/
+/* SourceId : ADC_SourceId_004 */
+/* DesignId : ADC_DesignId_004*/
+/* Requirements : HL_SR188 */
+void adcResetFiFo(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ /** - Reset FiFo */
+ adc->GxFIFORESETCR[group] = 1U;
+
+ /** @note The function adcInit has to be called before this function can be used.\n
+ * the conversion should be stopped before calling this function.
+ */
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data)
+* @brief Gets converted a ADC values
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+* @param[out] data Pointer to store ADC converted data
+* @return The function will return the number of converted values copied into data buffer:
+*
+* This function writes a ADC message into a ADC message box.
+*
+*/
+/* SourceId : ADC_SourceId_005 */
+/* DesignId : ADC_DesignId_005 */
+/* Requirements : HL_SR189 */
+uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data)
+{
+ uint32 i;
+ uint32 buf;
+ uint32 mode;
+ uint32 index = (adc == adcREG1) ? 0U : 1U;
+
+ uint32 intcr_reg = adc->GxINTCR[group];
+ uint32 count = (intcr_reg >= 256U) ? s_adcFiFoSize[index][group] : (s_adcFiFoSize[index][group] - (uint32)(intcr_reg & 0xFFU));
+ adcData_t *ptr = data;
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+ mode = (adc->OPMODECR & ADC_12_BIT_MODE);
+
+ if(mode == ADC_12_BIT_MODE)
+ {
+ /** - Get conversion data and channel/pin id */
+ for (i = 0U; i < count; i++)
+ {
+ buf = adc->GxBUF[group].BUF0;
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ ptr->value = (uint16)(buf & 0xFFFU);
+ ptr->id = (uint32)((buf >> 16U) & 0x1FU);
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ ptr++;
+ }
+ }
+ else
+ {
+ /** - Get conversion data and channel/pin id */
+ for (i = 0U; i < count; i++)
+ {
+ buf = adc->GxBUF[group].BUF0;
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ ptr->value = (uint16)(buf & 0x3FFU);
+ ptr->id = (uint32)((buf >> 10U) & 0x1FU);
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ ptr++;
+ }
+ }
+
+
+ adc->GxINTFLG[group] = 9U;
+
+ /** @note The function adcInit has to be called before this function can be used.\n
+ * The user is responsible to initialize the message box.
+ */
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ return count;
+}
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group)
+* @brief Checks if FiFo buffer is full
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+* @return The function will return:
+* - 0: When FiFo buffer is not full
+* - 1: When FiFo buffer is full
+* - 3: When FiFo buffer overflow occurred
+*
+* This function checks FiFo buffer status.
+*
+*/
+/* SourceId : ADC_SourceId_006 */
+/* DesignId : ADC_DesignId_006 */
+/* Requirements : HL_SR190 */
+uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group)
+{
+ uint32 flags;
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ /** - Read FiFo flags */
+ flags = adc->GxINTFLG[group] & 3U;
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+ return flags;
+}
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group)
+* @brief Checks if Conversion is complete
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+* @return The function will return:
+* - 0: When is not finished
+* - 8: When conversion is complete
+*
+* This function checks if conversion is complete.
+*
+*/
+/* SourceId : ADC_SourceId_007 */
+/* DesignId : ADC_DesignId_007 */
+/* Requirements : HL_SR191 */
+uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group)
+{
+ uint32 flags;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ /** - Read conversion flags */
+ flags = adc->GxINTFLG[group] & 8U;
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ return flags;
+}
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+/** @fn void adcCalibration(adcBASE_t *adc)
+* @brief Computes offset error using Calibration mode
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* This function computes offset error using Calibration mode
+*
+*/
+/* SourceId : ADC_SourceId_008 */
+/* DesignId : ADC_DesignId_010 */
+/* Requirements : HL_SR194 */
+void adcCalibration(adcBASE_t *adc)
+{
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+ uint32 conv_val[5U]={0U,0U,0U,0U,0U};
+ uint32 loop_index=0U;
+ uint32 offset_error=0U;
+ uint32 backup_mode;
+
+ /** - Backup Mode before Calibration */
+ backup_mode = adc->OPMODECR;
+
+ /** - Enable 12-BIT ADC */
+ adc->OPMODECR |= 0x80000000U;
+
+ /* Disable all channels for conversion */
+ adc->GxSEL[0U]=0x00U;
+ adc->GxSEL[1U]=0x00U;
+ adc->GxSEL[2U]=0x00U;
+
+ for(loop_index=0U;loop_index<4U;loop_index++)
+ {
+ /* Disable Self Test and Calibration mode */
+ adc->CALCR=0x0U;
+
+ switch(loop_index)
+ {
+ case 0U : /* Test 1 : Bride En = 0 , HiLo =0 */
+ adc->CALCR=0x0U;
+ break;
+
+ case 1U : /* Test 1 : Bride En = 0 , HiLo =1 */
+ adc->CALCR=0x0100U;
+ break;
+
+ case 2U : /* Test 1 : Bride En = 1 , HiLo =0 */
+ adc->CALCR=0x0200U;
+ break;
+
+ case 3U : /* Test 1 : Bride En = 1 , HiLo =1 */
+ adc->CALCR=0x0300U;
+ break;
+ default :
+ break;
+ }
+
+ /* Enable Calibration mode */
+ adc->CALCR|=0x1U;
+
+ /* Start calibration conversion */
+ adc->CALCR|=0x00010000U;
+
+ /* Wait for calibration conversion to complete */
+ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */
+ while((adc->CALCR & 0x00010000U)==0x00010000U)
+ {
+ } /* Wait */
+
+ /* Read converted value */
+ conv_val[loop_index]= adc->CALR;
+ }
+
+ /* Disable Self Test and Calibration mode */
+ adc->CALCR=0x0U;
+
+ /* Compute the Offset error correction value */
+ conv_val[4U]=conv_val[0U]+ conv_val[1U] + conv_val[2U] + conv_val[3U];
+
+ conv_val[4U]=(conv_val[4U]/4U);
+
+ offset_error=conv_val[4U]-0x7FFU;
+
+ /*Write the offset error to the Calibration register */
+ /* Load 2;s complement of the computed value to ADCALR register */
+ offset_error=~offset_error;
+ offset_error=offset_error & 0xFFFU;
+ offset_error=offset_error+1U;
+
+ adc->CALR = offset_error;
+
+ /** - Restore Mode after Calibration */
+ adc->OPMODECR = backup_mode;
+
+ /** @note The function adcInit has to be called before using this function. */
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+
+/** @fn void adcMidPointCalibration(adcBASE_t *adc)
+* @brief Computes offset error using Mid Point Calibration mode
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @return This function will return offset error using Mid Point Calibration mode
+*
+* This function computes offset error using Mid Point Calibration mode
+*
+*/
+/* SourceId : ADC_SourceId_009 */
+/* DesignId : ADC_DesignId_011 */
+/* Requirements : HL_SR195 */
+uint32 adcMidPointCalibration(adcBASE_t *adc)
+{
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+ uint32 conv_val[3U]={0U,0U,0U};
+ uint32 loop_index=0U;
+ uint32 offset_error=0U;
+ uint32 backup_mode;
+
+ /** - Backup Mode before Calibration */
+ backup_mode = adc->OPMODECR;
+
+ /** - Enable 12-BIT ADC */
+ adc->OPMODECR |= 0x80000000U;
+
+ /* Disable all channels for conversion */
+ adc->GxSEL[0U]=0x00U;
+ adc->GxSEL[1U]=0x00U;
+ adc->GxSEL[2U]=0x00U;
+
+ for(loop_index=0U;loop_index<2U;loop_index++)
+ {
+ /* Disable Self Test and Calibration mode */
+ adc->CALCR=0x0U;
+
+ switch(loop_index)
+ {
+ case 0U : /* Test 1 : Bride En = 0 , HiLo =0 */
+ adc->CALCR=0x0U;
+ break;
+
+ case 1U : /* Test 1 : Bride En = 0 , HiLo =1 */
+ adc->CALCR=0x0100U;
+ break;
+
+ default :
+ break;
+
+ }
+
+ /* Enable Calibration mode */
+ adc->CALCR|=0x1U;
+
+ /* Start calibration conversion */
+ adc->CALCR|=0x00010000U;
+
+ /* Wait for calibration conversion to complete */
+ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */
+ while((adc->CALCR & 0x00010000U)==0x00010000U)
+ {
+ } /* Wait */
+
+ /* Read converted value */
+ conv_val[loop_index]= adc->CALR;
+ }
+
+ /* Disable Self Test and Calibration mode */
+ adc->CALCR=0x0U;
+
+ /* Compute the Offset error correction value */
+ conv_val[2U]=(conv_val[0U])+ (conv_val[1U]);
+
+ conv_val[2U]=(conv_val[2U]/2U);
+
+ offset_error=conv_val[2U]-0x7FFU;
+
+ /* Write the offset error to the Calibration register */
+ /* Load 2's complement of the computed value to ADCALR register */
+ offset_error=~offset_error;
+ offset_error=offset_error+1U;
+ offset_error=offset_error & 0xFFFU;
+
+ adc->CALR = offset_error;
+
+ /** - Restore Mode after Calibration */
+ adc->OPMODECR = backup_mode;
+
+ return(offset_error);
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group)
+* @brief Enable notification
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function will enable the notification of a conversion.
+* In single conversion mode for conversion complete and
+* in continuous conversion mode when the FiFo buffer is full.
+*
+*/
+/* SourceId : ADC_SourceId_010 */
+/* DesignId : ADC_DesignId_008 */
+/* Requirements : HL_SR192 */
+void adcEnableNotification(adcBASE_t *adc, uint32 group)
+{
+ uint32 notif = (((uint32)(adc->GxMODECR[group]) & 2U) == 2U) ? 1U : 8U;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ adc->GxINTENA[group] = notif;
+
+ /** @note The function adcInit has to be called before this function can be used.\n
+ * This function should be called before the conversion is started
+ */
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+
+/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group)
+* @brief Disable notification
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* - adcREG2: ADC2 module pointer
+* @param[in] group Hardware group of ADC module:
+* - adcGROUP0: ADC event group
+* - adcGROUP1: ADC group 1
+* - adcGROUP2: ADC group 2
+*
+* This function will disable the notification of a conversion.
+*/
+/* SourceId : ADC_SourceId_011 */
+/* DesignId : ADC_DesignId_009 */
+/* Requirements : HL_SR193 */
+void adcDisableNotification(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+ adc->GxINTENA[group] = 0U;
+
+ /** @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+}
+
+/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value)
+* @brief Set ADCEVT pin
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* @param[in] value Value to be set: 0 or 1
+*
+* This function will set the ADC EVT pin if configured as an output pin.
+*/
+/* SourceId : ADC_SourceId_020 */
+/* DesignId : ADC_DesignId_014 */
+/* Requirements : HL_SR529 */
+void adcSetEVTPin(adcBASE_t *adc, uint32 value)
+{
+ adc->EVTOUT = value;
+}
+
+/** @fn uint32 adcGetEVTPin(adcBASE_t *adc)
+* @brief Set ADCEVT pin
+* @param[in] adc Pointer to ADC module:
+* - adcREG1: ADC1 module pointer
+* @return Value of the ADC EVT pin: 0 or 1
+*
+* This function will return the value of ADC EVT pin.
+*/
+/* SourceId : ADC_SourceId_021 */
+/* DesignId : ADC_DesignId_015 */
+/* Requirements : HL_SR529 */
+uint32 adcGetEVTPin(adcBASE_t *adc)
+{
+ return adc->EVTIN;
+}
+
+/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ADC_SourceId_012 */
+/* DesignId : ADC_DesignId_012 */
+/* Requirements : HL_SR203 */
+void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE;
+ config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE;
+ config_reg->CONFIG_GxMODECR[0U] = ADC1_G0MODECR_CONFIGVALUE;
+ config_reg->CONFIG_GxMODECR[1U] = ADC1_G1MODECR_CONFIGVALUE;
+ config_reg->CONFIG_GxMODECR[2U] = ADC1_G2MODECR_CONFIGVALUE;
+ config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE;
+ config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE;
+ config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE;
+ config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE;
+ config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE;
+ config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE;
+ config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE;
+ config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE;
+ config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE;
+ config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE;
+ config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE;
+ config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE;
+ }
+ else
+ {
+ config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR;
+ config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR;
+ config_reg->CONFIG_GxMODECR[0U] = adcREG1->GxMODECR[0U];
+ config_reg->CONFIG_GxMODECR[1U] = adcREG1->GxMODECR[1U];
+ config_reg->CONFIG_GxMODECR[2U] = adcREG1->GxMODECR[2U];
+ config_reg->CONFIG_G0SRC = adcREG1->EVSRC;
+ config_reg->CONFIG_G1SRC = adcREG1->G1SRC;
+ config_reg->CONFIG_G2SRC = adcREG1->G2SRC;
+ config_reg->CONFIG_BNDCR = adcREG1->BNDCR;
+ config_reg->CONFIG_BNDEND = adcREG1->BNDEND;
+ config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP;
+ config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP;
+ config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP;
+ config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN;
+ config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN;
+ config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN;
+ config_reg->CONFIG_PARCR = adcREG1->PARCR;
+ }
+}
+
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+/** @fn void adc1Group1Interrupt(void)
+* @brief ADC1 Group 1 Interrupt Handler
+*/
+
+/* SourceId : ADC_SourceId_015 */
+/* DesignId : ADC_DesignId_013 */
+/* Requirements : HL_SR197, HL_SR196 */
+void adc1Group1Interrupt(void)
+{
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+ adcREG1->GxINTFLG[1U] = 9U;
+
+ adcNotification(adcREG1, adcGROUP1);
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+}
+
+
+
+
Index: firmware/source/can.c
===================================================================
diff -u
--- firmware/source/can.c (revision 0)
+++ firmware/source/can.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1687 @@
+/** @file can.c
+* @brief CAN Driver Source File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - API Functions
+* - Interrupt Handlers
+* .
+* which are relevant for the CAN driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/* Include Files */
+
+#include "can.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/* Global and Static Variables */
+
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+#else
+ static const uint32 s_canByteOrder[8U] = {3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U};
+#endif
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+/** @fn void canInit(void)
+* @brief Initializes CAN Driver
+*
+* This function initializes the CAN driver.
+*
+*/
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+/* SourceId : CAN_SourceId_001 */
+/* DesignId : CAN_DesignId_001 */
+/* Requirements : HL_SR207 */
+void canInit(void)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+ /** @b Initialize @b CAN1: */
+
+ /** - Setup control register
+ * - Disable automatic wakeup on bus activity
+ * - Local power down mode disabled
+ * - Disable DMA request lines
+ * - Enable global Interrupt Line 0 and 1
+ * - Disable debug mode
+ * - Release from software reset
+ * - Enable/Disable parity or ECC
+ * - Enable/Disable auto bus on timer
+ * - Setup message completion before entering debug state
+ * - Setup normal operation mode
+ * - Request write access to the configuration registers
+ * - Setup automatic retransmission of messages
+ * - Disable error interrupts
+ * - Disable status interrupts
+ * - Enter initialization mode
+ */
+ canREG1->CTL = (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)((uint32)0x00000005U << 10U)
+ | (uint32)0x00020043U;
+
+ /** - Clear all pending error flags and reset current status */
+ canREG1->ES |= 0xFFFFFFFFU;
+
+ /** - Assign interrupt level for messages */
+ canREG1->INTMUXx[0U] = (uint32)0x00000000U
+ | (uint32)0x00000002U
+ | (uint32)0x00000004U
+ | (uint32)0x00000008U
+ | (uint32)0x00000010U
+ | (uint32)0x00000020U
+ | (uint32)0x00000040U
+ | (uint32)0x00000080U
+ | (uint32)0x00000100U
+ | (uint32)0x00000200U
+ | (uint32)0x00000400U
+ | (uint32)0x00000800U
+ | (uint32)0x00001000U
+ | (uint32)0x00002000U
+ | (uint32)0x00004000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U;
+
+ canREG1->INTMUXx[1U] = (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U;
+
+ /** - Setup auto bus on timer period */
+ canREG1->ABOTR = (uint32)0U;
+
+ /** - Initialize message 1
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+
+ canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x1U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF1CMD = (uint8) 0xF8U;
+ canREG1->IF1NO = 1U;
+
+ /** - Initialize message 2
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x2U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF2CMD = (uint8) 0xF8U;
+ canREG1->IF2NO = 2U;
+
+ /** - Initialize message 3
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x4U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF1CMD = (uint8) 0xF8U;
+ canREG1->IF1NO = 3U;
+
+ /** - Initialize message 4
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x8U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF2CMD = (uint8) 0xF8U;
+ canREG1->IF2NO = 4U;
+
+ /** - Initialize message 5
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x10U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF1CMD = (uint8) 0xF8U;
+ canREG1->IF1NO = 5U;
+
+ /** - Initialize message 6
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x11U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF2CMD = (uint8) 0xF8U;
+ canREG1->IF2NO = 6U;
+
+ /** - Initialize message 7
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x40U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF1CMD = (uint8) 0xF8U;
+ canREG1->IF1NO = 7U;
+
+ /** - Initialize message 8
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x41U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF2CMD = (uint8) 0xF8U;
+ canREG1->IF2NO = 8U;
+
+ /** - Initialize message 9
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x100U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF1CMD = (uint8) 0xF8U;
+ canREG1->IF1NO = 9U;
+
+ /** - Initialize message 10
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x101U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF2CMD = (uint8) 0xF8U;
+ canREG1->IF2NO = 10U;
+
+ /** - Initialize message 11
+ * - Wait until IF1 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF1 control byte
+ * - Set IF1 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x102U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF1CMD = (uint8) 0xF8U;
+ canREG1->IF1NO = 11U;
+
+ /** - Initialize message 12
+ * - Wait until IF2 is ready for use
+ * - Set message mask
+ * - Set message control word
+ * - Set message arbitration
+ * - Set IF2 control byte
+ * - Set IF2 message number
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x103U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+ canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+ canREG1->IF2CMD = (uint8) 0xF8U;
+ canREG1->IF2NO = 12U;
+
+ /** - Setup IF1 for data transmission
+ * - Wait until IF1 is ready for use
+ * - Set IF1 control byte
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+ canREG1->IF1CMD = 0x87U;
+
+ /** - Setup IF2 for reading data
+ * - Wait until IF1 is ready for use
+ * - Set IF1 control byte
+ */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+ canREG1->IF2CMD = 0x17U;
+
+ /** - Setup bit timing
+ * - Setup baud rate prescaler extension
+ * - Setup TSeg2
+ * - Setup TSeg1
+ * - Setup sample jump width
+ * - Setup baud rate prescaler
+ */
+ canREG1->BTR = (uint32)((uint32)0U << 16U) |
+ (uint32)((uint32)(6U - 1U) << 12U) |
+ (uint32)((uint32)((3U + 6U) - 1U) << 8U) |
+ (uint32)((uint32)(4U - 1U) << 6U) |
+ (uint32)25U;
+
+
+ /** - CAN1 Port output values */
+ canREG1->TIOC = (uint32)((uint32)1U << 18U )
+ | (uint32)((uint32)0U << 17U )
+ | (uint32)((uint32)0U << 16U )
+ | (uint32)((uint32)1U << 3U )
+ | (uint32)((uint32)1U << 2U )
+ | (uint32)((uint32)1U << 1U );
+
+ canREG1->RIOC = (uint32)((uint32)1U << 18U )
+ | (uint32)((uint32)0U << 17U )
+ | (uint32)((uint32)0U << 16U )
+ | (uint32)((uint32)1U << 3U )
+ | (uint32)((uint32)0U << 2U )
+ | (uint32)((uint32)0U <<1U );
+
+ /** - Leave configuration and initialization mode */
+ canREG1->CTL &= ~(uint32)(0x00000041U);
+
+
+ /** @b Initialize @b CAN2: */
+
+
+ /** - Setup control register
+ * - Enter initialization mode
+ */
+ canREG2->CTL = 0x00000001U;
+
+ /** - CAN2 Port output values */
+ canREG2->TIOC = (uint32)((uint32)1U << 18U )
+ | (uint32)((uint32)0U << 17U )
+ | (uint32)((uint32)0U << 16U )
+ | (uint32)((uint32)0U << 3U )
+ | (uint32)((uint32)1U << 2U )
+ | (uint32)((uint32)1U << 1U );
+
+ canREG2->RIOC = (uint32)((uint32)1U << 18U )
+ | (uint32)((uint32)0U << 17U )
+ | (uint32)((uint32)0U << 16U )
+ | (uint32)((uint32)0U << 3U )
+ | (uint32)((uint32)1U << 2U )
+ | (uint32)((uint32)0U <<1U );
+
+
+ /** @b Initialize @b CAN3: */
+
+
+ /** - Setup control register
+ * - Enter initialization mode
+ */
+ canREG3->CTL = 0x00000001U;
+
+ /** - CAN3 Port output values */
+ canREG3->TIOC = (uint32)((uint32)1U << 18U )
+ | (uint32)((uint32)0U << 17U )
+ | (uint32)((uint32)0U << 16U )
+ | (uint32)((uint32)0U << 3U )
+ | (uint32)((uint32)1U << 2U )
+ | (uint32)((uint32)1U << 1U );
+
+ canREG3->RIOC = (uint32)((uint32)1U << 18U )
+ | (uint32)((uint32)0U << 17U )
+ | (uint32)((uint32)0U << 16U )
+ | (uint32)((uint32)0U << 3U )
+ | (uint32)((uint32)1U << 2U )
+ | (uint32)((uint32)0U << 1U );
+
+
+ /** @note This function has to be called before the driver can be used.\n
+ * This function has to be executed in privileged mode.\n
+ */
+
+/* USER CODE BEGIN (5) */
+ // Enable EIE (error interrupts) // Enable error interrupts for bus transmission issues.
+ canREG1->CTL |= (uint32)0x00000008U;
+// // Enable SIE (error interrupts) // Enable status interrupts for errors on received frames. Not Needed except for some engineering testing.
+// canREG1->CTL |= (uint32)0x00000004U;
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+/** @fn uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data)
+* @brief Transmits a CAN message
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @param[in] data Pointer to CAN TX data
+* @return The function will return:
+* - 0: When the setup of the TX message box wasn't successful
+* - 1: When the setup of the TX message box was successful
+*
+* This function writes a CAN message into a CAN message box.
+* This function is not reentrant. However, if a CAN interrupt occurs, the values of
+* the IF registers are backup up and restored at the end of the ISR, since these are a shared resource.
+*
+*/
+/* SourceId : CAN_SourceId_002 */
+/* DesignId : CAN_DesignId_002 */
+/* Requirements : HL_SR208 */
+uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data)
+{
+ uint32 i;
+ uint32 success = 0U;
+ uint32 regIndex = (messageBox - 1U) >> 5U;
+ uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+
+ /** - Check for pending message:
+ * - pending message, return 0
+ * - no pending message, start new transmission
+ */
+ if ((node->TXRQx[regIndex] & bitIndex) != 0U)
+ {
+ success = 0U;
+ }
+
+ else
+ {
+ /** - Wait until IF1 is ready for use */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((node->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ /** - Configure IF1 for
+ * - Message direction - Write
+ * - Data Update
+ * - Start Transmission
+ */
+ node->IF1CMD = 0x87U;
+
+ /** - Copy TX data into IF1 */
+ for (i = 0U; i < 8U; i++)
+ {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ node->IF1DATx[i] = *data;
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ data++;
+#else
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ node->IF1DATx[s_canByteOrder[i]] = *data;
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ data++;
+#endif
+ }
+
+ /** - Copy TX data into message box */
+ /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */
+ node->IF1NO = (uint8) messageBox;
+
+ success = 1U;
+ }
+ /** @note The function canInit has to be called before this function can be used.\n
+ * The user is responsible to initialize the message box.
+ */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ return success;
+}
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+/** @fn uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data)
+* @brief Gets received a CAN message
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @param[out] data Pointer to store CAN RX data
+* @return The function will return:
+* - 0: When RX message box hasn't received new data
+* - 1: When RX data are stored in the data buffer
+* - 3: When RX data are stored in the data buffer and a message was lost
+*
+* This function writes a CAN message into a CAN message box.
+*
+*/
+/* SourceId : CAN_SourceId_003 */
+/* DesignId : CAN_DesignId_003 */
+/* Requirements : HL_SR209 */
+uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data)
+{
+ uint32 i;
+ uint32 size;
+ uint8 * pData = data;
+ uint32 success = 0U;
+ uint32 regIndex = (messageBox - 1U) >> 5U;
+ uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ /** - Check if new data have been arrived:
+ * - no new data, return 0
+ * - new data, get received message
+ */
+ if ((node->NWDATx[regIndex] & bitIndex) == 0U)
+ {
+ success = 0U;
+ }
+
+ else
+ {
+ /** - Wait until IF2 is ready for use */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((node->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ /** - Configure IF2 for
+ * - Message direction - Read
+ * - Data Read
+ * - Clears NewDat bit in the message object.
+ */
+ node->IF2CMD = 0x17U;
+
+ /** - Copy data into IF2 */
+ /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */
+ node->IF2NO = (uint8) messageBox;
+
+ /** - Wait until data are copied into IF2 */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((node->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ /** - Get number of received bytes
+ * - Value from 0x8 to 0xF equals length 8.
+ */
+ size = node->IF2MCTL & 0xFU;
+ if(size > 0x8U)
+ {
+ size = 0x8U;
+ }
+
+ /** - Copy RX data into destination buffer */
+ for (i = 0U; i < size; i++)
+ {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ *pData = node->IF2DATx[i];
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ pData++;
+#else
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ *pData = node->IF2DATx[s_canByteOrder[i]];
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ pData++;
+#endif
+ }
+
+ success = 1U;
+ }
+ /** - Check if data have been lost:
+ * - no data lost, return 1
+ * - data lost, return 3
+ */
+ if ((node->IF2MCTL & 0x4000U) == 0x4000U)
+ {
+ success = 3U;
+ }
+
+ /** @note The function canInit has to be called before this function can be used.\n
+ * The user is responsible to initialize the message box.
+ */
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ return success;
+}
+
+
+/** @fn uint32 canGetID(canBASE_t *node, uint32 messageBox)
+* @brief Gets the Message Box's ID
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @param[out] data Pointer to store CAN RX data
+* @return The function will return the ID of the message box.
+*
+* This function gets the identifier of a CAN message box.
+*
+*/
+/* SourceId : CAN_SourceId_026 */
+/* DesignId : CAN_DesignId_020 */
+/* Requirements : HL_SR537 */
+uint32 canGetID(canBASE_t *node, uint32 messageBox)
+{
+ uint32 msgBoxID = 0U;
+
+
+ /** - Wait until IF2 is ready for use */
+ while ((node->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ /** - Configure IF2 for
+ * - Message direction - Read
+ * - Data Read
+ * - Clears NewDat bit in the message object.
+ */
+ node->IF2CMD = 0x20U;
+
+ /** - Copy message box number into IF2 */
+ /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */
+ node->IF2NO = (uint8) messageBox;
+
+ /** - Wait until data are copied into IF2 */
+ while ((node->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ /* Read Message Box ID from Arbitration register. */
+ msgBoxID = (node->IF2ARB & 0x1FFFFFFFU);
+
+ return msgBoxID;
+
+}
+
+/** @fn uint32 canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal)
+* @brief Change CAN Message Box ID.
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @param[in] msgBoxArbitVal (32 bit value):
+* Bit 31 - Not used.
+* Bit 30 - 0 - The 11-bit ("standard") identifier is used for this message object.
+* 1 - The 29-bit ("extended") identifier is used for this message object.
+* Bit 29 - 0 - Direction = Receive
+* 1 - Direction = Transmit
+* Bit 28:0 - Message Identifier.
+* @return
+
+*
+* This function changes the Identifier and other arbitration parameters of a CAN Message Box.
+*
+*/
+/* SourceId : CAN_SourceId_027 */
+/* DesignId : CAN_DesignId_021 */
+/* Requirements : HL_SR538 */
+void canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal)
+{
+
+ /** - Wait until IF2 is ready for use */
+ while ((node->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ /** - Configure IF2 for
+ * - Message direction - Read
+ * - Data Read
+ * - Clears NewDat bit in the message object.
+ */
+ node->IF2CMD = 0xA0U;
+ /* Copy passed value into the arbitration register. */
+ node->IF2ARB &= 0x80000000U;
+ node->IF2ARB |= (msgBoxArbitVal & 0x7FFFFFFFU);
+
+ /** - Update message box number. */
+ /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */
+ node->IF2NO = (uint8) messageBox;
+
+ /** - Wait until data are copied into IF2 */
+ while ((node->IF2STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+}
+
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+/** @fn uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox)
+* @brief Transmits a CAN Remote Frame.
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @param[in] data Pointer to CAN TX data
+* @return The function will return:
+* - 0: When the setup of Send Remote Frame from message box wasn't successful
+* - 1: When the setup of Send Remote Frame from message box was successful
+*
+* This function triggers Remote Frame Transmission from CAN message box.
+* Note : Enable RTR must be set in the Message x Configuration in the GUI( x: 1 - 64)
+*
+*/
+/* SourceId : CAN_SourceId_028 */
+/* DesignId : CAN_DesignId_022 */
+/* Requirements : HL_SR531 */
+uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox)
+{
+
+ uint32 success = 0U;
+ uint32 regIndex = (messageBox - 1U) >> 5U;
+ uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+ /** - Check for pending message:
+ * - pending message, return 0
+ * - no pending message, start new transmission
+ */
+ if ((node->TXRQx[regIndex] & bitIndex) != 0U)
+ {
+ success = 0U;
+ }
+
+ else
+ {
+ /** - Wait until IF1 is ready for use */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((node->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ /** - Request Transmission by setting TxRqst in message box */
+ node->IF1CMD = (uint8) 0x84U;
+
+ /** - Trigger Remote Frame Transmit from message box */
+ /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */
+ node->IF1NO = (uint8) messageBox;
+
+ success = 1U;
+ }
+ /** @note The function canInit has to be called before this function can be used.\n
+ * The user is responsible to initialize the message box.
+ */
+ return success;
+}
+
+/** @fn uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * data)
+* @brief Fills the Message Object with the data but does not initiate transmission.
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @return The function will return:
+* - 0: When the Fill up of the TX message box wasn't successful
+* - 1: When the Fill up of the TX message box was successful
+*
+* This function fills the Message Object with the data but does not initiate transmission.
+*
+*/
+/* SourceId : CAN_SourceId_029 */
+/* DesignId : CAN_DesignId_023 */
+/* Requirements : HL_SR532 */
+uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * data)
+{
+ uint32 i;
+ uint32 success = 0U;
+ uint32 regIndex = (messageBox - 1U) >> 5U;
+ uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+ /** - Check for pending message:
+ * - pending message, return 0
+ * - no pending message, start new transmission
+ */
+ if ((node->TXRQx[regIndex] & bitIndex) != 0U)
+ {
+ success = 0U;
+ }
+ else
+ {
+ /** - Wait until IF1 is ready for use */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((node->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ /** - Configure IF1 for
+ * - Message direction - Write
+ * - Data Update
+ */
+ node->IF1CMD = 0x83U;
+
+ /** - Copy TX data into IF1 */
+ for (i = 0U; i < 8U; i++)
+ {
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ node->IF1DATx[i] = *data;
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ data++;
+#else
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ node->IF1DATx[s_canByteOrder[i]] = *data;
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ data++;
+#endif
+ }
+
+ /** - Copy TX data into message box */
+ /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */
+ node->IF1NO = (uint8) messageBox;
+
+ success = 1U;
+ }
+
+ return success;
+
+}
+
+/** @fn uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox)
+* @brief Gets Tx message box transmission status
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @return The function will return the tx request flag
+*
+* Checks to see if the Tx message box has a pending Tx request, returns
+* 0 is flag not set otherwise will return the Tx request flag itself.
+*/
+/* SourceId : CAN_SourceId_004 */
+/* DesignId : CAN_DesignId_004 */
+/* Requirements : HL_SR210 */
+uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox)
+{
+ uint32 flag;
+ uint32 regIndex = (messageBox - 1U) >> 5U;
+ uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ /** - Read Tx request register */
+ flag = node->TXRQx[regIndex] & bitIndex;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+ return flag;
+}
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+/** @fn uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox)
+* @brief Gets Rx message box reception status
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @return The function will return the new data flag
+*
+* Checks to see if the Rx message box has pending Rx data, returns
+* 0 is flag not set otherwise will return the Tx request flag itself.
+*/
+/* SourceId : CAN_SourceId_005 */
+/* DesignId : CAN_DesignId_005 */
+/* Requirements : HL_SR211 */
+uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox)
+{
+ uint32 flag;
+ uint32 regIndex = (messageBox - 1U) >> 5U;
+ uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+ /** - Read Tx request register */
+ flag = node->NWDATx[regIndex] & bitIndex;
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ return flag;
+}
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+/** @fn uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox)
+* @brief Checks if message box is valid
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] messageBox Message box number of CAN node:
+* - canMESSAGE_BOX1: CAN message box 1
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]
+* - canMESSAGE_BOX64: CAN message box 64
+* @return The function will return the new data flag
+*
+* Checks to see if the message box is valid for operation, returns
+* 0 is flag not set otherwise will return the validation flag itself.
+*/
+/* SourceId : CAN_SourceId_006 */
+/* DesignId : CAN_DesignId_006 */
+/* Requirements : HL_SR212 */
+uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox)
+{
+ uint32 flag;
+ uint32 regIndex = (messageBox - 1U) >> 5U;
+ uint32 bitIndex = 1U << ((messageBox - 1U) & 0x1FU);
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ /** - Read Tx request register */
+ flag = node->MSGVALx[regIndex] & bitIndex;
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+ return flag;
+}
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+/** @fn uint32 canGetLastError(canBASE_t *node)
+* @brief Gets last RX/TX-Error of CAN message traffic
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @return The function will return:
+* - canERROR_OK (0): When no CAN error occurred
+* - canERROR_STUFF (1): When a stuff error occurred on RX message
+* - canERROR_FORMAT (2): When a form/format error occurred on RX message
+* - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged
+* - canERROR_BIT1 (4): When a TX message monitored dominant level where recessive is expected
+* - canERROR_BIT0 (5): When a TX message monitored recessive level where dominant is expected
+* - canERROR_CRC (6): When a RX message has wrong CRC value
+* - canERROR_NO (7): When no error occurred since last call of this function
+*
+* This function returns the last occurred error code of an RX or TX message,
+* since the last call of this function.
+*
+*/
+/* SourceId : CAN_SourceId_007 */
+/* DesignId : CAN_DesignId_007 */
+/* Requirements : HL_SR213 */
+uint32 canGetLastError(canBASE_t *node)
+{
+ uint32 errorCode;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ /** - Get last error code */
+ errorCode = node->ES & 7U;
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ return errorCode;
+}
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+/** @fn uint32 canGetErrorLevel(canBASE_t *node)
+* @brief Gets error level of a CAN node
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @return The function will return:
+* - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96
+* - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127
+* - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and 255
+* - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255
+*
+* This function returns the current error level of a CAN node.
+*
+*/
+/* SourceId : CAN_SourceId_008 */
+/* DesignId : CAN_DesignId_008 */
+/* Requirements : HL_SR214 */
+uint32 canGetErrorLevel(canBASE_t *node)
+{
+ uint32 errorLevel;
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+ /** - Get error level */
+ errorLevel = node->ES & 0xE0U;
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+ return errorLevel;
+}
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+
+/** @fn void canEnableErrorNotification(canBASE_t *node)
+* @brief Enable error notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* This function will enable the notification for the reaching the error levels warning, passive and bus off.
+*/
+/* SourceId : CAN_SourceId_009 */
+/* DesignId : CAN_DesignId_009 */
+/* Requirements : HL_SR215 */
+void canEnableErrorNotification(canBASE_t *node)
+{
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ node->CTL |= 8U;
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+/** @fn void canEnableStatusChangeNotification(canBASE_t *node)
+* @brief Enable Status Change notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* This function will enable the notification for the status change RxOK, TxOK, PDA, WakeupPnd Interrupt.
+*/
+/* SourceId : CAN_SourceId_030 */
+/* DesignId : CAN_DesignId_024 */
+/* Requirements : HL_SR533 */
+void canEnableStatusChangeNotification(canBASE_t *node)
+{
+
+ node->CTL |= 4U;
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+}
+
+/** @fn void canDisableStatusChangeNotification(canBASE_t *node)
+* @brief Disable Status Change notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* This function will disable the notification for the status change RxOK, TxOK, PDA, WakeupPnd Interrupt.
+*/
+/* SourceId : CAN_SourceId_031 */
+/* DesignId : CAN_DesignId_025 */
+/* Requirements : HL_SR534 */
+void canDisableStatusChangeNotification(canBASE_t *node)
+{
+ node->CTL &= ~(uint32)(4U);
+
+ /** @note The function canInit has to be called before this function can be used. */
+}
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+/** @fn void canDisableErrorNotification(canBASE_t *node)
+* @brief Disable error notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* This function will disable the notification for the reaching the error levels warning, passive and bus off.
+*/
+/* SourceId : CAN_SourceId_010 */
+/* DesignId : CAN_DesignId_010 */
+/* Requirements : HL_SR216 */
+void canDisableErrorNotification(canBASE_t *node)
+{
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+ node->CTL &= ~(uint32)(8U);
+
+ /** @note The function canInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+}
+
+/** @fn void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype)
+* @brief Disable error notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] Loopbacktype Type of Loopback:
+* - Internal_Lbk: Internal Loop Back
+* - External_Lbk: External Loop Back
+* - Internal_Silent_Lbk: Internal Loop Back with Silent mode.
+*
+* This function will enable can loopback mode
+*/
+/* SourceId : CAN_SourceId_011 */
+/* DesignId : CAN_DesignId_011 */
+/* Requirements : HL_SR521 */
+void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype)
+{
+ /* Enter Test Mode */
+ node->CTL |= (uint32)((uint32)1U << 7U);
+
+ /* Configure Loopback */
+ node->TEST |= (uint32)Loopbacktype;
+
+ /** @note The function canInit has to be called before this function can be used. */
+}
+
+
+/** @fn void canDisableloopback(canBASE_t *node)
+* @brief Disable error notification
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* This function will disable can loopback mode
+*/
+/* SourceId : CAN_SourceId_012 */
+/* DesignId : CAN_DesignId_012 */
+/* Requirements : HL_SR522 */
+void canDisableloopback(canBASE_t *node)
+{
+
+
+ node->TEST &= ~(uint32)(0x00000118U);
+
+ /* Exit Test Mode */
+ node->CTL &= ~(uint32)((uint32)1U << 7U);
+
+ /** @note The function canInit has to be called before this function can be used. */
+}
+
+
+/** @fn void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir)
+* @brief Set Port Direction
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] TxDir - TX Pin direction
+* @param[in] RxDir - RX Pin direction
+*
+* Set the direction of CAN pins at runtime when configured as IO pins.
+*/
+/* SourceId : CAN_SourceId_013 */
+/* DesignId : CAN_DesignId_013 */
+/* Requirements : HL_SR217 */
+void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir)
+{
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+ node->TIOC = ((node->TIOC & 0xFFFFFFFBU) | (TxDir << 2U));
+ node->RIOC = ((node->RIOC & 0xFFFFFFFBU) | (RxDir << 2U));
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+}
+
+/** @fn void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue)
+* @brief Write Port Value
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+* @param[in] TxValue - TX Pin value 0 or 1
+* @param[in] RxValue - RX Pin value 0 or 1
+*
+* Writes a value to TX and RX pin of a given CAN module when configured as IO pins.
+*/
+/* SourceId : CAN_SourceId_014 */
+/* DesignId : CAN_DesignId_014 */
+/* Requirements : HL_SR218 */
+void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue)
+{
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+ node->TIOC = ((node->TIOC & 0xFFFFFFFDU) | (TxValue << 1U));
+ node->RIOC = ((node->RIOC & 0xFFFFFFFDU) | (RxValue << 1U));
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+}
+
+/** @fn uint32 canIoTxGetBit(canBASE_t *node)
+* @brief Read TX Bit
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* Reads a the current value from the TX pin of the given CAN port
+*/
+/* SourceId : CAN_SourceId_015 */
+/* DesignId : CAN_DesignId_015 */
+/* Requirements : HL_SR219 */
+uint32 canIoTxGetBit(canBASE_t *node)
+{
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+
+ return (node->TIOC & 1U);
+}
+
+/** @fn uint32 canIoRxGetBit(canBASE_t *node)
+* @brief Read RX Bit
+* @param[in] node Pointer to CAN node:
+* - canREG1: CAN1 node pointer
+* - canREG2: CAN2 node pointer
+* - canREG3: CAN3 node pointer
+*
+* Reads a the current value from the RX pin of the given CAN port
+*/
+/* SourceId : CAN_SourceId_016 */
+/* DesignId : CAN_DesignId_016 */
+/* Requirements : HL_SR220 */
+uint32 canIoRxGetBit(canBASE_t *node)
+{
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+ return (node->RIOC & 1U);
+}
+
+
+/** @fn void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the CAN1 configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : CAN_SourceId_017 */
+/* DesignId : CAN_DesignId_017 */
+/* Requirements : HL_SR224 */
+void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_CTL = CAN1_CTL_CONFIGVALUE;
+ config_reg->CONFIG_ES = CAN1_ES_CONFIGVALUE;
+ config_reg->CONFIG_BTR = CAN1_BTR_CONFIGVALUE;
+ config_reg->CONFIG_TEST = CAN1_TEST_CONFIGVALUE;
+ config_reg->CONFIG_ABOTR = CAN1_ABOTR_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX0 = CAN1_INTMUX0_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX1 = CAN1_INTMUX2_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX2 = CAN1_INTMUX2_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX3 = CAN1_INTMUX3_CONFIGVALUE;
+ config_reg->CONFIG_TIOC = CAN1_TIOC_CONFIGVALUE;
+ config_reg->CONFIG_RIOC = CAN1_RIOC_CONFIGVALUE;
+ }
+ else
+ {
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_CTL = canREG1->CTL;
+ config_reg->CONFIG_ES = canREG1->ES;
+ config_reg->CONFIG_BTR = canREG1->BTR;
+ config_reg->CONFIG_TEST = canREG1->TEST;
+ config_reg->CONFIG_ABOTR = canREG1->ABOTR;
+ config_reg->CONFIG_INTMUX0 = canREG1->INTMUXx[0];
+ config_reg->CONFIG_INTMUX1 = canREG1->INTMUXx[1];
+ config_reg->CONFIG_INTMUX2 = canREG1->INTMUXx[2];
+ config_reg->CONFIG_INTMUX3 = canREG1->INTMUXx[3];
+ config_reg->CONFIG_TIOC = canREG1->TIOC;
+ config_reg->CONFIG_RIOC = canREG1->RIOC;
+ }
+}
+/** @fn void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the CAN2 configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : CAN_SourceId_018 */
+/* DesignId : CAN_DesignId_017 */
+/* Requirements : HL_SR224 */
+void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_CTL = CAN2_CTL_CONFIGVALUE;
+ config_reg->CONFIG_ES = CAN2_ES_CONFIGVALUE;
+ config_reg->CONFIG_BTR = CAN2_BTR_CONFIGVALUE;
+ config_reg->CONFIG_TEST = CAN2_TEST_CONFIGVALUE;
+ config_reg->CONFIG_ABOTR = CAN2_ABOTR_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX0 = CAN2_INTMUX0_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX1 = CAN2_INTMUX2_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX2 = CAN2_INTMUX2_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX3 = CAN2_INTMUX3_CONFIGVALUE;
+ config_reg->CONFIG_TIOC = CAN2_TIOC_CONFIGVALUE;
+ config_reg->CONFIG_RIOC = CAN2_RIOC_CONFIGVALUE;
+ }
+ else
+ {
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_CTL = canREG2->CTL;
+ config_reg->CONFIG_ES = canREG2->ES;
+ config_reg->CONFIG_BTR = canREG2->BTR;
+ config_reg->CONFIG_TEST = canREG2->TEST;
+ config_reg->CONFIG_ABOTR = canREG2->ABOTR;
+ config_reg->CONFIG_INTMUX0 = canREG2->INTMUXx[0];
+ config_reg->CONFIG_INTMUX1 = canREG2->INTMUXx[1];
+ config_reg->CONFIG_INTMUX2 = canREG2->INTMUXx[2];
+ config_reg->CONFIG_INTMUX3 = canREG2->INTMUXx[3];
+ config_reg->CONFIG_TIOC = canREG2->TIOC;
+ config_reg->CONFIG_RIOC = canREG2->RIOC;
+ }
+}
+/** @fn void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the CAN3 configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : CAN_SourceId_019 */
+/* DesignId : CAN_DesignId_017 */
+/* Requirements : HL_SR224 */
+void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_CTL = CAN3_CTL_CONFIGVALUE;
+ config_reg->CONFIG_ES = CAN3_ES_CONFIGVALUE;
+ config_reg->CONFIG_BTR = CAN3_BTR_CONFIGVALUE;
+ config_reg->CONFIG_TEST = CAN3_TEST_CONFIGVALUE;
+ config_reg->CONFIG_ABOTR = CAN3_ABOTR_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX0 = CAN3_INTMUX0_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX1 = CAN3_INTMUX2_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX2 = CAN3_INTMUX2_CONFIGVALUE;
+ config_reg->CONFIG_INTMUX3 = CAN3_INTMUX3_CONFIGVALUE;
+ config_reg->CONFIG_TIOC = CAN3_TIOC_CONFIGVALUE;
+ config_reg->CONFIG_RIOC = CAN3_RIOC_CONFIGVALUE;
+ }
+ else
+ {
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_CTL = canREG3->CTL;
+ config_reg->CONFIG_ES = canREG3->ES;
+ config_reg->CONFIG_BTR = canREG3->BTR;
+ config_reg->CONFIG_TEST = canREG3->TEST;
+ config_reg->CONFIG_ABOTR = canREG3->ABOTR;
+ config_reg->CONFIG_INTMUX0 = canREG3->INTMUXx[0];
+ config_reg->CONFIG_INTMUX1 = canREG3->INTMUXx[1];
+ config_reg->CONFIG_INTMUX2 = canREG3->INTMUXx[2];
+ config_reg->CONFIG_INTMUX3 = canREG3->INTMUXx[3];
+ config_reg->CONFIG_TIOC = canREG3->TIOC;
+ config_reg->CONFIG_RIOC = canREG3->RIOC;
+ }
+}
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+/** @fn void can1HighLevelInterrupt(void)
+* @brief CAN1 Level 0 Interrupt Handler
+*/
+
+/* SourceId : CAN_SourceId_020 */
+/* DesignId : CAN_DesignId_018 */
+/* Requirements : HL_SR221, HL_SR222, HL_SR223 */
+void can1HighLevelInterrupt(void)
+{
+ uint32 value = canREG1->INT;
+ uint32 ES_value;
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
+
+ if (value == 0x8000U)
+ {
+ /* Read Error and Status Register*/
+ ES_value = canREG1->ES;
+
+ /* Check for Error (PES, Boff, EWarn & EPass) captured */
+ if((ES_value & 0x1E0U) != 0U)
+ {
+ canErrorNotification(canREG1, ES_value & 0x1E0U);
+ }
+ else
+ {
+ /* Call General Can notification incase of RxOK, TxOK, PDA, WakeupPnd Interrupt */
+ canStatusChangeNotification(canREG1, ES_value & 0x618U);
+ }
+ }
+ else
+ {
+ /** - Setup IF1 for clear pending interrupt flag */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF1CMD = 0x08U;
+ /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */
+ canREG1->IF1NO = (uint8) value;
+
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+ canREG1->IF1CMD = 0x87U;
+
+ canMessageNotification(canREG1, value);
+ }
+
+/* USER CODE BEGIN (42) */
+/* USER CODE END */
+
+}
+
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
+
+/** @fn void can1LowLevelInterrupt(void)
+* @brief CAN1 Level 1 Interrupt Handler
+*/
+
+/* SourceId : CAN_SourceId_021 */
+/* DesignId : CAN_DesignId_019 */
+/* Requirements : HL_SR221, HL_SR223 */
+void can1LowLevelInterrupt(void)
+{
+ uint32 messageBox = canREG1->INT >> 16U;
+
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+
+ /** - Setup IF1 for clear pending interrupt flag */
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+
+ canREG1->IF1CMD = 0x08U;
+ /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */
+ canREG1->IF1NO = (uint8) messageBox;
+
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+ {
+ } /* Wait */
+ canREG1->IF1CMD = 0x87U;
+
+ canMessageNotification(canREG1, messageBox);
+
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+
+}
+
+
+
+
+
Index: firmware/source/dabort.asm
===================================================================
diff -u
--- firmware/source/dabort.asm (revision 0)
+++ firmware/source/dabort.asm (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,146 @@
+;-------------------------------------------------------------------------------
+; dabort.asm
+;
+; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+;
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;
+;
+
+ .text
+ .arm
+
+
+;-------------------------------------------------------------------------------
+; Run Memory Test
+
+ .ref custom_dabort
+ .def _dabort
+ .asmfunc
+
+_dabort
+ stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack
+
+ ldr r12, esmsr3 ; ESM Group3 status register
+ ldr r0, [r12]
+ tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
+ bne ramErrorFound
+ tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
+ bne ramErrorFound2
+
+noRAMerror
+ tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
+ bne flashErrorFound
+
+ bl custom_dabort ; custom data abort handler required
+ ; If this custom handler is written in assembly, all registers used in the routine
+ ; and the link register must be saved on to the stack upon entry, and restored before
+ ; return from the routine.
+
+ ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack
+ subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted
+
+ramErrorFound
+ ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW
+ ldr r2, [r1]
+ tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
+ beq ramErrorReal
+ mov r2, #0x20
+ str r2, [r1, #0x10] ; clear RAM error status register
+
+ mov r2, #0x08
+ str r2, [r12] ; clear ESM group3 channel3 flag for uncorrectable RAM ECC errors
+ mov r2, #5
+ str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
+
+ ldmfd r13!, {r0 - r12, lr}
+ subs pc, lr, #4 ; branch to instruction after the one that caused the abort
+ ; this is the case because the data abort was caused intentionally
+ ; and we do not want to cause the same data abort again.
+
+ramErrorFound2
+ ldr r1, ram2ctrl ; RAM control register for B1TCM TCRAMW
+ ldr r2, [r1]
+ tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
+ beq ramErrorReal
+ mov r2, #0x20
+ str r2, [r1, #0x10] ; clear RAM error status register
+
+ mov r2, #0x20
+ str r2, [r12] ; clear ESM group3 flags channel5 flag for uncorrectable RAM ECC errors
+ mov r2, #5
+ str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
+
+ ldmfd r13!, {r0 - r12, lr}
+ subs pc, lr, #4 ; branch to instruction after the one that caused the abort
+ ; this is the case because the data abort was caused intentionally
+ ; and we do not want to cause the same data abort again.
+
+
+ramErrorReal
+ b ramErrorReal ; branch here forever as continuing operation is not recommended
+
+flashErrorFound
+ ldr r1, flashbase
+ ldr r2, [r1, #0x6C] ; read FDIAGCTRL register
+
+ mov r2, r2, lsr #16
+ tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
+ beq flashErrorReal
+ mov r2, #1
+ mov r2, r2, lsl #8
+
+ str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag
+
+ mov r2, #0x80
+ str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error
+ mov r2, #5
+ str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
+
+ ldmfd r13!, {r0 - r12, lr}
+ subs pc, lr, #4 ; branch to instruction after the one that caused the abort
+ ; this is the case because the data abort was caused intentionally
+ ; and we do not want to cause the same data abort again.
+
+
+flashErrorReal
+ b flashErrorReal ; branch here forever as continuing operation is not recommended
+
+esmsr3 .word 0xFFFFF520
+ramctrl .word 0xFFFFF800
+ram2ctrl .word 0xFFFFF900
+ram1errstat .word 0xFFFFF810
+ram2errstat .word 0xFFFFF910
+flashbase .word 0xFFF87000
+
+ .endasmfunc
+
+
Index: firmware/source/errata_SSWF021_45.c
===================================================================
diff -u
--- firmware/source/errata_SSWF021_45.c (revision 0)
+++ firmware/source/errata_SSWF021_45.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,358 @@
+/** @file errata_SSWF021_45.c
+* @brief errata for PLLs
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+#include "errata_SSWF021_45_defs.h"
+#include "errata_SSWF021_45.h"
+
+static uint32 check_frequency(uint32 cnt1_clksrc);
+static uint32 disable_plls(uint32 plls);
+
+/** @fn uint32 _errata_SSWF021_45_both_plls(uint32 count)
+* @brief This handles the errata for PLL1 and PLL2. This function is called in device startup
+*
+* @param[in] count : Number of retries until both PLLs are locked successfully
+* Minimum value recommended is 5
+*
+* @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled)
+* 1 = PLL1 failed to successfully lock in "count" tries
+* 2 = PLL2 failed to successfully lock in "count" tries
+* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries
+* 4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason
+ is that a PLL is already being used as a clock source. This can be caused by the workaround function
+ being called from the wrong place in the code.
+*/
+uint32 _errata_SSWF021_45_both_plls(uint32 count)
+{
+ uint32 failCode,retries,clkCntlSav;
+ /* save CLKCNTL */
+ clkCntlSav = systemREG1->CLKCNTL;
+ /* First set VCLK2 = HCLK */
+ systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U;
+ /* Now set VCLK = HCLK and enable peripherals */
+ systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA;
+ failCode = 0U;
+ for(retries = 0U;(retries < count);retries++)
+ {
+ failCode = 0U;
+ /* Disable PLL1 and PLL2 */
+ failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2);
+ if(failCode != 0U)
+ {
+ break;
+ }
+
+ /* Clear Global Status Register */
+ systemREG1->GBLSTAT = 0x00000301U;
+ /* Clear the ESM PLL slip flags */
+ esmREG->SR1[0U] = ESM_SR1_PLL1SLIP;
+ esmREG->SR4[0U] = ESM_SR4_PLL2SLIP;
+ /* set both PLLs to OSCIN/1*27/(2*1) */
+ systemREG1->PLLCTL1 = 0x20001A00U;
+ systemREG1->PLLCTL2 = 0x3FC0723DU;
+ systemREG2->PLLCTL3 = 0x20001A00U;
+ systemREG1->CSDISCLR = SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2;
+ /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */
+ while ((((systemREG1->CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && ((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) == 0U)) ||
+ (((systemREG1->CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && ((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) == 0U)))
+ {
+ /* Wait */
+ }
+ /* If PLL1 valid, check the frequency */
+ if(((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U))
+ {
+ failCode |= 1U;
+ }
+ else
+ {
+ failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1);
+ }
+ /* If PLL2 valid, check the frequency */
+ if(((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U))
+ {
+ failCode |= 2U;
+ }
+ else
+ {
+ failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U);
+ }
+ if (failCode == 0U)
+ {
+ break;
+ }
+ }
+ /* To avoid MISRA violation 382S
+ (void)missing for discarded return value */
+ failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2);
+ /* restore CLKCNTL, VCLKR and PENA first */
+ systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U);
+ /* restore CLKCNTL, VCLK2R */
+ systemREG1->CLKCNTL = clkCntlSav;
+ return failCode;
+}
+/** @fn uint32 _errata_SSWF021_45_pll1(uint32 count)
+* @brief This handles the errata for PLL1. This function is called in device startup
+*
+* @param[in] count : Number of retries until both PLL1 is locked successfully
+* Minimum value recommended is 5
+*
+* @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled)
+* 1 = PLL1 failed to successfully lock in "count" tries
+* 2 = PLL2 failed to successfully lock in "count" tries
+* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries
+* 4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason
+ is that a PLL is already being used as a clock source. This can be caused by the workaround function
+ being called from the wrong place in the code.
+*/
+uint32 _errata_SSWF021_45_pll1(uint32 count)
+{
+ uint32 failCode,retries,clkCntlSav;
+ /* save CLKCNTL */
+ clkCntlSav = systemREG1->CLKCNTL;
+ /* First set VCLK2 = HCLK */
+ systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U;
+ /* Now set VCLK = HCLK and enable peripherals */
+ systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA;
+ failCode = 0U;
+ for(retries = 0U;(retries < count);retries++)
+ {
+ failCode = 0U;
+ /* Disable PLL1 */
+ failCode = disable_plls(SYS_CLKSRC_PLL1);
+ if(failCode != 0U)
+ {
+ break;
+ }
+
+ /* Clear Global Status Register */
+ systemREG1->GBLSTAT = 0x00000301U;
+ /* Clear the ESM PLL slip flags */
+ esmREG->SR1[0U] = ESM_SR1_PLL1SLIP;
+ /* set PLL1 to OSCIN/1*27/(2*1) */
+ systemREG1->PLLCTL1 = 0x20001A00U;
+ systemREG1->PLLCTL2 = 0x3FC0723DU;
+ systemREG1->CSDISCLR = SYS_CLKSRC_PLL1;
+ /* Check for PLL1 valid or PLL1 slip*/
+ while(((systemREG1->CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && ((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) == 0U))
+ {
+ /* Wait */
+ }
+ /* If PLL1 valid, check the frequency */
+ if(((esmREG->SR1[0U] & ESM_SR1_PLL1SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U))
+ {
+ failCode |= 1U;
+ }
+ else
+ {
+ failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1);
+ }
+ if (failCode == 0U)
+ {
+ break;
+ }
+ }
+ /* To avoid MISRA violation 382S
+ (void)missing for discarded return value */
+ failCode = disable_plls(SYS_CLKSRC_PLL1);
+
+ /* restore CLKCNTL, VCLKR and PENA first */
+ systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U);
+ /* restore CLKCNTL, VCLK2R */
+ systemREG1->CLKCNTL = clkCntlSav;
+ return failCode;
+}
+/** @fn uint32 _errata_SSWF021_45_pll2(uint32 count)
+* @brief This handles the errata for PLL2. This function is called in device startup
+*
+* @param[in] count : Number of retries until PLL2 is locked successfully
+* Minimum value recommended is 5
+*
+* @return 0 = Success (the PLL or both PLLs have successfully locked and then been disabled)
+* 1 = PLL1 failed to successfully lock in "count" tries
+* 2 = PLL2 failed to successfully lock in "count" tries
+* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries
+* 4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason
+ is that a PLL is already being used as a clock source. This can be caused by the workaround function
+ being called from the wrong place in the code.
+*/
+uint32 _errata_SSWF021_45_pll2(uint32 count)
+{
+ uint32 failCode,retries,clkCntlSav;
+ /* save CLKCNTL */
+ clkCntlSav = systemREG1->CLKCNTL;
+ /* First set VCLK2 = HCLK */
+ systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U;
+ /* Now set VCLK = HCLK and enable peripherals */
+ systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA;
+ failCode = 0U;
+ for(retries = 0U;(retries < count);retries++)
+ {
+ failCode = 0U;
+ /* Disable PLL2 */
+ failCode = disable_plls(SYS_CLKSRC_PLL2);
+ if(failCode != 0U)
+ {
+ break;
+ }
+
+ /* Clear Global Status Register */
+ systemREG1->GBLSTAT = 0x00000301U;
+ /* Clear the ESM PLL slip flags */
+ esmREG->SR4[0U] = ESM_SR4_PLL2SLIP;
+ /* set PLL2 to OSCIN/1*27/(2*1) */
+ systemREG2->PLLCTL3 = 0x20001A00U;
+ systemREG1->CSDISCLR = SYS_CLKSRC_PLL2;
+ /* Check for PLL2 valid or PLL2 slip */
+ while (((systemREG1->CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && ((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) == 0U))
+ {
+ /* Wait */
+ }
+ /* If PLL2 valid, check the frequency */
+ if(((esmREG->SR4[0U] & ESM_SR4_PLL2SLIP) != 0U) || ((systemREG1->GBLSTAT & 0x00000300U) != 0U))
+ {
+ failCode |= 2U;
+ }
+ else
+ {
+ failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U);
+ }
+ if (failCode == 0U)
+ {
+ break;
+ }
+ }
+ /* To avoid MISRA violation 382S
+ (void)missing for discarded return value */
+ failCode = disable_plls(SYS_CLKSRC_PLL2);
+ /* restore CLKCNTL, VCLKR and PENA first */
+ systemREG1->CLKCNTL = (clkCntlSav & 0x000F0100U);
+ /* restore CLKCNTL, VCLK2R */
+ systemREG1->CLKCNTL = clkCntlSav;
+ return failCode;
+}
+/** @fn uint32 check_frequency(uint32 cnt1_clksrc)
+* @brief This function checks for the PLL frequency.
+*
+* @param[in] cnt1_clksrc : Clock source for Counter1
+* 0U - PLL1 (clock source 0)
+* 1U - PLL2 (clock source 1)
+*
+* @return DCC Error status
+* 0 - DCC error has not occurred
+* 1 - DCC error has occurred
+*/
+static uint32 check_frequency(uint32 cnt1_clksrc)
+{
+ /* Setup DCC1 */
+ /** DCC1 Global Control register configuration */
+ dccREG1->GCTRL = (uint32)0x5U | /** Disable DCC1 */
+ (uint32)((uint32)0x5U << 4U) | /** No Error Interrupt */
+ (uint32)((uint32)0xAU << 8U) | /** Single Shot mode */
+ (uint32)((uint32)0x5U << 12U); /** No Done Interrupt */
+ /* Clear ERR and DONE bits */
+ dccREG1->STAT = 3U;
+ /** DCC1 Clock0 Counter Seed value configuration */
+ dccREG1->CNT0SEED = 68U;
+ /** DCC1 Clock0 Valid Counter Seed value configuration */
+ dccREG1->VALID0SEED = 4U;
+ /** DCC1 Clock1 Counter Seed value configuration */
+ dccREG1->CNT1SEED = 972U;
+ /** DCC1 Clock1 Source 1 Select */
+ dccREG1->CNT1CLKSRC = (uint32)((uint32)10U << 12U) | /** DCC Enable / Disable Key */
+ (uint32) cnt1_clksrc; /** DCC1 Clock Source 1 */
+
+ dccREG1->CNT0CLKSRC = (uint32)DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */
+
+ /** DCC1 Global Control register configuration */
+ dccREG1->GCTRL = (uint32)0xAU | /** Enable DCC1 */
+ (uint32)((uint32)0x5U << 4U) | /** No Error Interrupt */
+ (uint32)((uint32)0xAU << 8U) | /** Single Shot mode */
+ (uint32)((uint32)0x5U << 12U); /** No Done Interrupt */
+ while(dccREG1->STAT == 0U)
+ {
+ /* Wait */
+ }
+ return (dccREG1->STAT & 0x01U);
+}
+/** @fn uint32 disable_plls(uint32 plls)
+* @brief This function disables plls and clears the respective ESM flags.
+*
+* @param[in] plls : Clock source for Counter1
+* 2U - PLL1
+* 40U - PLL2
+*
+* @return failCode
+* 0 = Success (the PLL or both PLLs have successfully locked and then been disabled)
+* 4 = The workaround function was not able to disable at least one of the PLLs. The most likely reason
+* is that a PLL is already being used as a clock source. This can be caused by the workaround function
+* being called from the wrong place in the code.
+*/
+static uint32 disable_plls(uint32 plls)
+{
+ uint32 timeout,failCode;
+
+ systemREG1->CSDISSET = plls;
+ failCode = 0U;
+ timeout = 0x10U;
+ timeout --;
+ while(((systemREG1->CSVSTAT & (plls)) != 0U) && (timeout != 0U))
+ {
+ /* Clear ESM and GLBSTAT PLL slip flags */
+ systemREG1->GBLSTAT = 0x00000300U;
+
+ if ((plls & SYS_CLKSRC_PLL1) == SYS_CLKSRC_PLL1)
+ {
+ esmREG->SR1[0U] = ESM_SR1_PLL1SLIP;
+ }
+ if ((plls & SYS_CLKSRC_PLL2) == SYS_CLKSRC_PLL2)
+ {
+ esmREG->SR4[0U] = ESM_SR4_PLL2SLIP;
+ }
+ timeout --;
+ /* Wait */
+ }
+ if(timeout == 0U)
+ {
+ failCode = 4U;
+ }
+ else
+ {
+ failCode = 0U;
+ }
+ return failCode;
+}
Index: firmware/source/esm.c
===================================================================
diff -u
--- firmware/source/esm.c (revision 0)
+++ firmware/source/esm.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,802 @@
+/** @file esm.c
+* @brief Esm Driver Source File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - API Functions
+* .
+* which are relevant for the Esm driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "esm.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void esmInit(void)
+* @brief Initializes Esm Driver
+*
+* This function initializes the Esm driver.
+*
+*/
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+/* SourceId : ESM_SourceId_001 */
+/* DesignId : ESM_DesignId_001 */
+/* Requirements : HL_SR4 */
+void esmInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /** - Disable error pin channels */
+ esmREG->DEPAPR1 = 0xFFFFFFFFU;
+ esmREG->IEPCR4 = 0xFFFFFFFFU;
+
+ /** - Disable interrupts */
+ esmREG->IECR1 = 0xFFFFFFFFU;
+ esmREG->IECR4 = 0xFFFFFFFFU;
+
+ /** - Clear error status flags */
+ esmREG->SR1[0U] = 0xFFFFFFFFU;
+ esmREG->SR1[1U] = 0xFFFFFFFFU;
+ esmREG->SSR2 = 0xFFFFFFFFU;
+ esmREG->SR1[2U] = 0xFFFFFFFFU;
+ esmREG->SR4[0U] = 0xFFFFFFFFU;
+
+ /** - Setup LPC preload */
+ esmREG->LTCPR = 16384U - 1U;
+
+ /** - Reset error pin */
+ if (esmREG->EPSR == 0U)
+ {
+ esmREG->EKR = 0x00000005U;
+ }
+ else
+ {
+ esmREG->EKR = 0x00000000U;
+ }
+
+ /** - Clear interrupt level */
+ esmREG->ILCR1 = 0xFFFFFFFFU;
+ esmREG->ILCR4 = 0xFFFFFFFFU;
+
+ /** - Set interrupt level */
+ esmREG->ILSR1 = (uint32)((uint32)0U << 31U)
+ | (uint32)((uint32)0U << 30U)
+ | (uint32)((uint32)0U << 29U)
+ | (uint32)((uint32)0U << 28U)
+ | (uint32)((uint32)0U << 27U)
+ | (uint32)((uint32)0U << 26U)
+ | (uint32)((uint32)0U << 25U)
+ | (uint32)((uint32)0U << 24U)
+ | (uint32)((uint32)0U << 23U)
+ | (uint32)((uint32)0U << 22U)
+ | (uint32)((uint32)0U << 21U)
+ | (uint32)((uint32)0U << 20U)
+ | (uint32)((uint32)0U << 19U)
+ | (uint32)((uint32)0U << 18U)
+ | (uint32)((uint32)0U << 17U)
+ | (uint32)((uint32)0U << 16U)
+ | (uint32)((uint32)0U << 15U)
+ | (uint32)((uint32)0U << 14U)
+ | (uint32)((uint32)0U << 13U)
+ | (uint32)((uint32)0U << 12U)
+ | (uint32)((uint32)0U << 11U)
+ | (uint32)((uint32)0U << 10U)
+ | (uint32)((uint32)0U << 9U)
+ | (uint32)((uint32)0U << 8U)
+ | (uint32)((uint32)0U << 7U)
+ | (uint32)((uint32)0U << 6U)
+ | (uint32)((uint32)0U << 5U)
+ | (uint32)((uint32)0U << 4U)
+ | (uint32)((uint32)0U << 3U)
+ | (uint32)((uint32)0U << 2U)
+ | (uint32)((uint32)0U << 1U)
+ | (uint32)((uint32)0U << 0U);
+
+ esmREG->ILSR4 = (uint32)((uint32)0U << 31U)
+ | (uint32)((uint32)0U << 30U)
+ | (uint32)((uint32)0U << 29U)
+ | (uint32)((uint32)0U << 28U)
+ | (uint32)((uint32)0U << 27U)
+ | (uint32)((uint32)0U << 26U)
+ | (uint32)((uint32)0U << 25U)
+ | (uint32)((uint32)0U << 24U)
+ | (uint32)((uint32)0U << 23U)
+ | (uint32)((uint32)0U << 22U)
+ | (uint32)((uint32)0U << 21U)
+ | (uint32)((uint32)0U << 20U)
+ | (uint32)((uint32)0U << 19U)
+ | (uint32)((uint32)0U << 18U)
+ | (uint32)((uint32)0U << 17U)
+ | (uint32)((uint32)0U << 16U)
+ | (uint32)((uint32)0U << 15U)
+ | (uint32)((uint32)0U << 14U)
+ | (uint32)((uint32)0U << 13U)
+ | (uint32)((uint32)0U << 12U)
+ | (uint32)((uint32)0U << 11U)
+ | (uint32)((uint32)0U << 10U)
+ | (uint32)((uint32)0U << 9U)
+ | (uint32)((uint32)0U << 8U)
+ | (uint32)((uint32)0U << 7U)
+ | (uint32)((uint32)0U << 6U)
+ | (uint32)((uint32)0U << 5U)
+ | (uint32)((uint32)0U << 4U)
+ | (uint32)((uint32)0U << 3U)
+ | (uint32)((uint32)0U << 2U)
+ | (uint32)((uint32)0U << 1U)
+ | (uint32)((uint32)0U << 0U);
+
+ /** - Enable error pin channels */
+ esmREG->EEPAPR1 = (uint32)((uint32)0U << 31U)
+ | (uint32)((uint32)0U << 30U)
+ | (uint32)((uint32)0U << 29U)
+ | (uint32)((uint32)0U << 28U)
+ | (uint32)((uint32)0U << 27U)
+ | (uint32)((uint32)0U << 26U)
+ | (uint32)((uint32)0U << 25U)
+ | (uint32)((uint32)0U << 24U)
+ | (uint32)((uint32)0U << 23U)
+ | (uint32)((uint32)0U << 22U)
+ | (uint32)((uint32)0U << 21U)
+ | (uint32)((uint32)0U << 20U)
+ | (uint32)((uint32)0U << 19U)
+ | (uint32)((uint32)0U << 18U)
+ | (uint32)((uint32)0U << 17U)
+ | (uint32)((uint32)0U << 16U)
+ | (uint32)((uint32)0U << 15U)
+ | (uint32)((uint32)0U << 14U)
+ | (uint32)((uint32)0U << 13U)
+ | (uint32)((uint32)0U << 12U)
+ | (uint32)((uint32)0U << 11U)
+ | (uint32)((uint32)0U << 10U)
+ | (uint32)((uint32)0U << 9U)
+ | (uint32)((uint32)0U << 8U)
+ | (uint32)((uint32)0U << 7U)
+ | (uint32)((uint32)0U << 6U)
+ | (uint32)((uint32)0U << 5U)
+ | (uint32)((uint32)0U << 4U)
+ | (uint32)((uint32)0U << 3U)
+ | (uint32)((uint32)0U << 2U)
+ | (uint32)((uint32)0U << 1U)
+ | (uint32)((uint32)0U << 0U);
+
+ esmREG->IEPSR4 = (uint32)((uint32)0U << 31U)
+ | (uint32)((uint32)0U << 30U)
+ | (uint32)((uint32)0U << 29U)
+ | (uint32)((uint32)0U << 28U)
+ | (uint32)((uint32)0U << 27U)
+ | (uint32)((uint32)0U << 26U)
+ | (uint32)((uint32)0U << 25U)
+ | (uint32)((uint32)0U << 24U)
+ | (uint32)((uint32)0U << 23U)
+ | (uint32)((uint32)0U << 22U)
+ | (uint32)((uint32)0U << 21U)
+ | (uint32)((uint32)0U << 20U)
+ | (uint32)((uint32)0U << 19U)
+ | (uint32)((uint32)0U << 18U)
+ | (uint32)((uint32)0U << 17U)
+ | (uint32)((uint32)0U << 16U)
+ | (uint32)((uint32)0U << 15U)
+ | (uint32)((uint32)0U << 14U)
+ | (uint32)((uint32)0U << 13U)
+ | (uint32)((uint32)0U << 12U)
+ | (uint32)((uint32)0U << 11U)
+ | (uint32)((uint32)0U << 10U)
+ | (uint32)((uint32)0U << 9U)
+ | (uint32)((uint32)0U << 8U)
+ | (uint32)((uint32)0U << 7U)
+ | (uint32)((uint32)0U << 6U)
+ | (uint32)((uint32)0U << 5U)
+ | (uint32)((uint32)0U << 4U)
+ | (uint32)((uint32)0U << 3U)
+ | (uint32)((uint32)0U << 2U)
+ | (uint32)((uint32)0U << 1U)
+ | (uint32)((uint32)0U << 0U);
+
+ /** - Enable interrupts */
+ esmREG->IESR1 = (uint32)((uint32)0U << 31U)
+ | (uint32)((uint32)0U << 30U)
+ | (uint32)((uint32)0U << 29U)
+ | (uint32)((uint32)0U << 28U)
+ | (uint32)((uint32)0U << 27U)
+ | (uint32)((uint32)0U << 26U)
+ | (uint32)((uint32)0U << 25U)
+ | (uint32)((uint32)0U << 24U)
+ | (uint32)((uint32)0U << 23U)
+ | (uint32)((uint32)0U << 22U)
+ | (uint32)((uint32)0U << 21U)
+ | (uint32)((uint32)0U << 20U)
+ | (uint32)((uint32)0U << 19U)
+ | (uint32)((uint32)0U << 18U)
+ | (uint32)((uint32)0U << 17U)
+ | (uint32)((uint32)0U << 16U)
+ | (uint32)((uint32)0U << 15U)
+ | (uint32)((uint32)0U << 14U)
+ | (uint32)((uint32)0U << 13U)
+ | (uint32)((uint32)0U << 12U)
+ | (uint32)((uint32)0U << 11U)
+ | (uint32)((uint32)0U << 10U)
+ | (uint32)((uint32)0U << 9U)
+ | (uint32)((uint32)0U << 8U)
+ | (uint32)((uint32)0U << 7U)
+ | (uint32)((uint32)0U << 6U)
+ | (uint32)((uint32)0U << 5U)
+ | (uint32)((uint32)0U << 4U)
+ | (uint32)((uint32)0U << 3U)
+ | (uint32)((uint32)0U << 2U)
+ | (uint32)((uint32)0U << 1U)
+ | (uint32)((uint32)0U << 0U);
+
+ esmREG->IESR4 = (uint32)((uint32)0U << 31U)
+ | (uint32)((uint32)0U << 30U)
+ | (uint32)((uint32)0U << 29U)
+ | (uint32)((uint32)0U << 28U)
+ | (uint32)((uint32)0U << 27U)
+ | (uint32)((uint32)0U << 26U)
+ | (uint32)((uint32)0U << 25U)
+ | (uint32)((uint32)0U << 24U)
+ | (uint32)((uint32)0U << 23U)
+ | (uint32)((uint32)0U << 22U)
+ | (uint32)((uint32)0U << 21U)
+ | (uint32)((uint32)0U << 20U)
+ | (uint32)((uint32)0U << 19U)
+ | (uint32)((uint32)0U << 18U)
+ | (uint32)((uint32)0U << 17U)
+ | (uint32)((uint32)0U << 16U)
+ | (uint32)((uint32)0U << 15U)
+ | (uint32)((uint32)0U << 14U)
+ | (uint32)((uint32)0U << 13U)
+ | (uint32)((uint32)0U << 12U)
+ | (uint32)((uint32)0U << 11U)
+ | (uint32)((uint32)0U << 10U)
+ | (uint32)((uint32)0U << 9U)
+ | (uint32)((uint32)0U << 8U)
+ | (uint32)((uint32)0U << 7U)
+ | (uint32)((uint32)0U << 6U)
+ | (uint32)((uint32)0U << 5U)
+ | (uint32)((uint32)0U << 4U)
+ | (uint32)((uint32)0U << 3U)
+ | (uint32)((uint32)0U << 2U)
+ | (uint32)((uint32)0U << 1U)
+ | (uint32)((uint32)0U << 0U);
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+
+/** @fn uint32 esmError(void)
+* @brief Return Error status
+*
+* @return The error status
+*
+* Returns the error status.
+*/
+/* SourceId : ESM_SourceId_002 */
+/* DesignId : ESM_DesignId_002 */
+/* Requirements : HL_SR5 */
+uint32 esmError(void)
+{
+ uint32 status;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+ status = esmREG->EPSR;
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ return status;
+}
+
+
+/** @fn void esmEnableError(uint64 channels)
+* @brief Enable Group 1 Channels Error Signals propagation
+*
+* @param[in] channels - Channel mask
+*
+* Enable Group 1 Channels Error Signals propagation to the error pin.
+*/
+/* SourceId : ESM_SourceId_003 */
+/* DesignId : ESM_DesignId_003 */
+/* Requirements : HL_SR6 */
+void esmEnableError(uint64 channels)
+{
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ esmREG->IEPSR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+ esmREG->EEPAPR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmDisableError(uint64 channels)
+* @brief Disable Group 1 Channels Error Signals propagation
+*
+* @param[in] channels - Channel mask
+*
+* Disable Group 1 Channels Error Signals propagation to the error pin.
+*/
+/* SourceId : ESM_SourceId_004 */
+/* DesignId : ESM_DesignId_004 */
+/* Requirements : HL_SR7 */
+void esmDisableError(uint64 channels)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ esmREG->IEPCR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+ esmREG->DEPAPR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmTriggerErrorPinReset(void)
+* @brief Trigger error pin reset and switch back to normal operation
+*
+* Trigger error pin reset and switch back to normal operation.
+*/
+/* SourceId : ESM_SourceId_005 */
+/* DesignId : ESM_DesignId_005 */
+/* Requirements : HL_SR8 */
+void esmTriggerErrorPinReset(void)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ esmREG->EKR = 5U;
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmActivateNormalOperation(void)
+* @brief Activate normal operation
+*
+* Activates normal operation mode.
+*/
+/* SourceId : ESM_SourceId_006 */
+/* DesignId : ESM_DesignId_006 */
+/* Requirements : HL_SR9 */
+void esmActivateNormalOperation(void)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ esmREG->EKR = 0U;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmEnableInterrupt(uint64 channels)
+* @brief Enable Group 1 Channels Interrupts
+*
+* @param[in] channels - Channel mask
+*
+* Enable Group 1 Channels Interrupts.
+*/
+/* SourceId : ESM_SourceId_007 */
+/* DesignId : ESM_DesignId_007 */
+/* Requirements : HL_SR10 */
+void esmEnableInterrupt(uint64 channels)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ esmREG->IESR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+ esmREG->IESR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmDisableInterrupt(uint64 channels)
+* @brief Disable Group 1 Channels Interrupts
+*
+* @param[in] channels - Channel mask
+*
+* Disable Group 1 Channels Interrupts.
+*/
+/* SourceId : ESM_SourceId_008 */
+/* DesignId : ESM_DesignId_008 */
+/* Requirements : HL_SR11 */
+void esmDisableInterrupt(uint64 channels)
+{
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ esmREG->IECR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+ esmREG->IECR1 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags)
+* @brief Set Group 1 Channels Interrupt Levels
+*
+* @param[in] channels - Channel mask
+* @param[in] flags - Level mask: - 0: Low priority interrupt
+* - 1: High priority interrupt
+*
+* Set Group 1 Channels Interrupts levels.
+*/
+/* SourceId : ESM_SourceId_009 */
+/* DesignId : ESM_DesignId_009 */
+/* Requirements : HL_SR12 */
+void esmSetInterruptLevel(uint64 channels, uint64 flags)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ esmREG->ILCR4 = (uint32)(((channels & (~flags)) >> 32U) & 0xFFFFFFFFU);
+ esmREG->ILSR4 = (uint32)(((channels & flags) >> 32U) & 0xFFFFFFFFU);
+ esmREG->ILCR1 = (uint32)((channels & (~flags)) & 0xFFFFFFFFU);
+ esmREG->ILSR1 = (uint32)((channels & flags) & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmClearStatus(uint32 group, uint64 channels)
+* @brief Clear Group error status
+*
+* @param[in] group - Error group
+* @param[in] channels - Channel mask
+*
+* Clear Group error status.
+*/
+/* SourceId : ESM_SourceId_010 */
+/* DesignId : ESM_DesignId_010 */
+/* Requirements : HL_SR13 */
+void esmClearStatus(uint32 group, uint64 channels)
+{
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+ esmREG->SR1[group] = (uint32)(channels & 0xFFFFFFFFU);
+ if(group == 0U)
+ {
+ esmREG->SR4[group] = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
+ }
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmClearStatusBuffer(uint64 channels)
+* @brief Clear Group 2 error status buffer
+*
+* @param[in] channels - Channel mask
+*
+* Clear Group 2 error status buffer.
+*/
+/* SourceId : ESM_SourceId_011 */
+/* DesignId : ESM_DesignId_011 */
+/* Requirements : HL_SR14 */
+void esmClearStatusBuffer(uint64 channels)
+{
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ esmREG->SSR2 = (uint32)(channels & 0xFFFFFFFFU);
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+
+/** @fn void esmSetCounterPreloadValue(uint32 value)
+* @brief Set counter preload value
+*
+* @param[in] value - Counter preload value
+*
+* Set counter preload value.
+*/
+/* SourceId : ESM_SourceId_012 */
+/* DesignId : ESM_DesignId_012 */
+/* Requirements : HL_SR15 */
+void esmSetCounterPreloadValue(uint32 value)
+{
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+ esmREG->LTCPR = value & 0xC000U;
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+
+/** @fn uint64 esmGetStatus(uint32 group, uint64 channels)
+* @brief Return Error status
+*
+* @param[in] group - Error group
+* @param[in] channels - Error Channels
+*
+* @return The channels status of selected group
+*
+* Returns the channels status of selected group.
+*/
+/* SourceId : ESM_SourceId_013 */
+/* DesignId : ESM_DesignId_013 */
+/* Requirements : HL_SR16 */
+uint64 esmGetStatus(uint32 group, uint64 channels)
+{
+ uint64 status;
+ uint32 ESM_ESTATUS4, ESM_ESTATUS1;
+ if(group == 0U)
+ {
+ ESM_ESTATUS4 = esmREG->SR4[group];
+ }
+ else
+ {
+ ESM_ESTATUS4 = 0U;
+ }
+ ESM_ESTATUS1 = esmREG->SR1[group];
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+ status = (((uint64)(ESM_ESTATUS4) << 32U) | (uint64)ESM_ESTATUS1) & channels;
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ return status;
+}
+
+
+/** @fn uint64 esmGetStatusBuffer(uint64 channels)
+* @brief Return Group 2 channel x Error status buffer
+*
+* @param[in] channels - Error Channels
+*
+* @return The channels status
+*
+* Returns the group 2 buffered status of selected channels.
+*/
+/* SourceId : ESM_SourceId_014 */
+/* DesignId : ESM_DesignId_014 */
+/* Requirements : HL_SR17 */
+uint64 esmGetStatusBuffer(uint64 channels)
+{
+ uint64 status;
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+ status = ((uint64)esmREG->SSR2) & channels;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ return status;
+}
+
+/** @fn esmSelfTestFlag_t esmEnterSelfTest(void)
+* @brief Return ESM Self test status
+*
+* @return ESM Self test status
+*
+* Returns the ESM Self test status.
+*/
+/* SourceId : ESM_SourceId_015 */
+/* DesignId : ESM_DesignId_015 */
+/* Requirements : HL_SR19 */
+esmSelfTestFlag_t esmEnterSelfTest(void)
+{
+ esmSelfTestFlag_t status;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+
+ uint32 errPinStat = esmREG->EPSR & 0x1U;
+ uint32 esmKeyReg = esmREG->EKR;
+ if((errPinStat == 0x0U) && (esmKeyReg == 0x0U))
+ {
+ status = esmSelfTest_NotStarted;
+ }
+ else
+ {
+ esmREG->EKR = 0xAU;
+ status = esmSelfTest_Active;
+ if((esmREG->EPSR & 0x1U) != 0x0U)
+ {
+ status = esmSelfTest_Failed;
+ }
+ esmREG->EKR = 0x5U;
+ }
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+ return status;
+}
+
+/** @fn esmSelfTestFlag_t esmSelfTestStatus(void)
+* @brief Return ESM Self test status
+*
+* Returns the ESM Self test status.
+*/
+/* SourceId : ESM_SourceId_016 */
+/* DesignId : ESM_DesignId_016 */
+/* Requirements : HL_SR18 */
+esmSelfTestFlag_t esmSelfTestStatus(void)
+{
+ esmSelfTestFlag_t status;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+ if((esmREG->EPSR & 0x1U) == 0x0U)
+ {
+ if(esmREG->EKR == 0x5U)
+ {
+ status = esmSelfTest_Active;
+ }
+ else
+ {
+ status = esmSelfTest_Failed;
+ }
+ }
+ else
+ {
+ status = esmSelfTest_Passed;
+ }
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+ return status;
+}
+
+/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ESM_SourceId_017 */
+/* DesignId : ESM_DesignId_017 */
+/* Requirements : HL_SR20, HL_SR24 */
+void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_EEPAPR1 = ESM_EEPAPR1_CONFIGVALUE;
+ config_reg->CONFIG_IESR1 = ESM_IESR1_CONFIGVALUE;
+ config_reg->CONFIG_ILSR1 = ESM_ILSR1_CONFIGVALUE;
+ config_reg->CONFIG_LTCPR = ESM_LTCPR_CONFIGVALUE;
+ config_reg->CONFIG_EKR = ESM_EKR_CONFIGVALUE;
+ config_reg->CONFIG_IEPSR4 = ESM_IEPSR4_CONFIGVALUE;
+ config_reg->CONFIG_IESR4 = ESM_IESR4_CONFIGVALUE;
+ config_reg->CONFIG_ILSR4 = ESM_ILSR4_CONFIGVALUE;
+ }
+ else
+ {
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_EEPAPR1 = esmREG->EEPAPR1;
+ config_reg->CONFIG_IESR1 = esmREG->IESR1;
+ config_reg->CONFIG_ILSR1 = esmREG->ILSR1;
+ config_reg->CONFIG_LTCPR = esmREG->LTCPR;
+ config_reg->CONFIG_EKR = esmREG->EKR;
+ config_reg->CONFIG_IEPSR4 = esmREG->IEPSR4;
+ config_reg->CONFIG_IESR4 = esmREG->IESR4;
+ config_reg->CONFIG_ILSR4 = esmREG->ILSR4;
+ }
+}
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+/** @fn void esmHighInterrupt(void)
+* @brief High Level Interrupt for ESM
+*/
+#pragma CODE_STATE(esmHighInterrupt, 32)
+#pragma INTERRUPT(esmHighInterrupt, FIQ)
+/* SourceId : ESM_SourceId_018 */
+/* DesignId : ESM_DesignId_018 */
+/* Requirements : HL_SR21, HL_SR22 */
+void esmHighInterrupt(void)
+{
+ uint32 vec = esmREG->IOFFHR - 1U;
+
+/* USER CODE BEGIN (36) */
+/* USER CODE END */
+
+ if (vec < 32U)
+ {
+ esmREG->SR1[0U] = (uint32)1U << vec;
+ esmGroup1Notification(vec);
+ }
+ else if (vec < 64U)
+ {
+ esmREG->SR1[1U] = (uint32)1U << (vec-32U);
+ esmGroup2Notification(vec-32U);
+ }
+ else if (vec < 96U)
+ {
+ esmREG->SR4[0U] = (uint32)1U << (vec-64U);
+ esmGroup1Notification(vec-32U);
+ }
+ else
+ {
+ esmREG->SR4[0U] = 0xFFFFFFFFU;
+ esmREG->SR1[1U] = 0xFFFFFFFFU;
+ esmREG->SR1[0U] = 0xFFFFFFFFU;
+ }
+
+/* USER CODE BEGIN (37) */
+/* USER CODE END */
+}
+
+
+/* USER CODE BEGIN (41) */
+/* USER CODE END */
Index: firmware/source/etpwm.c
===================================================================
diff -u
--- firmware/source/etpwm.c (revision 0)
+++ firmware/source/etpwm.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,2134 @@
+/** @file etpwm.c
+* @brief ETPWM Driver Source File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+* This file contains:
+* - API Functions
+* - Interrupt Handlers
+* .
+* which are relevant for the ETPWM driver.
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#include "etpwm.h"
+#include "pinmux.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+
+/** @fn void etpwmInit(void)
+* @brief Initializes the eTPWM Driver
+*
+* This function initializes the eTPWM module.
+*
+* @note This function sets the time-base counters in up-count mode.
+* Application can configure the module in a different mode using other functions in this driver.(Sample code provided in the examples folder)
+* In that case, application need not call etpwmInit function.
+* pinmuxInit needs to be called before this function.
+*
+*/
+/* SourceId : ETPWM_SourceId_001 */
+/* DesignId : ETPWM_DesignId_001 */
+/* Requirements : HL_EPWM_SR1 */
+void etpwmInit(void)
+{
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+ /** @b initialize @b ETPWM1 */
+
+ /** - Sets high speed time-base clock prescale bits */
+ etpwmREG1->TBCTL = (uint16)0U << 7U;
+
+ /** - Sets time-base clock prescale bits */
+ etpwmREG1->TBCTL |= (uint16)((uint16)0U << 10U);
+
+ /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
+ etpwmREG1->TBPRD = 25833U;
+
+ /** - Setup the duty cycle for PWMA */
+ etpwmREG1->CMPA = 0U;
+
+ /** - Setup the duty cycle for PWMB */
+ etpwmREG1->CMPB = 0U;
+
+ /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
+ etpwmREG1->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 4U));
+
+ /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */
+ etpwmREG1->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 8U));
+
+ /** - Mode setting for Dead Band Module
+ * -Select the input mode for Dead Band Module
+ * -Select the output mode for Dead Band Module
+ * -Select Polarity of the output PWMs
+ */
+ etpwmREG1->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0u << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */
+ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */
+ | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */
+ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */
+
+ /** - Set the rising edge delay */
+ etpwmREG1->DBRED = 1U;
+
+ /** - Set the falling edge delay */
+ etpwmREG1->DBFED = 1U ;
+
+ /** - Enable the chopper module for ETPWMx
+ * -Sets the One shot pulse width in a chopper modulated wave
+ * -Sets the dutycycle for the subsequent pulse train
+ * -Sets the period for the subsequent pulse train
+ */
+ etpwmREG1->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
+ | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */
+ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */
+ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */
+
+ /** - Set trip source enable */
+ etpwmREG1->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */
+ | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */
+
+ /** - Set interrupt enable */
+ etpwmREG1->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable one-shot interrupt generation */
+ | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */
+
+ /** - Sets up the event for interrupt */
+ etpwmREG1->ETSEL = (uint16)NO_EVENT;
+
+ if ((etpwmREG1->ETSEL & 0x0007U) != 0U)
+ {
+ etpwmREG1->ETSEL |= 0x0008U;
+ }
+ /** - Setup the frequency of the interrupt generation */
+ etpwmREG1->ETPS = 1U;
+
+ /** - Sets up the ADC SOC interrupt */
+ etpwmREG1->ETSEL |= ((uint16)(0x0000U)
+ | (uint16)(0x0000U)
+ | (uint16)((uint16)DCAEVT1 << 8U)
+ | (uint16)((uint16)DCBEVT1 << 12U));
+
+ /** - Sets up the ADC SOC period */
+ etpwmREG1->ETPS |= ((uint16)((uint16)1U << 8U)
+ | (uint16)((uint16)1U << 12U));
+
+ /** @b initialize @b ETPWM2 */
+
+ /** - Sets high speed time-base clock prescale bits */
+ etpwmREG2->TBCTL = (uint16)0U << 7U;
+
+ /** - Sets time-base clock prescale bits */
+ etpwmREG2->TBCTL |= (uint16)((uint16)0U << 10U);
+
+ /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
+ etpwmREG2->TBPRD = 25833U;
+
+ /** - Setup the duty cycle for PWMA */
+ etpwmREG2->CMPA = 0U;
+
+ /** - Setup the duty cycle for PWMB */
+ etpwmREG2->CMPB = 0U;
+
+ /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
+ etpwmREG2->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 4U));
+
+ /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */
+ etpwmREG2->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 8U));
+
+ /** - Mode setting for Dead Band Module
+ * -Select the input mode for Dead Band Module
+ * -Select the output mode for Dead Band Module
+ * -Select Polarity of the output PWMs
+ */
+ etpwmREG2->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */
+ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */
+ | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */
+ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */
+
+ /** - Set the rising edge delay */
+ etpwmREG2->DBRED = 1U;
+
+ /** - Set the falling edge delay */
+ etpwmREG2->DBFED = 1U;
+
+ /** - Enable the chopper module for ETPWMx
+ * -Sets the One shot pulse width in a chopper modulated wave
+ * -Sets the dutycycle for the subsequent pulse train
+ * -Sets the period for the subsequent pulse train
+ */
+ etpwmREG2->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
+ | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */
+ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */
+ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */
+
+ /** - Set trip source enable */
+ etpwmREG2->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */
+ | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */
+
+ /** - Set interrupt enable */
+ etpwmREG2->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable one-shot interrupt generation */
+ | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */
+
+ /** - Sets up the event for interrupt */
+ etpwmREG2->ETSEL = (uint16)NO_EVENT;
+
+ if ((etpwmREG2->ETSEL & 0x0007U) != 0U)
+ {
+ etpwmREG2->ETSEL |= 0x0008U;
+ }
+ /** - Setup the frequency of the interrupt generation */
+ etpwmREG2->ETPS = 1U;
+
+ /** - Sets up the ADC SOC interrupt */
+ etpwmREG2->ETSEL |= ((uint16)(0x0000U)
+ | (uint16)(0x0000U)
+ | (uint16)((uint16)DCAEVT1 << 8U)
+ | (uint16)((uint16)DCBEVT1 << 12U));
+
+ /** - Sets up the ADC SOC period */
+ etpwmREG2->ETPS |= ((uint16)((uint16)1U << 8U)
+ | (uint16)((uint16)1U << 12U));
+
+ /** @b initialize @b ETPWM3 */
+
+ /** - Sets high speed time-base clock prescale bits */
+ etpwmREG3->TBCTL = (uint16)0U << 7U;
+
+ /** - Sets time-base clock prescale bits */
+ etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U);
+
+ /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
+ etpwmREG3->TBPRD = 25833U;
+
+ /** - Setup the duty cycle for PWMA */
+ etpwmREG3->CMPA = 0U;
+
+ /** - Setup the duty cycle for PWMB */
+ etpwmREG3->CMPB = 0U;
+
+ /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
+ etpwmREG3->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 4U));
+
+ /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */
+ etpwmREG3->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 8U));
+
+ /** - Mode setting for Dead Band Module
+ * -Select the input mode for Dead Band Module
+ * -Select the output mode for Dead Band Module
+ * -Select Polarity of the output PWMs
+ */
+ etpwmREG3->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */
+ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */
+ | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */
+ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */
+
+ /** - Set the rising edge delay */
+ etpwmREG3->DBRED = 1U;
+
+ /** - Set the falling edge delay */
+ etpwmREG3->DBFED = 1U;
+
+ /** - Enable the chopper module for ETPWMx
+ * -Sets the One shot pulse width in a chopper modulated wave
+ * -Sets the dutycycle for the subsequent pulse train
+ * -Sets the period for the subsequent pulse train
+ */
+ etpwmREG3->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
+ | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */
+ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */
+ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */
+
+ /** - Set trip source enable */
+ etpwmREG3->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */
+ | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */
+
+ /** - Set interrupt enable */
+ etpwmREG3->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable one-shot interrupt generation */
+ | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */
+
+
+ /** - Sets up the event for interrupt */
+ etpwmREG3->ETSEL = (uint16)NO_EVENT;
+
+ if ((etpwmREG3->ETSEL & 0x0007U) != 0U)
+ {
+ etpwmREG3->ETSEL |= 0x0008U;
+ }
+ /** - Setup the frequency of the interrupt generation */
+ etpwmREG3->ETPS = 1U;
+
+ /** - Sets up the ADC SOC interrupt */
+ etpwmREG3->ETSEL |= ((uint16)(0x0000U)
+ | (uint16)(0x0000U)
+ | (uint16)((uint16)DCAEVT1 << 8U)
+ | (uint16)((uint16)DCBEVT1 << 12U));
+
+ /** - Sets up the ADC SOC period */
+ etpwmREG3->ETPS |= ((uint16)((uint16)1U << 8U)
+ | (uint16)((uint16)1U << 12U));
+
+ /** @b initialize @b ETPWM4 */
+
+ /** - Sets high speed time-base clock prescale bits */
+ etpwmREG4->TBCTL = (uint16)0U << 7U;
+
+ /** - Sets time-base clock prescale bits */
+ etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U);
+
+ /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
+ etpwmREG4->TBPRD = 25999U;
+
+ /** - Setup the duty cycle for PWMA */
+ etpwmREG4->CMPA = 0U;
+
+ /** - Setup the duty cycle for PWMB */
+ etpwmREG4->CMPB = 0U;
+
+ /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
+ etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 4U));
+
+ /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */
+ etpwmREG4->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 8U));
+
+ /** - Mode setting for Dead Band Module
+ * -Select the input mode for Dead Band Module
+ * -Select the output mode for Dead Band Module
+ * -Select Polarity of the output PWMs
+ */
+ etpwmREG4->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */
+ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */
+ | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */
+ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */
+
+ /** - Set the rising edge delay */
+ etpwmREG4->DBRED = 1U;
+
+ /** - Set the falling edge delay */
+ etpwmREG4->DBFED = 1U;
+
+ /** - Enable the chopper module for ETPWMx
+ * -Sets the One shot pulse width in a chopper modulated wave
+ * -Sets the dutycycle for the subsequent pulse train
+ * -Sets the period for the subsequent pulse train
+ */
+ etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
+ | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */
+ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */
+ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */
+
+ /** - Set trip source enable */
+ etpwmREG4->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */
+ | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */
+
+ /** - Set interrupt enable */
+ etpwmREG4->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable one-shot interrupt generation */
+ | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */
+
+ /** - Sets up the event for interrupt */
+ etpwmREG4->ETSEL = (uint16)NO_EVENT;
+
+ if ((etpwmREG4->ETSEL & 0x0007U) != 0U)
+ {
+ etpwmREG4->ETSEL |= 0x0008U;
+ }
+ /** - Setup the frequency of the interrupt generation */
+ etpwmREG4->ETPS = 1U;
+
+ /** - Sets up the ADC SOC interrupt */
+ etpwmREG4->ETSEL |= (uint16)(0x0000U)
+ | (uint16)(0x0000U)
+ | (uint16)((uint16)DCAEVT1 << 8U)
+ | (uint16)((uint16)DCBEVT1 << 12U);
+
+ /** - Sets up the ADC SOC period */
+ etpwmREG4->ETPS |= ((uint16)((uint16)1U << 8U)
+ | (uint16)((uint16)1U << 12U));
+
+ /** @b initialize @b ETPWM6 */
+
+ /** - Sets high speed time-base clock prescale bits */
+ etpwmREG6->TBCTL = (uint16)0U << 7U;
+
+ /** - Sets time-base clock prescale bits */
+ etpwmREG6->TBCTL |= (uint16)((uint16)0U << 10U);
+
+ /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
+ etpwmREG6->TBPRD = 25833U;
+
+ /** - Setup the duty cycle for PWMA */
+ etpwmREG6->CMPA = 0U;
+
+ /** - Setup the duty cycle for PWMB */
+ etpwmREG6->CMPB = 0U;
+
+
+ /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
+ etpwmREG6->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 4U));
+
+ /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */
+ etpwmREG6->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 8U));
+
+ /** - Mode setting for Dead Band Module
+ * -Select the input mode for Dead Band Module
+ * -Select the output mode for Dead Band Module
+ * -Select Polarity of the output PWMs
+ */
+ etpwmREG6->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */
+ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */
+ | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */
+ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */
+
+ /** - Set the rising edge delay */
+ etpwmREG6->DBRED = 1U;
+
+ /** - Set the falling edge delay */
+ etpwmREG6->DBFED = 1U;
+
+ /** - Enable the chopper module for ETPWMx
+ * -Sets the One shot pulse width in a chopper modulated wave
+ * -Sets the dutycycle for the subsequent pulse train
+ * -Sets the period for the subsequent pulse train
+ */
+ etpwmREG6->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
+ | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */
+ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */
+ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */
+
+
+ /** - Set trip source enable */
+ etpwmREG6->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */
+ | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */
+
+ /** - Set interrupt enable */
+ etpwmREG6->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable one-shot interrupt generation */
+ | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */
+
+
+ /** - Sets up the event for interrupt */
+ etpwmREG6->ETSEL = (uint16)NO_EVENT;
+
+ if ((etpwmREG6->ETSEL & 0x0007U) != 0U)
+ {
+ etpwmREG6->ETSEL |= 0x0008U;
+ }
+ /** - Setup the frequency of the interrupt generation */
+ etpwmREG6->ETPS = 1U;
+
+ /** - Sets up the ADC SOC interrupt */
+ etpwmREG6->ETSEL |= (uint16)(0x0000U)
+ | (uint16)(0x0000U)
+ | (uint16)((uint16)DCAEVT1 << 8U)
+ | (uint16)((uint16)DCBEVT1 << 12U);
+
+ /** - Sets up the ADC SOC period */
+ etpwmREG6->ETPS |= ((uint16)((uint16)1U << 8U)
+ | (uint16)((uint16)1U << 12U));
+
+ /** @b initialize @b ETPWM7 */
+
+ /** - Sets high speed time-base clock prescale bits */
+ etpwmREG7->TBCTL = (uint16)0U << 7U;
+
+ /** - Sets time-base clock prescale bits */
+ etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U);
+
+ /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
+ etpwmREG7->TBPRD = 4159U;
+
+ /** - Setup the duty cycle for PWMA */
+ etpwmREG7->CMPA = 0U;
+
+ /** - Setup the duty cycle for PWMB */
+ etpwmREG7->CMPB = 0U;
+
+
+ /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
+ etpwmREG7->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 4U));
+
+ /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */
+ etpwmREG7->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U)
+ | (uint16)((uint16)ActionQual_Clear << 8U));
+
+ /** - Mode setting for Dead Band Module
+ * -Select the input mode for Dead Band Module
+ * -Select the output mode for Dead Band Module
+ * -Select Polarity of the output PWMs
+ */
+ etpwmREG7->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */
+ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */
+ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */
+ | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */
+ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */
+
+ /** - Set the rising edge delay */
+ etpwmREG7->DBRED = 1U;
+
+ /** - Set the falling edge delay */
+ etpwmREG7->DBFED = 1U;
+
+ /** - Enable the chopper module for ETPWMx
+ * -Sets the One shot pulse width in a chopper modulated wave
+ * -Sets the dutycycle for the subsequent pulse train
+ * -Sets the period for the subsequent pulse train
+ */
+ etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
+ | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */
+ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */
+ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */
+
+
+ /** - Set trip source enable */
+ etpwmREG7->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */
+ | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */
+ | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */
+ | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */
+
+ /** - Set interrupt enable */
+ etpwmREG7->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */
+ | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */
+ | 0x0000U /** - Enable/Disable one-shot interrupt generation */
+ | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */
+
+ /** - Sets up the event for interrupt */
+ etpwmREG7->ETSEL = (uint16)NO_EVENT;
+
+ if ((etpwmREG7->ETSEL & 0x0007U) != 0U)
+ {
+ etpwmREG7->ETSEL |= 0x0008U;
+ }
+ /** - Setup the frequency of the interrupt generation */
+ etpwmREG7->ETPS = 1U;
+
+ /** - Sets up the ADC SOC interrupt */
+ etpwmREG7->ETSEL |= (uint16)(0x0000U)
+ | (uint16)(0x0000U)
+ | (uint16)((uint16)DCAEVT1 << 8U)
+ | (uint16)((uint16)DCBEVT1 << 12U);
+
+ /** - Sets up the ADC SOC period */
+ etpwmREG7->ETPS |= ((uint16)((uint16)1U << 8U)
+ | (uint16)((uint16)1U << 12U));
+
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+}
+
+/** @fn void etpwmStartTBCLK()
+* @brief Start the time-base clocks of all eTPWMx modules
+*
+* This function starts the time-base clocks of all eTPWMx modules.
+*/
+/* SourceId : ETPWM_SourceId_002 */
+/* DesignId : ETPWM_DesignId_002 */
+/* Requirements : HL_EPWM_SR36 */
+void etpwmStartTBCLK(void)
+{
+ /* Enable Pin Muxing */
+ kickerReg->KICKER0 = 0x83E70B13U;
+ kickerReg->KICKER1 = 0x95A4F1E0U;
+
+ pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_ON);
+
+ /* Disable Pin Muxing */
+ kickerReg->KICKER0 = 0x00000000U;
+ kickerReg->KICKER1 = 0x00000000U;
+}
+
+/** @fn void etpwmStopTBCLK()
+* @brief Stop the time-base clocks of all eTPWMx modules
+*
+* This function stops the time-base clocks of all eTPWMx modules.
+*/
+/* SourceId : ETPWM_SourceId_003 */
+/* DesignId : ETPWM_DesignId_003 */
+/* Requirements : HL_EPWM_SR36 */
+void etpwmStopTBCLK(void)
+{
+ /* Enable Pin Muxing */
+ kickerReg->KICKER0 = 0x83E70B13U;
+ kickerReg->KICKER1 = 0x95A4F1E0U;
+
+ pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_OFF);
+
+ /* Disable Pin Muxing */
+ kickerReg->KICKER0 = 0x00000000U;
+ kickerReg->KICKER1 = 0x00000000U;
+}
+
+/** @fn void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t hspclkdiv)
+* @brief Sets the Time-base Clock divider
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param clkdiv Time-base clock divider
+* - ClkDiv_by_1
+* - ClkDiv_by_2
+* - ClkDiv_by_4
+* - ClkDiv_by_8
+* - ClkDiv_by_16
+* - ClkDiv_by_32
+* - ClkDiv_by_64
+* - ClkDiv_by_128
+* @param hspclkdiv High Speed Time-base clock divider
+* - HspClkDiv_by_1
+* - HspClkDiv_by_2
+* - HspClkDiv_by_4
+* - HspClkDiv_by_6
+* - HspClkDiv_by_8
+* - HspClkDiv_by_10
+* - HspClkDiv_by_12
+* - HspClkDiv_by_14
+*
+* This function sets the TimeBase Clock and the High Speed time base clock divider
+* TBCLK = VCLK4 / (HSPCLKDIV � CLKDIV)
+*/
+/* SourceId : ETPWM_SourceId_004 */
+/* DesignId : ETPWM_DesignId_004 */
+/* Requirements : HL_EPWM_SR2 */
+void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t hspclkdiv)
+{
+ etpwm->TBCTL &= (uint16)~(uint16)0x1F80U;
+ etpwm->TBCTL |= (uint16)clkdiv | (uint16)hspclkdiv;
+}
+
+/** @fn void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period)
+* @brief Sets period of timebase counter
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param period 16-bit Time-base period
+*
+* This function sets period of timebase counter
+*/
+/* SourceId : ETPWM_SourceId_005 */
+/* DesignId : ETPWM_DesignId_005 */
+/* Requirements : HL_EPWM_SR3 */
+void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period)
+{
+ etpwm->TBPRD = period;
+}
+
+/** @fn void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count)
+* @brief Sets timebase counter
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param count 16-bit Counter value
+*
+* This function sets the timebase counter
+*/
+/* SourceId : ETPWM_SourceId_006 */
+/* DesignId : ETPWM_DesignId_006 */
+/* Requirements : HL_EPWM_SR4 */
+void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count)
+{
+ etpwm->TBCTR = count;
+}
+
+/** @fn void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm)
+* @brief Disable shadow mode for time-base period register
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function disables shadow mode for time-base period register
+*/
+/* SourceId : ETPWM_SourceId_007 */
+/* DesignId : ETPWM_DesignId_007 */
+/* Requirements : HL_EPWM_SR5 */
+void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm)
+{
+ etpwm->TBCTL |= 0x0008U;
+}
+
+/** @fn void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm)
+* @brief Enable shadow mode for time-base period register
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function enables shadow mode for time-base period register
+*/
+/* SourceId : ETPWM_SourceId_008 */
+/* DesignId : ETPWM_DesignId_008 */
+/* Requirements : HL_EPWM_SR5 */
+void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm)
+{
+ etpwm->TBCTL &= (uint16)~(uint16)0x0008U;
+}
+
+/** @fn void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 direction)
+* @brief Enable counter register load from phase register when a sync event occurs
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param phase Counter value to be loaded when a sync event occurs
+* @param direction Direction of the counter after the sync event (Applied only if counter is in updown-count mode, ignores otherwise)
+* - COUNT_UP
+* - COUNT_DOWN
+* - Pass 0 if not applied
+*
+* This function enables counter register load from phase register when a sync event occurs
+*/
+/* SourceId : ETPWM_SourceId_009 */
+/* DesignId : ETPWM_DesignId_009 */
+/* Requirements : HL_EPWM_SR6 */
+void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 direction)
+{
+ etpwm->TBCTL &= (uint16)~(uint16)0x2000U;
+ etpwm->TBCTL |= 0x0004U | direction;
+ etpwm->TBPHS = phase;
+}
+
+/** @fn void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm)
+* @brief Disable counter register load from phase register when a sync event occurs
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function disables counter register load from phase register when a sync event occurs
+*/
+/* SourceId : ETPWM_SourceId_010 */
+/* DesignId : ETPWM_DesignId_010 */
+/* Requirements : HL_EPWM_SR6 */
+void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm)
+{
+ etpwm->TBCTL &= (uint16)~(uint16)0x0004U;
+}
+
+/** @fn void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncMode_t syncmode)
+* @brief Set the source of EPWMxSYNCO signal
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param syncOutSrc Synchronization Output Select
+* - SyncOut_EPWMxSYNCI
+* - SyncOut_CtrEqZero
+* - SyncOut_CtrEqCmpB
+* - SyncOut_Disable
+*
+* This function sets the source of synchronization output signal
+*/
+/* SourceId : ETPWM_SourceId_011 */
+/* DesignId : ETPWM_DesignId_011 */
+/* Requirements : HL_EPWM_SR7 */
+void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncOut_t syncOutSrc)
+{
+ etpwm->TBCTL &= (uint16)~(uint16)0x0030U;
+ etpwm->TBCTL |= syncOutSrc;
+}
+
+/** @fn void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode)
+* @brief Set the time-base counter mode
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param countermode Counter Mode
+* - CounterMode_Up
+* - Countermode_Down
+* - CounterMode_UpDown
+* - CounterMode_Stop
+*
+* This function sets the time-base counter mode of operation.
+*/
+/* SourceId : ETPWM_SourceId_012 */
+/* DesignId : ETPWM_DesignId_012 */
+/* Requirements : HL_EPWM_SR8 */
+void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode)
+{
+ etpwm->TBCTL &= (uint16)~(uint16)0x0003U;
+ etpwm->TBCTL |= countermode;
+}
+
+/** @fn void etpwmTriggerSWSync(etpwmBASE_t *etpwm)
+* @brief Trigger a software synchronization pulse
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function triggers a software synchronization pulse. SWFSYNC is valid (operates) only when EPWMxSYNCI as SyncOut
+*/
+/* SourceId : ETPWM_SourceId_013 */
+/* DesignId : ETPWM_DesignId_013 */
+/* Requirements : HL_EPWM_SR9 */
+void etpwmTriggerSWSync(etpwmBASE_t *etpwm)
+{
+ etpwm->TBCTL |= 0x0040U;
+}
+
+/** @fn void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode)
+* @brief Set the pulse width modulation (ETPWM) run mode
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param runmode Run mode
+* - RunMode_SoftStopAfterIncr : Stop after the next time-base counter increment
+* - RunMode_SoftStopAfterDecr : Stop after the next time-base counter decrement
+* - RunMode_SoftStopAfterCycle : Stop when counter completes a whole cycle
+* - RunMode_FreeRun : Free-run
+*
+* This function select the behaviour of the ePWM time-base counter during emulation events
+*/
+/* SourceId : ETPWM_SourceId_014 */
+/* DesignId : ETPWM_DesignId_014 */
+/* Requirements : HL_EPWM_SR10 */
+void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode)
+{
+ etpwm->TBCTL &= (uint16)~(uint16)0xC000U;
+ etpwm->TBCTL |= runmode;
+}
+
+/** @fn void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value)
+* @brief Set the Compare A value
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param value 16-bit Compare A value
+*
+* This function sets the compare A value
+*/
+/* SourceId : ETPWM_SourceId_015 */
+/* DesignId : ETPWM_DesignId_015 */
+/* Requirements : HL_EPWM_SR11 */
+void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value)
+{
+ etpwm->CMPA = value;
+}
+
+/** @fn void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value)
+* @brief Set the Compare B value
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param value 16-bit Compare B value
+*
+* This function sets the compare B register
+*/
+/* SourceId : ETPWM_SourceId_016 */
+/* DesignId : ETPWM_DesignId_016 */
+/* Requirements : HL_EPWM_SR11 */
+void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value)
+{
+ etpwm->CMPB = value;
+}
+
+/** @fn void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode)
+* @brief Enable shadow mode for Compare A register
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param loadmode Active Counter-Compare A (CMPA) Load From Shadow Select Mode
+* - LoadMode_CtrEqZero : Load on CTR = Zero
+* - LoadMode_CtrEqPeriod : Load on CTR = PRD
+* - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD
+* - LoadMode_Freeze : Freeze (no loads possible)
+*
+* This function enables shadow mode for Compare A register
+*/
+/* SourceId : ETPWM_SourceId_017 */
+/* DesignId : ETPWM_DesignId_017 */
+/* Requirements : HL_EPWM_SR12 */
+void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode)
+{
+ etpwm->CMPCTL &= (uint16)~(uint16)0x0013U;
+ etpwm->CMPCTL |= loadmode;
+}
+
+/** @fn void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm)
+* @brief Disable shadow mode for Compare A register
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function disables shadow mode for Compare A register
+*/
+/* SourceId : ETPWM_SourceId_018 */
+/* DesignId : ETPWM_DesignId_018 */
+/* Requirements : HL_EPWM_SR12 */
+void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm)
+{
+ etpwm->CMPCTL |= 0x0010U;
+}
+
+/** @fn void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode)
+* @brief Enable shadow mode for Compare B register
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param loadmode Active Counter-Compare B (CMPB) Load From Shadow Select Mode
+* - LoadMode_CtrEqZero : Load on CTR = Zero
+* - LoadMode_CtrEqPeriod : Load on CTR = PRD
+* - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD
+* - LoadMode_Freeze : Freeze (no loads possible)
+*
+* This function enables shadow mode for Compare B register
+*/
+/* SourceId : ETPWM_SourceId_019 */
+/* DesignId : ETPWM_DesignId_019 */
+/* Requirements : HL_EPWM_SR12 */
+void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode)
+{
+ etpwm->CMPCTL &= (uint16)~(uint16)0x004CU;
+ etpwm->CMPCTL |= (uint16)((uint16)loadmode << 2U);
+}
+
+/** @fn void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm)
+* @brief Disable shadow mode for Compare B register
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function disables shadow mode for Compare B register
+*/
+/* SourceId : ETPWM_SourceId_020 */
+/* DesignId : ETPWM_DesignId_020 */
+/* Requirements : HL_EPWM_SR12 */
+void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm)
+{
+ etpwm->CMPCTL |= 0x0040U;
+}
+
+/** @fn void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig)
+* @brief Configure Action Qualifier submodule to generate PWMA
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param actionqualconfig Action Qualifier configuration
+*
+* Example usage (Removing semicolons to avoid MISRA warnings):
+* etpwmActionQualConfig_t configA
+* configA.CtrEqZero_Action = ActionQual_Set
+* configA.CtrEqPeriod_Action = ActionQual_Disabled
+* configA.CtrEqCmpAUp_Action = ActionQual_Clear
+* configA.CtrEqCmpADown_Action = ActionQual_Disabled
+* configA.CtrEqCmpBUp_Action = ActionQual_Disabled
+* configA.CtrEqCmpBDown_Action = ActionQual_Disabled
+* void etpwmSetActionQualPwmA(etpwmREG1, configA)
+*
+* This function configures Action Qualifier submodule to generate PWMA
+*/
+/* SourceId : ETPWM_SourceId_021 */
+/* DesignId : ETPWM_DesignId_021 */
+/* Requirements : HL_EPWM_SR13 */
+void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig)
+{
+ etpwm->AQCTLA = ((uint16)((uint16)actionqualconfig.CtrEqZero_Action << 0U) |
+ (uint16)((uint16)actionqualconfig.CtrEqPeriod_Action << 2U) |
+ (uint16)((uint16)actionqualconfig.CtrEqCmpAUp_Action << 4U) |
+ (uint16)((uint16)actionqualconfig.CtrEqCmpADown_Action << 6U) |
+ (uint16)((uint16)actionqualconfig.CtrEqCmpBUp_Action << 8U) |
+ (uint16)((uint16)actionqualconfig.CtrEqCmpBDown_Action << 10U));
+
+}
+
+/** @fn void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig)
+* @brief Configure Action Qualifier submodule to generate PWMB
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param actionqualconfig Action Qualifier configuration
+*
+* Example usage (Removing semicolons to avoid MISRA warnings):
+* etpwmActionQualConfig_t configB
+* configB.CtrEqZero_Action = ActionQual_Set
+* configB.CtrEqPeriod_Action = ActionQual_Disabled
+* configB.CtrEqCmpAUp_Action = ActionQual_Disabled
+* configB.CtrEqCmpADown_Action = ActionQual_Disabled
+* configB.CtrEqCmpBUp_Action = ActionQual_Clear
+* configB.CtrEqCmpBDown_Action = ActionQual_Disabled
+* void etpwmSetActionQualPwmB(etpwmREG1, configB)
+*
+* This function configures Action Qualifier submodule to generate PWMB
+*/
+/* SourceId : ETPWM_SourceId_022 */
+/* DesignId : ETPWM_DesignId_022 */
+/* Requirements : HL_EPWM_SR13 */
+void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig)
+{
+ etpwm->AQCTLB = ((uint16)((uint16)actionqualconfig.CtrEqZero_Action << 0U) |
+ (uint16)((uint16)actionqualconfig.CtrEqPeriod_Action << 2U) |
+ (uint16)((uint16)actionqualconfig.CtrEqCmpAUp_Action << 4U) |
+ (uint16)((uint16)actionqualconfig.CtrEqCmpADown_Action << 6U) |
+ (uint16)((uint16)actionqualconfig.CtrEqCmpBUp_Action << 8U) |
+ (uint16)((uint16)actionqualconfig.CtrEqCmpBDown_Action << 10U));
+
+}
+
+/** @fn void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig)
+* @brief Enable DeadBand module
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param deadbandconfig DeadBand configuration
+*
+* This function configures Action Qualifier submodule to generate PWMB
+*/
+/* SourceId : ETPWM_SourceId_023 */
+/* DesignId : ETPWM_DesignId_023 */
+/* Requirements : HL_EPWM_SR14 */
+void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig)
+{
+ uint16 halfCycleMask = (uint16)((deadbandconfig.halfCycleEnable) ? 0x8000U : 0U);
+ etpwm->DBCTL = ((uint16)deadbandconfig.inputmode |
+ (uint16)deadbandconfig.outputmode |
+ (uint16)deadbandconfig.polarity |
+ halfCycleMask);
+}
+
+/** @fn void etpwmDisableDeadband(etpwmBASE_t *etpwm)
+* @brief Disable DeadBand module
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function bypasses the Deadband submodule
+*/
+/* SourceId : ETPWM_SourceId_024 */
+/* DesignId : ETPWM_DesignId_024 */
+/* Requirements : HL_EPWM_SR14 */
+void etpwmDisableDeadband(etpwmBASE_t *etpwm)
+{
+ etpwm->DBCTL = 0U;
+}
+
+/** @fn void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay)
+* @brief Sets the rising and falling edge delay
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param Rdelay 16-bit rising edge delay in terms of TCLK ticks
+* @param Fdelay 16-bit falling edge delay in terms of TCLK ticks
+*
+* This function sets the rising and falling edge delays in the DeadBand submodule
+*/
+/* SourceId : ETPWM_SourceId_025 */
+/* DesignId : ETPWM_DesignId_025 */
+/* Requirements : HL_EPWM_SR14 */
+void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay)
+{
+ etpwm->DBRED = Rdelay;
+ etpwm->DBFED = Fdelay;
+}
+
+/** @fn void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig)
+* @brief Enable chopping
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param choppingconfig Chopper submodule configuration
+*
+* This function enables the chopper submodule with the given configuration
+*/
+/* SourceId : ETPWM_SourceId_026 */
+/* DesignId : ETPWM_DesignId_026 */
+/* Requirements : HL_EPWM_SR15 */
+void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig)
+{
+ etpwm->PCCTL = ((uint16)0x0001U |
+ (uint16)choppingconfig.oswdth |
+ (uint16)choppingconfig.freq |
+ (uint16)choppingconfig.duty);
+}
+
+/** @fn void etpwmDisableChopping(etpwmBASE_t *etpwm)
+* @brief Disable chopping
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function disables the chopper submodule
+*/
+/* SourceId : ETPWM_SourceId_027 */
+/* DesignId : ETPWM_DesignId_027 */
+/* Requirements : HL_EPWM_SR15 */
+void etpwmDisableChopping(etpwmBASE_t *etpwm)
+{
+ etpwm->PCCTL = 0U;
+}
+
+/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources)
+* @brief Select the tripzone zources
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param sources Trip zone sources (sources can be ORed)
+* - CycleByCycle_TZ1 : Enable TZ1 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ2 : Enable TZ2 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ3 : Enable TZ3 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ4 : Enable TZ4 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ5 : Enable TZ5 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ6 : Enable TZ6 as a Cycle-by-cycle trip source
+* - CycleByCycle_DCAEVT2 : Enable DCAEVT2 as a Cycle-by-cycle trip source
+* - CycleByCycle_DCBEVT2 : Enable DCBEVT2 as a Cycle-by-cycle trip source
+* - OneShot_TZ1 : Enable TZ1 as a One-shot trip source
+* - OneShot_TZ2 : Enable TZ2 as a One-shot trip source
+* - OneShot_TZ3 : Enable TZ3 as a One-shot trip source
+* - OneShot_TZ4 : Enable TZ4 as a One-shot trip source
+* - OneShot_TZ5 : Enable TZ5 as a One-shot trip source
+* - OneShot_TZ6 : Enable TZ6 as a One-shot trip source
+* - OneShot_DCAEVT1 : Enable DCAEVT1 as a One-shot trip source
+* - OneShot_DCBEVT1 : Enable DCBEVT1 as a One-shot trip source
+*
+* This function selects the tripzone sources for cycle-by-cycle and one-shot trip
+*/
+/* SourceId : ETPWM_SourceId_028 */
+/* DesignId : ETPWM_DesignId_028 */
+/* Requirements : HL_EPWM_SR16 */
+void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources)
+{
+ etpwm->TZSEL |= sources;
+}
+
+/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources)
+* @brief Disable the tripzone zources
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param sources Trip zone sources (sources can be ORed)
+* - CycleByCycle_TZ1 : Disable TZ1 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ2 : Disable TZ2 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ3 : Disable TZ3 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ4 : Disable TZ4 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ5 : Disable TZ5 as a Cycle-by-cycle trip source
+* - CycleByCycle_TZ6 : Disable TZ6 as a Cycle-by-cycle trip source
+* - CycleByCycle_DCAEVT2 : Disable DCAEVT2 as a Cycle-by-cycle trip source
+* - CycleByCycle_DCBEVT2 : Disable DCBEVT2 as a Cycle-by-cycle trip source
+* - OneShot_TZ1 : Disable TZ1 as a One-shot trip source
+* - OneShot_TZ2 : Disable TZ2 as a One-shot trip source
+* - OneShot_TZ3 : Disable TZ3 as a One-shot trip source
+* - OneShot_TZ4 : Disable TZ4 as a One-shot trip source
+* - OneShot_TZ5 : Disable TZ5 as a One-shot trip source
+* - OneShot_TZ6 : Disable TZ6 as a One-shot trip source
+* - OneShot_DCAEVT1 : Disable DCAEVT1 as a One-shot trip source
+* - OneShot_DCBEVT1 : Disable DCBEVT1 as a One-shot trip source
+*
+* This function disables the tripzone sources for cycle-by-cycle or one-shot trip
+*/
+/* SourceId : ETPWM_SourceId_029 */
+/* DesignId : ETPWM_DesignId_029 */
+/* Requirements : HL_EPWM_SR16 */
+void etpwmDisableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources)
+{
+ etpwm->TZSEL &= (uint16)~(uint16)sources;
+}
+
+/** @fn void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t tripactionconfig)
+* @brief Set the action for each trip event
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param tripactionconfig Trip action configuration
+*
+* This function sets the action for each trip event
+*/
+/* SourceId : ETPWM_SourceId_030 */
+/* DesignId : ETPWM_DesignId_030 */
+/* Requirements : HL_EPWM_SR17 */
+void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t tripactionconfig)
+{
+ etpwm->TZCTL = ((uint16)((uint16)tripactionconfig.TripEvent_ActionOnPWMA << 0U) |
+ (uint16)((uint16)tripactionconfig.TripEvent_ActionOnPWMB << 2U) |
+ (uint16)((uint16)tripactionconfig.DCAEVT1_ActionOnPWMA << 4U) |
+ (uint16)((uint16)tripactionconfig.DCAEVT2_ActionOnPWMA << 6U) |
+ (uint16)((uint16)tripactionconfig.DCBEVT1_ActionOnPWMB << 8U) |
+ (uint16)((uint16)tripactionconfig.DCBEVT2_ActionOnPWMB << 10U));
+}
+
+/** @fn void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts)
+* @brief Enables interrupt(EPWMx_TZINT) for the trip event
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param interrupts Interrupts to be enabled (Interrupts can be ORed)
+* - CycleByCycleTrip
+* - OneShotTrip
+* - DCAEVT1_inter
+* - DCAEVT2_inter
+* - DCBEVT1_inter
+* - DCBEVT2_inter
+*
+* This function enables interrupt(EPWMx_TZINT) for the trip event
+*/
+/* SourceId : ETPWM_SourceId_031 */
+/* DesignId : ETPWM_DesignId_031 */
+/* Requirements : HL_EPWM_SR18 */
+void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts)
+{
+ etpwm->TZEINT |= interrupts;
+}
+
+/** @fn void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts)
+* @brief Disables interrupt(EPWMx_TZINT) for the trip event
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param interrupts Trip Interrupts to be disabled (Interrupts can be ORed)
+* - CycleByCycleTrip
+* - OneShotTrip
+* - DCAEVT1_inter
+* - DCAEVT2_inter
+* - DCBEVT1_inter
+* - DCBEVT2_inter
+*
+* This function disables interrupt(EPWMx_TZINT) for the trip event
+*/
+/* SourceId : ETPWM_SourceId_032 */
+/* DesignId : ETPWM_DesignId_032 */
+/* Requirements : HL_EPWM_SR18 */
+void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts)
+{
+ etpwm->TZEINT &= (uint16)~(uint16)interrupts;
+}
+
+/** @fn void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips)
+* @brief Clears the trip event flag
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param trips Trip events
+* - CycleByCycleTrip
+* - OneShotTrip
+* - DCAEVT1_inter
+* - DCAEVT2_inter
+* - DCBEVT1_inter
+* - DCBEVT2_inter
+*
+* This function clears the trip event / Digital Compare output event flag
+*/
+/* SourceId : ETPWM_SourceId_033 */
+/* DesignId : ETPWM_DesignId_033 */
+/* Requirements : HL_EPWM_SR19 */
+void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips)
+{
+ etpwm->TZCLR = trips;
+}
+
+/** @fn void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm)
+* @brief Clears the trip interrupt flag
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function clears the trip interrupt flag
+*/
+/* SourceId : ETPWM_SourceId_034 */
+/* DesignId : ETPWM_DesignId_034 */
+/* Requirements : HL_EPWM_SR19 */
+void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm)
+{
+ etpwm->TZCLR = 1U;
+}
+
+/** @fn void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip)
+* @brief Force a trip event
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param trip Trip events
+* - CycleByCycleTrip
+* - OneShotTrip
+* - DCAEVT1_inter
+* - DCAEVT2_inter
+* - DCBEVT1_inter
+* - DCBEVT2_inter
+*
+* This function forces a trip event / Digital Compare trip event via software
+*/
+/* SourceId : ETPWM_SourceId_035 */
+/* DesignId : ETPWM_DesignId_035 */
+/* Requirements : HL_EPWM_SR20 */
+void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip)
+{
+ etpwm->TZFRC = trip;
+}
+
+/** @fn void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod)
+* @brief Enable ADC Start of Conversion A pulse
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param eventsource EPWMxSOCA Selection Options
+* - DCAEVT1 : DCAEVT1.soc event
+* - CTR_ZERO : Event CTR = Zero
+* - CTR_PRD : Event CTR = PRD
+* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD
+* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing
+* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing
+* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing
+* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing
+* @param eventperiod EPWMxSOCA Period Select
+* - EventPeriod_FirstEvent : Generate SOCA pulse on the first event
+* - EventPeriod_SecondEvent : Generate SOCA pulse on the second event
+* - EventPeriod_ThirdEvent : Generate SOCA pulse on the third event
+*
+* This function enables ADC Start of Conversion A pulse
+*/
+/* SourceId : ETPWM_SourceId_036 */
+/* DesignId : ETPWM_DesignId_036 */
+/* Requirements : HL_EPWM_SR21 */
+void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod)
+{
+ etpwm->ETSEL &= 0xF0FFU;
+ etpwm->ETSEL |= (uint16)((uint16)1U << 11U) | (uint16)((uint16)eventsource << 8U);
+
+ etpwm->ETPS &= 0xF0FFU;
+ etpwm->ETPS |= (uint16)((uint16)eventperiod << 8U);
+}
+
+/** @fn void etpwmDisableSOCA(etpwmBASE_t *etpwm)
+* @brief Disable ADC Start of Conversion A pulse
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function disables ADC Start of Conversion A pulse
+*/
+/* SourceId : ETPWM_SourceId_037 */
+/* DesignId : ETPWM_DesignId_037 */
+/* Requirements : HL_EPWM_SR21 */
+void etpwmDisableSOCA(etpwmBASE_t *etpwm)
+{
+ etpwm->ETSEL &= 0xF0FFU;
+}
+
+/** @fn void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod)
+* @brief Enable ADC Start of Conversion B pulse
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param eventsource EPWMxSOCB Selection Options
+* - DCBEVT1 : DCBEVT1.soc event
+* - CTR_ZERO : Event CTR = Zero
+* - CTR_PRD : Event CTR = PRD
+* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD
+* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing
+* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing
+* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing
+* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing
+* @param eventperiod EPWMxSOCB Period Select
+* - EventPeriod_FirstEvent : Generate SOCB pulse on the first event
+* - EventPeriod_SecondEvent : Generate SOCB pulse on the second event
+* - EventPeriod_ThirdEvent : Generate SOCB pulse on the third event
+*
+* This function enables ADC Start of Conversion B pulse
+*/
+/* SourceId : ETPWM_SourceId_038 */
+/* DesignId : ETPWM_DesignId_038 */
+/* Requirements : HL_EPWM_SR21 */
+void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod)
+{
+ etpwm->ETSEL &= 0x0FFFU;
+ etpwm->ETSEL |= (uint16)((uint16)1U << 15U) | (uint16)((uint16)eventsource << 12U);
+
+ etpwm->ETPS &= 0x0FFFU;
+ etpwm->ETPS |= (uint16)((uint16)eventperiod << 12U);
+}
+
+/** @fn void etpwmDisableSOCB(etpwmBASE_t *etpwm)
+* @brief Disable ADC Start of Conversion B pulse
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function disables ADC Start of Conversion B pulse
+*/
+/* SourceId : ETPWM_SourceId_039 */
+/* DesignId : ETPWM_DesignId_039 */
+/* Requirements : HL_EPWM_SR21 */
+void etpwmDisableSOCB(etpwmBASE_t *etpwm)
+{
+ etpwm->ETSEL &= 0x0FFFU;
+}
+
+/** @fn void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod)
+* @brief Enable ePWM Interrupt
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param eventsource EPWMx_INT Selection Options
+* - CTR_ZERO : Event CTR = Zero
+* - CTR_PRD : Event CTR = PRD
+* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD
+* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing
+* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing
+* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing
+* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing
+* @param eventperiod EPWMx_INT Period Select
+* - EventPeriod_FirstEvent : Generate interrupt on the first event
+* - EventPeriod_SecondEvent : Generate interrupt on the second event
+* - EventPeriod_ThirdEvent : Generate interrupt on the third event
+*
+* This function enables EPWMx_INT generation
+*/
+/* SourceId : ETPWM_SourceId_040 */
+/* DesignId : ETPWM_DesignId_040 */
+/* Requirements : HL_EPWM_SR22 */
+void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod)
+{
+ etpwm->ETSEL &= 0xFFF0U;
+ etpwm->ETSEL |= (uint16)((uint16)1U << 3U) | (uint16)((uint16)eventsource << 0U);
+
+ etpwm->ETPS &= 0xFFF0U;
+ etpwm->ETPS |= (uint16)((uint16)eventperiod << 0U);
+}
+
+/** @fn void etpwmDisableInterrupt(etpwmBASE_t *etpwm)
+* @brief Disable ePWM Interrupt
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+*
+* This function disables EPWMx_INT generation
+*/
+/* SourceId : ETPWM_SourceId_041 */
+/* DesignId : ETPWM_DesignId_041 */
+/* Requirements : HL_EPWM_SR22 */
+void etpwmDisableInterrupt(etpwmBASE_t *etpwm)
+{
+ etpwm->ETSEL &= 0xFFF0U;
+}
+
+/** @fn uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm)
+* @brief Return event status flag
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @return event status flag
+* Bit 0: ePWM Interrupt(EPWMx_INT) Status Flag
+* Bit 2: ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag
+* Bit 3: ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag
+*
+* This function returns the event status flags
+*/
+/* SourceId : ETPWM_SourceId_042 */
+/* DesignId : ETPWM_DesignId_042 */
+/* Requirements : HL_EPWM_SR23 */
+uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm)
+{
+ return etpwm->ETFLG;
+}
+
+/** @fn void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events)
+* @brief Clear event status flag
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param events status flag (flags can be ORed)
+* - Event_Interrupt
+* - Event_SOCA
+* - Event_SOCB
+*
+* This function clears the event status flags
+*/
+/* SourceId : ETPWM_SourceId_043 */
+/* DesignId : ETPWM_DesignId_043 */
+/* Requirements : HL_EPWM_SR24 */
+void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events)
+{
+ etpwm->ETCLR = events;
+}
+
+/** @fn void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events)
+* @brief Force an event
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @return events (events can be ORed)
+* - Event_Interrupt
+* - Event_SOCA
+* - Event_SOCB
+*
+* This function forces an event
+*/
+/* SourceId : ETPWM_SourceId_044 */
+/* DesignId : ETPWM_DesignId_044 */
+/* Requirements : HL_EPWM_SR25 */
+void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events)
+{
+ etpwm->ETFRC = events;
+}
+
+/** @fn void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, etpwmDigitalCompareConfig_t digitalcompareconfig)
+* @brief Enable and configure digital compare events
+*
+* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7)
+* @param digitalcompareconfig Digital Compare modue configuration
+*
+* Example usage (Removing semicolons to avoid MISRA warnings):
+* etpwmDigitalCompareConfig_t config1
+* config1.DCAH_src = TZ1
+* config1.DCAL_src = TZ2
+* config1.DCBH_src = TZ1
+* config1.DCBL_src = TZ3
+* config1.DCAEVT1_event = DCAH_High
+* config1.DCAEVT2_event = DCAL_High
+* config1.DCBEVT1_event = DCBL_High
+* config1.DCBEVT2_event = DCBL_High_DCBH_low
+* etpwmEnableDigitalCompareEvents(etpwmREG1, config1)
+*
+* This function enbales and configures the digital compare events. HTis function can also be used to disable digital compare events
+*/
+/* SourceId : ETPWM_SourceId_045 */
+/* DesignId : ETPWM_DesignId_045 */
+/* Requirements : HL_EPWM_SR26 */
+void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, etpwmDigitalCompareConfig_t digitalcompareconfig)
+{
+ etpwm->DCTRIPSEL = ((uint16)((uint16)digitalcompareconfig.DCAH_src << 0U) |
+ (uint16)((uint16)digitalcompareconfig.DCAL_src << 4U) |
+ (uint16)((uint16)digitalcompareconfig.DCBH_src << 8U) |
+ (uint16)((uint16)digitalcompareconfig.DCBL_src << 12U));
+
+ etpwm->TZDCSEL = ((uint16)((uint16)digitalcompareconfig.DCAEVT1_event << 0U) |
+ (uint16)((uint16)digitalcompareconfig.DCAEVT2_event << 3U) |
+ (uint16)((uint16)digitalcompareconfig.DCBEVT1_event << 6U) |
+ (uint16)((uint16)digitalcompareconfig.DCBEVT2_event << 9U));
+}
+
+/** @fn void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ETPWM_SourceId_046 */
+/* DesignId : ETPWM_DesignId_046 */
+/* Requirements : HL_EPWM_SR32 */
+void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE;
+ config_reg->CONFIG_TBPHS = ETPWM1_TBPHS_CONFIGVALUE;
+ config_reg->CONFIG_TBPRD = ETPWM1_TBPRD_CONFIGVALUE;
+ config_reg->CONFIG_CMPCTL = ETPWM1_CMPCTL_CONFIGVALUE;
+ config_reg->CONFIG_CMPA = ETPWM1_CMPA_CONFIGVALUE;
+ config_reg->CONFIG_CMPB = ETPWM1_CMPB_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLA = ETPWM1_AQCTLA_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLB = ETPWM1_AQCTLB_CONFIGVALUE;
+ config_reg->CONFIG_DBCTL = ETPWM1_DBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DBRED = ETPWM1_DBRED_CONFIGVALUE;
+ config_reg->CONFIG_DBFED = ETPWM1_DBFED_CONFIGVALUE;
+ config_reg->CONFIG_TZSEL = ETPWM1_TZSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZDCSEL = ETPWM1_TZDCSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZCTL = ETPWM1_TZCTL_CONFIGVALUE;
+ config_reg->CONFIG_TZEINT = ETPWM1_TZEINT_CONFIGVALUE;
+ config_reg->CONFIG_ETSEL = ETPWM1_ETSEL_CONFIGVALUE;
+ config_reg->CONFIG_ETPS = ETPWM1_ETPS_CONFIGVALUE;
+ config_reg->CONFIG_PCCTL = ETPWM1_PCCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCTRIPSEL = ETPWM1_DCTRIPSEL_CONFIGVALUE;
+ config_reg->CONFIG_DCACTL = ETPWM1_DCACTL_CONFIGVALUE;
+ config_reg->CONFIG_DCBCTL = ETPWM1_DCBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFCTL = ETPWM1_DCFCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCCAPCTL = ETPWM1_DCCAPCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOW = ETPWM1_DCFWINDOW_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOWCNT = ETPWM1_DCFWINDOWCNT_CONFIGVALUE;
+ }
+ else
+ {
+ config_reg->CONFIG_TBCTL = etpwmREG1->TBCTL;
+ config_reg->CONFIG_TBPHS = etpwmREG1->TBPHS;
+ config_reg->CONFIG_TBPRD = etpwmREG1->TBPRD;
+ config_reg->CONFIG_CMPCTL = etpwmREG1->CMPCTL;
+ config_reg->CONFIG_CMPA = etpwmREG1->CMPA;
+ config_reg->CONFIG_CMPB = etpwmREG1->CMPB;
+ config_reg->CONFIG_AQCTLA = etpwmREG1->AQCTLA;
+ config_reg->CONFIG_AQCTLB = etpwmREG1->AQCTLB;
+ config_reg->CONFIG_DBCTL = etpwmREG1->DBCTL;
+ config_reg->CONFIG_DBRED = etpwmREG1->DBRED;
+ config_reg->CONFIG_DBFED = etpwmREG1->DBFED;
+ config_reg->CONFIG_TZSEL = etpwmREG1->TZSEL;
+ config_reg->CONFIG_TZDCSEL = etpwmREG1->TZDCSEL;
+ config_reg->CONFIG_TZCTL = etpwmREG1->TZCTL;
+ config_reg->CONFIG_TZEINT = etpwmREG1->TZEINT;
+ config_reg->CONFIG_ETSEL = etpwmREG1->ETSEL;
+ config_reg->CONFIG_ETPS = etpwmREG1->ETPS;
+ config_reg->CONFIG_PCCTL = etpwmREG1->PCCTL;
+ config_reg->CONFIG_DCTRIPSEL = etpwmREG1->DCTRIPSEL;
+ config_reg->CONFIG_DCACTL = etpwmREG1->DCACTL;
+ config_reg->CONFIG_DCBCTL = etpwmREG1->DCBCTL;
+ config_reg->CONFIG_DCFCTL = etpwmREG1->DCFCTL;
+ config_reg->CONFIG_DCCAPCTL = etpwmREG1->DCCAPCTL;
+ config_reg->CONFIG_DCFWINDOW = etpwmREG1->DCFWINDOW;
+ config_reg->CONFIG_DCFWINDOWCNT = etpwmREG1->DCFWINDOWCNT;
+ }
+}
+
+/** @fn void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ETPWM_SourceId_47 */
+/* DesignId : ETPWM_DesignId_046 */
+/* Requirements : HL_EPWM_SR32 */
+void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_TBCTL = ETPWM2_TBCTL_CONFIGVALUE;
+ config_reg->CONFIG_TBPHS = ETPWM2_TBPHS_CONFIGVALUE;
+ config_reg->CONFIG_TBPRD = ETPWM2_TBPRD_CONFIGVALUE;
+ config_reg->CONFIG_CMPCTL = ETPWM2_CMPCTL_CONFIGVALUE;
+ config_reg->CONFIG_CMPA = ETPWM2_CMPA_CONFIGVALUE;
+ config_reg->CONFIG_CMPB = ETPWM2_CMPB_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLA = ETPWM2_AQCTLA_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLB = ETPWM2_AQCTLB_CONFIGVALUE;
+ config_reg->CONFIG_DBCTL = ETPWM2_DBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DBRED = ETPWM2_DBRED_CONFIGVALUE;
+ config_reg->CONFIG_DBFED = ETPWM2_DBFED_CONFIGVALUE;
+ config_reg->CONFIG_TZSEL = ETPWM2_TZSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZDCSEL = ETPWM2_TZDCSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZCTL = ETPWM2_TZCTL_CONFIGVALUE;
+ config_reg->CONFIG_TZEINT = ETPWM2_TZEINT_CONFIGVALUE;
+ config_reg->CONFIG_ETSEL = ETPWM2_ETSEL_CONFIGVALUE;
+ config_reg->CONFIG_ETPS = ETPWM2_ETPS_CONFIGVALUE;
+ config_reg->CONFIG_PCCTL = ETPWM2_PCCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCTRIPSEL = ETPWM2_DCTRIPSEL_CONFIGVALUE;
+ config_reg->CONFIG_DCACTL = ETPWM2_DCACTL_CONFIGVALUE;
+ config_reg->CONFIG_DCBCTL = ETPWM2_DCBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFCTL = ETPWM2_DCFCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCCAPCTL = ETPWM2_DCCAPCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOW = ETPWM2_DCFWINDOW_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOWCNT = ETPWM2_DCFWINDOWCNT_CONFIGVALUE;
+ }
+ else
+ {
+ config_reg->CONFIG_TBCTL = etpwmREG2->TBCTL;
+ config_reg->CONFIG_TBPHS = etpwmREG2->TBPHS;
+ config_reg->CONFIG_TBPRD = etpwmREG2->TBPRD;
+ config_reg->CONFIG_CMPCTL = etpwmREG2->CMPCTL;
+ config_reg->CONFIG_CMPA = etpwmREG2->CMPA;
+ config_reg->CONFIG_CMPB = etpwmREG2->CMPB;
+ config_reg->CONFIG_AQCTLA = etpwmREG2->AQCTLA;
+ config_reg->CONFIG_AQCTLB = etpwmREG2->AQCTLB;
+ config_reg->CONFIG_DBCTL = etpwmREG2->DBCTL;
+ config_reg->CONFIG_DBRED = etpwmREG2->DBRED;
+ config_reg->CONFIG_DBFED = etpwmREG2->DBFED;
+ config_reg->CONFIG_TZSEL = etpwmREG2->TZSEL;
+ config_reg->CONFIG_TZDCSEL = etpwmREG2->TZDCSEL;
+ config_reg->CONFIG_TZCTL = etpwmREG2->TZCTL;
+ config_reg->CONFIG_TZEINT = etpwmREG2->TZEINT;
+ config_reg->CONFIG_ETSEL = etpwmREG2->ETSEL;
+ config_reg->CONFIG_ETPS = etpwmREG2->ETPS;
+ config_reg->CONFIG_PCCTL = etpwmREG2->PCCTL;
+ config_reg->CONFIG_DCTRIPSEL = etpwmREG2->DCTRIPSEL;
+ config_reg->CONFIG_DCACTL = etpwmREG2->DCACTL;
+ config_reg->CONFIG_DCBCTL = etpwmREG2->DCBCTL;
+ config_reg->CONFIG_DCFCTL = etpwmREG2->DCFCTL;
+ config_reg->CONFIG_DCCAPCTL = etpwmREG2->DCCAPCTL;
+ config_reg->CONFIG_DCFWINDOW = etpwmREG2->DCFWINDOW;
+ config_reg->CONFIG_DCFWINDOWCNT = etpwmREG2->DCFWINDOWCNT;
+ }
+}
+
+/** @fn void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ETPWM_SourceId_048 */
+/* DesignId : ETPWM_DesignId_046 */
+/* Requirements : HL_EPWM_SR32 */
+void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_TBCTL = ETPWM3_TBCTL_CONFIGVALUE;
+ config_reg->CONFIG_TBPHS = ETPWM3_TBPHS_CONFIGVALUE;
+ config_reg->CONFIG_TBPRD = ETPWM3_TBPRD_CONFIGVALUE;
+ config_reg->CONFIG_CMPCTL = ETPWM3_CMPCTL_CONFIGVALUE;
+ config_reg->CONFIG_CMPA = ETPWM3_CMPA_CONFIGVALUE;
+ config_reg->CONFIG_CMPB = ETPWM3_CMPB_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLA = ETPWM3_AQCTLA_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLB = ETPWM3_AQCTLB_CONFIGVALUE;
+ config_reg->CONFIG_DBCTL = ETPWM3_DBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DBRED = ETPWM3_DBRED_CONFIGVALUE;
+ config_reg->CONFIG_DBFED = ETPWM3_DBFED_CONFIGVALUE;
+ config_reg->CONFIG_TZSEL = ETPWM3_TZSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZDCSEL = ETPWM3_TZDCSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZCTL = ETPWM3_TZCTL_CONFIGVALUE;
+ config_reg->CONFIG_TZEINT = ETPWM3_TZEINT_CONFIGVALUE;
+ config_reg->CONFIG_ETSEL = ETPWM3_ETSEL_CONFIGVALUE;
+ config_reg->CONFIG_ETPS = ETPWM3_ETPS_CONFIGVALUE;
+ config_reg->CONFIG_PCCTL = ETPWM3_PCCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCTRIPSEL = ETPWM3_DCTRIPSEL_CONFIGVALUE;
+ config_reg->CONFIG_DCACTL = ETPWM3_DCACTL_CONFIGVALUE;
+ config_reg->CONFIG_DCBCTL = ETPWM3_DCBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFCTL = ETPWM3_DCFCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCCAPCTL = ETPWM3_DCCAPCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOW = ETPWM3_DCFWINDOW_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOWCNT = ETPWM3_DCFWINDOWCNT_CONFIGVALUE;
+ }
+ else
+ {
+ config_reg->CONFIG_TBCTL = etpwmREG3->TBCTL;
+ config_reg->CONFIG_TBPHS = etpwmREG3->TBPHS;
+ config_reg->CONFIG_TBPRD = etpwmREG3->TBPRD;
+ config_reg->CONFIG_CMPCTL = etpwmREG3->CMPCTL;
+ config_reg->CONFIG_CMPA = etpwmREG3->CMPA;
+ config_reg->CONFIG_CMPB = etpwmREG3->CMPB;
+ config_reg->CONFIG_AQCTLA = etpwmREG3->AQCTLA;
+ config_reg->CONFIG_AQCTLB = etpwmREG3->AQCTLB;
+ config_reg->CONFIG_DBCTL = etpwmREG3->DBCTL;
+ config_reg->CONFIG_DBRED = etpwmREG3->DBRED;
+ config_reg->CONFIG_DBFED = etpwmREG3->DBFED;
+ config_reg->CONFIG_TZSEL = etpwmREG3->TZSEL;
+ config_reg->CONFIG_TZDCSEL = etpwmREG3->TZDCSEL;
+ config_reg->CONFIG_TZCTL = etpwmREG3->TZCTL;
+ config_reg->CONFIG_TZEINT = etpwmREG3->TZEINT;
+ config_reg->CONFIG_ETSEL = etpwmREG3->ETSEL;
+ config_reg->CONFIG_ETPS = etpwmREG3->ETPS;
+ config_reg->CONFIG_PCCTL = etpwmREG3->PCCTL;
+ config_reg->CONFIG_DCTRIPSEL = etpwmREG3->DCTRIPSEL;
+ config_reg->CONFIG_DCACTL = etpwmREG3->DCACTL;
+ config_reg->CONFIG_DCBCTL = etpwmREG3->DCBCTL;
+ config_reg->CONFIG_DCFCTL = etpwmREG3->DCFCTL;
+ config_reg->CONFIG_DCCAPCTL = etpwmREG3->DCCAPCTL;
+ config_reg->CONFIG_DCFWINDOW = etpwmREG3->DCFWINDOW;
+ config_reg->CONFIG_DCFWINDOWCNT = etpwmREG3->DCFWINDOWCNT;
+ }
+}
+
+/** @fn void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ETPWM_SourceId_049 */
+/* DesignId : ETPWM_DesignId_046 */
+/* Requirements : HL_EPWM_SR32 */
+void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_TBCTL = ETPWM4_TBCTL_CONFIGVALUE;
+ config_reg->CONFIG_TBPHS = ETPWM4_TBPHS_CONFIGVALUE;
+ config_reg->CONFIG_TBPRD = ETPWM4_TBPRD_CONFIGVALUE;
+ config_reg->CONFIG_CMPCTL = ETPWM4_CMPCTL_CONFIGVALUE;
+ config_reg->CONFIG_CMPA = ETPWM4_CMPA_CONFIGVALUE;
+ config_reg->CONFIG_CMPB = ETPWM4_CMPB_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLA = ETPWM4_AQCTLA_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLB = ETPWM4_AQCTLB_CONFIGVALUE;
+ config_reg->CONFIG_DBCTL = ETPWM4_DBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DBRED = ETPWM4_DBRED_CONFIGVALUE;
+ config_reg->CONFIG_DBFED = ETPWM4_DBFED_CONFIGVALUE;
+ config_reg->CONFIG_TZSEL = ETPWM4_TZSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZDCSEL = ETPWM4_TZDCSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZCTL = ETPWM4_TZCTL_CONFIGVALUE;
+ config_reg->CONFIG_TZEINT = ETPWM4_TZEINT_CONFIGVALUE;
+ config_reg->CONFIG_ETSEL = ETPWM4_ETSEL_CONFIGVALUE;
+ config_reg->CONFIG_ETPS = ETPWM4_ETPS_CONFIGVALUE;
+ config_reg->CONFIG_PCCTL = ETPWM4_PCCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCTRIPSEL = ETPWM4_DCTRIPSEL_CONFIGVALUE;
+ config_reg->CONFIG_DCACTL = ETPWM4_DCACTL_CONFIGVALUE;
+ config_reg->CONFIG_DCBCTL = ETPWM4_DCBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFCTL = ETPWM4_DCFCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCCAPCTL = ETPWM4_DCCAPCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOW = ETPWM4_DCFWINDOW_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOWCNT = ETPWM4_DCFWINDOWCNT_CONFIGVALUE;
+ }
+ else
+ {
+ config_reg->CONFIG_TBCTL = etpwmREG4->TBCTL;
+ config_reg->CONFIG_TBPHS = etpwmREG4->TBPHS;
+ config_reg->CONFIG_TBPRD = etpwmREG4->TBPRD;
+ config_reg->CONFIG_CMPCTL = etpwmREG4->CMPCTL;
+ config_reg->CONFIG_CMPA = etpwmREG4->CMPA;
+ config_reg->CONFIG_CMPB = etpwmREG4->CMPB;
+ config_reg->CONFIG_AQCTLA = etpwmREG4->AQCTLA;
+ config_reg->CONFIG_AQCTLB = etpwmREG4->AQCTLB;
+ config_reg->CONFIG_DBCTL = etpwmREG4->DBCTL;
+ config_reg->CONFIG_DBRED = etpwmREG4->DBRED;
+ config_reg->CONFIG_DBFED = etpwmREG4->DBFED;
+ config_reg->CONFIG_TZSEL = etpwmREG4->TZSEL;
+ config_reg->CONFIG_TZDCSEL = etpwmREG4->TZDCSEL;
+ config_reg->CONFIG_TZCTL = etpwmREG4->TZCTL;
+ config_reg->CONFIG_TZEINT = etpwmREG4->TZEINT;
+ config_reg->CONFIG_ETSEL = etpwmREG4->ETSEL;
+ config_reg->CONFIG_ETPS = etpwmREG4->ETPS;
+ config_reg->CONFIG_PCCTL = etpwmREG4->PCCTL;
+ config_reg->CONFIG_DCTRIPSEL = etpwmREG4->DCTRIPSEL;
+ config_reg->CONFIG_DCACTL = etpwmREG4->DCACTL;
+ config_reg->CONFIG_DCBCTL = etpwmREG4->DCBCTL;
+ config_reg->CONFIG_DCFCTL = etpwmREG4->DCFCTL;
+ config_reg->CONFIG_DCCAPCTL = etpwmREG4->DCCAPCTL;
+ config_reg->CONFIG_DCFWINDOW = etpwmREG4->DCFWINDOW;
+ config_reg->CONFIG_DCFWINDOWCNT = etpwmREG4->DCFWINDOWCNT;
+ }
+}
+
+/** @fn void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ETPWM_SourceId_050 */
+/* DesignId : ETPWM_DesignId_046 */
+/* Requirements : HL_EPWM_SR3232 */
+void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_TBCTL = ETPWM5_TBCTL_CONFIGVALUE;
+ config_reg->CONFIG_TBPHS = ETPWM5_TBPHS_CONFIGVALUE;
+ config_reg->CONFIG_TBPRD = ETPWM5_TBPRD_CONFIGVALUE;
+ config_reg->CONFIG_CMPCTL = ETPWM5_CMPCTL_CONFIGVALUE;
+ config_reg->CONFIG_CMPA = ETPWM5_CMPA_CONFIGVALUE;
+ config_reg->CONFIG_CMPB = ETPWM5_CMPB_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLA = ETPWM5_AQCTLA_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLB = ETPWM5_AQCTLB_CONFIGVALUE;
+ config_reg->CONFIG_DBCTL = ETPWM5_DBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DBRED = ETPWM5_DBRED_CONFIGVALUE;
+ config_reg->CONFIG_DBFED = ETPWM5_DBFED_CONFIGVALUE;
+ config_reg->CONFIG_TZSEL = ETPWM5_TZSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZDCSEL = ETPWM5_TZDCSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZCTL = ETPWM5_TZCTL_CONFIGVALUE;
+ config_reg->CONFIG_TZEINT = ETPWM5_TZEINT_CONFIGVALUE;
+ config_reg->CONFIG_ETSEL = ETPWM5_ETSEL_CONFIGVALUE;
+ config_reg->CONFIG_ETPS = ETPWM5_ETPS_CONFIGVALUE;
+ config_reg->CONFIG_PCCTL = ETPWM5_PCCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCTRIPSEL = ETPWM5_DCTRIPSEL_CONFIGVALUE;
+ config_reg->CONFIG_DCACTL = ETPWM5_DCACTL_CONFIGVALUE;
+ config_reg->CONFIG_DCBCTL = ETPWM5_DCBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFCTL = ETPWM5_DCFCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCCAPCTL = ETPWM5_DCCAPCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOW = ETPWM5_DCFWINDOW_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOWCNT = ETPWM5_DCFWINDOWCNT_CONFIGVALUE;
+ }
+ else
+ {
+ config_reg->CONFIG_TBCTL = etpwmREG5->TBCTL;
+ config_reg->CONFIG_TBPHS = etpwmREG5->TBPHS;
+ config_reg->CONFIG_TBPRD = etpwmREG5->TBPRD;
+ config_reg->CONFIG_CMPCTL = etpwmREG5->CMPCTL;
+ config_reg->CONFIG_CMPA = etpwmREG5->CMPA;
+ config_reg->CONFIG_CMPB = etpwmREG5->CMPB;
+ config_reg->CONFIG_AQCTLA = etpwmREG5->AQCTLA;
+ config_reg->CONFIG_AQCTLB = etpwmREG5->AQCTLB;
+ config_reg->CONFIG_DBCTL = etpwmREG5->DBCTL;
+ config_reg->CONFIG_DBRED = etpwmREG5->DBRED;
+ config_reg->CONFIG_DBFED = etpwmREG5->DBFED;
+ config_reg->CONFIG_TZSEL = etpwmREG5->TZSEL;
+ config_reg->CONFIG_TZDCSEL = etpwmREG5->TZDCSEL;
+ config_reg->CONFIG_TZCTL = etpwmREG5->TZCTL;
+ config_reg->CONFIG_TZEINT = etpwmREG5->TZEINT;
+ config_reg->CONFIG_ETSEL = etpwmREG5->ETSEL;
+ config_reg->CONFIG_ETPS = etpwmREG5->ETPS;
+ config_reg->CONFIG_PCCTL = etpwmREG5->PCCTL;
+ config_reg->CONFIG_DCTRIPSEL = etpwmREG5->DCTRIPSEL;
+ config_reg->CONFIG_DCACTL = etpwmREG5->DCACTL;
+ config_reg->CONFIG_DCBCTL = etpwmREG5->DCBCTL;
+ config_reg->CONFIG_DCFCTL = etpwmREG5->DCFCTL;
+ config_reg->CONFIG_DCCAPCTL = etpwmREG5->DCCAPCTL;
+ config_reg->CONFIG_DCFWINDOW = etpwmREG5->DCFWINDOW;
+ config_reg->CONFIG_DCFWINDOWCNT = etpwmREG5->DCFWINDOWCNT;
+ }
+}
+
+/** @fn void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ETPWM_SourceId_051 */
+/* DesignId : ETPWM_DesignId_046 */
+/* Requirements : HL_EPWM_SR32 */
+void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_TBCTL = ETPWM6_TBCTL_CONFIGVALUE;
+ config_reg->CONFIG_TBPHS = ETPWM6_TBPHS_CONFIGVALUE;
+ config_reg->CONFIG_TBPRD = ETPWM6_TBPRD_CONFIGVALUE;
+ config_reg->CONFIG_CMPCTL = ETPWM6_CMPCTL_CONFIGVALUE;
+ config_reg->CONFIG_CMPA = ETPWM6_CMPA_CONFIGVALUE;
+ config_reg->CONFIG_CMPB = ETPWM6_CMPB_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLA = ETPWM6_AQCTLA_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLB = ETPWM6_AQCTLB_CONFIGVALUE;
+ config_reg->CONFIG_DBCTL = ETPWM6_DBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DBRED = ETPWM6_DBRED_CONFIGVALUE;
+ config_reg->CONFIG_DBFED = ETPWM6_DBFED_CONFIGVALUE;
+ config_reg->CONFIG_TZSEL = ETPWM6_TZSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZDCSEL = ETPWM6_TZDCSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZCTL = ETPWM6_TZCTL_CONFIGVALUE;
+ config_reg->CONFIG_TZEINT = ETPWM6_TZEINT_CONFIGVALUE;
+ config_reg->CONFIG_ETSEL = ETPWM6_ETSEL_CONFIGVALUE;
+ config_reg->CONFIG_ETPS = ETPWM6_ETPS_CONFIGVALUE;
+ config_reg->CONFIG_PCCTL = ETPWM6_PCCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCTRIPSEL = ETPWM6_DCTRIPSEL_CONFIGVALUE;
+ config_reg->CONFIG_DCACTL = ETPWM6_DCACTL_CONFIGVALUE;
+ config_reg->CONFIG_DCBCTL = ETPWM6_DCBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFCTL = ETPWM6_DCFCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCCAPCTL = ETPWM6_DCCAPCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOW = ETPWM6_DCFWINDOW_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOWCNT = ETPWM6_DCFWINDOWCNT_CONFIGVALUE;
+ }
+ else
+ {
+ config_reg->CONFIG_TBCTL = etpwmREG6->TBCTL;
+ config_reg->CONFIG_TBPHS = etpwmREG6->TBPHS;
+ config_reg->CONFIG_TBPRD = etpwmREG6->TBPRD;
+ config_reg->CONFIG_CMPCTL = etpwmREG6->CMPCTL;
+ config_reg->CONFIG_CMPA = etpwmREG6->CMPA;
+ config_reg->CONFIG_CMPB = etpwmREG6->CMPB;
+ config_reg->CONFIG_AQCTLA = etpwmREG6->AQCTLA;
+ config_reg->CONFIG_AQCTLB = etpwmREG6->AQCTLB;
+ config_reg->CONFIG_DBCTL = etpwmREG6->DBCTL;
+ config_reg->CONFIG_DBRED = etpwmREG6->DBRED;
+ config_reg->CONFIG_DBFED = etpwmREG6->DBFED;
+ config_reg->CONFIG_TZSEL = etpwmREG6->TZSEL;
+ config_reg->CONFIG_TZDCSEL = etpwmREG6->TZDCSEL;
+ config_reg->CONFIG_TZCTL = etpwmREG6->TZCTL;
+ config_reg->CONFIG_TZEINT = etpwmREG6->TZEINT;
+ config_reg->CONFIG_ETSEL = etpwmREG6->ETSEL;
+ config_reg->CONFIG_ETPS = etpwmREG6->ETPS;
+ config_reg->CONFIG_PCCTL = etpwmREG6->PCCTL;
+ config_reg->CONFIG_DCTRIPSEL = etpwmREG6->DCTRIPSEL;
+ config_reg->CONFIG_DCACTL = etpwmREG6->DCACTL;
+ config_reg->CONFIG_DCBCTL = etpwmREG6->DCBCTL;
+ config_reg->CONFIG_DCFCTL = etpwmREG6->DCFCTL;
+ config_reg->CONFIG_DCCAPCTL = etpwmREG6->DCCAPCTL;
+ config_reg->CONFIG_DCFWINDOW = etpwmREG6->DCFWINDOW;
+ config_reg->CONFIG_DCFWINDOWCNT = etpwmREG6->DCFWINDOWCNT;
+ }
+}
+
+/** @fn void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ETPWM_SourceId_052 */
+/* DesignId : ETPWM_DesignId_046 */
+/* Requirements : HL_EPWM_SR32 */
+void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE;
+ config_reg->CONFIG_TBPHS = ETPWM7_TBPHS_CONFIGVALUE;
+ config_reg->CONFIG_TBPRD = ETPWM7_TBPRD_CONFIGVALUE;
+ config_reg->CONFIG_CMPCTL = ETPWM7_CMPCTL_CONFIGVALUE;
+ config_reg->CONFIG_CMPA = ETPWM7_CMPA_CONFIGVALUE;
+ config_reg->CONFIG_CMPB = ETPWM7_CMPB_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLA = ETPWM7_AQCTLA_CONFIGVALUE;
+ config_reg->CONFIG_AQCTLB = ETPWM7_AQCTLB_CONFIGVALUE;
+ config_reg->CONFIG_DBCTL = ETPWM7_DBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DBRED = ETPWM7_DBRED_CONFIGVALUE;
+ config_reg->CONFIG_DBFED = ETPWM7_DBFED_CONFIGVALUE;
+ config_reg->CONFIG_TZSEL = ETPWM7_TZSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZDCSEL = ETPWM7_TZDCSEL_CONFIGVALUE;
+ config_reg->CONFIG_TZCTL = ETPWM7_TZCTL_CONFIGVALUE;
+ config_reg->CONFIG_TZEINT = ETPWM7_TZEINT_CONFIGVALUE;
+ config_reg->CONFIG_ETSEL = ETPWM7_ETSEL_CONFIGVALUE;
+ config_reg->CONFIG_ETPS = ETPWM7_ETPS_CONFIGVALUE;
+ config_reg->CONFIG_PCCTL = ETPWM7_PCCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCTRIPSEL = ETPWM7_DCTRIPSEL_CONFIGVALUE;
+ config_reg->CONFIG_DCACTL = ETPWM7_DCACTL_CONFIGVALUE;
+ config_reg->CONFIG_DCBCTL = ETPWM7_DCBCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFCTL = ETPWM7_DCFCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCCAPCTL = ETPWM7_DCCAPCTL_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOW = ETPWM7_DCFWINDOW_CONFIGVALUE;
+ config_reg->CONFIG_DCFWINDOWCNT = ETPWM7_DCFWINDOWCNT_CONFIGVALUE;
+ }
+ else
+ {
+ config_reg->CONFIG_TBCTL = etpwmREG7->TBCTL;
+ config_reg->CONFIG_TBPHS = etpwmREG7->TBPHS;
+ config_reg->CONFIG_TBPRD = etpwmREG7->TBPRD;
+ config_reg->CONFIG_CMPCTL = etpwmREG7->CMPCTL;
+ config_reg->CONFIG_CMPA = etpwmREG7->CMPA;
+ config_reg->CONFIG_CMPB = etpwmREG7->CMPB;
+ config_reg->CONFIG_AQCTLA = etpwmREG7->AQCTLA;
+ config_reg->CONFIG_AQCTLB = etpwmREG7->AQCTLB;
+ config_reg->CONFIG_DBCTL = etpwmREG7->DBCTL;
+ config_reg->CONFIG_DBRED = etpwmREG7->DBRED;
+ config_reg->CONFIG_DBFED = etpwmREG7->DBFED;
+ config_reg->CONFIG_TZSEL = etpwmREG7->TZSEL;
+ config_reg->CONFIG_TZDCSEL = etpwmREG7->TZDCSEL;
+ config_reg->CONFIG_TZCTL = etpwmREG7->TZCTL;
+ config_reg->CONFIG_TZEINT = etpwmREG7->TZEINT;
+ config_reg->CONFIG_ETSEL = etpwmREG7->ETSEL;
+ config_reg->CONFIG_ETPS = etpwmREG7->ETPS;
+ config_reg->CONFIG_PCCTL = etpwmREG7->PCCTL;
+ config_reg->CONFIG_DCTRIPSEL = etpwmREG7->DCTRIPSEL;
+ config_reg->CONFIG_DCACTL = etpwmREG7->DCACTL;
+ config_reg->CONFIG_DCBCTL = etpwmREG7->DCBCTL;
+ config_reg->CONFIG_DCFCTL = etpwmREG7->DCFCTL;
+ config_reg->CONFIG_DCCAPCTL = etpwmREG7->DCCAPCTL;
+ config_reg->CONFIG_DCFWINDOW = etpwmREG7->DCFWINDOW;
+ config_reg->CONFIG_DCFWINDOWCNT = etpwmREG7->DCFWINDOWCNT;
+ }
+}
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
Index: firmware/source/gio.c
===================================================================
diff -u
--- firmware/source/gio.c (revision 0)
+++ firmware/source/gio.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,518 @@
+/** @file gio.c
+* @brief GIO Driver Implementation File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "gio.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void gioInit(void)
+* @brief Initializes the GIO Driver
+*
+* This function initializes the GIO module and set the GIO ports
+* to the initial values.
+*/
+/* SourceId : GIO_SourceId_001 */
+/* DesignId : GIO_DesignId_001 */
+/* Requirements : HL_SR26 */
+void gioInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+ /** bring GIO module out of reset */
+ gioREG->GCR0 = 1U;
+ gioREG->ENACLR = 0xFFU;
+ gioREG->LVLCLR = 0xFFU;
+
+ /** @b initialize @b Port @b A */
+
+ /** - Port A output values */
+ gioPORTA->DOUT = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)1U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** - Port A direction */
+ gioPORTA->DIR = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)1U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)1U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** - Port A open drain enable */
+ gioPORTA->PDR = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** - Port A pullup / pulldown selection */
+ gioPORTA->PSL = (uint32)((uint32)1U << 0U) /* Bit 0 */
+ | (uint32)((uint32)1U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)1U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** - Port A pullup / pulldown enable*/
+ gioPORTA->PULDIS = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)1U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** @b initialize @b Port @b B */
+
+ /** - Port B output values */
+ gioPORTB->DOUT = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** - Port B direction */
+ gioPORTB->DIR = (uint32)((uint32)1U << 0U) /* Bit 0 */
+ | (uint32)((uint32)1U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)1U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** - Port B open drain enable */
+ gioPORTB->PDR = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** - Port B pullup / pulldown selection */
+ gioPORTB->PSL = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+ /** - Port B pullup / pulldown enable*/
+ gioPORTB->PULDIS = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U); /* Bit 7 */
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /** @b initialize @b interrupts */
+
+ /** - interrupt polarity */
+ gioREG->POL = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U) /* Bit 7 */
+ | (uint32)((uint32)0U << 8U) /* Bit 8 */
+ | (uint32)((uint32)0U << 9U) /* Bit 9 */
+ | (uint32)((uint32)0U << 10U) /* Bit 10 */
+ | (uint32)((uint32)0U << 11U) /* Bit 11 */
+ | (uint32)((uint32)0U << 12U) /* Bit 12 */
+ | (uint32)((uint32)0U << 13U) /* Bit 13 */
+ | (uint32)((uint32)0U << 14U) /* Bit 14 */
+ | (uint32)((uint32)0U << 15U); /* Bit 15 */
+
+
+ /** - interrupt level */
+ gioREG->LVLSET = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U) /* Bit 7 */
+ | (uint32)((uint32)0U << 8U) /* Bit 8 */
+ | (uint32)((uint32)0U << 9U) /* Bit 9 */
+ | (uint32)((uint32)0U << 10U) /* Bit 10 */
+ | (uint32)((uint32)0U << 11U) /* Bit 11 */
+ | (uint32)((uint32)0U << 12U) /* Bit 12 */
+ | (uint32)((uint32)0U << 13U) /* Bit 13 */
+ | (uint32)((uint32)0U << 14U) /* Bit 14 */
+ | (uint32)((uint32)0U << 15U); /* Bit 15 */
+
+
+
+
+ /** - clear all pending interrupts */
+ gioREG->FLG = 0xFFU;
+
+ /** - enable interrupts */
+ gioREG->ENASET = (uint32)((uint32)0U << 0U) /* Bit 0 */
+ | (uint32)((uint32)0U << 1U) /* Bit 1 */
+ | (uint32)((uint32)0U << 2U) /* Bit 2 */
+ | (uint32)((uint32)0U << 3U) /* Bit 3 */
+ | (uint32)((uint32)0U << 4U) /* Bit 4 */
+ | (uint32)((uint32)0U << 5U) /* Bit 5 */
+ | (uint32)((uint32)0U << 6U) /* Bit 6 */
+ | (uint32)((uint32)0U << 7U) /* Bit 7 */
+ | (uint32)((uint32)0U << 8U) /* Bit 8 */
+ | (uint32)((uint32)0U << 9U) /* Bit 9 */
+ | (uint32)((uint32)0U << 10U) /* Bit 10 */
+ | (uint32)((uint32)0U << 11U) /* Bit 11 */
+ | (uint32)((uint32)0U << 12U) /* Bit 12 */
+ | (uint32)((uint32)0U << 13U) /* Bit 13 */
+ | (uint32)((uint32)0U << 14U) /* Bit 14 */
+ | (uint32)((uint32)0U << 15U); /* Bit 15 */
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+
+/** @fn void gioSetDirection(gioPORT_t *port, uint32 dir)
+* @brief Set Port Direction
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] dir value to write to DIR register
+*
+* Set the direction of GIO pins at runtime.
+*/
+/* SourceId : GIO_SourceId_002 */
+/* DesignId : GIO_DesignId_002 */
+/* Requirements : HL_SR27 */
+void gioSetDirection(gioPORT_t *port, uint32 dir)
+{
+ port->DIR = dir;
+}
+
+
+/** @fn void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value)
+* @brief Write Bit
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit number 0-7 that specifies the bit to be written to.
+* - 0: LSB
+* - 7: MSB
+* @param[in] value binary value to write to bit
+*
+* Writes a value to the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_003 */
+/* DesignId : GIO_DesignId_003 */
+/* Requirements : HL_SR28 */
+void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value)
+{
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+ if (value != 0U)
+ {
+ port->DSET = (uint32)1U << bit;
+ }
+ else
+ {
+ port->DCLR = (uint32)1U << bit;
+ }
+}
+
+
+/** @fn void gioSetPort(gioPORT_t *port, uint32 value)
+* @brief Write Port Value
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] value value to write to port
+*
+* Writes a value to all pin of a given GIO port
+*/
+/* SourceId : GIO_SourceId_004 */
+/* DesignId : GIO_DesignId_004 */
+/* Requirements : HL_SR29 */
+void gioSetPort(gioPORT_t *port, uint32 value)
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ port->DOUT = value;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+}
+
+
+/** @fn uint32 gioGetBit(gioPORT_t *port, uint32 bit)
+* @brief Read Bit
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit number 0-7 that specifies the bit to be written to.
+* - 0: LSB
+* - 7: MSB
+*
+* Reads a the current value from the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_005 */
+/* DesignId : GIO_DesignId_005 */
+/* Requirements : HL_SR30 */
+uint32 gioGetBit(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ return (port->DIN >> bit) & 1U;
+}
+
+
+/** @fn uint32 gioGetPort(gioPORT_t *port)
+* @brief Read Port Value
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+*
+* Reads a the current value of a given GIO port
+*/
+/* SourceId : GIO_SourceId_006 */
+/* DesignId : GIO_DesignId_006 */
+/* Requirements : HL_SR31 */
+uint32 gioGetPort(gioPORT_t *port)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ return port->DIN;
+}
+
+/** @fn void gioToggleBit(gioPORT_t *port, uint32 bit)
+* @brief Write Bit
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit number 0-7 that specifies the bit to be written to.
+* - 0: LSB
+* - 7: MSB
+*
+* Toggle a value to the specified pin of the given GIO port
+*/
+/* SourceId : GIO_SourceId_007 */
+/* DesignId : GIO_DesignId_007 */
+/* Requirements : HL_SR32 */
+void gioToggleBit(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+ if ((port->DIN & (uint32)((uint32)1U << bit)) != 0U)
+ {
+ port->DCLR = (uint32)1U << bit;
+ }
+ else
+ {
+ port->DSET = (uint32)1U << bit;
+ }
+}
+
+/** @fn void gioEnableNotification(uint32 bit)
+* @brief Enable Interrupt
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit interrupt pin to enable
+* - 0: LSB
+* - 7: MSB
+*
+* Enables an interrupt pin of selected port
+*/
+/* SourceId : GIO_SourceId_008 */
+/* DesignId : GIO_DesignId_008 */
+/* Requirements : HL_SR33 */
+void gioEnableNotification(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ if (port == gioPORTA)
+ {
+ gioREG->ENASET = (uint32)1U << bit;
+ }
+ else if (port == gioPORTB)
+ {
+ gioREG->ENASET = (uint32)1U << (bit + 8U);
+ }
+ else
+ {
+ /* Empty */
+ }
+}
+
+
+/** @fn void gioDisableNotification(uint32 bit)
+* @brief Disable Interrupt
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit interrupt pin to enable
+* - 0: LSB
+* - 7: MSB
+*
+* Disables an interrupt pin of selected port
+*/
+/* SourceId : GIO_SourceId_009 */
+/* DesignId : GIO_DesignId_009 */
+/* Requirements : HL_SR34 */
+void gioDisableNotification(gioPORT_t *port, uint32 bit)
+{
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+ if (port == gioPORTA)
+ {
+ gioREG->ENACLR = (uint32)1U << bit;
+ }
+ else if (port == gioPORTB)
+ {
+ gioREG->ENACLR = (uint32)1U << (bit + 8U);
+ }
+ else
+ {
+ /* Empty */
+ }
+}
+
+/** @fn void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : GIO_SourceId_010 */
+/* DesignId : GIO_DesignId_010 */
+/* Requirements : HL_SR37 */
+void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_INTDET = GIO_INTDET_CONFIGVALUE;
+ config_reg->CONFIG_POL = GIO_POL_CONFIGVALUE;
+ config_reg->CONFIG_INTENASET = GIO_INTENASET_CONFIGVALUE;
+ config_reg->CONFIG_LVLSET = GIO_LVLSET_CONFIGVALUE;
+
+ config_reg->CONFIG_PORTADIR = GIO_PORTADIR_CONFIGVALUE;
+ config_reg->CONFIG_PORTAPDR = GIO_PORTAPDR_CONFIGVALUE;
+ config_reg->CONFIG_PORTAPSL = GIO_PORTAPSL_CONFIGVALUE;
+ config_reg->CONFIG_PORTAPULDIS = GIO_PORTAPULDIS_CONFIGVALUE;
+
+ config_reg->CONFIG_PORTBDIR = GIO_PORTBDIR_CONFIGVALUE;
+ config_reg->CONFIG_PORTBPDR = GIO_PORTBPDR_CONFIGVALUE;
+ config_reg->CONFIG_PORTBPSL = GIO_PORTBPSL_CONFIGVALUE;
+ config_reg->CONFIG_PORTBPULDIS = GIO_PORTBPULDIS_CONFIGVALUE;
+ }
+ else
+ {
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_INTDET = gioREG->INTDET;
+ config_reg->CONFIG_POL = gioREG->POL;
+ config_reg->CONFIG_INTENASET = gioREG->ENASET;
+ config_reg->CONFIG_LVLSET = gioREG->LVLSET;
+
+ config_reg->CONFIG_PORTADIR = gioPORTA->DIR;
+ config_reg->CONFIG_PORTAPDR = gioPORTA->PDR;
+ config_reg->CONFIG_PORTAPSL = gioPORTA->PSL;
+ config_reg->CONFIG_PORTAPULDIS = gioPORTA->PULDIS;
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_PORTBDIR = gioPORTB->DIR;
+ config_reg->CONFIG_PORTBPDR = gioPORTB->PDR;
+ config_reg->CONFIG_PORTBPSL = gioPORTB->PSL;
+ config_reg->CONFIG_PORTBPULDIS = gioPORTB->PULDIS;
+ }
+}
+
+
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
Index: firmware/source/het.c
===================================================================
diff -u
--- firmware/source/het.c (revision 0)
+++ firmware/source/het.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,1966 @@
+/** @file het.c
+* @brief HET Driver Implementation File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#include "het.h"
+#include "sys_vim.h"
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/*----------------------------------------------------------------------------*/
+/* Global variables */
+
+static const uint32 s_het1pwmPolarity[8U] =
+{
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+ 3U,
+};
+
+
+/*----------------------------------------------------------------------------*/
+/* Default Program */
+
+/** @var static const hetINSTRUCTION_t het1PROGRAM[58]
+* @brief Default Program
+*
+* Het program running after initialization.
+*/
+
+static const hetINSTRUCTION_t het1PROGRAM[58U] =
+{
+ /* CNT: Timebase
+ * - Instruction = 0
+ * - Next instruction = 1
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = na
+ * - Reg = T
+ */
+ {
+ /* Program */
+ 0x00002C80U,
+ /* Control */
+ 0x01FFFFFFU,
+ /* Data */
+ 0xFFFFFF80U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 0 -> Duty Cycle
+ * - Instruction = 1
+ * - Next instruction = 2
+ * - Conditional next instruction = 2
+ * - Interrupt = 1
+ * - Pin = 8
+ */
+ {
+ /* Program */
+ 0x000055C0U,
+ /* Control */
+ (0x00004006U | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 0 -> Period
+ * - Instruction = 2
+ * - Next instruction = 3
+ * - Conditional next instruction = 41
+ * - Interrupt = 2
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00007480U,
+ /* Control */
+ 0x00052006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 1 -> Duty Cycle
+ * - Instruction = 3
+ * - Next instruction = 4
+ * - Conditional next instruction = 4
+ * - Interrupt = 3
+ * - Pin = 10
+ */
+ {
+ /* Program */
+ 0x000095C0U,
+ /* Control */
+ (0x00008006U | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 1 -> Period
+ * - Instruction = 4
+ * - Next instruction = 5
+ * - Conditional next instruction = 43
+ * - Interrupt = 4
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0000B480U,
+ /* Control */
+ 0x00056006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 2 -> Duty Cycle
+ * - Instruction = 5
+ * - Next instruction = 6
+ * - Conditional next instruction = 6
+ * - Interrupt = 5
+ * - Pin = 12
+ */
+ {
+ /* Program */
+ 0x0000D5C0U,
+ /* Control */
+ (0x0000C006U | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 2 -> Period
+ * - Instruction = 6
+ * - Next instruction = 7
+ * - Conditional next instruction = 45
+ * - Interrupt = 6
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0000F480U,
+ /* Control */
+ 0x0005A006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 3 -> Duty Cycle
+ * - Instruction = 7
+ * - Next instruction = 8
+ * - Conditional next instruction = 8
+ * - Interrupt = 7
+ * - Pin = 14
+ */
+ {
+ /* Program */
+ 0x000115C0U,
+ /* Control */
+ (0x00010006U | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 3 -> Period
+ * - Instruction = 8
+ * - Next instruction = 9
+ * - Conditional next instruction = 47
+ * - Interrupt = 8
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00013480U,
+ /* Control */
+ 0x0005E006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 4 -> Duty Cycle
+ * - Instruction = 9
+ * - Next instruction = 10
+ * - Conditional next instruction = 10
+ * - Interrupt = 9
+ * - Pin = 16
+ */
+ {
+ /* Program */
+ 0x000155C0U,
+ /* Control */
+ (0x00014006U | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 4 -> Period
+ * - Instruction = 10
+ * - Next instruction = 11
+ * - Conditional next instruction = 49
+ * - Interrupt = 10
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00017480U,
+ /* Control */
+ 0x00062006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 5 -> Duty Cycle
+ * - Instruction = 11
+ * - Next instruction = 12
+ * - Conditional next instruction = 12
+ * - Interrupt = 11
+ * - Pin = 17
+ */
+ {
+ /* Program */
+ 0x000195C0U,
+ /* Control */
+ (0x00018006U | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 5 -> Period
+ * - Instruction = 12
+ * - Next instruction = 13
+ * - Conditional next instruction = 51
+ * - Interrupt = 12
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001B480U,
+ /* Control */
+ 0x00066006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 6 -> Duty Cycle
+ * - Instruction = 13
+ * - Next instruction = 14
+ * - Conditional next instruction = 14
+ * - Interrupt = 13
+ * - Pin = 18
+ */
+ {
+ /* Program */
+ 0x0001D5C0U,
+ /* Control */
+ (0x0001C006U | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 6 -> Period
+ * - Instruction = 14
+ * - Next instruction = 15
+ * - Conditional next instruction = 53
+ * - Interrupt = 14
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001F480U,
+ /* Control */
+ 0x0006A006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PWCNT: PWM 7 -> Duty Cycle
+ * - Instruction = 15
+ * - Next instruction = 16
+ * - Conditional next instruction = 16
+ * - Interrupt = 15
+ * - Pin = 19
+ */
+ {
+ /* Program */
+ 0x000215C0U,
+ /* Control */
+ (0x00020006U | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* DJZ: PWM 7 -> Period
+ * - Instruction = 16
+ * - Next instruction = 17
+ * - Conditional next instruction = 55
+ * - Interrupt = 16
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00023480U,
+ /* Control */
+ 0x0006E006U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 0
+ * - Instruction = 17
+ * - Next instruction = 18
+ * - Conditional next instruction = 18
+ * - Interrupt = 17
+ * - Pin = 12
+ */
+ {
+ /* Program */
+ 0x00025440U,
+ /* Control */
+ (0x00024007U | (uint32)((uint32)12U << 8U) | (uint32)((uint32)1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 1
+ * - Instruction = 18
+ * - Next instruction = 19
+ * - Conditional next instruction = 19
+ * - Interrupt = 18
+ * - Pin = 14
+ */
+ {
+ /* Program */
+ 0x00027440U,
+ /* Control */
+ (0x00026007U | (uint32)((uint32)14U << 8U) | (uint32)((uint32)1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 2
+ * - Instruction = 19
+ * - Next instruction = 20
+ * - Conditional next instruction = 20
+ * - Interrupt = 19
+ * - Pin = 30
+ */
+ {
+ /* Program */
+ 0x00029440U,
+ /* Control */
+ (0x00028007U | (uint32)((uint32)30U << 8U) | (uint32)((uint32)1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 3
+ * - Instruction = 20
+ * - Next instruction = 21
+ * - Conditional next instruction = 21
+ * - Interrupt = 20
+ * - Pin = 15
+ */
+ {
+ /* Program */
+ 0x0002B440U,
+ /* Control */
+ (0x0002A007U | (uint32)((uint32)15U << 8U) | (uint32)((uint32)1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 4
+ * - Instruction = 21
+ * - Next instruction = 22
+ * - Conditional next instruction = 22
+ * - Interrupt = 21
+ * - Pin = 20
+ */
+ {
+ /* Program */
+ 0x0002D440U,
+ /* Control */
+ (0x0002C007U | (uint32)((uint32)20U << 8U) | (uint32)((uint32)1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 5
+ * - Instruction = 22
+ * - Next instruction = 23
+ * - Conditional next instruction = 23
+ * - Interrupt = 22
+ * - Pin = 21
+ */
+ {
+ /* Program */
+ 0x0002F440U,
+ /* Control */
+ (0x0002E007U | (uint32)((uint32)21U << 8U) | (uint32)((uint32)1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 6
+ * - Instruction = 23
+ * - Next instruction = 24
+ * - Conditional next instruction = 24
+ * - Interrupt = 23
+ * - Pin = 22
+ */
+ {
+ /* Program */
+ 0x00031440U,
+ /* Control */
+ (0x00030007U | (uint32)((uint32)22U << 8U) | (uint32)((uint32)1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* ECNT: CCU Edge 7
+ * - Instruction = 24
+ * - Next instruction = 25
+ * - Conditional next instruction = 25
+ * - Interrupt = 24
+ * - Pin = 23
+ */
+ {
+ /* Program */
+ 0x00033440U,
+ /* Control */
+ (0x00032007U | (uint32)((uint32)23U << 8U) | (uint32)((uint32)1U << 4U)),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 0
+ * - Instruction = 25
+ * - Next instruction = 26
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 0
+ */
+ {
+ /* Program */
+ 0x00034E00U | (uint32)((uint32)0U << 6U) | (uint32)(0U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 0
+ * - Instruction = 26
+ * - Next instruction = 27
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 0 + 1
+ */
+ {
+ /* Program */
+ 0x00036E80U | (uint32)((uint32)0U << 6U) | (uint32)((0U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 1
+ * - Instruction = 27
+ * - Next instruction = 28
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 2
+ */
+ {
+ /* Program */
+ 0x00038E00U | (uint32)((uint32)0U << 6U) | (uint32)(2U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 1
+ * - Instruction = 28
+ * - Next instruction = 29
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 2 + 1
+ */
+ {
+ /* Program */
+ 0x0003AE80U | (uint32)((uint32)0U << 6U) | (uint32)((2U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 2
+ * - Instruction = 29
+ * - Next instruction = 30
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 4
+ */
+ {
+ /* Program */
+ 0x0003CE00U | (uint32)((uint32)0U << 6U) | (uint32)(4U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 2
+ * - Instruction = 30
+ * - Next instruction = 31
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 4 + 1
+ */
+ {
+ /* Program */
+ 0x0003EE80U | (uint32)((uint32)0U << 6U) | (uint32)((4U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 3
+ * - Instruction = 31
+ * - Next instruction = 32
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 6
+ */
+ {
+ /* Program */
+ 0x00040E00U | (uint32)((uint32)0U << 6U) | (uint32)(6U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 3
+ * - Instruction = 32
+ * - Next instruction = 33
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 6 + 1
+ */
+ {
+ /* Program */
+ 0x00042E80U | (uint32)((uint32)0U << 6U) | (uint32)((6U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 4
+ * - Instruction = 33
+ * - Next instruction = 34
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 24
+ */
+ {
+ /* Program */
+ 0x00044E00U | (uint32)((uint32)0U << 6U) | (uint32)(24U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 4
+ * - Instruction = 34
+ * - Next instruction = 35
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 24 + 1
+ */
+ {
+ /* Program */
+ 0x00046E80U | (uint32)((uint32)0U << 6U) | (uint32)((24U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 5
+ * - Instruction = 35
+ * - Next instruction = 36
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 26
+ */
+ {
+ /* Program */
+ 0x00048E00U | (uint32)((uint32)0U << 6U) | (uint32)(26U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 5
+ * - Instruction = 36
+ * - Next instruction = 37
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 26 + 1
+ */
+ {
+ /* Program */
+ 0x0004AE80U | (uint32)((uint32)0U << 6U) | (uint32)((26U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 6
+ * - Instruction = 37
+ * - Next instruction = 38
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 28
+ */
+ {
+ /* Program */
+ 0x0004CE00U | (uint32)((uint32)0U << 6U) | (uint32)(28U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 6
+ * - Instruction = 38
+ * - Next instruction = 39
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 28 + 1
+ */
+ {
+ /* Program */
+ 0x0004EE80U | (uint32)((uint32)0U << 6U) | (uint32)((28U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Duty 7
+ * - Instruction = 39
+ * - Next instruction = 40
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 30
+ */
+ {
+ /* Program */
+ 0x00050E00U | (uint32)((uint32)0U << 6U) | (uint32)(30U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* PCNT: Capture Period 7
+ * - Instruction = 40
+ * - Next instruction = 57
+ * - Conditional next instruction = na
+ * - Interrupt = na
+ * - Pin = 30 + 1
+ */
+ {
+ /* Program */
+ 0x00072E80U | (uint32)((uint32)0U << 6U) | (uint32)((30U) + 1U),
+ /* Control */
+ 0x00000000U,
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 0 -> Duty Cycle Update
+ * - Instruction = 41
+ * - Next instruction = 42
+ * - Conditional next instruction = 2
+ * - Interrupt = 1
+ * - Pin = 8
+ */
+ {
+ /* Program */
+ 0x00054201U,
+ /* Control */
+ (0x00004007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 52224U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 0 -> Period Update
+ * - Instruction = 42
+ * - Next instruction = 3
+ * - Conditional next instruction = 41
+ * - Interrupt = 2
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00006202U,
+ /* Control */
+ (0x00052007U),
+ /* Data */
+ 103936U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 1 -> Duty Cycle Update
+ * - Instruction = 43
+ * - Next instruction = 44
+ * - Conditional next instruction = 4
+ * - Interrupt = 3
+ * - Pin = 10
+ */
+ {
+ /* Program */
+ 0x00058203U,
+ /* Control */
+ (0x00008007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 52224U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 1 -> Period Update
+ * - Instruction = 44
+ * - Next instruction = 5
+ * - Conditional next instruction = 43
+ * - Interrupt = 4
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0000A204U,
+ /* Control */
+ (0x00056007U),
+ /* Data */
+ 103936U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 2 -> Duty Cycle Update
+ * - Instruction = 45
+ * - Next instruction = 46
+ * - Conditional next instruction = 6
+ * - Interrupt = 5
+ * - Pin = 12
+ */
+ {
+ /* Program */
+ 0x0005C205U,
+ /* Control */
+ (0x0000C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 52224U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 2 -> Period Update
+ * - Instruction = 46
+ * - Next instruction = 7
+ * - Conditional next instruction = 45
+ * - Interrupt = 6
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0000E206U,
+ /* Control */
+ (0x0005A007U),
+ /* Data */
+ 103936U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 3 -> Duty Cycle Update
+ * - Instruction = 47
+ * - Next instruction = 48
+ * - Conditional next instruction = 8
+ * - Interrupt = 7
+ * - Pin = 14
+ */
+ {
+ /* Program */
+ 0x00060207U,
+ /* Control */
+ (0x00010007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 52224U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 3 -> Period Update
+ * - Instruction = 48
+ * - Next instruction = 9
+ * - Conditional next instruction = 47
+ * - Interrupt = 8
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00012208U,
+ /* Control */
+ (0x0005E007U),
+ /* Data */
+ 103936U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 4 -> Duty Cycle Update
+ * - Instruction = 49
+ * - Next instruction = 50
+ * - Conditional next instruction = 10
+ * - Interrupt = 9
+ * - Pin = 16
+ */
+ {
+ /* Program */
+ 0x00064209U,
+ /* Control */
+ (0x00014007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 52224U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 4 -> Period Update
+ * - Instruction = 50
+ * - Next instruction = 11
+ * - Conditional next instruction = 49
+ * - Interrupt = 10
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001620AU,
+ /* Control */
+ (0x00062007U),
+ /* Data */
+ 103936U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 5 -> Duty Cycle Update
+ * - Instruction = 51
+ * - Next instruction = 52
+ * - Conditional next instruction = 12
+ * - Interrupt = 11
+ * - Pin = 17
+ */
+ {
+ /* Program */
+ 0x0006820BU,
+ /* Control */
+ (0x00018007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 52224U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 5 -> Period Update
+ * - Instruction = 52
+ * - Next instruction = 13
+ * - Conditional next instruction = 51
+ * - Interrupt = 12
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001A20CU,
+ /* Control */
+ (0x00066007U),
+ /* Data */
+ 103936U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 6 -> Duty Cycle Update
+ * - Instruction = 53
+ * - Next instruction = 54
+ * - Conditional next instruction = 14
+ * - Interrupt = 13
+ * - Pin = 18
+ */
+ {
+ /* Program */
+ 0x0006C20DU,
+ /* Control */
+ (0x0001C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 52224U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 6 -> Period Update
+ * - Instruction = 54
+ * - Next instruction = 15
+ * - Conditional next instruction = 53
+ * - Interrupt = 14
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x0001E20EU,
+ /* Control */
+ (0x0006A007U),
+ /* Data */
+ 103936U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 7 -> Duty Cycle Update
+ * - Instruction = 55
+ * - Next instruction = 56
+ * - Conditional next instruction = 16
+ * - Interrupt = 15
+ * - Pin = 19
+ */
+ {
+ /* Program */
+ 0x0007020FU,
+ /* Control */
+ (0x00020007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)),
+ /* Data */
+ 52224U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* MOV64: PWM 7 -> Period Update
+ * - Instruction = 56
+ * - Next instruction = 17
+ * - Conditional next instruction = 55
+ * - Interrupt = 16
+ * - Pin = na
+ */
+ {
+ /* Program */
+ 0x00022210U,
+ /* Control */
+ (0x0006E007U),
+ /* Data */
+ 103936U,
+ /* Reserved */
+ 0x00000000U
+ },
+ /* WCAP: Capture timestamp
+ * - Instruction = 57
+ * - Next instruction = 0
+ * - Conditional next instruction = 0
+ * - Interrupt = na
+ * - Pin = na
+ * - Reg = T
+ */
+ {
+ /* Program */
+ 0x00001600U,
+ /* Control */
+ (0x00000004U),
+ /* Data */
+ 0x00000000U,
+ /* Reserved */
+ 0x00000000U
+ },
+};
+
+
+
+/** @fn void hetInit(void)
+* @brief Initializes the het Driver
+*
+* This function initializes the het 1 module.
+*/
+/* SourceId : HET_SourceId_001 */
+/* DesignId : HET_DesignId_001 */
+/* Requirements : HL_SR363 */
+void hetInit(void)
+{
+ /** @b initialize @b HET */
+
+ /** - Set HET pins default output value */
+ hetREG1->DOUT = (uint32)((uint32)0U << 31U)
+ | (uint32)((uint32)0U << 30U)
+ | (uint32)((uint32)0U << 29U)
+ | (uint32)((uint32)0U << 28U)
+ | (uint32)((uint32)0U << 27U)
+ | (uint32)((uint32)0U << 26U)
+ | (uint32)((uint32)0U << 25U)
+ | (uint32)((uint32)0U << 24U)
+ | (uint32)((uint32)0U << 23U)
+ | (uint32)((uint32)0U << 22U)
+ | (uint32)((uint32)0U << 21U)
+ | (uint32)((uint32)0U << 20U)
+ | (uint32)((uint32)0U << 19U)
+ | (uint32)((uint32)0U << 18U)
+ | (uint32)((uint32)0U << 17U)
+ | (uint32)((uint32)0U << 16U)
+ | (uint32)((uint32)0U << 15U)
+ | (uint32)((uint32)0U << 14U)
+ | (uint32)((uint32)0U << 13U)
+ | (uint32)((uint32)0U << 12U)
+ | (uint32)((uint32)0U << 11U)
+ | (uint32)((uint32)0U << 10U)
+ | (uint32)((uint32)0U << 9U)
+ | (uint32)((uint32)0U << 8U)
+ | (uint32)((uint32)0U << 7U)
+ | (uint32)((uint32)0U << 6U)
+ | (uint32)((uint32)0U << 5U)
+ | (uint32)((uint32)0U << 4U)
+ | (uint32)((uint32)0U << 3U)
+ | (uint32)((uint32)0U << 2U)
+ | (uint32)((uint32)0U << 1U)
+ | (uint32)((uint32)0U << 0U);
+
+ /** - Set HET pins direction */
+ hetREG1->DIR = (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00400000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00040000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000010U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U;
+
+ /** - Set HET pins open drain enable */
+ hetREG1->PDR = (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U;
+
+ /** - Set HET pins pullup/down enable */
+ hetREG1->PULDIS = (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U;
+
+ /** - Set HET pins pullup/down select */
+ hetREG1->PSL = (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00400000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U;
+
+ /** - Set HET pins high resolution share */
+ hetREG1->HRSH = (uint32) 0x00008000U
+ | (uint32) 0x00004000U
+ | (uint32) 0x00002000U
+ | (uint32) 0x00001000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000008U
+ | (uint32) 0x00000004U
+ | (uint32) 0x00000002U
+ | (uint32) 0x00000001U;
+
+ /** - Set HET pins AND share */
+ hetREG1->AND = (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U;
+
+ /** - Set HET pins XOR share */
+ hetREG1->XOR = (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U;
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+ /** - Setup prescaler values
+ * - Loop resolution prescaler
+ * - High resolution prescaler
+ */
+ hetREG1->PFR = (uint32)((uint32) 7U << 8U)
+ | ((uint32) 0U);
+
+
+ /** - Parity control register
+ * - Enable/Disable Parity check
+ */
+ hetREG1->PCR = (uint32) 0x00000005U;
+
+ /** - Fill HET RAM with opcodes and Data */
+ /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
+ /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
+ /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
+ /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
+ (void)memcpy((void *)hetRAM1, (const void *)het1PROGRAM, sizeof(het1PROGRAM));
+
+ /** - Setup interrupt priority level
+ * - PWM 0 end of duty level
+ * - PWM 0 end of period level
+ * - PWM 1 end of duty level
+ * - PWM 1 end of period level
+ * - PWM 2 end of duty level
+ * - PWM 2 end of period level
+ * - PWM 3 end of duty level
+ * - PWM 3 end of period level
+ * - PWM 4 end of duty level
+ * - PWM 4 end of period level
+ * - PWM 5 end of duty level
+ * - PWM 5 end of period level
+ * - PWM 6 end of duty level
+ * - PWM 6 end of period level
+ * - PWM 7 end of duty level
+ * - PWM 7 end of period level
+
+ * - CCU Edge Detection 0 level
+ * - CCU Edge Detection 1 level
+ * - CCU Edge Detection 2 level
+ * - CCU Edge Detection 3 level
+ * - CCU Edge Detection 4 level
+ * - CCU Edge Detection 5 level
+ * - CCU Edge Detection 6 level
+ * - CCU Edge Detection 7 level
+ */
+ hetREG1->PRY = (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00020000U
+ | (uint32) 0x00040000U
+ | (uint32) 0x00080000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U;
+
+ /** - Enable interrupts
+ * - PWM 0 end of duty
+ * - PWM 0 end of period
+ * - PWM 1 end of duty
+ * - PWM 1 end of period
+ * - PWM 2 end of duty
+ * - PWM 2 end of period
+ * - PWM 3 end of duty
+ * - PWM 3 end of period
+ * - PWM 4 end of duty
+ * - PWM 4 end of period
+ * - PWM 5 end of duty
+ * - PWM 5 end of period
+ * - PWM 6 end of duty
+ * - PWM 6 end of period
+ * - PWM 7 end of duty
+ * - PWM 7 end of period
+ * - CCU Edge Detection 0
+ * - CCU Edge Detection 1
+ * - CCU Edge Detection 2
+ * - CCU Edge Detection 3
+ * - CCU Edge Detection 4
+ * - CCU Edge Detection 5
+ * - CCU Edge Detection 6
+ * - CCU Edge Detection 7
+ */
+ hetREG1->INTENAC = 0xFFFFFFFFU;
+ hetREG1->INTENAS = (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00020000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U
+ | (uint32) 0x00000000U;
+
+
+ /** - Setup control register
+ * - Enable output buffers
+ * - Ignore software breakpoints
+ * - Master or Slave Clock Mode
+ * - Enable HET
+ */
+ hetREG1->GCR = ( 0x00000001U
+ | (uint32)((uint32)0U << 24U)
+ | (uint32)((uint32)1U << 16U)
+ | (0x00020000U));
+
+
+}
+/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm)
+* @brief Start pwm signal
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+*
+* Start the given pwm signal
+*/
+/* SourceId : HET_SourceId_002 */
+/* DesignId : HET_DesignId_002 */
+/* Requirements : HL_SR364 */
+void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm)
+{
+
+ hetRAM->Instruction[(pwm << 1U) + 41U].Control |= 0x00400000U;
+}
+
+
+/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm)
+* @brief Stop pwm signal
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+*
+* Stop the given pwm signal
+*/
+/* SourceId : HET_SourceId_003 */
+/* DesignId : HET_DesignId_003 */
+/* Requirements : HL_SR365 */
+void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm)
+{
+ hetRAM->Instruction[(pwm << 1U) + 41U].Control &= ~(uint32)0x00400000U;
+}
+
+
+/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty)
+* @brief Set duty cycle
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] pwmDuty duty cycle in %.
+*
+* Sets a new duty cycle on the given pwm signal
+*/
+/* SourceId : HET_SourceId_004 */
+/* DesignId : HET_DesignId_004 */
+/* Requirements : HL_SR366 */
+void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty)
+{
+ uint32 action;
+ uint32 pwmPolarity =0U;
+ uint32 pwmPeriod = hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128U;
+ pwmPeriod = pwmPeriod >> 7U;
+
+ if(hetRAM == hetRAM1)
+ {
+ pwmPolarity = s_het1pwmPolarity[pwm];
+ }
+ else
+ {
+ }
+ if (pwmDuty == 0U)
+ {
+ action = (pwmPolarity == 3U) ? 0U : 2U;
+ }
+ else if (pwmDuty >= 100U)
+ {
+ action = (pwmPolarity == 3U) ? 2U : 0U;
+ }
+ else
+ {
+ action = pwmPolarity;
+ }
+
+ hetRAM->Instruction[(pwm << 1U) + 41U].Control = ((hetRAM->Instruction[(pwm << 1U) + 41U].Control) & (~(uint32)(0x00000018U))) | (action << 3U);
+ hetRAM->Instruction[(pwm << 1U) + 41U].Data = (((pwmPeriod * pwmDuty) / 100U) << 7U) + 128U;
+}
+
+
+/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal)
+* @brief Set period
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] signal signal
+ - duty cycle in %.
+* - period period in us.
+*
+* Sets a new pwm signal
+*/
+/* SourceId : HET_SourceId_005 */
+/* DesignId : HET_DesignId_005 */
+/* Requirements : HL_SR367 */
+void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal)
+{
+ uint32 action;
+ uint32 pwmPolarity = 0U;
+ float64 pwmPeriod = 0.0F;
+
+ if(hetRAM == hetRAM1)
+ {
+ pwmPeriod = (signal.period * 1000.0F) / 1230.769F;
+ pwmPolarity = s_het1pwmPolarity[pwm];
+ }
+ else
+ {
+ }
+ if (signal.duty == 0U)
+ {
+ action = (pwmPolarity == 3U) ? 0U : 2U;
+ }
+ else if (signal.duty >= 100U)
+ {
+ action = (pwmPolarity == 3U) ? 2U : 0U;
+ }
+ else
+ {
+ action = pwmPolarity;
+ }
+
+ hetRAM->Instruction[(pwm << 1U) + 41U].Control = ((hetRAM->Instruction[(pwm << 1U) + 41U].Control) & (~(uint32)(0x00000018U))) | (action << 3U);
+ hetRAM->Instruction[(pwm << 1U) + 41U].Data = ((((uint32)pwmPeriod * signal.duty) / 100U) << 7U ) + 128U;
+ hetRAM->Instruction[(pwm << 1U) + 42U].Data = ((uint32)pwmPeriod << 7U) - 128U;
+
+}
+
+
+/** @fn void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal)
+* @brief Get duty cycle
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] signal signal
+* - duty cycle in %.
+* - period period in us.
+*
+* Gets current signal of the given pwm signal.
+*/
+/* SourceId : HET_SourceId_006 */
+/* DesignId : HET_DesignId_006 */
+/* Requirements : HL_SR368 */
+void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t* signal)
+{
+ uint32 pwmDuty = (hetRAM->Instruction[(pwm << 1U) + 41U].Data - 128U) >> 7U;
+ uint32 pwmPeriod = (hetRAM->Instruction[(pwm << 1U) + 42U].Data + 128U) >> 7U;
+
+ signal->duty = (pwmDuty * 100U) / pwmPeriod;
+
+ if(hetRAM == hetRAM1)
+ {
+ signal->period = ((float64)pwmPeriod * 1230.769F) / 1000.0F;
+ }
+ else
+ {
+ signal->period = ((float64)pwmPeriod * 1230.769F) / 1000.0F;
+ }
+}
+
+/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification)
+* @brief Enable pwm notification
+* @param[in] hetREG Pointer to HET Module:
+* - hetREG1: HET1 Module pointer
+* - hetREG2: HET2 Module pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] notification Pwm notification:
+* - pwmEND_OF_DUTY: Notification on end of duty
+* - pwmEND_OF_PERIOD: Notification on end of end period
+* - pwmEND_OF_BOTH: Notification on end of both duty and period
+*/
+/* SourceId : HET_SourceId_007 */
+/* DesignId : HET_DesignId_007 */
+/* Requirements : HL_SR369 */
+void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification)
+{
+ hetREG->FLG = notification << (pwm << 1U);
+ hetREG->INTENAS = notification << (pwm << 1U);
+}
+
+
+/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification)
+* @brief Enable pwm notification
+* @param[in] hetREG Pointer to HET Module:
+* - hetREG1: HET1 Module pointer
+* - hetREG2: HET2 Module pointer
+* @param[in] pwm Pwm signal:
+* - pwm0: Pwm 0
+* - pwm1: Pwm 1
+* - pwm2: Pwm 2
+* - pwm3: Pwm 3
+* - pwm4: Pwm 4
+* - pwm5: Pwm 5
+* - pwm6: Pwm 6
+* - pwm7: Pwm 7
+* @param[in] notification Pwm notification:
+* - pwmEND_OF_DUTY: Notification on end of duty
+* - pwmEND_OF_PERIOD: Notification on end of end period
+* - pwmEND_OF_BOTH: Notification on end of both duty and period
+*/
+/* SourceId : HET_SourceId_008 */
+/* DesignId : HET_DesignId_008 */
+/* Requirements : HL_SR370 */
+void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification)
+{
+ hetREG->INTENAC = notification << (pwm << 1U);
+}
+
+
+/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge)
+* @brief Resets edge counter to 0
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] edge Edge signal:
+* - edge0: Edge 0
+* - edge1: Edge 1
+* - edge2: Edge 2
+* - edge3: Edge 3
+* - edge4: Edge 4
+* - edge5: Edge 5
+* - edge6: Edge 6
+* - edge7: Edge 7
+*
+* Reset edge counter to 0.
+*/
+/* SourceId : HET_SourceId_009 */
+/* DesignId : HET_DesignId_009 */
+/* Requirements : HL_SR372 */
+void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge)
+{
+ hetRAM->Instruction[edge + 17U].Data = 0U;
+}
+
+
+/** @fn uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge)
+* @brief Get current edge counter value
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] edge Edge signal:
+* - edge0: Edge 0
+* - edge1: Edge 1
+* - edge2: Edge 2
+* - edge3: Edge 3
+* - edge4: Edge 4
+* - edge5: Edge 5
+* - edge6: Edge 6
+* - edge7: Edge 7
+*
+* Gets current edge counter value.
+*/
+/* SourceId : HET_SourceId_010 */
+/* DesignId : HET_DesignId_010 */
+/* Requirements : HL_SR373 */
+uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge)
+{
+ return hetRAM->Instruction[edge + 17U].Data >> 7U;
+}
+
+
+/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge)
+* @brief Enable edge notification
+* @param[in] hetREG Pointer to HET Module:
+* - hetREG1: HET1 Module pointer
+* - hetREG2: HET2 Module pointer
+* @param[in] edge Edge signal:
+* - edge0: Edge 0
+* - edge1: Edge 1
+* - edge2: Edge 2
+* - edge3: Edge 3
+* - edge4: Edge 4
+* - edge5: Edge 5
+* - edge6: Edge 6
+* - edge7: Edge 7
+*/
+/* SourceId : HET_SourceId_011 */
+/* DesignId : HET_DesignId_011 */
+/* Requirements : HL_SR374 */
+void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge)
+{
+ hetREG->FLG = (uint32)0x20000U << edge;
+ hetREG->INTENAS = (uint32)0x20000U << edge;
+}
+
+
+/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge)
+* @brief Enable edge notification
+* @param[in] hetREG Pointer to HET Module:
+* - hetREG1: HET1 Module pointer
+* - hetREG2: HET2 Module pointer
+* @param[in] edge Edge signal:
+* - edge0: Edge 0
+* - edge1: Edge 1
+* - edge2: Edge 2
+* - edge3: Edge 3
+* - edge4: Edge 4
+* - edge5: Edge 5
+* - edge6: Edge 6
+* - edge7: Edge 7
+*/
+/* SourceId : HET_SourceId_012 */
+/* DesignId : HET_DesignId_012 */
+/* Requirements : HL_SR375 */
+void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge)
+{
+ hetREG->INTENAC = (uint32)0x20000U << edge;
+}
+
+
+/** @fn void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t signal)
+* @brief Get capture signal
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+* @param[in] cap captured signal:
+* - cap0: Captured signal 0
+* - cap1: Captured signal 1
+* - cap2: Captured signal 2
+* - cap3: Captured signal 3
+* - cap4: Captured signal 4
+* - cap5: Captured signal 5
+* - cap6: Captured signal 6
+* - cap7: Captured signal 7
+* @param[in] signal signal
+* - duty cycle in %.
+* - period period in us.
+*
+* Gets current signal of the given capture signal.
+*/
+/* SourceId : HET_SourceId_013 */
+/* DesignId : HET_DesignId_013 */
+/* Requirements : HL_SR377 */
+void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t *signal)
+{
+ uint32 pwmDuty = (hetRAM->Instruction[(cap << 1U) + 25U].Data) >> 7U;
+ uint32 pwmPeriod = (hetRAM->Instruction[(cap << 1U) + 26U].Data) >> 7U;
+
+ signal->duty = (pwmDuty * 100U) / pwmPeriod;
+
+ if( hetRAM == hetRAM1)
+ {
+ signal->period = ((float64)pwmPeriod * 1230.769F) / 1000.0F;
+ }
+ else
+ {
+ signal->period = ((float64)pwmPeriod * 1230.769F) / 1000.0F;
+ }
+}
+
+
+/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM)
+* @brief Resets timestamp
+* @param[in] hetRAM Pointer to HET RAM:
+* - hetRAM1: HET1 RAM pointer
+* - hetRAM2: HET2 RAM pointer
+*
+* Resets loop count based timestamp.
+*/
+/* SourceId : HET_SourceId_014 */
+/* DesignId : HET_DesignId_014 */
+/* Requirements : HL_SR378 */
+void hetResetTimestamp(hetRAMBASE_t * hetRAM)
+{
+ hetRAM->Instruction[0U].Data = 0U;
+}
+
+
+/** @fn uint32 hetGetTimestamp(hetRAMBASE_t *hetRAM)
+* @brief Returns timestamp
+*
+* Returns loop count based timestamp.
+*/
+/* SourceId : HET_SourceId_015 */
+/* DesignId : HET_DesignId_015 */
+/* Requirements : HL_SR379 */
+uint32 hetGetTimestamp(hetRAMBASE_t * hetRAM)
+{
+ return hetRAM->Instruction[57U].Data;
+}
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+
+/** @fn void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the HET1 configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : HET_SourceId_016 */
+/* DesignId : HET_DesignId_016 */
+/* Requirements : HL_SR379 */
+void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_GCR = HET1_GCR_CONFIGVALUE;
+ config_reg->CONFIG_PFR = HET1_PFR_CONFIGVALUE;
+ config_reg->CONFIG_INTENAS = HET1_INTENAS_CONFIGVALUE;
+ config_reg->CONFIG_INTENAC = HET1_INTENAC_CONFIGVALUE;
+ config_reg->CONFIG_PRY = HET1_PRY_CONFIGVALUE;
+ config_reg->CONFIG_AND = HET1_AND_CONFIGVALUE;
+ config_reg->CONFIG_HRSH = HET1_HRSH_CONFIGVALUE;
+ config_reg->CONFIG_XOR = HET1_XOR_CONFIGVALUE;
+ config_reg->CONFIG_DIR = HET1_DIR_CONFIGVALUE;
+ config_reg->CONFIG_PDR = HET1_PDR_CONFIGVALUE;
+ config_reg->CONFIG_PULDIS = HET1_PULDIS_CONFIGVALUE;
+ config_reg->CONFIG_PSL = HET1_PSL_CONFIGVALUE;
+ config_reg->CONFIG_PCR = HET1_PCR_CONFIGVALUE;
+ }
+ else
+ {
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_GCR = hetREG1->GCR;
+ config_reg->CONFIG_PFR = hetREG1->PFR;
+ config_reg->CONFIG_INTENAS = hetREG1->INTENAS;
+ config_reg->CONFIG_INTENAC = hetREG1->INTENAC;
+ config_reg->CONFIG_PRY = hetREG1->PRY;
+ config_reg->CONFIG_AND = hetREG1->AND;
+ config_reg->CONFIG_HRSH = hetREG1->HRSH;
+ config_reg->CONFIG_XOR = hetREG1->XOR;
+ config_reg->CONFIG_DIR = hetREG1->DIR;
+ config_reg->CONFIG_PDR = hetREG1->PDR;
+ config_reg->CONFIG_PULDIS = hetREG1->PULDIS;
+ config_reg->CONFIG_PSL = hetREG1->PSL;
+ config_reg->CONFIG_PCR = hetREG1->PCR;
+ }
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+/** @fn void het1HighLevelInterrupt(void)
+* @brief Level 0 Interrupt for HET1
+*/
+
+/* SourceId : HET_SourceId_018 */
+/* DesignId : HET_DesignId_017 */
+/* Requirements : HL_SR371, HL_SR380, HL_SR381 */
+void het1HighLevelInterrupt(void)
+{
+ uint32 vec = hetREG1->OFF1;
+
+ if (vec < 18U)
+ {
+ if ((vec & 1U) != 0U)
+ {
+ pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_PERIOD);
+ }
+ else
+ {
+ pwmNotification(hetREG1,(vec >> 1U) - 1U, pwmEND_OF_DUTY);
+ }
+ }
+ else
+ {
+ edgeNotification(hetREG1,vec - 18U);
+ }
+}
+
+
Index: firmware/source/i2c.c
===================================================================
diff -u
--- firmware/source/i2c.c (revision 0)
+++ firmware/source/i2c.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,849 @@
+/** @file i2c.c
+* @brief I2C Driver Implementation File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "i2c.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @struct g_i2CTransfer
+* @brief Interrupt mode globals
+*
+*/
+static struct g_i2cTransfer
+{
+ uint32 mode;
+ uint32 length;
+ uint8 * data;
+} g_i2cTransfer_t;
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+/** @fn void i2cInit(void)
+* @brief Initializes the i2c Driver
+*
+* This function initializes the i2c module.
+*/
+/* SourceId : I2C_SourceId_001 */
+/* DesignId : I2C_DesignId_001 */
+/* Requirements : HL_SR279 */
+void i2cInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+ /** @b initialize @b I2C */
+
+ /** - i2c Enter reset */
+ i2cREG1->MDR = (uint32)((uint32)0U << 5U);
+
+ /** - set i2c mode */
+ i2cREG1->MDR = (uint32)((uint32)0U << 15U) /* nack mode */
+ | (uint32)((uint32)0U << 14U) /* free running */
+ | (uint32)(0U) /* start condition - master only */
+ | (uint32)((uint32)1U <<11U) /* stop condition */
+ | (uint32)((uint32)1U <<10U) /* Master/Slave mode */
+ | (uint32)((uint32)I2C_TRANSMITTER) /* Transmitter/receiver */
+ | (uint32)((uint32)I2C_7BIT_AMODE) /* xpanded address */
+ | (uint32)((uint32)1U << 7U) /* repeat mode */
+ | (uint32)((uint32)0U << 6U) /* digital loop back */
+ | (uint32)((uint32)0U << 4U) /* start byte - master only */
+ | (uint32)((uint32)0U << 3U) /* free data format */
+ | (uint32)(I2C_8_BIT); /* bit count */
+
+
+ /** - set i2c Backward Compatibility mode */
+ i2cREG1->EMDR = 0U;
+
+ /** - Disable DMA */
+ i2cREG1->DMACR = 0x00U;
+
+ /** - set i2c data count */
+ i2cREG1->CNT = 8U;
+
+ /** - disable all interrupts */
+ i2cREG1->IMR = 0x00U;
+
+ /** - set prescale */
+ i2cREG1->PSC = 12U;
+
+ /** - set clock rate */
+ i2cREG1->CKH = 35U;
+ i2cREG1->CKL = 35U;
+
+ /** - set i2c pins functional mode */
+ i2cREG1->PFNC = (0U);
+
+ /** - set i2c pins default output value */
+ i2cREG1->DOUT = (uint32)((uint32)0U << 1U) /* sda pin */
+ | (uint32)(0U); /* scl pin */
+
+ /** - set i2c pins output direction */
+ i2cREG1->DIR = (uint32)((uint32)0U << 1U) /* sda pin */
+ | (uint32)(0U); /* scl pin */
+
+ /** - set i2c pins open drain enable */
+ i2cREG1->PDR = (uint32)((uint32)1U << 1U) /* sda pin */
+ | (uint32)(1U); /* scl pin */
+
+ /** - set i2c pins pullup/pulldown enable */
+ i2cREG1->PDIS = (uint32)((uint32)0U << 1U) /* sda pin */
+ | (uint32)(0U); /* scl pin */
+
+ /** - set i2c pins pullup/pulldown select */
+ i2cREG1->PSEL = (uint32)((uint32)1U << 1U) /* sda pin */
+ | (uint32)(1U); /* scl pin */
+
+ /** - set interrupt enable */
+ i2cREG1->IMR = (uint32)((uint32)0U << 6U) /* Address as slave interrupt */
+ | (uint32)((uint32)0U << 5U) /* Stop Condition detect interrupt */
+ | (uint32)((uint32)0U << 4U) /* Transmit data ready interrupt */
+ | (uint32)((uint32)0U << 3U) /* Receive data ready interrupt */
+ | (uint32)((uint32)0U << 2U) /* Register Access ready interrupt */
+ | (uint32)((uint32)0U << 1U) /* No Acknowledgement interrupt */
+ | (uint32)((uint32)0U); /* Arbitration Lost interrupt */
+
+ /** - i2c Out of reset */
+ i2cREG1->MDR |= (uint32)I2C_RESET_OUT;
+
+ /** - initialize global transfer variables */
+ g_i2cTransfer_t.mode = (uint32)0U << 4U;
+ g_i2cTransfer_t.length = 0U;
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+}
+
+/** @fn void i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd)
+* @brief Set I2C Own Address
+* @param[in] oadd - I2C Own address (7-bit or 10 -bit address)
+* @param[in] i2c - i2c module base address
+* Set the Own address of the I2C module.
+*/
+/* SourceId : I2C_SourceId_002 */
+/* DesignId : I2C_DesignId_002 */
+/* Requirements : HL_SR280 */
+void i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd)
+{
+ i2c->OAR = oadd; /* set own address */
+}
+
+/** @fn void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd)
+* @brief Set Port Direction
+* @param[in] sadd - I2C Slave address
+* @param[in] i2c - i2c module base address
+* Set the Slave address to communicate which is must in Master mode.
+*/
+/* SourceId : I2C_SourceId_003 */
+/* DesignId : I2C_DesignId_003 */
+/* Requirements : HL_SR281 */
+void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd)
+{
+ i2c->SAR = sadd; /* set slave address */
+}
+
+/** @fn void i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud)
+* @brief Change baudrate at runtime.
+* @param[in] i2c - i2c module base address
+* @param[in] baud - baudrate in KHz
+*
+* Change the i2c baudrate at runtime. The I2C module needs to be taken to reset( nIRS=0 in I2CMDR) in order to change baud rate.
+*/
+/* SourceId : I2C_SourceId_004 */
+/* DesignId : I2C_DesignId_004 */
+/* Requirements : HL_SR282 */
+void i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud)
+{
+ uint32 prescale;
+ uint32 d;
+ uint32 ck;
+ float64 vclk = 104.000F * 1000000.0F;
+ float64 divider= 0.0F;
+ uint32 temp = 0U;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+ divider = vclk / 8000000.0F;
+ prescale = (uint32)divider - 1U;
+
+ if(prescale>=2U)
+ {
+ d = 5U;
+ }
+ else
+ {
+ d = (prescale != 0U) ? 6U : 7U;
+ }
+
+ temp = 2U * baud * 1000U * (prescale + 1U);
+ divider = vclk / ((float64)temp);
+ ck = (uint32)divider - d;
+
+ i2c->PSC = prescale;
+ i2c->CKH = ck;
+ i2c->CKL = ck;
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+}
+
+/** @fn void i2cSetStart(i2cBASE_t *i2c)
+* @brief Set i2c start condition
+* @param[in] i2c - i2c module base address
+* Set i2c to generate a start bit (Only in Master mode)
+*/
+/* SourceId : I2C_SourceId_005 */
+/* DesignId : I2C_DesignId_015 */
+/* Requirements : HL_SR293 */
+void i2cSetStart(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+ i2c->MDR |= (uint32)I2C_START_COND; /* set start condition */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+/** @fn void i2cSetStop(i2cBASE_t *i2c)
+* @brief Set i2c stop condition
+* @param[in] i2c - i2c module base address
+* Set i2c to generate a stop bit (Only in Master mode)
+*/
+/* SourceId : I2C_SourceId_006 */
+/* DesignId : I2C_DesignId_016 */
+/* Requirements : HL_SR294 */
+void i2cSetStop(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+ i2c->MDR |= (uint32)I2C_STOP_COND; /* generate stop condition */
+
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+}
+
+/** @fn void i2cSetCount(i2cBASE_t *i2c,uint32 cnt)
+* @brief Set i2c data count
+* @param[in] i2c - i2c module base address
+* @param[in] cnt - data count
+* Set i2c count to a transfer value after which the stop condition needs to be generated.
+* (Only in Master Mode)
+*/
+/* SourceId : I2C_SourceId_007 */
+/* DesignId : I2C_DesignId_017 */
+/* Requirements : HL_SR295 */
+void i2cSetCount(i2cBASE_t *i2c ,uint32 cnt)
+{
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+
+ i2c->CNT = cnt; /* set i2c count */
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+}
+
+/** @fn uint32 i2cIsTxReady(i2cBASE_t *i2c)
+* @brief Check if Tx buffer empty
+* @param[in] i2c - i2c module base address
+*
+* @return The TX ready flag
+*
+* Checks to see if the Tx buffer ready flag is set, returns
+* 0 is flags not set otherwise will return the Tx flag itself.
+*/
+/* SourceId : I2C_SourceId_008 */
+/* DesignId : I2C_DesignId_005 */
+/* Requirements : HL_SR283 */
+uint32 i2cIsTxReady(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+ return i2c->STR & (uint32)I2C_TX_INT;
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+/** @fn void i2cSendByte(i2cBASE_t *i2c, uint8 byte)
+* @brief Send Byte
+* @param[in] i2c - i2c module base address
+* @param[in] byte - byte to transfer
+*
+* Sends a single byte in polling mode, will wait in the
+* routine until the transmit buffer is empty before sending
+* the byte. Use i2cIsTxReady to check for Tx buffer empty
+* before calling i2cSendByte to avoid waiting.
+*/
+/* SourceId : I2C_SourceId_009 */
+/* DesignId : I2C_DesignId_006 */
+/* Requirements : HL_SR284 */
+void i2cSendByte(i2cBASE_t *i2c, uint8 byte)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((i2c->STR & (uint32)I2C_TX_INT) == 0U)
+ {
+ } /* Wait */
+ i2c->DXR = (uint32)byte;
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+/** @fn void i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data)
+* @brief Send Data
+* @param[in] i2c - i2c module base address
+* @param[in] length - number of data words to transfer
+* @param[in] data - pointer to data to send
+*
+* Send a block of data pointed to by 'data' and 'length' bytes
+* long. If interrupts have been enabled the data is sent using
+* interrupt mode, otherwise polling mode is used. In interrupt
+* mode transmission of the first byte is started and the routine
+* returns immediately, i2cSend must not be called again until the
+* transfer is complete, when the i2cNotification callback will
+* be called. In polling mode, i2cSend will not return until
+* the transfer is complete.
+*
+* @note if data word is less than 8 bits, then the data must be left
+* aligned in the data byte.
+*/
+/* SourceId : I2C_SourceId_010 */
+/* DesignId : I2C_DesignId_007 */
+/* Requirements : HL_SR285 */
+void i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data)
+{
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ if ((g_i2cTransfer_t.mode & (uint32)I2C_TX_INT) != 0U)
+ {
+ /* Interrupt mode */
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ g_i2cTransfer_t.data = data;
+ /* start transmit by sending first byte */
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ i2c->DXR = (uint32)(*g_i2cTransfer_t.data);
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ g_i2cTransfer_t.data++;
+
+ /* Length -1 since one data is written already */
+ g_i2cTransfer_t.length = (length - 1U);
+
+ /* Enable Transmit Interrupt */
+ i2c->IMR |= (uint32)I2C_TX_INT;
+ }
+ else
+ {
+ /* send the data */
+ while (length > 0U)
+ {
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((i2c->STR & (uint32)I2C_TX_INT) == 0U)
+ {
+ } /* Wait */
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ i2c->DXR = (uint32)(*data);
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ data++;
+ length--;
+ }
+ }
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+/** @fn uint32 i2cIsRxReady(i2cBASE_t *i2c)
+* @brief Check if Rx buffer full
+* @param[in] i2c - i2c module base address
+*
+* @return The Rx ready flag
+*
+* Checks to see if the Rx buffer full flag is set, returns
+* 0 is flags not set otherwise will return the Rx flag itself.
+*/
+/* SourceId : I2C_SourceId_011 */
+/* DesignId : I2C_DesignId_008 */
+/* Requirements : HL_SR286 */
+uint32 i2cIsRxReady(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ return i2c->STR & (uint32)I2C_RX_INT;
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+}
+
+/** @fn uint32 i2cIsStopDetected(i2cBASE_t *i2c)
+* @brief Check if Stop Condition Detected
+* @param[in] i2c - i2c module base address
+*
+* @return The Stop Condition Detected flag
+*
+* Checks to see if the Stop Condition Detected flag is set,
+* returns 0 if flags not set otherwise will return the Stop
+* Condition Detected flag itself.
+*/
+/* SourceId : I2C_SourceId_023 */
+/* DesignId : I2C_DesignId_023 */
+/* Requirements : HL_SR539 */
+uint32 i2cIsStopDetected(i2cBASE_t *i2c)
+{
+ return i2c->STR & (uint32)I2C_SCD_INT;
+}
+
+/** @fn uint32 i2cRxError(i2cBASE_t *i2c)
+* @brief Return Rx Error flags
+* @param[in] i2c - i2c module base address
+*
+* @return The Rx error flags
+*
+* Returns the Rx framing, overrun and parity errors flags,
+* also clears the error flags before returning.
+*/
+/* SourceId : I2C_SourceId_012 */
+/* DesignId : I2C_DesignId_010 */
+/* Requirements : HL_SR288 */
+uint32 i2cRxError(i2cBASE_t *i2c)
+{
+ uint32 status = i2c->STR & ((uint32)I2C_AL_INT | (uint32)I2C_NACK_INT);
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+ i2c->STR = (uint32)((uint32)I2C_AL_INT | (uint32)I2C_NACK_INT);
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ return status;
+
+}
+
+/** @fn void i2cClearSCD(i2cBASE_t *i2c)
+* @brief Clears the Stop condition detect flags.
+* @param[in] i2c - i2c module base address
+*
+* This function is called to clear the Stop condition detect(SCD) flag
+*/
+/* SourceId : I2C_SourceId_013 */
+/* DesignId : I2C_DesignId_009 */
+/* Requirements : HL_SR287 */
+void i2cClearSCD(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+ i2c->STR = (uint32)I2C_SCD_INT;
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+}
+
+/** @fn uint8 i2cReceiveByte(i2cBASE_t *i2c)
+* @brief Receive Byte
+* @param[in] i2c - i2c module base address
+*
+* @return Received byte
+*
+* Receives a single byte in polling mode. If there is
+* not a byte in the receive buffer the routine will wait
+* until one is received. Use i2cIsRxReady to check to
+* see if the buffer is full to avoid waiting.
+*/
+/* SourceId : I2C_SourceId_014 */
+/* DesignId : I2C_DesignId_011 */
+/* Requirements : HL_SR289 */
+uint8 i2cReceiveByte(i2cBASE_t *i2c)
+{
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((i2c->STR & (uint32)I2C_RX_INT) == 0U)
+ {
+ } /* Wait */
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+
+ return ((uint8)i2c->DRR);
+}
+
+/** @fn void i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data)
+* @brief Receive Data
+* @param[in] i2c - i2c module base address
+* @param[in] length - number of data words to transfer
+* @param[in] data - pointer to data buffer
+*
+* Receive a block of 'length' bytes long and place it into the
+* data buffer pointed to by 'data'. If interrupts have been
+* enabled the data is received using interrupt mode, otherwise
+* polling mode is used. In interrupt mode receive is setup and
+* the routine returns immediately, i2cReceive must not be called
+* again until the transfer is complete, when the i2cNotification
+* callback will be called. In polling mode, i2cReceive will not
+* return until the transfer is complete.
+*/
+/* SourceId : I2C_SourceId_015 */
+/* DesignId : I2C_DesignId_012 */
+/* Requirements : HL_SR290 */
+void i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data)
+{
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+ if ((i2c->IMR & (uint32)I2C_RX_INT) != 0U)
+ {
+ /* we are in interrupt mode */
+ /* clear error flags */
+ i2c->STR = (uint32)I2C_AL_INT | (uint32)I2C_NACK_INT;
+
+ g_i2cTransfer_t.length = length;
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ g_i2cTransfer_t.data = data;
+ }
+ else
+ {
+ while (length > 0U)
+ {
+ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */
+ while ((i2c->STR & (uint32)I2C_RX_INT) == 0U)
+ {
+ } /* Wait */
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ *data = ((uint8)i2c->DRR);
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ data++;
+ length--;
+ }
+ }
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+
+/** @fn void i2cEnableLoopback(i2cBASE_t *i2c)
+* @brief Enable Loopback mode for self test
+* @param[in] i2c - i2c module base address
+*
+* This function enables the Loopback mode for self test.
+*/
+/* SourceId : I2C_SourceId_016 */
+/* DesignId : I2C_DesignId_018 */
+/* Requirements : HL_SR296 */
+void i2cEnableLoopback(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ /* enable digital loopback */
+ i2c->MDR |= ((uint32)1U << 6U);
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+/** @fn void i2cDisableLoopback(i2cBASE_t *i2c)
+* @brief Enable Loopback mode for self test
+* @param[in] i2c - i2c module base address
+*
+* This function disable the Loopback mode.
+*/
+/* SourceId : I2C_SourceId_017 */
+/* DesignId : I2C_DesignId_019 */
+/* Requirements : HL_SR297 */
+void i2cDisableLoopback(i2cBASE_t *i2c)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ /* Disable Loopback Mode */
+ i2c->MDR &= 0xFFFFFFBFU;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+/** @fn i2cEnableNotification(i2cBASE_t *i2c, uint32 flags)
+* @brief Enable interrupts
+* @param[in] i2c - i2c module base address
+* @param[in] flags - Interrupts to be enabled, can be ored value of:
+* i2c_FE_INT - framing error,
+* i2c_OE_INT - overrun error,
+* i2c_PE_INT - parity error,
+* i2c_RX_INT - receive buffer ready,
+* i2c_TX_INT - transmit buffer ready,
+* i2c_WAKE_INT - wakeup,
+* i2c_BREAK_INT - break detect
+*/
+/* SourceId : I2C_SourceId_018 */
+/* DesignId : I2C_DesignId_013 */
+/* Requirements : HL_SR291 */
+void i2cEnableNotification(i2cBASE_t *i2c, uint32 flags)
+{
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+ g_i2cTransfer_t.mode |= (flags & (uint32)I2C_TX_INT);
+ i2c->IMR = (flags & (uint32)(~(uint32)I2C_TX_INT));
+}
+
+/** @fn i2cDisableNotification(i2cBASE_t *i2c, uint32 flags)
+* @brief Disable interrupts
+* @param[in] i2c - i2c module base address
+* @param[in] flags - Interrupts to be disabled, can be ored value of:
+* i2c_FE_INT - framing error,
+* i2c_OE_INT - overrun error,
+* i2c_PE_INT - parity error,
+* i2c_RX_INT - receive buffer ready,
+* i2c_TX_INT - transmit buffer ready,
+* i2c_WAKE_INT - wakeup,
+* i2c_BREAK_INT - break detect
+*/
+/* SourceId : I2C_SourceId_019 */
+/* DesignId : I2C_DesignId_014 */
+/* Requirements : HL_SR292 */
+void i2cDisableNotification(i2cBASE_t *i2c, uint32 flags)
+{
+ uint32 int_mask;
+
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+ g_i2cTransfer_t.mode &= (uint32)(~(flags & (uint32)I2C_TX_INT));
+ int_mask = i2c->IMR &(uint32)(~(uint32)(flags | (uint32)I2C_TX_INT));
+ i2c->IMR = int_mask;
+}
+
+
+/** @fn i2cSetMode(i2cBASE_t *i2c, uint32 mode)
+* @brief Sets Master or Slave mode.
+* @param[in] i2c - i2c module base address
+* @param[in] mode - Mode can be either:
+* I2C_MASTER - Master Mode,
+* I2C_SLAVE - Slave Mode
+*/
+/* SourceId : I2C_SourceId_020 */
+/* DesignId : I2C_DesignId_024 */
+/* Requirements : HL_SR526 */
+void i2cSetMode(i2cBASE_t *i2c, uint32 mode)
+{
+ uint32 temp_mdr;
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+
+ /* set Master or Slave Mode */
+ temp_mdr = (i2c->MDR & (~I2C_MASTER));
+ i2c->MDR = (temp_mdr | mode);
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+}
+
+
+/** @fn void i2cGetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the I2C configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : I2C_SourceId_021 */
+/* DesignId : I2C_DesignId_021 */
+/* Requirements : HL_SR300 */
+void i2cGetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_OAR = I2C_OAR_CONFIGVALUE;
+ config_reg->CONFIG_IMR = I2C_IMR_CONFIGVALUE;
+ config_reg->CONFIG_CLKL = I2C_CLKL_CONFIGVALUE;
+ config_reg->CONFIG_CLKH = I2C_CLKH_CONFIGVALUE;
+ config_reg->CONFIG_CNT = I2C_CNT_CONFIGVALUE;
+ config_reg->CONFIG_SAR = I2C_SAR_CONFIGVALUE;
+ config_reg->CONFIG_MDR = I2C_MDR_CONFIGVALUE;
+ config_reg->CONFIG_EMDR = I2C_EMDR_CONFIGVALUE;
+ config_reg->CONFIG_PSC = I2C_PSC_CONFIGVALUE;
+ config_reg->CONFIG_DMAC = I2C_DMAC_CONFIGVALUE;
+ config_reg->CONFIG_FUN = I2C_FUN_CONFIGVALUE;
+ config_reg->CONFIG_DIR = I2C_DIR_CONFIGVALUE;
+ config_reg->CONFIG_ODR = I2C_ODR_CONFIGVALUE;
+ config_reg->CONFIG_PD = I2C_PD_CONFIGVALUE;
+ config_reg->CONFIG_PSL = I2C_PSL_CONFIGVALUE;
+ }
+ else
+ {
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_OAR = i2cREG1->OAR;
+ config_reg->CONFIG_IMR = i2cREG1->IMR;
+ config_reg->CONFIG_CLKL = i2cREG1->CKL;
+ config_reg->CONFIG_CLKH = i2cREG1->CKH;
+ config_reg->CONFIG_CNT = i2cREG1->CNT;
+ config_reg->CONFIG_SAR = i2cREG1->SAR;
+ config_reg->CONFIG_MDR = i2cREG1->MDR;
+ config_reg->CONFIG_EMDR = i2cREG1->EMDR;
+ config_reg->CONFIG_PSC = i2cREG1->PSC;
+ config_reg->CONFIG_DMAC = i2cREG1->DMACR;
+ config_reg->CONFIG_FUN = i2cREG1->PFNC;
+ config_reg->CONFIG_DIR = i2cREG1->DIR;
+ config_reg->CONFIG_ODR = i2cREG1->PDR;
+ config_reg->CONFIG_PD = i2cREG1->PDIS;
+ config_reg->CONFIG_PSL = i2cREG1->PSEL;
+ }
+}
+
+
+
+/** @fn i2cSetDirection(i2cBASE_t *i2c, uint32 dir)
+* @brief Sets I2C as transmitter or receiver.
+* @param[in] i2c - i2c module base address
+* @param[in] dir - This can be one of the following:
+* I2C_TRANSMITTER - Transmit Mode,
+* I2C_RECEIVER - Receive Mode
+*/
+/* SourceId : I2C_SourceId_024 */
+/* DesignId : I2C_DesignId_020 */
+/* Requirements : HL_SR540 */
+void i2cSetDirection(i2cBASE_t *i2c, uint32 dir)
+{
+/* USER CODE BEGIN (47) */
+/* USER CODE END */
+
+ /* set Transmit/Receive mode */
+ i2c->MDR &= ~I2C_TRANSMITTER;
+ i2c->MDR |= dir;
+
+/* USER CODE BEGIN (48) */
+/* USER CODE END */
+}
+
+/** @fn i2cIsMasterReady(i2cBASE_t *i2c)
+* @brief Indicates whether MST bit is set or cleared to indicate that stop
+* condition was generated. This API should be called after Master Tx or Rx
+* to check if the transaction is complete.
+* @param[in] i2c - i2c module base address
+* @return boolean value to indicate whether MST bit is cleared after STOP bit is generated.
+* - TRUE, if MST bit is cleared.
+* - FALSE, if MST bit is set.
+*/
+/* SourceId : I2C_SourceId_025 */
+/* DesignId : I2C_DesignId_025 */
+/* Requirements : HL_SR541 */
+bool i2cIsMasterReady(i2cBASE_t *i2c)
+{
+ bool retVal = 0U;
+/* USER CODE BEGIN (49) */
+/* USER CODE END */
+
+ /* check if MST bit is cleared. */
+ if((i2c->MDR & I2C_MASTER) == 0)
+ {
+ retVal = true;
+ }
+ else
+ {
+ retVal = false;
+ }
+ return retVal;
+
+/* USER CODE BEGIN (50) */
+/* USER CODE END */
+}
+
+/** @fn i2cIsBusBusy(i2cBASE_t *i2c)
+* @brief Returns the state of the bus busy flag. True if it is set and false otherwise.
+* @param[in] i2c - i2c module base address
+* @return boolean value to indicate whether BB bit is set in the status register.
+* - TRUE, if BB bit is set.
+* - FALSE, if BB bit is cleared.
+*/
+/* SourceId : I2C_SourceId_026 */
+/* DesignId : I2C_DesignId_026 */
+/* Requirements : HL_SR542 */
+bool i2cIsBusBusy(i2cBASE_t *i2c)
+{
+ bool retVal = 0U;
+/* USER CODE BEGIN (51) */
+/* USER CODE END */
+
+ /* check if BB bit is set. */
+ if((i2c->STR & I2C_BUSBUSY) == I2C_BUSBUSY)
+ {
+ retVal = true;
+ }
+ else
+ {
+ retVal = false;
+ }
+ return retVal;
+
+/* USER CODE BEGIN (52) */
+/* USER CODE END */
+}
+
Index: firmware/source/lin.c
===================================================================
diff -u
--- firmware/source/lin.c (revision 0)
+++ firmware/source/lin.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,769 @@
+/** @file lin.c
+* @brief LIN Driver Implementation File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "lin.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void linInit(void)
+* @brief Initializes the lin Driver
+*
+* This function initializes the lin module.
+*/
+/* SourceId : LIN_SourceId_001 */
+/* DesignId : LIN_DesignId_001 */
+/* Requirements : HL_SR253 */
+void linInit(void)
+{
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+ /** @b initialize @b LIN */
+
+ /** - Release from reset */
+ linREG->GCR0 = 1U;
+
+ /** - Start LIN configuration
+ * - Keep state machine in software reset
+ */
+ linREG->GCR1 = 0U;
+
+ /** - Enable LIN Mode */
+ linREG->GCR1 = 0x40U;
+
+ /** - Setup control register 1
+ * - Enable transmitter
+ * - Enable receiver
+ * - Stop when debug mode is entered
+ * - Disable Loopback mode
+ * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte)
+ * - Use enhance checksum
+ * - Enable multi buffer mode
+ * - Disable automatic baudrate adjustment
+ * - Disable sleep mode
+ * - Set LIN module as master
+ * - Enable/Disable parity
+ * - Disable data length control in ID4 and ID5
+ */
+ linREG->GCR1 |= 0x03000C40U
+ | (uint32)((uint32)0U << 12U)
+ | (uint32)((uint32)0U << 2U)
+ | (uint32)((uint32)0U << 5U);
+
+ /** - Setup maximum baud rate prescaler */
+ linREG->MBRSR = (uint32)4954U;
+
+ /** - Setup baud rate prescaler */
+ linREG->BRS = (uint32)343U;
+
+ /** - Setup RX and TX reception masks */
+ linREG->MASK = ((uint32)((uint32)0x00U << 16U) | (uint32)0x00U);
+
+ /** - Setup compare
+ * - Sync delimiter
+ * - Sync break extension
+ */
+ linREG->COMP = ((uint32)((uint32)(1U - 1U) << 8U) | ((uint32)13U - 13U));
+
+ /** - Setup response length */
+ linREG->FORMAT = ((linREG->FORMAT & 0xFFF8FFFFU) | (uint32)(((uint32)8U - 1U) << 16U));
+
+ /** - Set LIN pins functional mode
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->PIO0 = ((uint32)4U | (uint32)2U | (uint32)0U);
+
+ /** - Set LIN pins default output value
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->PIO3 = ((uint32)0U | (uint32)0U | (uint32)0U);
+
+ /** - Set LIN pins output direction
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->PIO1 = ((uint32)0U | (uint32)0U | (uint32)0U);
+
+ /** - Set LIN pins open drain enable
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->PIO6 = ((uint32)0U | (uint32)0U | (uint32)0U);
+
+ /** - Set LIN pins pullup/pulldown enable
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->PIO7 = ((uint32)0U | (uint32)0U | (uint32)0U);
+
+ /** - Set LIN pins pullup/pulldown select
+ * - TX
+ * - RX
+ * - CLK
+ */
+ linREG->PIO8 = ((uint32)0U | (uint32)0U | (uint32)1U);
+
+ /** - Set interrupt level
+ * - Bit error level
+ * - Physical bus error level
+ * - Checksum error level
+ * - Inconsistent sync field error level
+ * - No response error level
+ * - Framing error level
+ * - Overrun error level
+ * - Parity error level
+ * - Identifier level
+ * - RX level
+ * - TX level
+ * - Timeout after 3 wakeup signals level
+ * - Timeout after wakeup signal level
+ * - Timeout level
+ * - Wakeup level
+ * - Break detect level
+ */
+ linREG->SETINTLVL = ((uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U);
+
+ /** - Set interrupt enable
+ * - Enable/Disable bit error
+ * - Enable/Disable physical bus error level
+ * - Enable/Disable checksum error level
+ * - Enable/Disable inconsistent sync field error level
+ * - Enable/Disable no response error level
+ * - Enable/Disable framing error level
+ * - Enable/Disable overrun error level
+ * - Enable/Disable parity error level
+ * - Enable/Disable identifier level
+ * - Enable/Disable RX level
+ * - Enable/Disable TX level
+ * - Enable/Disable timeout after 3 wakeup signals level
+ * - Enable/Disable timeout after wakeup signal level
+ * - Enable/Disable timeout level
+ * - Enable/Disable wakeup level
+ * - Enable/Disable break detect level
+ */
+ linREG->SETINT = ((uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U
+ | (uint32)0x00000000U);
+
+ /** - Finaly start LIN */
+ linREG->GCR1 |= 0x00000080U;
+
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+}
+
+
+/** @fn void linSetFunctional(linBASE_t *lin, uint32 port)
+* @brief Change functional behavior of pins at runtime.
+* @param[in] lin - lin module base address
+* @param[in] port - Value to write to PIO0 register
+*
+* Change the value of the PCFUN register at runtime, this allows to
+* dynamically change the functionality of the LIN pins between functional
+* and GIO mode.
+*/
+/* SourceId : LIN_SourceId_002 */
+/* DesignId : LIN_DesignId_002 */
+/* Requirements : HL_SR254 */
+void linSetFunctional(linBASE_t *lin, uint32 port)
+{
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+
+ lin->PIO0 = port;
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+}
+
+
+/** @fn void linSendHeader(linBASE_t *lin, uint8 identifier)
+* @brief Send lin header.
+* @param[in] lin - lin module base address
+* @param[in] identifier - lin header id
+*
+* Send lin header including sync break field, sync field and identifier.
+*/
+/* SourceId : LIN_SourceId_003 */
+/* DesignId : LIN_DesignId_003 */
+/* Requirements : HL_SR255 */
+void linSendHeader(linBASE_t *lin, uint8 identifier)
+{
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+ lin->ID = ((lin->ID & 0xFFFFFF00U) | (uint32)identifier);
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+}
+
+
+/** @fn void linSendWakupSignal(linBASE_t *lin)
+* @brief Send lin wakeup signal.
+* @param[in] lin - lin module base address
+*
+* Send lin wakeup signal to terminate the sleep mode of any lin node connected to the BUS.
+*/
+/* SourceId : LIN_SourceId_004 */
+/* DesignId : LIN_DesignId_004 */
+/* Requirements : HL_SR256 */
+void linSendWakupSignal(linBASE_t *lin)
+{
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+
+ lin->TDx[0U] = 0xF0U;
+ lin->GCR2 |= 0x00000100U;
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+}
+
+/** @fn void linEnterSleep(linBASE_t *lin)
+* @brief Take Module to Sleep.
+* @param[in] lin - lin module base address
+*
+* Application must call this function to take Module to Sleep when Sleep command is received.
+* This function can also be called to forcefully enter Sleep when no activity on BUS.
+*/
+/* SourceId : LIN_SourceId_005 */
+/* DesignId : LIN_DesignId_005 */
+/* Requirements : HL_SR257 */
+void linEnterSleep(linBASE_t *lin)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+ lin->GCR2 |= 0x00000001U;
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+/** @fn void linSoftwareReset(linBASE_t *lin)
+* @brief Perform software reset.
+* @param[in] lin - lin module base address
+*
+* Perform software reset of lin module.
+* This function will reset the lin state machine and clear all pending flags.
+* It is required to call this function after a wakeup signal has been sent.
+*/
+/* SourceId : LIN_SourceId_006 */
+/* DesignId : LIN_DesignId_006 */
+/* Requirements : HL_SR258 */
+void linSoftwareReset(linBASE_t *lin)
+{
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+ lin->GCR1 &= ~(uint32)(0x00000080U);
+ lin->GCR1 |= 0x00000080U;
+
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+}
+
+/** @fn uint32 linIsTxReady(linBASE_t *lin)
+* @brief Check if Tx buffer empty
+* @param[in] lin - lin module base address
+*
+* @return The TX ready flag
+*
+* Checks to see if the Tx buffer ready flag is set, returns
+* 0 is flags not set otherwise will return the Tx flag itself.
+*/
+/* SourceId : LIN_SourceId_007 */
+/* DesignId : LIN_DesignId_007 */
+/* Requirements : HL_SR259 */
+uint32 linIsTxReady(linBASE_t *lin)
+{
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+
+ return lin->FLR & LIN_TX_READY;
+}
+
+/** @fn void linSetLength(linBASE_t *lin, uint32 length)
+* @brief Send Data
+* @param[in] lin - lin module base address
+* @param[in] length - number of data words in bytes. Range: 1-8.
+*
+* Send data response length in bytes.
+*/
+/* SourceId : LIN_SourceId_008 */
+/* DesignId : LIN_DesignId_008 */
+/* Requirements : HL_SR260 */
+void linSetLength(linBASE_t *lin, uint32 length)
+{
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+ lin->FORMAT = ((lin->FORMAT & 0xFFF8FFFFU) | ((length - 1U) << 16U));
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+}
+
+/** @fn void linSend(linBASE_t *lin, uint8 * data)
+* @brief Send Data
+* @param[in] lin - lin module base address
+* @param[in] data - pointer to data to send
+*
+* Send a block of data pointed to by 'data'.
+* The number of data to transmit must be set with 'linSetLength' before.
+*/
+/* SourceId : LIN_SourceId_009 */
+/* DesignId : LIN_DesignId_009 */
+/* Requirements : HL_SR261 */
+void linSend(linBASE_t *lin, uint8 * data)
+{
+ uint32 i;
+ uint32 length = (uint32)((uint32)(lin->FORMAT & 0x00070000U) >> 16U);
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ uint8 * pData = data + length;
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+ for (i=0U; i<=length; i++)
+ {
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ lin->TDx[length-i] = *pData;
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ pData--;
+ }
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+}
+
+/** @fn uint32 linIsRxReady(linBASE_t *lin)
+* @brief Check if Rx buffer full
+* @param[in] lin - lin module base address
+*
+* @return The Rx ready flag
+*
+* Checks to see if the Rx buffer full flag is set, returns
+* 0 is flags not set otherwise will return the Rx flag itself.
+*/
+/* SourceId : LIN_SourceId_010 */
+/* DesignId : LIN_DesignId_010 */
+/* Requirements : HL_SR262 */
+uint32 linIsRxReady(linBASE_t *lin)
+{
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+ return lin->FLR & LIN_RX_INT;
+}
+
+
+/** @fn uint32 linTxRxError(linBASE_t *lin)
+* @brief Return Tx and Rx Error flags
+* @param[in] lin - lin module base address
+*
+* @return The Tx and Rx error flags
+*
+* Returns the bit, physical bus, checksum, inconsistent sync field,
+* no response, framing, overrun, parity and timeout error flags.
+* It also clears the error flags before returning.
+*/
+/* SourceId : LIN_SourceId_011 */
+/* DesignId : LIN_DesignId_011 */
+/* Requirements : HL_SR263 */
+uint32 linTxRxError(linBASE_t *lin)
+{
+ uint32 status = lin->FLR & (LIN_BE_INT
+ | LIN_PBE_INT
+ | LIN_CE_INT
+ | LIN_ISFE_INT
+ | LIN_NRE_INT
+ | LIN_FE_INT
+ | LIN_OE_INT
+ | LIN_PE_INT
+ | LIN_TOA3WUS_INT
+ | LIN_TOAWUS_INT
+ | LIN_TO_INT);
+
+ lin->FLR = LIN_BE_INT
+ | LIN_PBE_INT
+ | LIN_CE_INT
+ | LIN_ISFE_INT
+ | LIN_NRE_INT
+ | LIN_FE_INT
+ | LIN_OE_INT
+ | LIN_PE_INT
+ | LIN_TOA3WUS_INT
+ | LIN_TOAWUS_INT
+ | LIN_TO_INT;
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+ return status;
+}
+
+
+/** @fn uint32 linGetIdentifier(linBASE_t *lin)
+* @brief Get last received identifier
+* @param[in] lin - lin module base address
+*
+* @return Identifier
+*
+* Read last received identifier.
+*/
+/* SourceId : LIN_SourceId_012 */
+/* DesignId : LIN_DesignId_012 */
+/* Requirements : HL_SR262 */
+uint32 linGetIdentifier(linBASE_t *lin)
+{
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+ return (uint32)((uint32)(lin->ID & 0x00FF0000U) >> 16U);
+}
+
+
+/** @fn void linGetData(linBASE_t *lin, uint8 * const data)
+* @brief Read received data
+* @param[in] lin - lin module base address
+* @param[in] data - pointer to data buffer
+*
+* Read a block of bytes and place it into the data buffer pointed to by 'data'.
+*/
+/* SourceId : LIN_SourceId_013 */
+/* DesignId : LIN_DesignId_013 */
+/* Requirements : HL_SR265 */
+void linGetData(linBASE_t *lin, uint8 * const data)
+{
+ uint32 i;
+ uint32 length = (uint32)((uint32)(lin->FORMAT & 0x00070000U) >> 16U);
+ uint8 * pData = data;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+ for (i = 0U; i <= length; i++)
+ {
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ *pData = lin->RDx[i];
+ /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */
+ /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */
+ pData++;
+ }
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+}
+
+
+/** @fn void linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype)
+* @brief Enable Loopback mode for self test
+* @param[in] lin - lin module base address
+* @param[in] Loopbacktype - Digital or Analog
+*
+* This function enables the Loopback mode for self test.
+*/
+/* SourceId : LIN_SourceId_014 */
+/* DesignId : LIN_DesignId_016 */
+/* Requirements : HL_SR268 */
+void linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype)
+{
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+ /* Clear Loopback incase enabled already */
+ lin->IODFTCTRL = 0U;
+
+ /* Enable Loopback either in Analog or Digital Mode */
+ lin->IODFTCTRL = ((uint32)(0x00000A00U)
+ | (uint32)((uint32)Loopbacktype << 1U));
+
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+}
+
+/** @fn void linDisableLoopback(linBASE_t *lin)
+* @brief Enable Loopback mode for self test
+* @param[in] lin - lin module base address
+*
+* This function disable the Loopback mode.
+*/
+/* SourceId : LIN_SourceId_015 */
+/* DesignId : LIN_DesignId_017 */
+/* Requirements : HL_SR269 */
+void linDisableLoopback(linBASE_t *lin)
+{
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+
+ /* Disable Loopback Mode */
+ lin->IODFTCTRL = 0x00000500U;
+
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+}
+
+
+/** @fn linEnableNotification(linBASE_t *lin, uint32 flags)
+* @brief Enable interrupts
+* @param[in] lin - lin module base address
+* @param[in] flags - Interrupts to be enabled, can be ored value of:
+* LIN_BE_INT - bit error,
+* LIN_PBE_INT - physical bus error,
+* LIN_CE_INT - checksum error,
+* LIN_ISFE_INT - inconsistent sync field error,
+* LIN_NRE_INT - no response error,
+* LIN_FE_INT - framing error,
+* LIN_OE_INT - overrun error,
+* LIN_PE_INT - parity error,
+* LIN_ID_INT - received matching identifier,
+* LIN_RX_INT - receive buffer ready,
+* LIN_TOA3WUS_INT - time out after 3 wakeup signals,
+* LIN_TOAWUS_INT - time out after wakeup signal,
+* LIN_TO_INT - time out signal,
+* LIN_WAKEUP_INT - wakeup,
+* LIN_BREAK_INT - break detect
+*/
+/* SourceId : LIN_SourceId_016 */
+/* DesignId : LIN_DesignId_014 */
+/* Requirements : HL_SR266 */
+void linEnableNotification(linBASE_t *lin, uint32 flags)
+{
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+
+ lin->SETINT = flags;
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+}
+
+
+/** @fn linDisableNotification(linBASE_t *lin, uint32 flags)
+* @brief Disable interrupts
+* @param[in] lin - lin module base address
+* @param[in] flags - Interrupts to be disabled, can be or'ed value of:
+* LIN_BE_INT - bit error,
+* LIN_PBE_INT - physical bus error,
+* LIN_CE_INT - checksum error,
+* LIN_ISFE_INT - inconsistent sync field error,
+* LIN_NRE_INT - no response error,
+* LIN_FE_INT - framing error,
+* LIN_OE_INT - overrun error,
+* LIN_PE_INT - parity error,
+* LIN_ID_INT - received matching identifier,
+* LIN_RX_INT - receive buffer ready,
+* LIN_TOA3WUS_INT - time out after 3 wakeup signals,
+* LIN_TOAWUS_INT - time out after wakeup signal,
+* LIN_TO_INT - time out signal,
+* LIN_WAKEUP_INT - wakeup,
+* LIN_BREAK_INT - break detect
+*/
+/* SourceId : LIN_SourceId_017 */
+/* DesignId : LIN_DesignId_015 */
+/* Requirements : HL_SR267 */
+void linDisableNotification(linBASE_t *lin, uint32 flags)
+{
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+ lin->CLEARINT = flags;
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+
+/** @fn void linGetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type)
+* @brief Get the initial or current values of the LIN configuration registers
+*
+* @param[in] *config_reg: pointer to the struct to which the initial or current
+* value of the configuration registers need to be stored
+* @param[in] type: whether initial or current value of the configuration registers need to be stored
+* - InitialValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+* - CurrentValue: initial value of the configuration registers will be stored
+* in the struct pointed by config_reg
+*
+* This function will copy the initial or current value (depending on the parameter 'type')
+* of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : LIN_SourceId_018 */
+/* DesignId : LIN_DesignId_018 */
+/* Requirements : HL_SR272 */
+void linGetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type)
+{
+ if (type == InitialValue)
+ {
+ config_reg->CONFIG_GCR0 = LIN_GCR0_CONFIGVALUE;
+ config_reg->CONFIG_GCR1 = LIN_GCR1_CONFIGVALUE;
+ config_reg->CONFIG_GCR2 = LIN_GCR2_CONFIGVALUE;
+ config_reg->CONFIG_SETINT = LIN_SETINT_CONFIGVALUE;
+ config_reg->CONFIG_SETINTLVL = LIN_SETINTLVL_CONFIGVALUE;
+ config_reg->CONFIG_FORMAT = LIN_FORMAT_CONFIGVALUE;
+ config_reg->CONFIG_BRSR = LIN_BRSR_CONFIGVALUE;
+ config_reg->CONFIG_FUN = LIN_FUN_CONFIGVALUE;
+ config_reg->CONFIG_DIR = LIN_DIR_CONFIGVALUE;
+ config_reg->CONFIG_ODR = LIN_ODR_CONFIGVALUE;
+ config_reg->CONFIG_PD = LIN_PD_CONFIGVALUE;
+ config_reg->CONFIG_PSL = LIN_PSL_CONFIGVALUE;
+ config_reg->CONFIG_COMP = LIN_COMP_CONFIGVALUE;
+ config_reg->CONFIG_MASK = LIN_MASK_CONFIGVALUE;
+ config_reg->CONFIG_MBRSR = LIN_MBRSR_CONFIGVALUE;
+ }
+ else
+ {
+ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */
+ config_reg->CONFIG_GCR0 = linREG->GCR0;
+ config_reg->CONFIG_GCR1 = linREG->GCR1;
+ config_reg->CONFIG_GCR2 = linREG->GCR2;
+ config_reg->CONFIG_SETINT = linREG->SETINT;
+ config_reg->CONFIG_SETINTLVL = linREG->SETINTLVL;
+ config_reg->CONFIG_FORMAT = linREG->FORMAT;
+ config_reg->CONFIG_BRSR = linREG->BRS;
+ config_reg->CONFIG_FUN = linREG->PIO0;
+ config_reg->CONFIG_DIR = linREG->PIO1;
+ config_reg->CONFIG_ODR = linREG->PIO6;
+ config_reg->CONFIG_PD = linREG->PIO7;
+ config_reg->CONFIG_PSL = linREG->PIO8;
+ config_reg->CONFIG_COMP = linREG->COMP;
+ config_reg->CONFIG_MASK = linREG->MASK;
+ config_reg->CONFIG_MBRSR = linREG->MBRSR;
+ }
+}
+
+
+
+/** @fn uint32 linGetStatusFlag(linBASE_t *lin)
+* @brief Get LIN status register value
+* @param[in] lin - lin module base address
+*
+* @return Status Flag register content
+*
+* Read current Status Flag register.
+*/
+/* SourceId : LIN_SourceId_021 */
+/* DesignId : LIN_DesignId_020 */
+/* Requirements : HL_SR544 */
+uint32 linGetStatusFlag(linBASE_t *lin)
+{
+ return lin->FLR;
+}
+
+/** @fn void linClearStatusFlag(linBASE_t *lin, uint32 flags)
+* @brief Clear LIN status register
+* @param[in] lin - lin module base address
+* @param[in] flags - Interrupts to be disabled, can be or'ed value of:
+* LIN_BE_INT - bit error,
+* LIN_PBE_INT - physical bus error,
+* LIN_CE_INT - checksum error,
+* LIN_ISFE_INT - inconsistent sync field error,
+* LIN_NRE_INT - no response error,
+* LIN_FE_INT - framing error,
+* LIN_OE_INT - overrun error,
+* LIN_PE_INT - parity error,
+* LIN_ID_INT - received matching identifier,
+* LIN_RX_INT - receive buffer ready,
+* LIN_TOA3WUS_INT - time out after 3 wakeup signals,
+* LIN_TOAWUS_INT - time out after wakeup signal,
+* LIN_TO_INT - time out signal,
+* LIN_WAKEUP_INT - wakeup,
+* LIN_BREAK_INT - break detect,
+* LIN_BUSY_FLAG - Bus Busy Flag,
+* LIN_TXEMPTY_INT - Transmit Empty Flag
+*
+* Clear Status Flags passed as parameter.
+*/
+/* SourceId : LIN_SourceId_022 */
+/* DesignId : LIN_DesignId_021 */
+/* Requirements : HL_SR545 */
+void linClearStatusFlag(linBASE_t *lin, uint32 flags)
+{
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+ lin->FLR = flags;
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+
+}
+
Index: firmware/source/mibspi.c
===================================================================
diff -u
--- firmware/source/mibspi.c (revision 0)
+++ firmware/source/mibspi.c (revision 73d8423edc56daed591bc0b3f7baee5540aea423)
@@ -0,0 +1,2051 @@
+/** @file mibspi.c
+* @brief MIBSPI Driver Implementation File
+* @date 11-Dec-2018
+* @version 04.07.01
+*
+*/
+
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+#include "mibspi.h"
+#include "sys_vim.h"
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+/** @fn void mibspiInit(void)
+* @brief Initializes the MIBSPI Driver
+*
+* This function initializes the MIBSPI module.
+*/
+/* SourceId : MIBSPI_SourceId_001 */
+/* DesignId : MIBSPI_DesignId_001 */
+/* Requirements : HL_SR153 */
+void mibspiInit(void)
+{
+uint32 i ;
+
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+
+
+ /** @b initialize @b MIBSPI1 */
+
+ /** bring MIBSPI out of reset */
+ mibspiREG1->GCR0 = 0U;
+ mibspiREG1->GCR0 = 1U;
+
+ /** enable MIBSPI1 multibuffered mode and enable buffer RAM */
+ mibspiREG1->MIBSPIE = (mibspiREG1->MIBSPIE & 0xFFFFFFFEU) | 1U;
+
+ /** MIBSPI1 master mode and clock configuration */
+ mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */
+ | 1U); /* MASTER */
+
+ /** MIBSPI1 enable pin configuration */
+ mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */
+
+ /** - Delays */
+ mibspiREG1->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */
+ | (uint32)((uint32)0U << 16U) /* T2CDELAY */
+ | (uint32)((uint32)0U << 8U) /* T2EDELAY */
+ | (uint32)((uint32)0U << 0U); /* C2EDELAY */
+
+ /** - Data Format 0 */
+ mibspiREG1->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Data Format 1 */
+ mibspiREG1->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Data Format 2 */
+ mibspiREG1->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Data Format 3 */
+ mibspiREG1->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Default Chip Select */
+ mibspiREG1->DEF = (uint32)(0xFFU);
+
+ /** - wait for buffer initialization complete before accessing MibSPI registers */
+ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */
+ while ((mibspiREG1->FLG & 0x01000000U) != 0U)
+ {
+ } /* Wait */
+
+ /** enable MIBSPI RAM Parity */
+ mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U);
+
+ /** - initialize transfer groups */
+ mibspiREG1->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)0U << 8U); /* start buffer */
+
+ mibspiREG1->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)8U << 8U); /* start buffer */
+
+ mibspiREG1->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U) << 8U); /* start buffer */
+
+ mibspiREG1->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG1->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG1->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG1->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG1->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+
+ mibspiREG1->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
+
+ mibspiREG1->LTGPEND = (mibspiREG1->LTGPEND & 0xFFFF00FFU) | (uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
+
+ /** - initialize buffer ram */
+ {
+ i = 0U;
+
+#if (8U > 0U)
+ {
+
+#if (8U > 1U)
+
+ while (i < (8U-1U))
+ {
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */
+ i++;
+ }
+#endif
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */
+
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U)-1U))
+ {
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U)-1U))
+ {
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U)-1U))
+ {
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */
+ i++;
+ }
+#endif
+ }
+
+ /** - set interrupt levels */
+ mibspiREG1->LVL = (uint32)((uint32)0U << 9U) /* TXINT */
+ | (uint32)((uint32)0U << 8U) /* RXINT */
+ | (uint32)((uint32)0U << 6U) /* OVRNINT */
+ | (uint32)((uint32)0U << 4U) /* BITERR */
+ | (uint32)((uint32)0U << 3U) /* DESYNC */
+ | (uint32)((uint32)0U << 2U) /* PARERR */
+ | (uint32)((uint32)0U << 1U) /* TIMEOUT */
+ | (uint32)((uint32)0U << 0U); /* DLENERR */
+
+ /** - clear any pending interrupts */
+ mibspiREG1->FLG |= 0xFFFFU;
+
+ /** - enable interrupts */
+ mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFFFF0000U)
+ | (uint32)((uint32)0U << 9U) /* TXINT */
+ | (uint32)((uint32)0U << 8U) /* RXINT */
+ | (uint32)((uint32)0U << 6U) /* OVRNINT */
+ | (uint32)((uint32)0U << 4U) /* BITERR */
+ | (uint32)((uint32)0U << 3U) /* DESYNC */
+ | (uint32)((uint32)0U << 2U) /* PARERR */
+ | (uint32)((uint32)0U << 1U) /* TIMEOUT */
+ | (uint32)((uint32)0U << 0U); /* DLENERR */
+
+ /** @b initialize @b MIBSPI1 @b Port */
+
+ /** - MIBSPI1 Port output values */
+ mibspiREG1->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */
+ | (uint32)((uint32)1U << 1U) /* SCS[1] */
+ | (uint32)((uint32)1U << 2U) /* SCS[2] */
+ | (uint32)((uint32)1U << 3U) /* SCS[3] */
+ | (uint32)((uint32)1U << 4U) /* SCS[4] */
+ | (uint32)((uint32)1U << 5U) /* SCS[5] */
+ | (uint32)((uint32)0U << 8U) /* ENA */
+ | (uint32)((uint32)0U << 9U) /* CLK */
+ | (uint32)((uint32)0U << 10U) /* SIMO[0] */
+ | (uint32)((uint32)0U << 11U) /* SOMI[0] */
+ | (uint32)((uint32)0U << 17U) /* SIMO[1] */
+ | (uint32)((uint32)0U << 25U); /* SOMI[1] */
+
+ /** - MIBSPI1 Port direction */
+ mibspiREG1->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */
+ | (uint32)((uint32)1U << 1U) /* SCS[1] */
+ | (uint32)((uint32)1U << 2U) /* SCS[2] */
+ | (uint32)((uint32)1U << 3U) /* SCS[3] */
+ | (uint32)((uint32)0U << 4U) /* SCS[4] */
+ | (uint32)((uint32)1U << 5U) /* SCS[5] */
+ | (uint32)((uint32)0U << 8U) /* ENA */
+ | (uint32)((uint32)1U << 9U) /* CLK */
+ | (uint32)((uint32)1U << 10U) /* SIMO[0] */
+ | (uint32)((uint32)0U << 11U) /* SOMI[0] */
+ | (uint32)((uint32)0U << 17U) /* SIMO[1] */
+ | (uint32)((uint32)0U << 25U); /* SOMI[1] */
+
+ /** - MIBSPI1 Port open drain enable */
+ mibspiREG1->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */
+ | (uint32)((uint32)0U << 1U) /* SCS[1] */
+ | (uint32)((uint32)0U << 2U) /* SCS[2] */
+ | (uint32)((uint32)0U << 3U) /* SCS[3] */
+ | (uint32)((uint32)0U << 4U) /* SCS[4] */
+ | (uint32)((uint32)0U << 5U) /* SCS[5] */
+ | (uint32)((uint32)0U << 8U) /* ENA */
+ | (uint32)((uint32)0U << 9U) /* CLK */
+ | (uint32)((uint32)0U << 10U) /* SIMO[0] */
+ | (uint32)((uint32)0U << 11U) /* SOMI[0] */
+ | (uint32)((uint32)0U << 17U) /* SIMO[1] */
+ | (uint32)((uint32)0U << 25U); /* SOMI[1] */
+
+ /** - MIBSPI1 Port pullup / pulldown selection */
+ mibspiREG1->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */
+ | (uint32)((uint32)1U << 1U) /* SCS[1] */
+ | (uint32)((uint32)1U << 2U) /* SCS[2] */
+ | (uint32)((uint32)1U << 3U) /* SCS[3] */
+ | (uint32)((uint32)1U << 4U) /* SCS[4] */
+ | (uint32)((uint32)1U << 5U) /* SCS[5] */
+ | (uint32)((uint32)1U << 8U) /* ENA */
+ | (uint32)((uint32)1U << 9U) /* CLK */
+ | (uint32)((uint32)1U << 10U) /* SIMO[0] */
+ | (uint32)((uint32)1U << 11U) /* SOMI[0] */
+ | (uint32)((uint32)1U << 17U) /* SIMO[1] */
+ | (uint32)((uint32)1U << 25U); /* SOMI[1] */
+
+ /** - MIBSPI1 Port pullup / pulldown enable*/
+ mibspiREG1->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */
+ | (uint32)((uint32)0U << 1U) /* SCS[1] */
+ | (uint32)((uint32)0U << 2U) /* SCS[2] */
+ | (uint32)((uint32)0U << 3U) /* SCS[3] */
+ | (uint32)((uint32)0U << 4U) /* SCS[4] */
+ | (uint32)((uint32)0U << 5U) /* SCS[5] */
+ | (uint32)((uint32)0U << 8U) /* ENA */
+ | (uint32)((uint32)0U << 9U) /* CLK */
+ | (uint32)((uint32)0U << 10U) /* SIMO[0] */
+ | (uint32)((uint32)0U << 11U) /* SOMI[0] */
+ | (uint32)((uint32)0U << 17U) /* SIMO[1] */
+ | (uint32)((uint32)0U << 25U); /* SOMI[1] */
+
+ /* MIBSPI1 set all pins to functional */
+ mibspiREG1->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */
+ | (uint32)((uint32)0U << 1U) /* SCS[1] */
+ | (uint32)((uint32)0U << 2U) /* SCS[2] */
+ | (uint32)((uint32)0U << 3U) /* SCS[3] */
+ | (uint32)((uint32)0U << 4U) /* SCS[4] */
+ | (uint32)((uint32)0U << 5U) /* SCS[5] */
+ | (uint32)((uint32)1U << 8U) /* ENA */
+ | (uint32)((uint32)1U << 9U) /* CLK */
+ | (uint32)((uint32)0U << 10U) /* SIMO[0] */
+ | (uint32)((uint32)1U << 11U) /* SOMI[0] */
+ | (uint32)((uint32)1U << 17U) /* SIMO[1] */
+ | (uint32)((uint32)1U << 25U); /* SOMI[1] */
+
+ /** - Finally start MIBSPI1 */
+ mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
+
+
+
+ /** @b initialize @b MIBSPI3 */
+
+ /** bring MIBSPI out of reset */
+ mibspiREG3->GCR0 = 0U;
+ mibspiREG3->GCR0 = 1U;
+
+ /** enable MIBSPI3 multibuffered mode and enable buffer RAM */
+ mibspiREG3->MIBSPIE = (mibspiREG3->MIBSPIE & 0xFFFFFFFEU) | 1U;
+
+ /** MIBSPI3 master mode and clock configuration */
+ mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */
+ | 1U); /* MASTER */
+
+ /** MIBSPI3 enable pin configuration */
+ mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */
+
+ /** - Delays */
+ mibspiREG3->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */
+ | (uint32)((uint32)0U << 16U) /* T2CDELAY */
+ | (uint32)((uint32)0U << 8U) /* T2EDELAY */
+ | (uint32)((uint32)0U << 0U); /* C2EDELAY */
+
+ /** - Data Format 0 */
+ mibspiREG3->FMT0 = (uint32)((uint32)20U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)1U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)8U << 0U); /* data word length */
+
+ /** - Data Format 1 */
+ mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Data Format 2 */
+ mibspiREG3->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Data Format 3 */
+ mibspiREG3->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Default Chip Select */
+ mibspiREG3->DEF = (uint32)(0xFFU);
+
+ /** - wait for buffer initialization complete before accessing MibSPI registers */
+ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */
+ while ((mibspiREG3->FLG & 0x01000000U) != 0U)
+ {
+ } /* Wait */
+
+ /** enable MIBSPI RAM Parity */
+ mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U);
+
+ /** - initialize transfer groups */
+ mibspiREG3->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)0U << 8U); /* start buffer */
+
+ mibspiREG3->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)11U << 8U); /* start buffer */
+
+ mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(11U+0U) << 8U); /* start buffer */
+
+ mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(11U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(11U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+
+ mibspiREG3->TGCTRL[8U] = (uint32)(11U+0U+0U+0U+0U+0U+0U+0U) << 8U;
+
+ mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
+
+ /** - initialize buffer ram */
+ {
+ i = 0U;
+
+#if (11U > 0U)
+ {
+
+#if (11U > 1U)
+
+ while (i < (11U-1U))
+ {
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)1U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */
+ i++;
+ }
+#endif
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */
+
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((11U+0U)-1U))
+ {
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((11U+0U+0U)-1U))
+ {
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((11U+0U+0U+0U)-1U))
+ {
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((11U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((11U+0U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((11U+0U+0U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((11U+0U+0U+0U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */
+ i++;
+ }
+#endif
+ }
+
+ /** - set interrupt levels */
+ mibspiREG3->LVL = (uint32)((uint32)0U << 9U) /* TXINT */
+ | (uint32)((uint32)0U << 8U) /* RXINT */
+ | (uint32)((uint32)0U << 6U) /* OVRNINT */
+ | (uint32)((uint32)0U << 4U) /* BITERR */
+ | (uint32)((uint32)0U << 3U) /* DESYNC */
+ | (uint32)((uint32)0U << 2U) /* PARERR */
+ | (uint32)((uint32)0U << 1U) /* TIMEOUT */
+ | (uint32)((uint32)0U << 0U); /* DLENERR */
+
+ /** - clear any pending interrupts */
+ mibspiREG3->FLG |= 0xFFFFU;
+
+ /** - enable interrupts */
+ mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U)
+ | (uint32)((uint32)0U << 9U) /* TXINT */
+ | (uint32)((uint32)0U << 8U) /* RXINT */
+ | (uint32)((uint32)1U << 6U) /* OVRNINT */
+ | (uint32)((uint32)1U << 4U) /* BITERR */
+ | (uint32)((uint32)1U << 3U) /* DESYNC */
+ | (uint32)((uint32)1U << 2U) /* PARERR */
+ | (uint32)((uint32)1U << 1U) /* TIMEOUT */
+ | (uint32)((uint32)1U << 0U); /* DLENERR */
+
+ /** @b initialize @b MIBSPI3 @b Port */
+
+ /** - MIBSPI3 Port output values */
+ mibspiREG3->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */
+ | (uint32)((uint32)1U << 1U) /* SCS[1] */
+ | (uint32)((uint32)1U << 2U) /* SCS[2] */
+ | (uint32)((uint32)1U << 3U) /* SCS[3] */
+ | (uint32)((uint32)1U << 4U) /* SCS[4] */
+ | (uint32)((uint32)1U << 5U) /* SCS[5] */
+ | (uint32)((uint32)0U << 8U) /* ENA */
+ | (uint32)((uint32)0U << 9U) /* CLK */
+ | (uint32)((uint32)0U << 10U) /* SIMO */
+ | (uint32)((uint32)0U << 11U); /* SOMI */
+
+ /** - MIBSPI3 Port direction */
+ mibspiREG3->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */
+ | (uint32)((uint32)1U << 1U) /* SCS[1] */
+ | (uint32)((uint32)1U << 2U) /* SCS[2] */
+ | (uint32)((uint32)1U << 3U) /* SCS[3] */
+ | (uint32)((uint32)1U << 4U) /* SCS[4] */
+ | (uint32)((uint32)1U << 5U) /* SCS[5] */
+ | (uint32)((uint32)0U << 8U) /* ENA */
+ | (uint32)((uint32)1U << 9U) /* CLK */
+ | (uint32)((uint32)1U << 10U) /* SIMO */
+ | (uint32)((uint32)0U << 11U); /* SOMI */
+
+ /** - MIBSPI3 Port open drain enable */
+ mibspiREG3->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */
+ | (uint32)((uint32)0U << 1U) /* SCS[1] */
+ | (uint32)((uint32)0U << 2U) /* SCS[2] */
+ | (uint32)((uint32)0U << 3U) /* SCS[3] */
+ | (uint32)((uint32)0U << 4U) /* SCS[4] */
+ | (uint32)((uint32)0U << 5U) /* SCS[5] */
+ | (uint32)((uint32)0U << 8U) /* ENA */
+ | (uint32)((uint32)0U << 9U) /* CLK */
+ | (uint32)((uint32)0U << 10U) /* SIMO */
+ | (uint32)((uint32)0U << 11U); /* SOMI */
+
+
+ /** - MIBSPI3 Port pullup / pulldown selection */
+ mibspiREG3->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */
+ | (uint32)((uint32)1U << 1U) /* SCS[1] */
+ | (uint32)((uint32)1U << 2U) /* SCS[2] */
+ | (uint32)((uint32)1U << 3U) /* SCS[3] */
+ | (uint32)((uint32)1U << 4U) /* SCS[4] */
+ | (uint32)((uint32)1U << 5U) /* SCS[5] */
+ | (uint32)((uint32)1U << 8U) /* ENA */
+ | (uint32)((uint32)1U << 9U) /* CLK */
+ | (uint32)((uint32)1U << 10U) /* SIMO */
+ | (uint32)((uint32)1U << 11U); /* SOMI */
+
+
+ /** - MIBSPI3 Port pullup / pulldown enable*/
+ mibspiREG3->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */
+ | (uint32)((uint32)0U << 1U) /* SCS[1] */
+ | (uint32)((uint32)0U << 2U) /* SCS[2] */
+ | (uint32)((uint32)0U << 3U) /* SCS[3] */
+ | (uint32)((uint32)0U << 4U) /* SCS[4] */
+ | (uint32)((uint32)0U << 5U) /* SCS[5] */
+ | (uint32)((uint32)0U << 8U) /* ENA */
+ | (uint32)((uint32)0U << 9U) /* CLK */
+ | (uint32)((uint32)0U << 10U) /* SIMO */
+ | (uint32)((uint32)0U << 11U); /* SOMI */
+
+
+ /* MIBSPI3 set all pins to functional */
+ mibspiREG3->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */
+ | (uint32)((uint32)1U << 1U) /* SCS[1] */
+ | (uint32)((uint32)0U << 2U) /* SCS[2] */
+ | (uint32)((uint32)0U << 3U) /* SCS[3] */
+ | (uint32)((uint32)0U << 4U) /* SCS[4] */
+ | (uint32)((uint32)1U << 5U) /* SCS[5] */
+ | (uint32)((uint32)1U << 8U) /* ENA */
+ | (uint32)((uint32)1U << 9U) /* CLK */
+ | (uint32)((uint32)1U << 10U) /* SIMO */
+ | (uint32)((uint32)1U << 11U); /* SOMI */
+
+ /** - Finally start MIBSPI3 */
+ mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
+
+
+
+ /** @b initialize @b MIBSPI5 */
+
+ /** bring MIBSPI out of reset */
+ mibspiREG5->GCR0 = 0U;
+ mibspiREG5->GCR0 = 1U;
+
+ /** enable MIBSPI5 multibuffered mode and enable buffer RAM */
+ mibspiREG5->MIBSPIE = (mibspiREG5->MIBSPIE & 0xFFFFFFFEU) | 1U;
+
+ /** MIBSPI5 master mode and clock configuration */
+ mibspiREG5->GCR1 = (mibspiREG5->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */
+ | 1U); /* MASTER */
+
+ /** MIBSPI5 enable pin configuration */
+ mibspiREG5->INT0 = (mibspiREG5->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */
+
+ /** - Delays */
+ mibspiREG5->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */
+ | (uint32)((uint32)0U << 16U) /* T2CDELAY */
+ | (uint32)((uint32)0U << 8U) /* T2EDELAY */
+ | (uint32)((uint32)0U << 0U); /* C2EDELAY */
+
+ /** - Data Format 0 */
+ mibspiREG5->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Data Format 1 */
+ mibspiREG5->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Data Format 2 */
+ mibspiREG5->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Data Format 3 */
+ mibspiREG5->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */
+ | (uint32)((uint32)0U << 23U) /* parity Polarity */
+ | (uint32)((uint32)0U << 22U) /* parity enable */
+ | (uint32)((uint32)0U << 21U) /* wait on enable */
+ | (uint32)((uint32)0U << 20U) /* shift direction */
+ | (uint32)((uint32)0U << 17U) /* clock polarity */
+ | (uint32)((uint32)0U << 16U) /* clock phase */
+ | (uint32)((uint32)103U << 8U) /* baudrate prescale */
+ | (uint32)((uint32)16U << 0U); /* data word length */
+
+ /** - Default Chip Select */
+ mibspiREG5->DEF = (uint32)(0xFFU);
+
+ /** - wait for buffer initialization complete before accessing MibSPI registers */
+ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */
+ while ((mibspiREG5->FLG & 0x01000000U) != 0U)
+ {
+ } /* Wait */
+
+ /** enable MIBSPI RAM Parity */
+ mibspiREG5->UERRCTRL = (mibspiREG5->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U);
+
+ /** - initialize transfer groups */
+ mibspiREG5->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)0U << 8U); /* start buffer */
+
+ mibspiREG5->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)8U << 8U); /* start buffer */
+
+ mibspiREG5->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U) << 8U); /* start buffer */
+
+ mibspiREG5->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG5->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG5->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG5->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+ mibspiREG5->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */
+ | (uint32)((uint32)0U << 29U) /* pcurrent reset */
+ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
+ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
+ | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */
+
+
+ mibspiREG5->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
+
+ mibspiREG5->LTGPEND = (mibspiREG5->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
+
+ /** - initialize buffer ram */
+ {
+ i = 0U;
+
+#if (8U > 0U)
+ {
+
+#if (8U > 1U)
+
+ while (i < (8U-1U))
+ {
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */
+ i++;
+ }
+#endif
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */
+
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U)-1U))
+ {
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U)-1U))
+ {
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U)-1U))
+ {
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+
+#if (0U > 0U)
+ {
+
+#if (0U > 1U)
+
+ while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U))
+ {
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 11U) /* lock transmission */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */
+ | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */
+
+ i++;
+ }
+#endif
+ mibspiRAM5->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
+ | (uint16)((uint16)0U << 12U) /* chip select hold */
+ | (uint16)((uint16)0U << 10U) /* enable WDELAY */
+ | (uint16)((uint16)0U << 8U) /* data format */
+ /*SAFETYMCUSW 334 S MR:10.5