Index: firmware/TD.dil =================================================================== diff -u -r25824b289643df0560feea73f5529a0f30b7de6d -r86d861623e84ebdebae69d710fef89fa86f96712 --- firmware/TD.dil (.../TD.dil) (revision 25824b289643df0560feea73f5529a0f30b7de6d) +++ firmware/TD.dil (.../TD.dil) (revision 86d861623e84ebdebae69d710fef89fa86f96712) @@ -1,4 +1,4 @@ -# RM46L852PGE 09/05/25 09:54:54 +# RM46L852PGE 01/19/26 17:52:56 # ARCH=RM46L852PGE # @@ -105,7 +105,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18 DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATEVALUE.VALUE=0x5 DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0 @@ -240,7 +240,7 @@ DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=etpwm6Interrupt DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1 -DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_RAMPARITYCHECK_ENA.VALUE=0 @@ -351,8 +351,8 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE -DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE @@ -707,7 +707,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1 -DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=0 DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=104.000 DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=165.0 Index: firmware/source/sys_link.cmd =================================================================== diff -u -r73d8423edc56daed591bc0b3f7baee5540aea423 -r86d861623e84ebdebae69d710fef89fa86f96712 --- firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 73d8423edc56daed591bc0b3f7baee5540aea423) +++ firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 86d861623e84ebdebae69d710fef89fa86f96712) @@ -67,18 +67,50 @@ #if 1 MEMORY { - VECTORS (X) : origin=0x00000000 length=0x00000020 - CRCMEM (RX) : origin=0x00000020 length=0x000001E0 - FLASH0 (RX) : origin=0x00000200 length=0x0013FE00 - STACKS (RW) : origin=0x08000000 length=0x00003400 - RAM (RW) : origin=0x08003400 length=0x0002cc00 + VECTORS (X) : origin=0x00010000 + length=0x00000020 + vfill = 0xffffffff + CRCMEM (RX) : origin=end(VECTORS) + length=0x000001E0 + vfill = 0xffffffff + + FLASH0 (RX) : origin=end(CRCMEM) + length=(0x0013FFFF - end(CRCMEM)) + vfill = 0xffffffff + + STACKS (RW) : origin=0x08000000 + length=0x00004c00 + + RAM (RW) : origin=0x08004c00 + length=0x0002b400 #endif +// TODO do we need ECC? +//#if 1 +// ECC_VEC (R) : origin=(0xf0400000 + (start(VECTORS) >> 3)) +// length=(size(VECTORS) >> 3) +// ECC={algorithm=algoL2R4F021, input_range=VECTORS} +// +// ECC_CRC (R) : origin=(0xf0400000 + (start(CRCMEM) >> 3)) +// length=(size(CRCMEM) >> 3) +// ECC={algorithm=algoL2R4F021, input_range=CRCMEM } +// +// ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0) >> 3)) +// length=(size(FLASH0) >> 3) +// ECC={algorithm=algoL2R4F021, input_range=FLASH0 } +//#endif /* USER CODE END */ } /* USER CODE BEGIN (3) */ /* IGNORE the generated Sections code, overridden below */ +//ECC +//{ +// algoL2R4F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */ +// hamming_mask = R4 /* Use R4/R5 build in Mask */ +// parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */ +// mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */ +//} #if 0 /* USER CODE END */ Index: firmware/source/sys_main.c =================================================================== diff -u -rf979c391268b595e44fb6747d43487e4d2294e68 -r86d861623e84ebdebae69d710fef89fa86f96712 --- firmware/source/sys_main.c (.../sys_main.c) (revision f979c391268b595e44fb6747d43487e4d2294e68) +++ firmware/source/sys_main.c (.../sys_main.c) (revision 86d861623e84ebdebae69d710fef89fa86f96712) @@ -71,6 +71,7 @@ #include "DDInterface.h" #include "Ejector.h" #include "FpgaTD.h" +#include "Integrity.h" #include "InternalADC.h" #include "Interrupts.h" #include "MsgQueues.h" @@ -183,7 +184,7 @@ initTestConfigs(); initCommBuffers(); initDDInterface(); -// initIntegrity(); + initIntegrity(); initFpgaTD(); initMsgQueues(); // initNVDataMgmt(); Index: firmware/source/sys_mpu.asm =================================================================== diff -u -r73d8423edc56daed591bc0b3f7baee5540aea423 -r86d861623e84ebdebae69d710fef89fa86f96712 --- firmware/source/sys_mpu.asm (.../sys_mpu.asm) (revision 73d8423edc56daed591bc0b3f7baee5540aea423) +++ firmware/source/sys_mpu.asm (.../sys_mpu.asm) (revision 86d861623e84ebdebae69d710fef89fa86f96712) @@ -181,16 +181,6 @@ mcr p15, #0, r0, c6, c1, #2 - ; Enable mpu background region - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x20000 - mcr p15, #0, r0, c1, c0, #0 - ; Enable mpu - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #1 - dsb - mcr p15, #0, r0, c1, c0, #0 - isb bx lr r1Base .word 0x00000000 Index: firmware/source/sys_startup.c =================================================================== diff -u -r794a0f21a465227d432a91d7b7fd7d513cfe3ecb -r86d861623e84ebdebae69d710fef89fa86f96712 --- firmware/source/sys_startup.c (.../sys_startup.c) (revision 794a0f21a465227d432a91d7b7fd7d513cfe3ecb) +++ firmware/source/sys_startup.c (.../sys_startup.c) (revision 86d861623e84ebdebae69d710fef89fa86f96712) @@ -120,19 +120,7 @@ * by its ECC logic for accesses to program flash or data RAM. */ _coreEnableEventBusExport_(); -/* USER CODE BEGIN (9) */ -/* USER CODE END */ - /* Enable response to ECC errors indicated by CPU for accesses to flash */ - flashWREG->FEDACCTRL1 = 0x000A060AU; - -/* USER CODE BEGIN (10) */ -/* USER CODE END */ - - /* Enable CPU ECC checking for ATCM (flash accesses) */ - _coreEnableFlashEcc_(); - - /* USER CODE BEGIN (11) */ /* USER CODE END */ @@ -385,26 +373,6 @@ /* USER CODE BEGIN (37) */ /* USER CODE END */ - - /* Initialize CPU RAM. - * This function uses the system module's hardware for auto-initialization of memories and their - * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. - * Hence the value 0x1 passed to the function. - * This function will initialize the entire CPU RAM and the corresponding ECC locations. - */ - memoryInit(0x1U); - -/* USER CODE BEGIN (38) */ -/* USER CODE END */ - - /* Enable ECC checking for TCRAM accesses. - * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. - */ - _coreEnableRamEcc_(); - -/* USER CODE BEGIN (39) */ -/* USER CODE END */ - /* Start PBIST on all dual-port memories */ /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories. PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. @@ -431,18 +399,6 @@ /* USER CODE BEGIN (40) */ /* USER CODE END */ - - /* Test the CPU ECC mechanism for RAM accesses. - * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses - * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error - * in the ECC causes a data abort exception. The data abort handler is written to look for - * deliberately caused exception and to return the code execution to the instruction - * following the one that caused the abort. - */ - checkRAMECC(); - -/* USER CODE BEGIN (41) */ -/* USER CODE END */ /* USER CODE BEGIN (43) */ /* USER CODE END */