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Commits this week: 2
Total Committers: 13
Last Commit: 04 Jun
Commits this week: 2

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Wednesday 28 Jul 2021
8:54 pm

Dara Navaei

This is fixed in the latest commit.

This is fixed in the latest commit.

8:46 pm

Dara Navaei

Done.

Done.

8:45 pm

Dara Navaei

The default pump control mode is none.

The default pump control mode is none.

8:44 pm

Dara Navaei

Done.

Done.

8:09 pm

Dara Navaei

Done.

Done.

8:07 pm

Dara Navaei

Done.

Done.

8:06 pm

Dara Navaei

Done.

Done.

8:04 pm

Dara Navaei

8:04 pm

Dara Navaei

This structure was transferred DGDefs.h

This structure was transferred DGDefs.h

Tuesday 27 Jul 2021
5:50 pm

Sean Nash

Where did this go?

Where did this go?

5:15 pm

Sean Nash

So these & operators are going to yield a zero or a non-zero number that will be different for each switch (not a boolean). I think your intent is for these switch data to be an enum. So, for examp...

So these & operators are going to yield a zero or a non-zero number that will be different for each switch (not a boolean). I think your intent is for these switch data to be an enum. So, for example, this one should be "... = ( ( fpgaRegister & CONCENTRATE_CAP_SWITCH_BIT_MASK ) != 0 ? OPEN : CLOSED );

5:13 pm

Sean Nash

Put test functions at bottom of module (after usual banner).

Put test functions at bottom of module (after usual banner).

5:04 pm

Sean Nash

I don't see this being initialized in init function.

I don't see this being initialized in init function.

4:16 pm

Sean Nash

I like to add a comment to right of system library includes explaining why they are needed (i.e. which math functions are you using in this module).

I like to add a comment to right of system library includes explaining why they are needed (i.e. which math functions are you using in this module).

Monday 26 Jul 2021
10:31 am

Sean Nash

Should we close both drain valves VRd1 and VRd2 here?

Should we close both drain valves VRd1 and VRd2 here?

10:24 am

Sean Nash

I think other fill volumes would come from HD, so we can remove this TODO.

I think other fill volumes would come from HD, so we can remove this TODO.

10:21 am

Sean Nash

The GPIO register is shared (e.g. see fluid leak in above function). So I think we should have separate functions for each bit that we use in the GPIO register. Also - why does the function name ha...

The GPIO register is shared (e.g. see fluid leak in above function). So I think we should have separate functions for each bit that we use in the GPIO register.
Also - why does the function name have the word Count in it?

10:17 am

Sean Nash

Please restore the vector length test.

Please restore the vector length test.

10:12 am

Sean Nash

How is this used?

How is this used?

10:10 am

Sean Nash

I think these @param descriptions could fit in one line for a cleaner look.

I think these @param descriptions could fit in one line for a cleaner look.

10:07 am

Sean Nash

For consistency, can we put Dialin functions at end?

For consistency, can we put Dialin functions at end?

10:00 am

Sean Nash

Compatibility check should be before FPGA test at end where it was. We can't do it this early because UI may not have provided us with version/compatibility info yet.

Compatibility check should be before FPGA test at end where it was. We can't do it this early because UI may not have provided us with version/compatibility info yet.

Tuesday 20 Jul 2021
10:12 pm

Dara Navaei

DG-DEN-9054_DG HD Switches
DG-DEN-9054_DG HD Switches
Friday 25 Jun 2021
10:42 am

qnguyen  (deleted user)

10:42 am

Dara Navaei , Sean Nash and pmontazemi  (deleted user)

10:35 am

pmontazemi  (deleted user)

RESOLVED in CODE WALKTHROUGH.

RESOLVED in CODE WALKTHROUGH.

10:34 am

Sean Nash

RESOLVED in CODE WALKTHROUGH.

RESOLVED in CODE WALKTHROUGH.

Thursday 24 Jun 2021
11:31 am

qnguyen  (deleted user)

Duplicate declaration from line 330.

Duplicate declaration from line 330.

Wednesday 23 Jun 2021
10:08 am

qnguyen  (deleted user)

Done.

Done.

9:28 am

Sean Nash

Why removed?

Why removed?