Do you want to update the TD and RO FPGA compatiable rev as zero? looks currently FPGA returning them as zero and will fail in init mode - FPGA self test.
Do you want to update the TD and RO FPGA compatiable rev as zero? looks currently FPGA returning them as zero and will fail in init mode - FPGA self test.
Initial foundation based on code from Denali HD. AlarmMgmt, SystemComm and FPGA are split with common parts going to a fwcommon unit and reset going to sub-sys specific unit. WatchdogMgmt moved to fwcommon.