This is a reset call, as the default requirement is to be on Beta 1.9 HW The logic is checking if the user is resetting the Beta 2.0 config, if yes, we will have to fall back to the Beta 1.9 FPGA r...
This is a reset call, as the default requirement is to be on Beta 1.9 HW
The logic is checking if the user is resetting the Beta 2.0 config, if yes, we will have to fall back to the Beta 1.9 FPGA registers