Should we be filtering a new sample every 700ms or should we do it when a new sample is received? FPGA is giving us a read count right? So we will know when we have a new data set from sensor. It makes more sense to me to take them when they come. Otherwise, we will get out of phase with true sample frequency and occasionally process the previous sample again (if true sample freq is a little slower than 700ms) or miss a sample (if true sample freq is a little faster than 700ms).
Who is calling this function? Should be coming from UI, right? So should be a message handler (returns BOOL, takes a message as param, function is in table at top of Messaging.c).
I don't think these min/max (for control output in output units i.e. PWM) are appropriate for limiting maximum error sum step size (error is in feedback/target units i.e. RPM).
Vinayakam Mani, how does that signal happen normally? In your example, when would DD signal FP when starting pre-gen mode? If that signal happened in pre-gen transition function, it would always happen regardless of how we got to pre-gen mode.
I don't see a TODO. If we intend to uncomment this line out later, we should add a TODO comment to the right as a reminder. If we do not intend to uncomment this later, we should just delete it.
